[Intel-gfx] [PATCH v2 0/9] Reduce MTL-specific platform checks

[Intel-gfx] [PATCH v2 0/9] Reduce MTL-specific platform checks

[Matt Roper]

Starting with MTL, the hardware moved to a disaggregated IP design where
graphics, media, and display are supposed to be treated independently of
the base platform that they're incorporated into.  For driver logic that
is conditional on these IPs, the code should be checking the IP versions
(as read from the GMD_ID registers) rather than trying to match on a
specific platform (e.g., MTL).  It's possible that these IPs could show
up again, without changes, on future non-MTL platforms, or that the
current MTL platform could be extended to include new IP versions in
future SKUs or refreshes; making sure our driver's conditions are
handled appropriately future-proofs for both of these cases.

Going forward, conditions like IS_METEORLAKE should be very rare in the
driver; in most places our logic will be conditional upon the IP rather
than the base platform.

v2:
 - Rework macros slightly; new IP range and stepping range macros can be
   used with both GFX or MEDIA rather than needing separate macros for
   each IP.  (Tvrtko, Gustavo)
 - Fix a > that should have been a >=.  (Gustavo)
 - Split non-inheritance of media workarounds by future platforms into
   its own patch.  (Gustavo)
 - Extra documentation comments

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>

Matt Roper (9):
  drm/i915: Consolidate condition for Wa_22011802037
  drm/i915/xelpmp: Don't assume workarounds extend to future platforms
  drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version
  drm/i915: Eliminate IS_MTL_GRAPHICS_STEP
  drm/i915: Eliminate IS_MTL_MEDIA_STEP
  drm/i915: Eliminate IS_MTL_DISPLAY_STEP
  drm/i915/mtl: Eliminate subplatforms
  drm/i915/display: Eliminate IS_METEORLAKE checks
  drm/i915: Replace several IS_METEORLAKE with proper IP version checks

 drivers/gpu/drm/i915/display/intel_cdclk.c    |  4 +-
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  2 +-
 .../drm/i915/display/intel_display_device.h   | 17 ++++
 drivers/gpu/drm/i915/display/intel_dmc.c      |  2 +-
 drivers/gpu/drm/i915/display/intel_fbc.c      |  3 +-
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 10 +-
 .../drm/i915/display/skl_universal_plane.c    |  4 +-
 drivers/gpu/drm/i915/gem/i915_gem_create.c    |  4 +-
 drivers/gpu/drm/i915/gem/i915_gem_pages.c     |  8 +-
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  9 +-
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |  4 +-
 drivers/gpu/drm/i915/gt/intel_engine_pm.c     |  2 +-
 .../drm/i915/gt/intel_execlists_submission.c  |  4 +-
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c           |  8 +-
 drivers/gpu/drm/i915/gt/intel_mocs.c          |  2 +-
 drivers/gpu/drm/i915/gt/intel_rc6.c           |  3 +-
 drivers/gpu/drm/i915/gt/intel_reset.c         | 20 +++-
 drivers/gpu/drm/i915/gt/intel_reset.h         |  2 +
 drivers/gpu/drm/i915/gt/intel_rps.c           |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 92 ++++++++++---------
 drivers/gpu/drm/i915/gt/uc/intel_guc.c        | 10 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  6 +-
 drivers/gpu/drm/i915/i915_debugfs.c           |  2 +-
 drivers/gpu/drm/i915/i915_drv.h               | 67 ++++++++++----
 drivers/gpu/drm/i915/i915_perf.c              | 23 ++---
 drivers/gpu/drm/i915/intel_device_info.c      | 14 ---
 drivers/gpu/drm/i915/intel_device_info.h      |  4 -
 include/drm/i915_pciids.h                     | 11 +--
 31 files changed, 196 insertions(+), 151 deletions(-)

-- 
2.41.0

[Intel-gfx] [PATCH v2 1/9] drm/i915: Consolidate condition for Wa_22011802037

[Matt Roper]

The workaround bounds for Wa_22011802037 are somewhat complex and are
replicated in several places throughout the code.  Pull the condition
out to a helper function to prevent mistakes if this condition needs to
change again in the future.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c      |  4 +---
 .../drm/i915/gt/intel_execlists_submission.c   |  4 +---
 drivers/gpu/drm/i915/gt/intel_reset.c          | 18 ++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_reset.h          |  2 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc.c         |  4 +---
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c  |  4 +---
 6 files changed, 24 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index ee15486fed0d..dfb69fc977a0 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1617,9 +1617,7 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
 	 * Wa_22011802037: Prior to doing a reset, ensure CS is
 	 * stopped, set ring stop bit and prefetch disable bit to halt CS
 	 */
-	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
-	    (GRAPHICS_VER(engine->i915) >= 11 &&
-	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
+	if (intel_engine_reset_needs_wa_22011802037(engine->gt))
 		intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
 				      _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
 
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 8a641bcf777c..4d05321dc5b5 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3001,9 +3001,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
 	 * Wa_22011802037: In addition to stopping the cs, we need
 	 * to wait for any pending mi force wakeups
 	 */
-	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
-	    (GRAPHICS_VER(engine->i915) >= 11 &&
-	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
+	if (intel_engine_reset_needs_wa_22011802037(engine->gt))
 		intel_engine_wait_for_pending_mi_fw(engine);
 
 	engine->execlists.reset_ccid = active_ccid(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index cc6bd21a3e51..1ff7b42521c9 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1632,6 +1632,24 @@ void __intel_fini_wedge(struct intel_wedge_me *w)
 	w->gt = NULL;
 }
 
+/*
+ * Wa_22011802037 requires that we (or the GuC) ensure that no command
+ * streamers are executing MI_FORCE_WAKE while an engine reset is initiated.
+ */
+bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
+{
+	if (GRAPHICS_VER(gt->i915) < 11)
+		return false;
+
+	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
+		return true;
+
+	if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
+		return false;
+
+	return true;
+}
+
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 #include "selftest_reset.c"
 #include "selftest_hangcheck.c"
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h b/drivers/gpu/drm/i915/gt/intel_reset.h
index 25c975b6e8fc..f615b30b81c5 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.h
+++ b/drivers/gpu/drm/i915/gt/intel_reset.h
@@ -78,4 +78,6 @@ void __intel_fini_wedge(struct intel_wedge_me *w);
 bool intel_has_gpu_reset(const struct intel_gt *gt);
 bool intel_has_reset_engine(const struct intel_gt *gt);
 
+bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt);
+
 #endif /* I915_RESET_H */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 2eb891b270ae..1e532981f74e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -292,9 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
 		flags |= GUC_WA_DUAL_QUEUE;
 
 	/* Wa_22011802037: graphics version 11/12 */
-	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
-	    (GRAPHICS_VER(gt->i915) >= 11 &&
-	    GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
+	if (intel_engine_reset_needs_wa_22011802037(gt))
 		flags |= GUC_WA_PRE_PARSER;
 
 	/* Wa_16011777198:dg2 */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index a0e3ef1c65d2..1bd5d8f7c40b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1658,9 +1658,7 @@ static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
 	 * Wa_22011802037: In addition to stopping the cs, we need
 	 * to wait for any pending mi force wakeups
 	 */
-	if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
-	    (GRAPHICS_VER(engine->i915) >= 11 &&
-	     GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
+	if (intel_engine_reset_needs_wa_22011802037(engine->gt)) {
 		intel_engine_stop_cs(engine);
 		intel_engine_wait_for_pending_mi_fw(engine);
 	}
-- 
2.41.0

[Intel-gfx] [PATCH v2 2/9] drm/i915/xelpmp: Don't assume workarounds extend to future platforms

[Matt Roper]

The currently implemented Xe_LPM+ workarounds are specific to media
version 13.00.  When new IP versions show up in the future, they'll need
their own workaround lists.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 589d009032fc..d8a1eaa44e69 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1817,10 +1817,10 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
 	gt_tuning_settings(gt, wal);
 
 	if (gt->type == GT_MEDIA) {
-		if (MEDIA_VER(i915) >= 13)
+		if (MEDIA_VER_FULL(i915) == IP_VER(13, 0))
 			xelpmp_gt_workarounds_init(gt, wal);
 		else
-			MISSING_CASE(MEDIA_VER(i915));
+			MISSING_CASE(MEDIA_VER_FULL(i915));
 
 		return;
 	}
-- 
2.41.0

[Intel-gfx] [PATCH v2 3/9] drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version

[Matt Roper]

Although some of our Xe_LPG workarounds were already being applied based
on IP version correctly, others were matching on MTL as a base platform,
which is incorrect.  Although MTL is the only platform right now that
uses Xe_LPG IP, this may not always be the case.  If a future platform
re-uses this graphics IP, the same workarounds should be applied, even
if it isn't a "MTL" platform.

We were also incorrectly applying Xe_LPG workarounds/tuning to the
Xe_LPM+ media IP in one or two places; we should make sure that we don't
try to apply graphics workarounds to the media GT and vice versa where
they don't belong.  A new helper macro IS_GT_IP_RANGE() is added to help
ensure this is handled properly -- it checks that the GT matches the IP
type being tested as well as the IP version falling in the proper range.

Note that many of the stepping-based workarounds are still incorrectly
checking for a MTL base platform; that will be remedied in a later
patch.

v2:
 - Rework macro into a slightly more generic IS_GT_IP_RANGE() that can
   be used for either GFX or MEDIA checks.

Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 38 +++++++++++----------
 drivers/gpu/drm/i915/i915_drv.h             | 23 +++++++++++++
 2 files changed, 43 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index d8a1eaa44e69..c4663541c5dd 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -805,8 +805,8 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
 	wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
 }
 
-static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
-				   struct i915_wa_list *wal)
+static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
+				     struct i915_wa_list *wal)
 {
 	struct drm_i915_private *i915 = engine->i915;
 
@@ -817,12 +817,12 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
 		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
 }
 
-static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
-				     struct i915_wa_list *wal)
+static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
+				       struct i915_wa_list *wal)
 {
 	struct drm_i915_private *i915 = engine->i915;
 
-	mtl_ctx_gt_tuning_init(engine, wal);
+	xelpg_ctx_gt_tuning_init(engine, wal);
 
 	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
 	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
@@ -931,8 +931,8 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 	if (engine->class != RENDER_CLASS)
 		goto done;
 
-	if (IS_METEORLAKE(i915))
-		mtl_ctx_workarounds_init(engine, wal);
+	if (IS_GT_IP_RANGE(GFX, engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
+		xelpg_ctx_workarounds_init(engine, wal);
 	else if (IS_PONTEVECCHIO(i915))
 		; /* noop; none at this time */
 	else if (IS_DG2(i915))
@@ -1790,10 +1790,8 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
  */
 static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
 {
-	if (IS_METEORLAKE(gt->i915)) {
-		if (gt->type != GT_MEDIA)
-			wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
-
+	if (IS_GT_IP_RANGE(GFX, gt, IP_VER(12, 70), IP_VER(12, 71))) {
+		wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
 		wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
 	}
 
@@ -1825,7 +1823,7 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
 		return;
 	}
 
-	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+	if (IS_GT_IP_RANGE(GFX, gt, IP_VER(12, 70), IP_VER(12, 71)))
 		xelpg_gt_workarounds_init(gt, wal);
 	else if (IS_PONTEVECCHIO(i915))
 		pvc_gt_workarounds_init(gt, wal);
@@ -2293,7 +2291,7 @@ static void pvc_whitelist_build(struct intel_engine_cs *engine)
 	blacklist_trtt(engine);
 }
 
-static void mtl_whitelist_build(struct intel_engine_cs *engine)
+static void xelpg_whitelist_build(struct intel_engine_cs *engine)
 {
 	struct i915_wa_list *w = &engine->whitelist;
 
@@ -2315,8 +2313,10 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
 
 	wa_init_start(w, engine->gt, "whitelist", engine->name);
 
-	if (IS_METEORLAKE(i915))
-		mtl_whitelist_build(engine);
+	if (engine->gt->type == GT_MEDIA)
+		; /* none yet */
+	else if (IS_GT_IP_RANGE(GFX, engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
+		xelpg_whitelist_build(engine);
 	else if (IS_PONTEVECCHIO(i915))
 		pvc_whitelist_build(engine);
 	else if (IS_DG2(i915))
@@ -2974,10 +2974,12 @@ ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
  * function invoked by __intel_engine_init_ctx_wa().
  */
 static void
-add_render_compute_tuning_settings(struct drm_i915_private *i915,
+add_render_compute_tuning_settings(struct intel_gt *gt,
 				   struct i915_wa_list *wal)
 {
-	if (IS_METEORLAKE(i915) || IS_DG2(i915))
+	struct drm_i915_private *i915 = gt->i915;
+
+	if (IS_GT_IP_RANGE(GFX, gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))
 		wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
 
 	/*
@@ -3007,7 +3009,7 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 {
 	struct drm_i915_private *i915 = engine->i915;
 
-	add_render_compute_tuning_settings(i915, wal);
+	add_render_compute_tuning_settings(engine->gt, wal);
 
 	if (GRAPHICS_VER(i915) >= 11) {
 		/* This is not a Wa (although referred to as
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 682ef2b5c7d5..6bb825d40451 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -431,6 +431,29 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
 #define IS_GRAPHICS_VER(i915, from, until) \
 	(GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
 
+#define __IS_MEDIA_GT(gt) ((gt)->type == GT_MEDIA)
+#define __IS_GFX_GT(gt) (!__IS_MEDIA_GT(gt))
+#define __GT_VER_FULL(gt) (__IS_MEDIA_GT(gt) ? \
+			   MEDIA_VER_FULL((gt)->i915) : \
+			   GRAPHICS_VER_FULL((gt)->i915))
+
+/*
+ * Check that a GT contains IP of the specified type and within the specified
+ * IP range.  E.g.,
+ *
+ *    IS_GT_IP_RANGE(GFX, IP_VER(12, 70), IP_VER(12, 71))
+ *    IS_GT_IP_RANGE(MEDIA, IP_VER(13, 00), IP_VER(18, 02))
+ *
+ * Note that media version checks with this macro will only work on platforms
+ * with standalone media design (i.e., media version 13 and higher).
+ */
+#define IS_GT_IP_RANGE(type, gt, from, until) ( \
+	BUILD_BUG_ON_ZERO(from < IP_VER(2, 0)) + \
+	BUILD_BUG_ON_ZERO(until < from) + \
+	(__IS_##type##_GT(gt) && \
+	 __GT_VER_FULL(gt) >= (from) && \
+	 __GT_VER_FULL(gt) <= (until)))
+
 #define MEDIA_VER(i915)			(RUNTIME_INFO(i915)->media.ip.ver)
 #define MEDIA_VER_FULL(i915)		IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
 					       RUNTIME_INFO(i915)->media.ip.rel)
-- 
2.41.0

[Intel-gfx] [PATCH v2 4/9] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP

[Matt Roper]

Several workarounds are guarded by IS_MTL_GRAPHICS_STEP.  However none
of these workarounds are actually tied to MTL as a platform; they only
relate to the Xe_LPG graphics IP, regardless of what platform it appears
in.  At the moment MTL is the only platform that uses Xe_LPG with IP
versions 12.70 and 12.71, but we can't count on this being true in the
future.  Switch these to use a new IS_GT_IP_STEP() macro instead that is
purely based on IP version.  IS_GT_IP_STEP() is also GT-based rather
than device-based, which will help prevent mistakes where we
accidentally try to apply Xe_LPG graphics workarounds to the Xe_LPM+
media GT and vice-versa.

v2:
 - Switch to a more generic and shorter IS_GT_IP_STEP macro that can be
   used for both graphics and media IP (and any other kind of GTs that
   show up in the future).

Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 .../drm/i915/display/skl_universal_plane.c    |  4 +-
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  9 ++--
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
 drivers/gpu/drm/i915/gt/intel_reset.c         |  2 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 52 ++++++++++---------
 drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  2 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  2 +-
 drivers/gpu/drm/i915/i915_drv.h               | 30 +++++++++--
 9 files changed, 67 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 6b01a0b68b97..5fd8a42b3ec1 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
 				 enum pipe pipe, enum plane_id plane_id)
 {
 	/* Wa_14017240301 */
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_GT_IP_STEP(GFX, to_gt(i915), IP_VER(12, 70), A0, B0) ||
+	    IS_GT_IP_STEP(GFX, to_gt(i915), IP_VER(12, 71), A0, B0))
 		return false;
 
 	/* Wa_22011186057 */
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 3ba20ea030e8..9d04591f3b4a 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
 static int mtl_dummy_pipe_control(struct i915_request *rq)
 {
 	/* Wa_14016712196 */
-	if (IS_MTL_GRAPHICS_STEP(rq->i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(rq->i915, P, STEP_A0, STEP_B0)) {
+	if (IS_GT_IP_STEP(GFX, rq->engine->gt, IP_VER(12, 70), A0, B0) ||
+	    IS_GT_IP_STEP(GFX, rq->engine->gt, IP_VER(12, 71), A0, B0)) {
 		u32 *cs;
 
 		/* dummy PIPE_CONTROL + depth flush */
@@ -755,6 +755,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
 u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
 {
 	struct drm_i915_private *i915 = rq->i915;
+	struct intel_gt *gt = rq->engine->gt;
 	u32 flags = (PIPE_CONTROL_CS_STALL |
 		     PIPE_CONTROL_TLB_INVALIDATE |
 		     PIPE_CONTROL_TILE_CACHE_FLUSH |
@@ -765,8 +766,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
 		     PIPE_CONTROL_FLUSH_ENABLE);
 
 	/* Wa_14016712196 */
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
+	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0))
 		/* dummy PIPE_CONTROL + depth flush */
 		cs = gen12_emit_pipe_control(cs, 0,
 					     PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 0b414eae1683..c66373176f6c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
 		gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
 	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
 		/* Wa_14016747170 */
-		if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-		    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+		if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
+		    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0))
 			fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
 					     intel_uncore_read(gt->uncore,
 							       MTL_GT_ACTIVITY_FACTOR));
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 1b710102390b..8057cc5800b3 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1377,8 +1377,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
 					      cs, GEN12_GFX_CCS_AUX_NV);
 
 	/* Wa_16014892111 */
-	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
+	if (IS_GT_IP_STEP(GFX, ce->engine->gt, IP_VER(12, 70), A0, B0) ||
+	    IS_GT_IP_STEP(GFX, ce->engine->gt, IP_VER(12, 71), A0, B0) ||
 	    IS_DG2(ce->engine->i915))
 		cs = dg2_emit_draw_watermark_setting(cs);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 1ff7b42521c9..efe83157ef78 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1641,7 +1641,7 @@ bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
 	if (GRAPHICS_VER(gt->i915) < 11)
 		return false;
 
-	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
+	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0))
 		return true;
 
 	if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index c4663541c5dd..b7cf1790c827 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -808,24 +808,24 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
 static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
 				     struct i915_wa_list *wal)
 {
-	struct drm_i915_private *i915 = engine->i915;
+	struct intel_gt *gt = engine->gt;
 
 	dg2_ctx_gt_tuning_init(engine, wal);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
+	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), B0, FOREVER) ||
+	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), B0, FOREVER))
 		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
 }
 
 static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
 				       struct i915_wa_list *wal)
 {
-	struct drm_i915_private *i915 = engine->i915;
+	struct intel_gt *gt = engine->gt;
 
 	xelpg_ctx_gt_tuning_init(engine, wal);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
+	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
+	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0)) {
 		/* Wa_14014947963 */
 		wa_masked_field_set(wal, VF_PREEMPTION,
 				    PREEMPTION_VERTEX_COUNT, 0x4000);
@@ -1746,8 +1746,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
 	/* Wa_22016670082 */
 	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
 
-	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
+	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
+	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0)) {
 		/* Wa_14014830051 */
 		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
 
@@ -2424,16 +2424,17 @@ static void
 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 {
 	struct drm_i915_private *i915 = engine->i915;
+	struct intel_gt *gt = engine->gt;
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
+	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
+	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0)) {
 		/* Wa_22014600077 */
 		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
 				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
+	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0) ||
 	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
 	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
 		/* Wa_1509727124 */
@@ -2443,7 +2444,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 
 	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
 	    IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
-	    IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
+	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0)) {
 		/* Wa_22012856258 */
 		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
 				 GEN12_DISABLE_READ_SUPPRESSION);
@@ -3008,8 +3009,9 @@ static void
 general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 {
 	struct drm_i915_private *i915 = engine->i915;
+	struct intel_gt *gt = engine->gt;
 
-	add_render_compute_tuning_settings(engine->gt, wal);
+	add_render_compute_tuning_settings(gt, wal);
 
 	if (GRAPHICS_VER(i915) >= 11) {
 		/* This is not a Wa (although referred to as
@@ -3030,13 +3032,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 				 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
+	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), B0, FOREVER) ||
+	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), B0, FOREVER))
 		/* Wa_14017856879 */
 		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
+	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0))
 		/*
 		 * Wa_14017066071
 		 * Wa_14017654203
@@ -3044,13 +3046,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
 				 MTL_DISABLE_SAMPLER_SC_OOO);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0))
 		/* Wa_22015279794 */
 		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
 				 DISABLE_PREFETCH_INTO_IC);
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
+	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0) ||
 	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
 	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
 		/* Wa_22013037850 */
@@ -3058,16 +3060,16 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
 				DISABLE_128B_EVICTION_COMMAND_UDW);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
+	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0) ||
 	    IS_PONTEVECCHIO(i915) ||
 	    IS_DG2(i915)) {
 		/* Wa_22014226127 */
 		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
 	}
 
-	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
+	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0) ||
 	    IS_DG2(i915)) {
 		/* Wa_18017747507 */
 		wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 1e532981f74e..c733d43816f4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
 		flags |= GUC_WA_GAM_CREDITS;
 
 	/* Wa_14014475959 */
-	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
+	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
 	    IS_DG2(gt->i915))
 		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 1bd5d8f7c40b..01d6534dc7e8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4265,7 +4265,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
 
 	/* Wa_14014475959:dg2 */
 	if (engine->class == COMPUTE_CLASS)
-		if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+		if (IS_GT_IP_STEP(GFX, engine->gt, IP_VER(12, 70), A0, B0) ||
 		    IS_DG2(engine->i915))
 			engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6bb825d40451..687745550355 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -436,6 +436,9 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
 #define __GT_VER_FULL(gt) (__IS_MEDIA_GT(gt) ? \
 			   MEDIA_VER_FULL((gt)->i915) : \
 			   GRAPHICS_VER_FULL((gt)->i915))
+#define __GT_STEP(gt) (__IS_MEDIA_GT(gt) ? \
+		       INTEL_MEDIA_STEP((gt)->i915) : \
+		       INTEL_GRAPHICS_STEP((gt)->i915))
 
 /*
  * Check that a GT contains IP of the specified type and within the specified
@@ -454,6 +457,29 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
 	 __GT_VER_FULL(gt) >= (from) && \
 	 __GT_VER_FULL(gt) <= (until)))
 
+/*
+ * Check whether a GT contains the specific IP version and a stepping within
+ * the specified range [from, until).  The lower stepping bound is inclusive,
+ * the upper bound is exclusive (corresponding to the first hardware stepping
+ * at when the workaround is no longer needed).  E.g.,
+ *
+ *    IS_GT_IP_STEP(GFX, IP_VER(12, 70), A0, B0)
+ *    IS_GT_IP_STEP(MEDIA, IP_VER(13, 00), B1, D0)
+ *    IS_GT_IP_STEP(GFX, IP_VER(12, 71), B1, FOREVER)
+ *
+ * "FOREVER" can be passed as the upper stepping bound for workarounds that
+ * have no upper bound on steppings of the specified IP version.
+ *
+ * Note that media version checks with this macro will only work on platforms
+ * with standalone media design (i.e., media version 13 and higher).
+ */
+#define IS_GT_IP_STEP(type, gt, ipver, since, until) \
+	(BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
+	 (__IS_##type##_GT(gt) && \
+	  __GT_VER_FULL(gt) == ipver && \
+	  __GT_STEP(gt) >= STEP_##since && \
+	  __GT_STEP(gt) <= STEP_##until))
+
 #define MEDIA_VER(i915)			(RUNTIME_INFO(i915)->media.ip.ver)
 #define MEDIA_VER_FULL(i915)		IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
 					       RUNTIME_INFO(i915)->media.ip.rel)
@@ -710,10 +736,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
 	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
 
-#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
-	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
-	 IS_GRAPHICS_STEP(__i915, since, until))
-
 #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
 	(IS_METEORLAKE(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))
-- 
2.41.0

[Intel-gfx] [PATCH v2 5/9] drm/i915: Eliminate IS_MTL_MEDIA_STEP

[Matt Roper]

Stepping-specific media behavior shouldn't be tied to MTL as a platform,
but rather specifically to the Xe_LPM+ IP.  Future non-MTL platforms may
re-use this IP and will need to follow the exact same logic and apply
the same workarounds.  IS_MTL_MEDIA_STEP() is dropped in favor of
IS_GT_IP_STEP, which checks the media IP version associated with a
specific IP and also ensures that we're operating on the media GT, not
the primary GT.

v2:
 - Switch to the IS_GT_IP_STEP macro.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_rc6.c |  3 +--
 drivers/gpu/drm/i915/i915_drv.h     |  4 ----
 drivers/gpu/drm/i915/i915_perf.c    | 15 ++++-----------
 3 files changed, 5 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 58bb1c55294c..721006fc80e5 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -526,8 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
 		return false;
 	}
 
-	if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
-	    gt->type == GT_MEDIA) {
+	if (IS_GT_IP_STEP(MEDIA, gt, IP_VER(13, 0), A0, B0)) {
 		drm_notice(&i915->drm,
 			   "Media RC6 disabled on A step\n");
 		return false;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 687745550355..a417aa3e0202 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -740,10 +740,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	(IS_METEORLAKE(__i915) && \
 	 IS_DISPLAY_STEP(__i915, since, until))
 
-#define IS_MTL_MEDIA_STEP(__i915, since, until) \
-	(IS_METEORLAKE(__i915) && \
-	 IS_MEDIA_STEP(__i915, since, until))
-
 /*
  * DG2 hardware steppings are a bit unusual.  The hardware design was forked to
  * create three variants (G10, G11, and G12) which each have distinct
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 04bc1f4a1115..980e99e24d18 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4223,7 +4223,7 @@ static int read_properties_unlocked(struct i915_perf *perf,
 	 * C6 disable in BIOS. Fail if Media C6 is enabled on steppings where OAM
 	 * does not work as expected.
 	 */
-	if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
+	if (IS_GT_IP_STEP(MEDIA, props->engine->gt, IP_VER(13, 0), A0, C0) &&
 	    props->engine->oa_group->type == TYPE_OAM &&
 	    intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
 		drm_dbg(&perf->i915->drm,
@@ -5332,16 +5332,9 @@ int i915_perf_ioctl_version(struct drm_i915_private *i915)
 	 * C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
 	 * to indicate that OA media is not supported.
 	 */
-	if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
-		struct intel_gt *gt;
-		int i;
-
-		for_each_gt(gt, i915, i) {
-			if (gt->type == GT_MEDIA &&
-			    intel_check_bios_c6_setup(&gt->rc6))
-				return 6;
-		}
-	}
+	if (IS_GT_IP_STEP(MEDIA, i915->media_gt, IP_VER(13, 0), A0, C0) &&
+	    intel_check_bios_c6_setup(&i915->media_gt->rc6))
+		return 6;
 
 	return 7;
 }
-- 
2.41.0

[Intel-gfx] [PATCH v2 6/9] drm/i915: Eliminate IS_MTL_DISPLAY_STEP

[Matt Roper]

Stepping-specific display behavior shouldn't be tied to MTL as a
platform, but rather specifically to the Xe_LPD+ IP.  Future non-MTL
platforms may re-use this IP and will need to follow the exact same
logic and apply the same workarounds.  IS_MTL_DISPLAY_STEP() is dropped
in favor of a new macro IS_DISPLAY_IP_STEP() that only checks the
display IP version.

v2:
 - Rename macro to IS_DISPLAY_IP_STEP for consistency with the
   corresponding GT macro and handle steppings the same way.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 .../gpu/drm/i915/display/intel_display_device.h | 17 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_fbc.c        |  3 ++-
 drivers/gpu/drm/i915/display/intel_pmdemand.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c        | 10 +++++-----
 drivers/gpu/drm/i915/i915_drv.h                 |  6 ++----
 5 files changed, 27 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 3324bd453ca7..383bddf032d7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -71,6 +71,23 @@ struct drm_printer;
 #define OVERLAY_NEEDS_PHYSICAL(i915)	(DISPLAY_INFO(i915)->overlay_needs_physical)
 #define SUPPORTS_TV(i915)		(DISPLAY_INFO(i915)->supports_tv)
 
+/*
+ * Check if a device has a specific IP version as well as a stepping within
+ * the specified range [from, until).  The lower bound is inclusive, the upper
+ * bound is exclusive (corresponding to the first hardware stepping when the
+ * workaround is no longer needed).  E.g.,
+ *
+ *    IS_DISPLAY_IP_STEP(GFX, IP_VER(14, 0), A0, B2)
+ *    IS_DISPLAY_IP_STEP(GFX, IP_VER(14, 0), C0, FOREVER)
+ *
+ * "FOREVER" can be passed as the upper stepping bound for workarounds that
+ * have no upper bound on steppings of the specified IP version.
+ */
+#define IS_DISPLAY_IP_STEP(__i915, ipver, since, until) \
+	(BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
+	 DISPLAY_VER_FULL(__i915) == (ipver) && \
+	 IS_DISPLAY_STEP(__i915, STEP_##since, STEP_##until))
+
 struct intel_display_runtime_info {
 	struct {
 		u16 ver;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7f8b2d7713c7..f29c3b921f31 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -49,6 +49,7 @@
 #include "i915_vgpu.h"
 #include "intel_cdclk.h"
 #include "intel_de.h"
+#include "intel_display_device.h"
 #include "intel_display_trace.h"
 #include "intel_display_types.h"
 #include "intel_fbc.h"
@@ -1093,7 +1094,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
 
 	/* Wa_14016291713 */
 	if ((IS_DISPLAY_VER(i915, 12, 13) ||
-	     IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
+	     IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), A0, C0)) &&
 	    crtc_state->has_psr) {
 		plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
 		return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index f7608d363634..296ab6dfd947 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
 				     &pmdemand_state->base,
 				     &intel_pmdemand_funcs);
 
-	if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
+	if (IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), A0, C0))
 		/* Wa_14016740474 */
 		intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 04ab034a8d57..839c52939fa7 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1360,7 +1360,7 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
 	bool set_wa_bit = false;
 
 	/* Wa_14015648006 */
-	if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+	if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), A0, B0) ||
 	    IS_DISPLAY_VER(dev_priv, 11, 13))
 		set_wa_bit |= crtc_state->wm_level_disabled;
 
@@ -1447,7 +1447,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 		 * All supported adlp panels have 1-based X granularity, this may
 		 * cause issues if non-supported panels are used.
 		 */
-		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+		if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), A0, B0))
 			intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 0,
 				     ADLP_1_BASED_X_GRANULARITY);
 		else if (IS_ALDERLAKE_P(dev_priv))
@@ -1455,7 +1455,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 				     ADLP_1_BASED_X_GRANULARITY);
 
 		/* Wa_16012604467:adlp,mtl[a0,b0] */
-		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+		if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), A0, B0))
 			intel_de_rmw(dev_priv,
 				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
 				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
@@ -1613,7 +1613,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 
 	if (intel_dp->psr.psr2_enabled) {
 		/* Wa_16012604467:adlp,mtl[a0,b0] */
-		if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+		if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), A0, B0))
 			intel_de_rmw(dev_priv,
 				     MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
 				     MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
@@ -2087,7 +2087,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 		goto skip_sel_fetch_set_loop;
 
 	/* Wa_14014971492 */
-	if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+	if ((IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), A0, B0) ||
 	     IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
 	    crtc_state->splitter.enable)
 		pipe_clip.y1 = 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a417aa3e0202..459a013f0a99 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -487,6 +487,8 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
 	(MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
 
 #define DISPLAY_VER(i915)	(DISPLAY_RUNTIME_INFO(i915)->ip.ver)
+#define DISPLAY_VER_FULL(i915)	IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \
+				       DISPLAY_RUNTIME_INFO(i915)->ip.rel)
 #define IS_DISPLAY_VER(i915, from, until) \
 	(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
 
@@ -736,10 +738,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
 	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
 
-#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
-	(IS_METEORLAKE(__i915) && \
-	 IS_DISPLAY_STEP(__i915, since, until))
-
 /*
  * DG2 hardware steppings are a bit unusual.  The hardware design was forked to
  * create three variants (G10, G11, and G12) which each have distinct
-- 
2.41.0

[Intel-gfx] [PATCH v2 7/9] drm/i915/mtl: Eliminate subplatforms

[Matt Roper]

Now that we properly match the Xe_LPG IP versions associated with
various workarounds, there's no longer any need to define separate MTL
subplatform in the driver.  Nothing in the code is conditional on MTL-M
or MTL-P base platforms.  Furthermore, I'm not sure the "M" and "P"
designations are even an accurate representation of which specific
platforms would have which IP versions; those were mostly just
placeholders from a long time ago.  The reality is that the IP version
present on a platform gets read from a fuse register at driver init; we
shouldn't be trying to guess which IP is present based on PCI ID
anymore.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          |  4 ----
 drivers/gpu/drm/i915/intel_device_info.c | 14 --------------
 drivers/gpu/drm/i915/intel_device_info.h |  4 ----
 include/drm/i915_pciids.h                | 11 +++--------
 4 files changed, 3 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 459a013f0a99..88082fb938a2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -625,10 +625,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
 #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
 
-#define IS_METEORLAKE_M(i915) \
-	IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
-#define IS_METEORLAKE_P(i915) \
-	IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
 #define IS_DG2_G10(i915) \
 	IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
 #define IS_DG2_G11(i915) \
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index ea0ec6174ce5..9dfa680a4c62 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -206,14 +206,6 @@ static const u16 subplatform_g12_ids[] = {
 	INTEL_DG2_G12_IDS(0),
 };
 
-static const u16 subplatform_m_ids[] = {
-	INTEL_MTL_M_IDS(0),
-};
-
-static const u16 subplatform_p_ids[] = {
-	INTEL_MTL_P_IDS(0),
-};
-
 static bool find_devid(u16 id, const u16 *p, unsigned int num)
 {
 	for (; num; num--, p++) {
@@ -275,12 +267,6 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
 	} else if (find_devid(devid, subplatform_g12_ids,
 			      ARRAY_SIZE(subplatform_g12_ids))) {
 		mask = BIT(INTEL_SUBPLATFORM_G12);
-	} else if (find_devid(devid, subplatform_m_ids,
-			      ARRAY_SIZE(subplatform_m_ids))) {
-		mask = BIT(INTEL_SUBPLATFORM_M);
-	} else if (find_devid(devid, subplatform_p_ids,
-			      ARRAY_SIZE(subplatform_p_ids))) {
-		mask = BIT(INTEL_SUBPLATFORM_P);
 	}
 
 	GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index dbfe6443457b..2ca54417d19b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -129,10 +129,6 @@ enum intel_platform {
 #define INTEL_SUBPLATFORM_N    1
 #define INTEL_SUBPLATFORM_RPLU  2
 
-/* MTL */
-#define INTEL_SUBPLATFORM_M	0
-#define INTEL_SUBPLATFORM_P	1
-
 enum intel_ppgtt_type {
 	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
 	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index e1e10dfbb661..38dae757d1a8 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -738,18 +738,13 @@
 #define INTEL_ATS_M_IDS(info) \
 	INTEL_ATS_M150_IDS(info), \
 	INTEL_ATS_M75_IDS(info)
+
 /* MTL */
-#define INTEL_MTL_M_IDS(info) \
+#define INTEL_MTL_IDS(info) \
 	INTEL_VGA_DEVICE(0x7D40, info), \
-	INTEL_VGA_DEVICE(0x7D60, info)
-
-#define INTEL_MTL_P_IDS(info) \
 	INTEL_VGA_DEVICE(0x7D45, info), \
 	INTEL_VGA_DEVICE(0x7D55, info), \
+	INTEL_VGA_DEVICE(0x7D60, info), \
 	INTEL_VGA_DEVICE(0x7DD5, info)
 
-#define INTEL_MTL_IDS(info) \
-	INTEL_MTL_M_IDS(info), \
-	INTEL_MTL_P_IDS(info)
-
 #endif /* _I915_PCIIDS_H */
-- 
2.41.0

[Intel-gfx] [PATCH v2 8/9] drm/i915/display: Eliminate IS_METEORLAKE checks

[Matt Roper]

Most of the IS_METEORLAKE checks in the display code shouldn't actually
be tied to MTL as a platform, but rather to the Xe_LPD+ display IP
(which is used in MTL, but may show up again in future platforms).  In
cases where we're trying to match that specific IP, use a version check
against IP_VER(14, 0).  For cases where we're just handling new behavior
introduced by this IP (but which may also be inherited by future IP as
well), use a ver >= 14 check.

The one exception here is the stolen memory workaround Wa_13010847436
(which is mislabelled as "Wa_22018444074" in the code).  That's truly a
MTL-specific issue rather than being tied to any of the IP blocks, so
leaving the condition as IS_METEORLAKE is correct there.

v2:
 - cdclk check should be >=, not >.  (Gustavo)

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c   | 4 ++--
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
 drivers/gpu/drm/i915/display/intel_display.c | 2 +-
 drivers/gpu/drm/i915/display/intel_dmc.c     | 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index dcc1f6941b60..5ec39cc15332 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1840,7 +1840,7 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
 
 static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
 {
-	return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) &&
+	return ((IS_DG2(dev_priv) || DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0)) &&
 		dev_priv->display.cdclk.hw.vco > 0 &&
 		HAS_CDCLK_SQUASH(dev_priv));
 }
@@ -3559,7 +3559,7 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
  */
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
-	if (IS_METEORLAKE(dev_priv)) {
+	if (DISPLAY_VER(dev_priv) >= 14) {
 		dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
 		dev_priv->display.cdclk.table = mtl_cdclk_table;
 	} else if (IS_DG2(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 1b00ef2c6185..a42b3c4c0ed7 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -31,7 +31,7 @@
 
 bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy)
 {
-	if (IS_METEORLAKE(i915) && (phy < PHY_C))
+	if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0) && phy < PHY_C)
 		return true;
 
 	return false;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 43cba98f7753..85efd77f491b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1767,7 +1767,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 	if (IS_DG2(dev_priv))
 		/* DG2's "TC1" output uses a SNPS PHY */
 		return false;
-	else if (IS_ALDERLAKE_P(dev_priv) || IS_METEORLAKE(dev_priv))
+	else if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0))
 		return phy >= PHY_F && phy <= PHY_I;
 	else if (IS_TIGERLAKE(dev_priv))
 		return phy >= PHY_D && phy <= PHY_I;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 5f479f3828bb..1623c0c5e8a1 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -998,7 +998,7 @@ void intel_dmc_init(struct drm_i915_private *i915)
 
 	INIT_WORK(&dmc->work, dmc_load_work_fn);
 
-	if (IS_METEORLAKE(i915)) {
+	if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) {
 		dmc->fw_path = MTL_DMC_PATH;
 		dmc->max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
 	} else if (IS_DG2(i915)) {
-- 
2.41.0

[Intel-gfx] [PATCH v2 9/9] drm/i915: Replace several IS_METEORLAKE with proper IP version checks

[Matt Roper]

Many of the IS_METEORLAKE conditions throughout the driver are supposed
to be checks for Xe_LPG and/or Xe_LPM+ IP, not for the MTL platform
specifically.  Update those checks to ensure that the code will still
operate properly if/when these IP versions show up on future platforms.

v2:
 - Add comment to i915_coherent_map_type() noting that the current
   implementation of the workaround is too broad.  (Tvrtko)

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_create.c | 4 ++--
 drivers/gpu/drm/i915/gem/i915_gem_pages.c  | 8 ++++++--
 drivers/gpu/drm/i915/gt/intel_engine_pm.c  | 2 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c        | 4 ++--
 drivers/gpu/drm/i915/gt/intel_mocs.c       | 2 +-
 drivers/gpu/drm/i915/gt/intel_reset.c      | 2 +-
 drivers/gpu/drm/i915/gt/intel_rps.c        | 2 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc.c     | 4 ++--
 drivers/gpu/drm/i915/i915_debugfs.c        | 2 +-
 drivers/gpu/drm/i915/i915_perf.c           | 8 +++++---
 10 files changed, 22 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index d24c0ce8805c..19156ba4b9ef 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -405,8 +405,8 @@ static int ext_set_pat(struct i915_user_extension __user *base, void *data)
 	BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
 		     offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd));
 
-	/* Limiting the extension only to Meteor Lake */
-	if (!IS_METEORLAKE(i915))
+	/* Limiting the extension only to Xe_LPG and beyond */
+	if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 70))
 		return -ENODEV;
 
 	if (copy_from_user(&ext, base, sizeof(ext)))
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 89fc8ea6bcfc..8c74855b6d04 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -470,9 +470,13 @@ enum i915_map_type i915_coherent_map_type(struct drm_i915_private *i915,
 					  bool always_coherent)
 {
 	/*
-	 * Wa_22016122933: always return I915_MAP_WC for MTL
+	 * Wa_22016122933: always return I915_MAP_WC for Xe_LPM+
+	 *
+	 * FIXME: The scope of this workaround is too wide right now and
+	 * is applying to objects used solely on the primary GT.  We need to
+	 * take into account which GT will be operating on the shared object.
 	 */
-	if (i915_gem_object_is_lmem(obj) || IS_METEORLAKE(i915))
+	if (i915_gem_object_is_lmem(obj) || MEDIA_VER_FULL(i915) == IP_VER(13, 0))
 		return I915_MAP_WC;
 	if (HAS_LLC(i915) || always_coherent)
 		return I915_MAP_WB;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 21af0ec52223..24060278e7a2 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -21,7 +21,7 @@ static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *i915 = engine->i915;
 
-	if (IS_METEORLAKE(i915) && engine->id == GSC0) {
+	if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) {
 		intel_uncore_write(engine->gt->uncore,
 				   RC_PSMI_CTRL_GSCCS,
 				   _MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 8057cc5800b3..4cd7f16283b0 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1095,10 +1095,10 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
 	if (IS_ERR(obj)) {
 		obj = i915_gem_object_create_shmem(engine->i915, context_size);
 		/*
-		 * Wa_22016122933: For MTL the shared memory needs to be mapped
+		 * Wa_22016122933: For Xe_LPM+ the shared memory needs to be mapped
 		 * as WC on CPU side and UC (PAT index 2) on GPU side
 		 */
-		if (IS_METEORLAKE(engine->i915))
+		if (MEDIA_VER_FULL(engine->i915) == IP_VER(13, 0))
 			i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
 	}
 	if (IS_ERR(obj))
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 2c014407225c..393bac84a175 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -507,7 +507,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
 	memset(table, 0, sizeof(struct drm_i915_mocs_table));
 
 	table->unused_entries_index = I915_MOCS_PTE;
-	if (IS_METEORLAKE(i915)) {
+	if (IS_GT_IP_RANGE(GFX, &i915->gt0, IP_VER(12, 70), IP_VER(12, 71))) {
 		table->size = ARRAY_SIZE(mtl_mocs_table);
 		table->table = mtl_mocs_table;
 		table->n_entries = MTL_NUM_MOCS_ENTRIES;
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index efe83157ef78..56960d602d45 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -705,7 +705,7 @@ static int __reset_guc(struct intel_gt *gt)
 
 static bool needs_wa_14015076503(struct intel_gt *gt, intel_engine_mask_t engine_mask)
 {
-	if (!IS_METEORLAKE(gt->i915) || !HAS_ENGINE(gt, GSC0))
+	if (MEDIA_VER_FULL(gt->i915) != IP_VER(13, 0) || !HAS_ENGINE(gt, GSC0))
 		return false;
 
 	if (!__HAS_ENGINE(engine_mask, GSC0))
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 092542f53aad..4feef874e6d6 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1161,7 +1161,7 @@ void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *c
 {
 	struct drm_i915_private *i915 = rps_to_i915(rps);
 
-	if (IS_METEORLAKE(i915))
+	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
 		return mtl_get_freq_caps(rps, caps);
 	else
 		return __gen6_rps_get_freq_caps(rps, caps);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index c733d43816f4..1d917ef8825d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -743,10 +743,10 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
 		return ERR_CAST(obj);
 
 	/*
-	 * Wa_22016122933: For MTL the shared memory needs to be mapped
+	 * Wa_22016122933: For Xe_LPM+ the shared memory needs to be mapped
 	 * as WC on CPU side and UC (PAT index 2) on GPU side
 	 */
-	if (IS_METEORLAKE(gt->i915))
+	if (MEDIA_VER_FULL(gt->i915) == IP_VER(13, 0))
 		i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
 
 	vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 4de44cf1026d..df688a95a312 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -144,7 +144,7 @@ static const char *i915_cache_level_str(struct drm_i915_gem_object *obj)
 {
 	struct drm_i915_private *i915 = obj_to_i915(obj);
 
-	if (IS_METEORLAKE(i915)) {
+	if (IS_GT_IP_RANGE(GFX, to_gt(i915), IP_VER(12, 70), IP_VER(12, 71))) {
 		switch (obj->pat_index) {
 		case 0: return " WB";
 		case 1: return " WT";
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 980e99e24d18..278ec8dc533e 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3227,11 +3227,13 @@ get_sseu_config(struct intel_sseu *out_sseu,
  */
 u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
 {
+	struct intel_gt *gt = to_gt(i915);
+
 	/*
 	 * Wa_18013179988:dg2
-	 * Wa_14015846243:mtl
+	 * Wa_14015846243:xelpg
 	 */
-	if (IS_DG2(i915) || IS_METEORLAKE(i915)) {
+	if (IS_DG2(i915) || IS_GT_IP_RANGE(GFX, gt, IP_VER(12, 70), IP_VER(12, 71))) {
 		intel_wakeref_t wakeref;
 		u32 reg, shift;
 
@@ -4539,7 +4541,7 @@ static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
 
 static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
 {
-	if (IS_METEORLAKE(perf->i915))
+	if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 70))
 		return reg_in_range_table(addr, mtl_oa_mux_regs);
 	else
 		return reg_in_range_table(addr, gen12_oa_mux_regs);
-- 
2.41.0

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Reduce MTL-specific platform checks (rev2)

[Patchwork]

== Series Details ==

Series: Reduce MTL-specific platform checks (rev2)
URL   : https://patchwork.freedesktop.org/series/120943/
State : warning

== Summary ==

Error: dim checkpatch failed
270297a58c66 drm/i915: Consolidate condition for Wa_22011802037
e464ca89ccdb drm/i915/xelpmp: Don't assume workarounds extend to future platforms
6766e7143d29 drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version
-:153: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'gt' - possible side-effects?
#153: FILE: drivers/gpu/drm/i915/i915_drv.h:436:
+#define __GT_VER_FULL(gt) (__IS_MEDIA_GT(gt) ? \
+			   MEDIA_VER_FULL((gt)->i915) : \
+			   GRAPHICS_VER_FULL((gt)->i915))

-:167: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'gt' - possible side-effects?
#167: FILE: drivers/gpu/drm/i915/i915_drv.h:450:
+#define IS_GT_IP_RANGE(type, gt, from, until) ( \
+	BUILD_BUG_ON_ZERO(from < IP_VER(2, 0)) + \
+	BUILD_BUG_ON_ZERO(until < from) + \
+	(__IS_##type##_GT(gt) && \
+	 __GT_VER_FULL(gt) >= (from) && \
+	 __GT_VER_FULL(gt) <= (until)))

-:167: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'from' - possible side-effects?
#167: FILE: drivers/gpu/drm/i915/i915_drv.h:450:
+#define IS_GT_IP_RANGE(type, gt, from, until) ( \
+	BUILD_BUG_ON_ZERO(from < IP_VER(2, 0)) + \
+	BUILD_BUG_ON_ZERO(until < from) + \
+	(__IS_##type##_GT(gt) && \
+	 __GT_VER_FULL(gt) >= (from) && \
+	 __GT_VER_FULL(gt) <= (until)))

-:167: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'from' may be better as '(from)' to avoid precedence issues
#167: FILE: drivers/gpu/drm/i915/i915_drv.h:450:
+#define IS_GT_IP_RANGE(type, gt, from, until) ( \
+	BUILD_BUG_ON_ZERO(from < IP_VER(2, 0)) + \
+	BUILD_BUG_ON_ZERO(until < from) + \
+	(__IS_##type##_GT(gt) && \
+	 __GT_VER_FULL(gt) >= (from) && \
+	 __GT_VER_FULL(gt) <= (until)))

-:167: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'until' - possible side-effects?
#167: FILE: drivers/gpu/drm/i915/i915_drv.h:450:
+#define IS_GT_IP_RANGE(type, gt, from, until) ( \
+	BUILD_BUG_ON_ZERO(from < IP_VER(2, 0)) + \
+	BUILD_BUG_ON_ZERO(until < from) + \
+	(__IS_##type##_GT(gt) && \
+	 __GT_VER_FULL(gt) >= (from) && \
+	 __GT_VER_FULL(gt) <= (until)))

-:167: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'until' may be better as '(until)' to avoid precedence issues
#167: FILE: drivers/gpu/drm/i915/i915_drv.h:450:
+#define IS_GT_IP_RANGE(type, gt, from, until) ( \
+	BUILD_BUG_ON_ZERO(from < IP_VER(2, 0)) + \
+	BUILD_BUG_ON_ZERO(until < from) + \
+	(__IS_##type##_GT(gt) && \
+	 __GT_VER_FULL(gt) >= (from) && \
+	 __GT_VER_FULL(gt) <= (until)))

total: 0 errors, 0 warnings, 6 checks, 126 lines checked
3bc429e68faa drm/i915: Eliminate IS_MTL_GRAPHICS_STEP
-:296: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'gt' - possible side-effects?
#296: FILE: drivers/gpu/drm/i915/i915_drv.h:439:
+#define __GT_STEP(gt) (__IS_MEDIA_GT(gt) ? \
+		       INTEL_MEDIA_STEP((gt)->i915) : \
+		       INTEL_GRAPHICS_STEP((gt)->i915))

-:322: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'gt' - possible side-effects?
#322: FILE: drivers/gpu/drm/i915/i915_drv.h:476:
+#define IS_GT_IP_STEP(type, gt, ipver, since, until) \
+	(BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
+	 (__IS_##type##_GT(gt) && \
+	  __GT_VER_FULL(gt) == ipver && \
+	  __GT_STEP(gt) >= STEP_##since && \
+	  __GT_STEP(gt) <= STEP_##until))

-:322: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ipver' - possible side-effects?
#322: FILE: drivers/gpu/drm/i915/i915_drv.h:476:
+#define IS_GT_IP_STEP(type, gt, ipver, since, until) \
+	(BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
+	 (__IS_##type##_GT(gt) && \
+	  __GT_VER_FULL(gt) == ipver && \
+	  __GT_STEP(gt) >= STEP_##since && \
+	  __GT_STEP(gt) <= STEP_##until))

-:322: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'ipver' may be better as '(ipver)' to avoid precedence issues
#322: FILE: drivers/gpu/drm/i915/i915_drv.h:476:
+#define IS_GT_IP_STEP(type, gt, ipver, since, until) \
+	(BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
+	 (__IS_##type##_GT(gt) && \
+	  __GT_VER_FULL(gt) == ipver && \
+	  __GT_STEP(gt) >= STEP_##since && \
+	  __GT_STEP(gt) <= STEP_##until))

total: 0 errors, 0 warnings, 4 checks, 261 lines checked
4802115c5e0b drm/i915: Eliminate IS_MTL_MEDIA_STEP
3f13ddca72c4 drm/i915: Eliminate IS_MTL_DISPLAY_STEP
-:39: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects?
#39: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:86:
+#define IS_DISPLAY_IP_STEP(__i915, ipver, since, until) \
+	(BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
+	 DISPLAY_VER_FULL(__i915) == (ipver) && \
+	 IS_DISPLAY_STEP(__i915, STEP_##since, STEP_##until))

-:39: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ipver' - possible side-effects?
#39: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:86:
+#define IS_DISPLAY_IP_STEP(__i915, ipver, since, until) \
+	(BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
+	 DISPLAY_VER_FULL(__i915) == (ipver) && \
+	 IS_DISPLAY_STEP(__i915, STEP_##since, STEP_##until))

-:39: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'ipver' may be better as '(ipver)' to avoid precedence issues
#39: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:86:
+#define IS_DISPLAY_IP_STEP(__i915, ipver, since, until) \
+	(BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
+	 DISPLAY_VER_FULL(__i915) == (ipver) && \
+	 IS_DISPLAY_STEP(__i915, STEP_##since, STEP_##until))

-:138: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#138: FILE: drivers/gpu/drm/i915/i915_drv.h:490:
+#define DISPLAY_VER_FULL(i915)	IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \
+				       DISPLAY_RUNTIME_INFO(i915)->ip.rel)

total: 0 errors, 0 warnings, 4 checks, 104 lines checked
3fd78ec5b343 drm/i915/mtl: Eliminate subplatforms
-:94: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#94: FILE: include/drm/i915_pciids.h:743:
+#define INTEL_MTL_IDS(info) \
 	INTEL_VGA_DEVICE(0x7D40, info), \
 	INTEL_VGA_DEVICE(0x7D45, info), \
 	INTEL_VGA_DEVICE(0x7D55, info), \
+	INTEL_VGA_DEVICE(0x7D60, info), \
 	INTEL_VGA_DEVICE(0x7DD5, info)

-:94: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#94: FILE: include/drm/i915_pciids.h:743:
+#define INTEL_MTL_IDS(info) \
 	INTEL_VGA_DEVICE(0x7D40, info), \
 	INTEL_VGA_DEVICE(0x7D45, info), \
 	INTEL_VGA_DEVICE(0x7D55, info), \
+	INTEL_VGA_DEVICE(0x7D60, info), \
 	INTEL_VGA_DEVICE(0x7DD5, info)

total: 1 errors, 0 warnings, 1 checks, 67 lines checked
03c39d0914ba drm/i915/display: Eliminate IS_METEORLAKE checks
172d8c4c6884 drm/i915: Replace several IS_METEORLAKE with proper IP version checks

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Reduce MTL-specific platform checks (rev2)

[Patchwork]

== Series Details ==

Series: Reduce MTL-specific platform checks (rev2)
URL   : https://patchwork.freedesktop.org/series/120943/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✓ Fi.CI.BAT: success for Reduce MTL-specific platform checks (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 7490 bytes --]

== Series Details ==

Series: Reduce MTL-specific platform checks (rev2)
URL   : https://patchwork.freedesktop.org/series/120943/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13418 -> Patchwork_120943v2
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/index.html

Participating hosts (41 -> 42)
------------------------------

  Additional (1): fi-kbl-soraka 

Known issues
------------

  Here are the changes found in Patchwork_120943v2 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@basic:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-tgl-1115g4:      [PASS][3] -> [FAIL][4] ([i915#7940])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/fi-tgl-1115g4/igt@i915_pm_rpm@basic-pci-d3-state.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/fi-tgl-1115g4/igt@i915_pm_rpm@basic-pci-d3-state.html
    - fi-skl-guc:         [PASS][5] -> [FAIL][6] ([i915#7940])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/fi-skl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/fi-skl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_pm_rpm@basic-rte:
    - fi-cfl-guc:         [PASS][7] -> [FAIL][8] ([i915#7940])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/fi-cfl-guc/igt@i915_pm_rpm@basic-rte.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/fi-cfl-guc/igt@i915_pm_rpm@basic-rte.html

  * igt@i915_selftest@live@gt_pm:
    - fi-kbl-soraka:      NOTRUN -> [DMESG-FAIL][9] ([i915#1886] / [i915#7913])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@requests:
    - bat-rpls-1:         [PASS][10] -> [ABORT][11] ([i915#4983] / [i915#7911] / [i915#7920])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/bat-rpls-1/igt@i915_selftest@live@requests.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/bat-rpls-1/igt@i915_selftest@live@requests.html

  * igt@i915_selftest@live@reset:
    - bat-rpls-2:         NOTRUN -> [ABORT][12] ([i915#7461] / [i915#7913] / [i915#7981] / [i915#8347])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/bat-rpls-2/igt@i915_selftest@live@reset.html

  * igt@i915_selftest@live@slpc:
    - bat-mtlp-6:         [PASS][13] -> [DMESG-WARN][14] ([i915#6367])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/bat-mtlp-6/igt@i915_selftest@live@slpc.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/bat-mtlp-6/igt@i915_selftest@live@slpc.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][15] ([fdo#109271]) +15 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/fi-kbl-soraka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
    - bat-rplp-1:         [PASS][16] -> [ABORT][17] ([i915#8442] / [i915#8668])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@requests:
    - bat-rpls-2:         [ABORT][18] ([i915#4983] / [i915#7913]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/bat-rpls-2/igt@i915_selftest@live@requests.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/bat-rpls-2/igt@i915_selftest@live@requests.html

  
#### Warnings ####

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-cfl-guc:         [FAIL][20] ([i915#7940]) -> [FAIL][21] ([i915#7691])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/fi-cfl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/fi-cfl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_pm_rpm@basic-rte:
    - fi-kbl-8809g:       [FAIL][22] ([i915#8843]) -> [FAIL][23] ([i915#7940])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/fi-kbl-8809g/igt@i915_pm_rpm@basic-rte.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/fi-kbl-8809g/igt@i915_pm_rpm@basic-rte.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
  [i915#7691]: https://gitlab.freedesktop.org/drm/intel/issues/7691
  [i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
  [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
  [i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
  [i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
  [i915#7981]: https://gitlab.freedesktop.org/drm/intel/issues/7981
  [i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
  [i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
  [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
  [i915#8843]: https://gitlab.freedesktop.org/drm/intel/issues/8843


Build changes
-------------

  * Linux: CI_DRM_13418 -> Patchwork_120943v2

  CI-20190529: 20190529
  CI_DRM_13418: e31a5b300385ef52e6db1cda820518cb2da089ca @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7401: 0c66a6560eda687effa9088659577a520d913908 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_120943v2: e31a5b300385ef52e6db1cda820518cb2da089ca @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

79c68c569972 drm/i915: Replace several IS_METEORLAKE with proper IP version checks
5726f287171a drm/i915/display: Eliminate IS_METEORLAKE checks
6b3b182fdde8 drm/i915/mtl: Eliminate subplatforms
040868e0c494 drm/i915: Eliminate IS_MTL_DISPLAY_STEP
fd057242273a drm/i915: Eliminate IS_MTL_MEDIA_STEP
a74d8c178684 drm/i915: Eliminate IS_MTL_GRAPHICS_STEP
da28edffda4f drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version
477b9fb2f8c5 drm/i915/xelpmp: Don't assume workarounds extend to future platforms
617398c13f56 drm/i915: Consolidate condition for Wa_22011802037

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/index.html

[-- Attachment #2: Type: text/html, Size: 9066 bytes --]

Re: [Intel-gfx] [PATCH v2 1/9] drm/i915: Consolidate condition for Wa_22011802037

[Andi Shyti]

Hi Matt,

> +/*
> + * Wa_22011802037 requires that we (or the GuC) ensure that no command
> + * streamers are executing MI_FORCE_WAKE while an engine reset is initiated.
> + */
> +bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)

I've seen this format in a recent Jonathan's patch and I see it
becoming a pattern in the future. Should we already agree on the
naming? Would intel_needs_wa_22011802037() be sufficient? Or a
prefix as intel_wa_* for all the similar functions?

Andi

> +{
> +	if (GRAPHICS_VER(gt->i915) < 11)
> +		return false;
> +
> +	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
> +		return true;
> +
> +	if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
> +		return false;
> +
> +	return true;
> +}

Re: [Intel-gfx] [PATCH v2 2/9] drm/i915/xelpmp: Don't assume workarounds extend to future platforms

[Andi Shyti]

Hi Matt,

On Mon, Jul 24, 2023 at 05:13:15PM -0700, Matt Roper wrote:
> The currently implemented Xe_LPM+ workarounds are specific to media
> version 13.00.  When new IP versions show up in the future, they'll need
> their own workaround lists.

Makes sense...

Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> 

Andi

> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

[Intel-gfx] ✗ Fi.CI.IGT: failure for Reduce MTL-specific platform checks (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 49484 bytes --]

== Series Details ==

Series: Reduce MTL-specific platform checks (rev2)
URL   : https://patchwork.freedesktop.org/series/120943/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13418_full -> Patchwork_120943v2_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_120943v2_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_120943v2_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_120943v2_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_whisper@basic-contexts-forked-all:
    - shard-mtlp:         [PASS][1] -> [TIMEOUT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-mtlp-2/igt@gem_exec_whisper@basic-contexts-forked-all.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-2/igt@gem_exec_whisper@basic-contexts-forked-all.html

  * igt@kms_cursor_crc@cursor-random-128x42@pipe-a-edp-1:
    - shard-mtlp:         [PASS][3] -> [ABORT][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-mtlp-1/igt@kms_cursor_crc@cursor-random-128x42@pipe-a-edp-1.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-6/igt@kms_cursor_crc@cursor-random-128x42@pipe-a-edp-1.html

  * igt@kms_flip@bo-too-big@b-vga1:
    - shard-snb:          [PASS][5] -> [ABORT][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-snb6/igt@kms_flip@bo-too-big@b-vga1.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-snb7/igt@kms_flip@bo-too-big@b-vga1.html

  * igt@perf@gen12-invalid-class-instance:
    - shard-apl:          [PASS][7] -> [ABORT][8] +12 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-apl3/igt@perf@gen12-invalid-class-instance.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-apl4/igt@perf@gen12-invalid-class-instance.html

  * igt@perf@gen12-mi-rpc@rcs0:
    - shard-rkl:          [PASS][9] -> [ABORT][10] +16 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-rkl-6/igt@perf@gen12-mi-rpc@rcs0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-rkl-2/igt@perf@gen12-mi-rpc@rcs0.html

  * igt@perf@global-sseu-config:
    - shard-tglu:         NOTRUN -> [ABORT][11]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-tglu-7/igt@perf@global-sseu-config.html
    - shard-apl:          NOTRUN -> [ABORT][12]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-apl6/igt@perf@global-sseu-config.html
    - shard-glk:          NOTRUN -> [ABORT][13]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-glk2/igt@perf@global-sseu-config.html
    - shard-rkl:          NOTRUN -> [ABORT][14]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-rkl-2/igt@perf@global-sseu-config.html

  * igt@perf@missing-sample-flags:
    - shard-tglu:         [PASS][15] -> [ABORT][16] +16 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-tglu-3/igt@perf@missing-sample-flags.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-tglu-9/igt@perf@missing-sample-flags.html

  * igt@perf@non-system-wide-paranoid:
    - shard-dg2:          [PASS][17] -> [ABORT][18] +14 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-dg2-7/igt@perf@non-system-wide-paranoid.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@perf@non-system-wide-paranoid.html

  * igt@perf@non-zero-reason@0-rcs0:
    - shard-glk:          [PASS][19] -> [ABORT][20] +12 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-glk5/igt@perf@non-zero-reason@0-rcs0.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-glk1/igt@perf@non-zero-reason@0-rcs0.html

  * igt@perf@oa-exponents@0-rcs0:
    - shard-apl:          [PASS][21] -> [INCOMPLETE][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-apl3/igt@perf@oa-exponents@0-rcs0.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-apl3/igt@perf@oa-exponents@0-rcs0.html
    - shard-glk:          [PASS][23] -> [INCOMPLETE][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-glk9/igt@perf@oa-exponents@0-rcs0.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-glk7/igt@perf@oa-exponents@0-rcs0.html
    - shard-dg2:          [PASS][25] -> [INCOMPLETE][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-dg2-5/igt@perf@oa-exponents@0-rcs0.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-7/igt@perf@oa-exponents@0-rcs0.html
    - shard-rkl:          [PASS][27] -> [INCOMPLETE][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-rkl-7/igt@perf@oa-exponents@0-rcs0.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-rkl-7/igt@perf@oa-exponents@0-rcs0.html
    - shard-tglu:         [PASS][29] -> [INCOMPLETE][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-tglu-5/igt@perf@oa-exponents@0-rcs0.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-tglu-9/igt@perf@oa-exponents@0-rcs0.html

  
#### Warnings ####

  * igt@perf@gen12-mi-rpc:
    - shard-glk:          [SKIP][31] ([fdo#109271]) -> [ABORT][32] +5 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-glk6/igt@perf@gen12-mi-rpc.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-glk9/igt@perf@gen12-mi-rpc.html

  * igt@perf@gen12-oa-tlb-invalidate:
    - shard-apl:          [SKIP][33] ([fdo#109271]) -> [ABORT][34] +5 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-apl6/igt@perf@gen12-oa-tlb-invalidate.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-apl1/igt@perf@gen12-oa-tlb-invalidate.html

  * igt@perf@global-sseu-config:
    - shard-dg2:          [SKIP][35] ([i915#7387]) -> [ABORT][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-dg2-3/igt@perf@global-sseu-config.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-7/igt@perf@global-sseu-config.html

  * igt@perf@mi-rpc:
    - shard-dg2:          [SKIP][37] ([i915#2434]) -> [ABORT][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-dg2-11/igt@perf@mi-rpc.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-5/igt@perf@mi-rpc.html
    - shard-rkl:          [SKIP][39] ([i915#2434]) -> [ABORT][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-rkl-1/igt@perf@mi-rpc.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-rkl-2/igt@perf@mi-rpc.html

  * igt@perf@unprivileged-single-ctx-counters:
    - shard-rkl:          [SKIP][41] ([i915#2433]) -> [ABORT][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-rkl-2/igt@perf@unprivileged-single-ctx-counters.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-rkl-4/igt@perf@unprivileged-single-ctx-counters.html
    - shard-tglu:         [SKIP][43] ([fdo#109289]) -> [ABORT][44] +1 similar issue
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-tglu-4/igt@perf@unprivileged-single-ctx-counters.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-tglu-3/igt@perf@unprivileged-single-ctx-counters.html
    - shard-dg2:          [SKIP][45] ([fdo#109289]) -> [ABORT][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-dg2-2/igt@perf@unprivileged-single-ctx-counters.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-5/igt@perf@unprivileged-single-ctx-counters.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@perf@gen12-unprivileged-single-ctx-counters@rcs0:
    - {shard-dg1}:        [PASS][47] -> [ABORT][48] +15 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-dg1-17/igt@perf@gen12-unprivileged-single-ctx-counters@rcs0.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg1-15/igt@perf@gen12-unprivileged-single-ctx-counters@rcs0.html

  * igt@perf@global-sseu-config:
    - {shard-dg1}:        NOTRUN -> [ABORT][49]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg1-19/igt@perf@global-sseu-config.html

  * igt@perf@mi-rpc:
    - {shard-dg1}:        [SKIP][50] ([i915#2434]) -> [ABORT][51]
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-dg1-13/igt@perf@mi-rpc.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg1-13/igt@perf@mi-rpc.html

  * igt@perf@oa-exponents@0-rcs0:
    - {shard-dg1}:        [PASS][52] -> [INCOMPLETE][53]
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-dg1-19/igt@perf@oa-exponents@0-rcs0.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg1-12/igt@perf@oa-exponents@0-rcs0.html

  * igt@perf@unprivileged-single-ctx-counters:
    - {shard-dg1}:        [SKIP][54] ([fdo#109289] / [i915#2433]) -> [ABORT][55]
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-dg1-16/igt@perf@unprivileged-single-ctx-counters.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg1-17/igt@perf@unprivileged-single-ctx-counters.html

  
Known issues
------------

  Here are the changes found in Patchwork_120943v2_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@blit-reloc-purge-cache:
    - shard-dg2:          NOTRUN -> [SKIP][56] ([i915#8411])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@api_intel_bb@blit-reloc-purge-cache.html

  * igt@gem_close_race@multigpu-basic-process:
    - shard-dg2:          NOTRUN -> [SKIP][57] ([i915#7697])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@gem_close_race@multigpu-basic-process.html

  * igt@gem_ctx_persistence@engines-queued:
    - shard-snb:          NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#1099]) +1 similar issue
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-snb1/igt@gem_ctx_persistence@engines-queued.html

  * igt@gem_ctx_persistence@hang:
    - shard-dg2:          NOTRUN -> [SKIP][59] ([i915#8555])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-5/igt@gem_ctx_persistence@hang.html

  * igt@gem_exec_balancer@sliced:
    - shard-dg2:          NOTRUN -> [SKIP][60] ([i915#4812]) +1 similar issue
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@gem_exec_balancer@sliced.html

  * igt@gem_exec_fair@basic-none-solo:
    - shard-mtlp:         NOTRUN -> [SKIP][61] ([i915#4473])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@gem_exec_fair@basic-none-solo.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-glk:          [PASS][62] -> [FAIL][63] ([i915#2842])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-glk9/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-glk7/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-rkl:          [PASS][64] -> [FAIL][65] ([i915#2842]) +2 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-rkl-1/igt@gem_exec_fair@basic-throttle@rcs0.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-rkl-4/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_reloc@basic-range-active:
    - shard-dg2:          NOTRUN -> [SKIP][66] ([i915#3281]) +1 similar issue
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-5/igt@gem_exec_reloc@basic-range-active.html

  * igt@gem_exec_reloc@basic-write-wc:
    - shard-mtlp:         NOTRUN -> [SKIP][67] ([i915#3281]) +2 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@gem_exec_reloc@basic-write-wc.html

  * igt@gem_exec_schedule@preempt-queue:
    - shard-mtlp:         NOTRUN -> [SKIP][68] ([i915#4812])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-5/igt@gem_exec_schedule@preempt-queue.html

  * igt@gem_exec_schedule@reorder-wide:
    - shard-dg2:          NOTRUN -> [SKIP][69] ([i915#4537] / [i915#4812]) +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@gem_exec_schedule@reorder-wide.html

  * igt@gem_exec_whisper@basic-contexts-priority-all:
    - shard-mtlp:         [PASS][70] -> [ABORT][71] ([i915#8131])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-mtlp-7/igt@gem_exec_whisper@basic-contexts-priority-all.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-7/igt@gem_exec_whisper@basic-contexts-priority-all.html

  * igt@gem_fence_thrash@bo-write-verify-none:
    - shard-dg2:          NOTRUN -> [SKIP][72] ([i915#4860])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@gem_fence_thrash@bo-write-verify-none.html

  * igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible:
    - shard-mtlp:         NOTRUN -> [SKIP][73] ([i915#4860])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-5/igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible.html

  * igt@gem_lmem_swapping@verify-random:
    - shard-mtlp:         NOTRUN -> [SKIP][74] ([i915#4613])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_madvise@dontneed-before-pwrite:
    - shard-dg2:          NOTRUN -> [SKIP][75] ([i915#3282])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@gem_madvise@dontneed-before-pwrite.html

  * igt@gem_mmap_gtt@cpuset-medium-copy-xy:
    - shard-dg2:          NOTRUN -> [SKIP][76] ([i915#4077]) +4 similar issues
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-5/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html

  * igt@gem_mmap_wc@bad-object:
    - shard-dg2:          NOTRUN -> [SKIP][77] ([i915#4083]) +1 similar issue
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@gem_mmap_wc@bad-object.html

  * igt@gem_mmap_wc@read-write:
    - shard-mtlp:         NOTRUN -> [SKIP][78] ([i915#4083]) +1 similar issue
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-5/igt@gem_mmap_wc@read-write.html

  * igt@gem_pread@snoop:
    - shard-mtlp:         NOTRUN -> [SKIP][79] ([i915#3282])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@gem_pread@snoop.html

  * igt@gem_pxp@display-protected-crc:
    - shard-dg2:          NOTRUN -> [SKIP][80] ([i915#4270])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@gem_pxp@display-protected-crc.html

  * igt@gem_pxp@protected-raw-src-copy-not-readible:
    - shard-mtlp:         NOTRUN -> [SKIP][81] ([i915#4270])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@gem_pxp@protected-raw-src-copy-not-readible.html

  * igt@gem_render_copy@x-tiled-to-vebox-y-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][82] ([i915#8428])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@gem_render_copy@x-tiled-to-vebox-y-tiled.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][83] ([i915#4079]) +1 similar issue
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-mtlp:         NOTRUN -> [SKIP][84] ([i915#3297]) +1 similar issue
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-dg2:          NOTRUN -> [FAIL][85] ([i915#3318])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@gem_userptr_blits@vma-merge.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-dg2:          [PASS][86] -> [FAIL][87] ([fdo#103375])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-dg2-2/igt@gem_workarounds@suspend-resume-fd.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-5/igt@gem_workarounds@suspend-resume-fd.html

  * igt@gen3_render_tiledx_blits:
    - shard-mtlp:         NOTRUN -> [SKIP][88] ([fdo#109289])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-5/igt@gen3_render_tiledx_blits.html

  * igt@gen3_render_tiledy_blits:
    - shard-dg2:          NOTRUN -> [SKIP][89] ([fdo#109289]) +3 similar issues
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-5/igt@gen3_render_tiledy_blits.html

  * igt@gen9_exec_parse@batch-zero-length:
    - shard-dg2:          NOTRUN -> [SKIP][90] ([i915#2856]) +1 similar issue
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@gen9_exec_parse@batch-zero-length.html

  * igt@i915_pm_backlight@fade-with-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][91] ([i915#5354] / [i915#7561])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@i915_pm_backlight@fade-with-dpms.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
    - shard-dg2:          NOTRUN -> [SKIP][92] ([i915#1937])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-6/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html

  * igt@i915_pm_rpm@cursor-dpms:
    - shard-tglu:         [PASS][93] -> [FAIL][94] ([i915#7940])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-tglu-9/igt@i915_pm_rpm@cursor-dpms.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-tglu-4/igt@i915_pm_rpm@cursor-dpms.html

  * igt@i915_pm_rpm@dpms-non-lpsp:
    - shard-rkl:          [PASS][95] -> [SKIP][96] ([i915#1397])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-rkl-1/igt@i915_pm_rpm@dpms-non-lpsp.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-rkl-7/igt@i915_pm_rpm@dpms-non-lpsp.html

  * igt@i915_pm_rpm@modeset-lpsp:
    - shard-dg2:          NOTRUN -> [SKIP][97] ([i915#1397])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@i915_pm_rpm@modeset-lpsp.html

  * igt@i915_pm_rpm@system-suspend-devices:
    - shard-snb:          NOTRUN -> [SKIP][98] ([fdo#109271]) +121 similar issues
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-snb1/igt@i915_pm_rpm@system-suspend-devices.html

  * igt@i915_pm_rpm@system-suspend-modeset:
    - shard-dg2:          NOTRUN -> [FAIL][99] ([fdo#103375]) +1 similar issue
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-5/igt@i915_pm_rpm@system-suspend-modeset.html

  * igt@i915_pm_rps@min-max-config-loaded:
    - shard-dg2:          NOTRUN -> [SKIP][100] ([i915#6621])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@i915_pm_rps@min-max-config-loaded.html

  * igt@i915_selftest@live@gt_mocs:
    - shard-mtlp:         NOTRUN -> [DMESG-FAIL][101] ([i915#7059])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@i915_selftest@live@gt_mocs.html

  * igt@i915_selftest@live@slpc:
    - shard-mtlp:         NOTRUN -> [DMESG-WARN][102] ([i915#6367])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@i915_selftest@live@slpc.html

  * igt@i915_selftest@live@workarounds:
    - shard-mtlp:         NOTRUN -> [DMESG-FAIL][103] ([i915#6763])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@i915_selftest@live@workarounds.html

  * igt@kms_async_flips@crc@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [FAIL][104] ([i915#8247]) +3 similar issues
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-1/igt@kms_async_flips@crc@pipe-a-hdmi-a-3.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-90:
    - shard-mtlp:         NOTRUN -> [SKIP][105] ([fdo#111614])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-mtlp:         [PASS][106] -> [FAIL][107] ([i915#5138]) +1 similar issue
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-90:
    - shard-dg2:          NOTRUN -> [SKIP][108] ([fdo#111614])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-addfb:
    - shard-mtlp:         NOTRUN -> [SKIP][109] ([i915#6187])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-5/igt@kms_big_fb@y-tiled-addfb.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-dg2:          NOTRUN -> [SKIP][110] ([i915#5190]) +5 similar issues
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-5/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-mtlp:         NOTRUN -> [SKIP][111] ([fdo#111615]) +3 similar issues
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-dg2:          NOTRUN -> [SKIP][112] ([i915#4538] / [i915#5190]) +1 similar issue
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-5/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][113] ([i915#6095]) +12 similar issues
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-3/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs.html

  * igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
    - shard-mtlp:         NOTRUN -> [SKIP][114] ([i915#3886] / [i915#6095])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-5/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc:
    - shard-mtlp:         [PASS][115] -> [SKIP][116] ([i915#6095]) +64 similar issues
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-mtlp-7/igt@kms_ccs@pipe-b-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-7/igt@kms_ccs@pipe-b-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
    - shard-dg2:          NOTRUN -> [SKIP][117] ([i915#3689] / [i915#3886] / [i915#5354]) +4 similar issues
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs:
    - shard-dg2:          NOTRUN -> [SKIP][118] ([i915#3689] / [i915#5354]) +4 similar issues
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs.html

  * igt@kms_ccs@pipe-d-ccs-on-another-bo-4_tiled_mtl_rc_ccs:
    - shard-dg2:          NOTRUN -> [SKIP][119] ([i915#5354]) +13 similar issues
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@kms_ccs@pipe-d-ccs-on-another-bo-4_tiled_mtl_rc_ccs.html

  * igt@kms_chamelium_color@ctm-0-75:
    - shard-mtlp:         NOTRUN -> [SKIP][120] ([fdo#111827])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@kms_chamelium_color@ctm-0-75.html

  * igt@kms_chamelium_color@ctm-limited-range:
    - shard-dg2:          NOTRUN -> [SKIP][121] ([fdo#111827])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@kms_chamelium_color@ctm-limited-range.html

  * igt@kms_chamelium_edid@hdmi-edid-read:
    - shard-mtlp:         NOTRUN -> [SKIP][122] ([i915#7828]) +3 similar issues
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-5/igt@kms_chamelium_edid@hdmi-edid-read.html

  * igt@kms_chamelium_edid@hdmi-mode-timings:
    - shard-dg2:          NOTRUN -> [SKIP][123] ([i915#7828]) +2 similar issues
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-5/igt@kms_chamelium_edid@hdmi-mode-timings.html

  * igt@kms_content_protection@atomic@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [TIMEOUT][124] ([i915#7173])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-11/igt@kms_content_protection@atomic@pipe-a-dp-4.html

  * igt@kms_content_protection@srm:
    - shard-mtlp:         NOTRUN -> [SKIP][125] ([i915#6944])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@kms_content_protection@srm.html

  * igt@kms_content_protection@type1:
    - shard-dg2:          NOTRUN -> [SKIP][126] ([i915#7118]) +2 similar issues
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-5/igt@kms_content_protection@type1.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-dg2:          NOTRUN -> [SKIP][127] ([i915#3359])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-mtlp:         NOTRUN -> [SKIP][128] ([i915#3359])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
    - shard-dg2:          NOTRUN -> [SKIP][129] ([fdo#109274] / [i915#5354]) +1 similar issue
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
    - shard-mtlp:         NOTRUN -> [SKIP][130] ([i915#3546]) +1 similar issue
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-glk:          [PASS][131] -> [FAIL][132] ([i915#2346])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-flip-vs-panning-vs-hang:
    - shard-dg2:          NOTRUN -> [SKIP][133] ([fdo#109274])
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-5/igt@kms_flip@2x-flip-vs-panning-vs-hang.html

  * igt@kms_flip@2x-flip-vs-rmfb-interruptible:
    - shard-mtlp:         NOTRUN -> [SKIP][134] ([fdo#111767] / [i915#3637])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html

  * igt@kms_flip@flip-vs-suspend@b-vga1:
    - shard-snb:          NOTRUN -> [DMESG-WARN][135] ([i915#8841]) +1 similar issue
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-snb4/igt@kms_flip@flip-vs-suspend@b-vga1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][136] ([i915#2672])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][137] ([i915#2672]) +1 similar issue
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][138] ([i915#8708]) +4 similar issues
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
    - shard-mtlp:         NOTRUN -> [SKIP][139] ([i915#1825]) +8 similar issues
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][140] ([i915#3458]) +7 similar issues
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][141] ([i915#8708]) +3 similar issues
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html

  * igt@kms_getfb@getfb-reject-ccs:
    - shard-mtlp:         [PASS][142] -> [SKIP][143] ([i915#8438])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-mtlp-3/igt@kms_getfb@getfb-reject-ccs.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-3/igt@kms_getfb@getfb-reject-ccs.html

  * igt@kms_getfb@getfb2-accept-ccs:
    - shard-mtlp:         [PASS][144] -> [SKIP][145] ([i915#8439])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-mtlp-7/igt@kms_getfb@getfb2-accept-ccs.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-7/igt@kms_getfb@getfb2-accept-ccs.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][146] ([i915#3555] / [i915#8228])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-5/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_panel_fitting@legacy:
    - shard-dg2:          NOTRUN -> [SKIP][147] ([i915#6301])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@kms_panel_fitting@legacy.html

  * igt@kms_plane_multiple@tiling-y:
    - shard-dg2:          NOTRUN -> [SKIP][148] ([i915#8806])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-5/igt@kms_plane_multiple@tiling-y.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [FAIL][149] ([i915#8292])
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-11/igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-4.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2:
    - shard-rkl:          [PASS][150] -> [FAIL][151] ([i915#8292])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-rkl-4/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-rkl-6/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html

  * igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][152] ([i915#5176]) +5 similar issues
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-rkl-6/igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-2.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][153] ([i915#5235]) +1 similar issue
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-rkl-7/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-hdmi-a-1.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-dp-4:
    - shard-dg2:          NOTRUN -> [SKIP][154] ([i915#5235]) +11 similar issues
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-11/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-dp-4.html

  * igt@kms_prime@basic-crc-hybrid:
    - shard-mtlp:         NOTRUN -> [SKIP][155] ([i915#6524])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@kms_prime@basic-crc-hybrid.html

  * igt@kms_psr@cursor_mmap_gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][156] ([i915#4077]) +3 similar issues
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@kms_psr@cursor_mmap_gtt.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-dg2:          NOTRUN -> [SKIP][157] ([i915#1072]) +2 similar issues
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-5/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@kms_rotation_crc@primary-rotation-270:
    - shard-dg2:          NOTRUN -> [SKIP][158] ([i915#4235])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@kms_rotation_crc@primary-rotation-270.html

  * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
    - shard-mtlp:         NOTRUN -> [SKIP][159] ([i915#4235])
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html

  * igt@kms_vrr@negative-basic:
    - shard-dg2:          NOTRUN -> [SKIP][160] ([i915#3555])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-2/igt@kms_vrr@negative-basic.html

  * igt@perf@disabled-read-error:
    - shard-dg2:          NOTRUN -> [ABORT][161] ([i915#8862])
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-5/igt@perf@disabled-read-error.html

  * igt@perf_pmu@rc6@other-idle-gt0:
    - shard-dg2:          NOTRUN -> [SKIP][162] ([i915#8516])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@perf_pmu@rc6@other-idle-gt0.html

  * igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
    - shard-dg2:          NOTRUN -> [INCOMPLETE][163] ([i915#5493])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html

  * igt@prime_vgem@basic-read:
    - shard-dg2:          NOTRUN -> [SKIP][164] ([i915#3291] / [i915#3708])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@prime_vgem@basic-read.html

  * igt@v3d/v3d_submit_csd@bad-perfmon:
    - shard-mtlp:         NOTRUN -> [SKIP][165] ([i915#2575]) +2 similar issues
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@v3d/v3d_submit_csd@bad-perfmon.html

  * igt@v3d/v3d_wait_bo@used-bo-1ns:
    - shard-dg2:          NOTRUN -> [SKIP][166] ([i915#2575]) +3 similar issues
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@v3d/v3d_wait_bo@used-bo-1ns.html

  * igt@vc4/vc4_perfmon@get-values-invalid-perfmon:
    - shard-dg2:          NOTRUN -> [SKIP][167] ([i915#7711]) +1 similar issue
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-8/igt@vc4/vc4_perfmon@get-values-invalid-perfmon.html

  * igt@vc4/vc4_purgeable_bo@access-purged-bo-mem:
    - shard-mtlp:         NOTRUN -> [SKIP][168] ([i915#7711]) +1 similar issue
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-5/igt@vc4/vc4_purgeable_bo@access-purged-bo-mem.html

  
#### Possible fixes ####

  * igt@gem_eio@in-flight-contexts-1us:
    - shard-mtlp:         [ABORT][169] ([i915#8503]) -> [PASS][170]
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-mtlp-2/igt@gem_eio@in-flight-contexts-1us.html
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-4/igt@gem_eio@in-flight-contexts-1us.html

  * igt@gem_eio@reset-stress:
    - {shard-dg1}:        [FAIL][171] ([i915#5784]) -> [PASS][172]
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-dg1-18/igt@gem_eio@reset-stress.html
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg1-19/igt@gem_eio@reset-stress.html

  * igt@gem_exec_fair@basic-none@bcs0:
    - shard-rkl:          [FAIL][173] ([i915#2842]) -> [PASS][174]
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-rkl-1/igt@gem_exec_fair@basic-none@bcs0.html
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-rkl-2/igt@gem_exec_fair@basic-none@bcs0.html

  * igt@i915_pm_rpm@cursor-dpms:
    - {shard-dg1}:        [FAIL][175] ([i915#7940]) -> [PASS][176]
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-dg1-16/igt@i915_pm_rpm@cursor-dpms.html
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg1-18/igt@i915_pm_rpm@cursor-dpms.html

  * igt@i915_pm_rpm@dpms-non-lpsp:
    - {shard-dg1}:        [SKIP][177] ([i915#1397]) -> [PASS][178]
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-dg1-19/igt@i915_pm_rpm@dpms-non-lpsp.html
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg1-17/igt@i915_pm_rpm@dpms-non-lpsp.html
    - shard-dg2:          [SKIP][179] ([i915#1397]) -> [PASS][180]
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-dg2-12/igt@i915_pm_rpm@dpms-non-lpsp.html
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-dg2-2/igt@i915_pm_rpm@dpms-non-lpsp.html

  * igt@i915_pm_rpm@modeset-non-lpsp:
    - shard-rkl:          [SKIP][181] ([i915#1397]) -> [PASS][182]
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp.html
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-rkl-6/igt@i915_pm_rpm@modeset-non-lpsp.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-mtlp:         [FAIL][183] ([i915#3743]) -> [PASS][184]
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-mtlp-5/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_busy@extended-pageflip-hang-newfb@pipe-a:
    - shard-snb:          [ABORT][185] -> [PASS][186]
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-snb7/igt@kms_busy@extended-pageflip-hang-newfb@pipe-a.html
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-snb7/igt@kms_busy@extended-pageflip-hang-newfb@pipe-a.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
    - shard-glk:          [FAIL][187] ([i915#72]) -> [PASS][188]
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
    - shard-mtlp:         [FAIL][189] ([i915#8248]) -> [PASS][190]
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-mtlp-5/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-8/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-apl:          [FAIL][191] ([i915#2346]) -> [PASS][192]
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  
#### Warnings ####

  * igt@kms_async_flips@crc@pipe-a-edp-1:
    - shard-mtlp:         [DMESG-FAIL][193] ([i915#1982] / [i915#8561]) -> [DMESG-FAIL][194] ([i915#8561])
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-mtlp-4/igt@kms_async_flips@crc@pipe-a-edp-1.html
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-5/igt@kms_async_flips@crc@pipe-a-edp-1.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-mtlp:         [DMESG-FAIL][195] ([i915#2017] / [i915#5954]) -> [DMESG-FAIL][196] ([i915#1982] / [i915#2017] / [i915#5954])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13418/shard-mtlp-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/shard-mtlp-8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
  [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
  [i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#5954]: https://gitlab.freedesktop.org/drm/intel/issues/5954
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6187]: https://gitlab.freedesktop.org/drm/intel/issues/6187
  [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6763]: https://gitlab.freedesktop.org/drm/intel/issues/6763
  [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
  [i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
  [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
  [i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
  [i915#8131]: https://gitlab.freedesktop.org/drm/intel/issues/8131
  [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
  [i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
  [i915#8248]: https://gitlab.freedesktop.org/drm/intel/issues/8248
  [i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
  [i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
  [i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
  [i915#8438]: https://gitlab.freedesktop.org/drm/intel/issues/8438
  [i915#8439]: https://gitlab.freedesktop.org/drm/intel/issues/8439
  [i915#8503]: https://gitlab.freedesktop.org/drm/intel/issues/8503
  [i915#8516]: https://gitlab.freedesktop.org/drm/intel/issues/8516
  [i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
  [i915#8561]: https://gitlab.freedesktop.org/drm/intel/issues/8561
  [i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
  [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
  [i915#8806]: https://gitlab.freedesktop.org/drm/intel/issues/8806
  [i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
  [i915#8862]: https://gitlab.freedesktop.org/drm/intel/issues/8862


Build changes
-------------

  * Linux: CI_DRM_13418 -> Patchwork_120943v2

  CI-20190529: 20190529
  CI_DRM_13418: e31a5b300385ef52e6db1cda820518cb2da089ca @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7401: 0c66a6560eda687effa9088659577a520d913908 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_120943v2: e31a5b300385ef52e6db1cda820518cb2da089ca @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v2/index.html

[-- Attachment #2: Type: text/html, Size: 57058 bytes --]

Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version

[Andi Shyti]

Hi Matt,

[...]

all good

[...]

> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h

Is this the right place to define this? Maybe in
i915/gt/intel_gt.h?

> @@ -431,6 +431,29 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
>  #define IS_GRAPHICS_VER(i915, from, until) \
>  	(GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
>  
> +#define __IS_MEDIA_GT(gt) ((gt)->type == GT_MEDIA)
> +#define __IS_GFX_GT(gt) (!__IS_MEDIA_GT(gt))
> +#define __GT_VER_FULL(gt) (__IS_MEDIA_GT(gt) ? \
> +			   MEDIA_VER_FULL((gt)->i915) : \
> +			   GRAPHICS_VER_FULL((gt)->i915))

I think you can remove the '__' they can be widely used all
around the gt/ code.

> +/*
> + * Check that a GT contains IP of the specified type and within the specified
> + * IP range.  E.g.,
> + *
> + *    IS_GT_IP_RANGE(GFX, IP_VER(12, 70), IP_VER(12, 71))
> + *    IS_GT_IP_RANGE(MEDIA, IP_VER(13, 00), IP_VER(18, 02))
> + *
> + * Note that media version checks with this macro will only work on platforms
> + * with standalone media design (i.e., media version 13 and higher).
> + */
> +#define IS_GT_IP_RANGE(type, gt, from, until) ( \
> +	BUILD_BUG_ON_ZERO(from < IP_VER(2, 0)) + \
> +	BUILD_BUG_ON_ZERO(until < from) + \
> +	(__IS_##type##_GT(gt) && \
> +	 __GT_VER_FULL(gt) >= (from) && \
> +	 __GT_VER_FULL(gt) <= (until)))

This helper deservers its own patch :) Can we split it from the
rest?

Thanks,
Andi

>  #define MEDIA_VER(i915)			(RUNTIME_INFO(i915)->media.ip.ver)
>  #define MEDIA_VER_FULL(i915)		IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
>  					       RUNTIME_INFO(i915)->media.ip.rel)
> -- 
> 2.41.0

Re: [Intel-gfx] [PATCH v2 4/9] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP

[Andi Shyti]

Hi Matt,

> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -436,6 +436,9 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
>  #define __GT_VER_FULL(gt) (__IS_MEDIA_GT(gt) ? \
>  			   MEDIA_VER_FULL((gt)->i915) : \
>  			   GRAPHICS_VER_FULL((gt)->i915))
> +#define __GT_STEP(gt) (__IS_MEDIA_GT(gt) ? \
> +		       INTEL_MEDIA_STEP((gt)->i915) : \
> +		       INTEL_GRAPHICS_STEP((gt)->i915))
>  
>  /*
>   * Check that a GT contains IP of the specified type and within the specified
> @@ -454,6 +457,29 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
>  	 __GT_VER_FULL(gt) >= (from) && \
>  	 __GT_VER_FULL(gt) <= (until)))
>  
> +/*
> + * Check whether a GT contains the specific IP version and a stepping within
> + * the specified range [from, until).  The lower stepping bound is inclusive,
> + * the upper bound is exclusive (corresponding to the first hardware stepping
> + * at when the workaround is no longer needed).  E.g.,
> + *
> + *    IS_GT_IP_STEP(GFX, IP_VER(12, 70), A0, B0)
> + *    IS_GT_IP_STEP(MEDIA, IP_VER(13, 00), B1, D0)
> + *    IS_GT_IP_STEP(GFX, IP_VER(12, 71), B1, FOREVER)
> + *
> + * "FOREVER" can be passed as the upper stepping bound for workarounds that
> + * have no upper bound on steppings of the specified IP version.
> + *
> + * Note that media version checks with this macro will only work on platforms
> + * with standalone media design (i.e., media version 13 and higher).
> + */
> +#define IS_GT_IP_STEP(type, gt, ipver, since, until) \
> +	(BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
> +	 (__IS_##type##_GT(gt) && \
> +	  __GT_VER_FULL(gt) == ipver && \
> +	  __GT_STEP(gt) >= STEP_##since && \
> +	  __GT_STEP(gt) <= STEP_##until))
> +

Should this go in intel_gt.h?

>  #define MEDIA_VER(i915)			(RUNTIME_INFO(i915)->media.ip.ver)
>  #define MEDIA_VER_FULL(i915)		IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
>  					       RUNTIME_INFO(i915)->media.ip.rel)
> @@ -710,10 +736,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
>  	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
>  
> -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
> -	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
> -	 IS_GRAPHICS_STEP(__i915, since, until))
> -

For completeness I would either leave this or remove all the
above. Or I would make this a wrapper around IS_GT_IP_STEP() with
a compile error if we are outside the MTL range.

Andi

>  #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
>  	(IS_METEORLAKE(__i915) && \
>  	 IS_DISPLAY_STEP(__i915, since, until))
> -- 
> 2.41.0

Re: [Intel-gfx] [PATCH v2 9/9] drm/i915: Replace several IS_METEORLAKE with proper IP version checks

[Andi Shyti]

Hi Matt,

> --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> @@ -470,9 +470,13 @@ enum i915_map_type i915_coherent_map_type(struct drm_i915_private *i915,
>  					  bool always_coherent)
>  {
>  	/*
> -	 * Wa_22016122933: always return I915_MAP_WC for MTL
> +	 * Wa_22016122933: always return I915_MAP_WC for Xe_LPM+
> +	 *
> +	 * FIXME: The scope of this workaround is too wide right now and
> +	 * is applying to objects used solely on the primary GT.  We need to
> +	 * take into account which GT will be operating on the shared object.
>  	 */
> -	if (i915_gem_object_is_lmem(obj) || IS_METEORLAKE(i915))
> +	if (i915_gem_object_is_lmem(obj) || MEDIA_VER_FULL(i915) == IP_VER(13, 0))
>  		return I915_MAP_WC;
>  	if (HAS_LLC(i915) || always_coherent)
>  		return I915_MAP_WB;
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> index 21af0ec52223..24060278e7a2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> @@ -21,7 +21,7 @@ static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine)
>  {
>  	struct drm_i915_private *i915 = engine->i915;
>  
> -	if (IS_METEORLAKE(i915) && engine->id == GSC0) {
> +	if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) {

this is a bit in countertrend... why isn't this

	MEDIA_VER_FULL(engine->i915) == IP_VER(13, 0)

Like all others?

Andi

Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version

[Tvrtko Ursulin]

On 25/07/2023 01:13, Matt Roper wrote:
> Although some of our Xe_LPG workarounds were already being applied based
> on IP version correctly, others were matching on MTL as a base platform,
> which is incorrect.  Although MTL is the only platform right now that
> uses Xe_LPG IP, this may not always be the case.  If a future platform
> re-uses this graphics IP, the same workarounds should be applied, even
> if it isn't a "MTL" platform.
> 
> We were also incorrectly applying Xe_LPG workarounds/tuning to the
> Xe_LPM+ media IP in one or two places; we should make sure that we don't
> try to apply graphics workarounds to the media GT and vice versa where
> they don't belong.  A new helper macro IS_GT_IP_RANGE() is added to help
> ensure this is handled properly -- it checks that the GT matches the IP
> type being tested as well as the IP version falling in the proper range.
> 
> Note that many of the stepping-based workarounds are still incorrectly
> checking for a MTL base platform; that will be remedied in a later
> patch.
> 
> v2:
>   - Rework macro into a slightly more generic IS_GT_IP_RANGE() that can
>     be used for either GFX or MEDIA checks.
> 
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 38 +++++++++++----------
>   drivers/gpu/drm/i915/i915_drv.h             | 23 +++++++++++++
>   2 files changed, 43 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index d8a1eaa44e69..c4663541c5dd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -805,8 +805,8 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
>   	wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
>   }
>   
> -static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> -				   struct i915_wa_list *wal)
> +static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> +				     struct i915_wa_list *wal)
>   {
>   	struct drm_i915_private *i915 = engine->i915;
>   
> @@ -817,12 +817,12 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
>   		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
>   }
>   
> -static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
> -				     struct i915_wa_list *wal)
> +static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
> +				       struct i915_wa_list *wal)
>   {
>   	struct drm_i915_private *i915 = engine->i915;
>   
> -	mtl_ctx_gt_tuning_init(engine, wal);
> +	xelpg_ctx_gt_tuning_init(engine, wal);
>   
>   	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>   	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> @@ -931,8 +931,8 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>   	if (engine->class != RENDER_CLASS)
>   		goto done;
>   
> -	if (IS_METEORLAKE(i915))
> -		mtl_ctx_workarounds_init(engine, wal);
> +	if (IS_GT_IP_RANGE(GFX, engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
> +		xelpg_ctx_workarounds_init(engine, wal);
>   	else if (IS_PONTEVECCHIO(i915))
>   		; /* noop; none at this time */
>   	else if (IS_DG2(i915))
> @@ -1790,10 +1790,8 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>    */
>   static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
>   {
> -	if (IS_METEORLAKE(gt->i915)) {
> -		if (gt->type != GT_MEDIA)
> -			wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
> -
> +	if (IS_GT_IP_RANGE(GFX, gt, IP_VER(12, 70), IP_VER(12, 71))) {
> +		wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
>   		wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
>   	}
>   
> @@ -1825,7 +1823,7 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
>   		return;
>   	}
>   
> -	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> +	if (IS_GT_IP_RANGE(GFX, gt, IP_VER(12, 70), IP_VER(12, 71)))
>   		xelpg_gt_workarounds_init(gt, wal);
>   	else if (IS_PONTEVECCHIO(i915))
>   		pvc_gt_workarounds_init(gt, wal);
> @@ -2293,7 +2291,7 @@ static void pvc_whitelist_build(struct intel_engine_cs *engine)
>   	blacklist_trtt(engine);
>   }
>   
> -static void mtl_whitelist_build(struct intel_engine_cs *engine)
> +static void xelpg_whitelist_build(struct intel_engine_cs *engine)
>   {
>   	struct i915_wa_list *w = &engine->whitelist;
>   
> @@ -2315,8 +2313,10 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>   
>   	wa_init_start(w, engine->gt, "whitelist", engine->name);
>   
> -	if (IS_METEORLAKE(i915))
> -		mtl_whitelist_build(engine);
> +	if (engine->gt->type == GT_MEDIA)
> +		; /* none yet */
> +	else if (IS_GT_IP_RANGE(GFX, engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
> +		xelpg_whitelist_build(engine);
>   	else if (IS_PONTEVECCHIO(i915))
>   		pvc_whitelist_build(engine);
>   	else if (IS_DG2(i915))
> @@ -2974,10 +2974,12 @@ ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>    * function invoked by __intel_engine_init_ctx_wa().
>    */
>   static void
> -add_render_compute_tuning_settings(struct drm_i915_private *i915,
> +add_render_compute_tuning_settings(struct intel_gt *gt,
>   				   struct i915_wa_list *wal)
>   {
> -	if (IS_METEORLAKE(i915) || IS_DG2(i915))
> +	struct drm_i915_private *i915 = gt->i915;
> +
> +	if (IS_GT_IP_RANGE(GFX, gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))
>   		wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
>   
>   	/*
> @@ -3007,7 +3009,7 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>   {
>   	struct drm_i915_private *i915 = engine->i915;
>   
> -	add_render_compute_tuning_settings(i915, wal);
> +	add_render_compute_tuning_settings(engine->gt, wal);
>   
>   	if (GRAPHICS_VER(i915) >= 11) {
>   		/* This is not a Wa (although referred to as
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 682ef2b5c7d5..6bb825d40451 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -431,6 +431,29 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
>   #define IS_GRAPHICS_VER(i915, from, until) \
>   	(GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
>   
> +#define __IS_MEDIA_GT(gt) ((gt)->type == GT_MEDIA)
> +#define __IS_GFX_GT(gt) (!__IS_MEDIA_GT(gt))
> +#define __GT_VER_FULL(gt) (__IS_MEDIA_GT(gt) ? \
> +			   MEDIA_VER_FULL((gt)->i915) : \
> +			   GRAPHICS_VER_FULL((gt)->i915))
> +
> +/*
> + * Check that a GT contains IP of the specified type and within the specified
> + * IP range.  E.g.,
> + *
> + *    IS_GT_IP_RANGE(GFX, IP_VER(12, 70), IP_VER(12, 71))
> + *    IS_GT_IP_RANGE(MEDIA, IP_VER(13, 00), IP_VER(18, 02))

I think without the magic GFX/MEDIA first argument would be better and 
more readable. That is simply IS_GT_IP_RANGE(gt, IP_VER(), IP_VER). GT 
type checks feel would be more readable on the outside, and some of them 
will even probably come from a level above. Even when split out on the 
same line it reads more readable to me, like:

   if (IS_MEDIA_GT(gt) && IS_GT_IP_RANGE(gt, IP_VER(), IP_VER())

Regards,

Tvrtko

> + *
> + * Note that media version checks with this macro will only work on platforms
> + * with standalone media design (i.e., media version 13 and higher).
> + */
> +#define IS_GT_IP_RANGE(type, gt, from, until) ( \
> +	BUILD_BUG_ON_ZERO(from < IP_VER(2, 0)) + \
> +	BUILD_BUG_ON_ZERO(until < from) + \
> +	(__IS_##type##_GT(gt) && \
> +	 __GT_VER_FULL(gt) >= (from) && \
> +	 __GT_VER_FULL(gt) <= (until)))
> +
>   #define MEDIA_VER(i915)			(RUNTIME_INFO(i915)->media.ip.ver)
>   #define MEDIA_VER_FULL(i915)		IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
>   					       RUNTIME_INFO(i915)->media.ip.rel)

Re: [Intel-gfx] [PATCH v2 4/9] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP

[Tvrtko Ursulin]

On 25/07/2023 01:13, Matt Roper wrote:
> Several workarounds are guarded by IS_MTL_GRAPHICS_STEP.  However none
> of these workarounds are actually tied to MTL as a platform; they only
> relate to the Xe_LPG graphics IP, regardless of what platform it appears
> in.  At the moment MTL is the only platform that uses Xe_LPG with IP
> versions 12.70 and 12.71, but we can't count on this being true in the
> future.  Switch these to use a new IS_GT_IP_STEP() macro instead that is
> purely based on IP version.  IS_GT_IP_STEP() is also GT-based rather
> than device-based, which will help prevent mistakes where we
> accidentally try to apply Xe_LPG graphics workarounds to the Xe_LPM+
> media GT and vice-versa.
> 
> v2:
>   - Switch to a more generic and shorter IS_GT_IP_STEP macro that can be
>     used for both graphics and media IP (and any other kind of GTs that
>     show up in the future).
> 
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>   .../drm/i915/display/skl_universal_plane.c    |  4 +-
>   drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  9 ++--
>   drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
>   drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
>   drivers/gpu/drm/i915/gt/intel_reset.c         |  2 +-
>   drivers/gpu/drm/i915/gt/intel_workarounds.c   | 52 ++++++++++---------
>   drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  2 +-
>   .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  2 +-
>   drivers/gpu/drm/i915/i915_drv.h               | 30 +++++++++--
>   9 files changed, 67 insertions(+), 42 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 6b01a0b68b97..5fd8a42b3ec1 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
>   				 enum pipe pipe, enum plane_id plane_id)
>   {
>   	/* Wa_14017240301 */
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +	if (IS_GT_IP_STEP(GFX, to_gt(i915), IP_VER(12, 70), A0, B0) ||
> +	    IS_GT_IP_STEP(GFX, to_gt(i915), IP_VER(12, 71), A0, B0))
>   		return false;
>   
>   	/* Wa_22011186057 */
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index 3ba20ea030e8..9d04591f3b4a 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
>   static int mtl_dummy_pipe_control(struct i915_request *rq)
>   {
>   	/* Wa_14016712196 */
> -	if (IS_MTL_GRAPHICS_STEP(rq->i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(rq->i915, P, STEP_A0, STEP_B0)) {
> +	if (IS_GT_IP_STEP(GFX, rq->engine->gt, IP_VER(12, 70), A0, B0) ||
> +	    IS_GT_IP_STEP(GFX, rq->engine->gt, IP_VER(12, 71), A0, B0)) {
>   		u32 *cs;
>   
>   		/* dummy PIPE_CONTROL + depth flush */
> @@ -755,6 +755,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
>   u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
>   {
>   	struct drm_i915_private *i915 = rq->i915;
> +	struct intel_gt *gt = rq->engine->gt;
>   	u32 flags = (PIPE_CONTROL_CS_STALL |
>   		     PIPE_CONTROL_TLB_INVALIDATE |
>   		     PIPE_CONTROL_TILE_CACHE_FLUSH |
> @@ -765,8 +766,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
>   		     PIPE_CONTROL_FLUSH_ENABLE);
>   
>   	/* Wa_14016712196 */
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
> +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0))
>   		/* dummy PIPE_CONTROL + depth flush */
>   		cs = gen12_emit_pipe_control(cs, 0,
>   					     PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> index 0b414eae1683..c66373176f6c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
>   		gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
>   	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
>   		/* Wa_14016747170 */
> -		if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -		    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +		if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
> +		    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0))
>   			fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
>   					     intel_uncore_read(gt->uncore,
>   							       MTL_GT_ACTIVITY_FACTOR));
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 1b710102390b..8057cc5800b3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1377,8 +1377,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
>   					      cs, GEN12_GFX_CCS_AUX_NV);
>   
>   	/* Wa_16014892111 */
> -	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_GT_IP_STEP(GFX, ce->engine->gt, IP_VER(12, 70), A0, B0) ||
> +	    IS_GT_IP_STEP(GFX, ce->engine->gt, IP_VER(12, 71), A0, B0) ||
>   	    IS_DG2(ce->engine->i915))
>   		cs = dg2_emit_draw_watermark_setting(cs);
>   
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 1ff7b42521c9..efe83157ef78 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -1641,7 +1641,7 @@ bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
>   	if (GRAPHICS_VER(gt->i915) < 11)
>   		return false;
>   
> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
> +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0))
>   		return true;
>   
>   	if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index c4663541c5dd..b7cf1790c827 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -808,24 +808,24 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
>   static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
>   				     struct i915_wa_list *wal)
>   {
> -	struct drm_i915_private *i915 = engine->i915;
> +	struct intel_gt *gt = engine->gt;
>   
>   	dg2_ctx_gt_tuning_init(engine, wal);
>   
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), B0, FOREVER) ||
> +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), B0, FOREVER))
>   		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
>   }
>   
>   static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
>   				       struct i915_wa_list *wal)
>   {
> -	struct drm_i915_private *i915 = engine->i915;
> +	struct intel_gt *gt = engine->gt;
>   
>   	xelpg_ctx_gt_tuning_init(engine, wal);
>   
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
> +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0)) {
>   		/* Wa_14014947963 */
>   		wa_masked_field_set(wal, VF_PREEMPTION,
>   				    PREEMPTION_VERTEX_COUNT, 0x4000);
> @@ -1746,8 +1746,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>   	/* Wa_22016670082 */
>   	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
>   
> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
> +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0)) {
>   		/* Wa_14014830051 */
>   		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
>   
> @@ -2424,16 +2424,17 @@ static void
>   rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>   {
>   	struct drm_i915_private *i915 = engine->i915;
> +	struct intel_gt *gt = engine->gt;
>   
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
> +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0)) {
>   		/* Wa_22014600077 */
>   		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>   				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
>   	}
>   
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
> +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0) ||
>   	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>   	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>   		/* Wa_1509727124 */
> @@ -2443,7 +2444,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>   
>   	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>   	    IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
> +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0)) {
>   		/* Wa_22012856258 */
>   		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
>   				 GEN12_DISABLE_READ_SUPPRESSION);
> @@ -3008,8 +3009,9 @@ static void
>   general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>   {
>   	struct drm_i915_private *i915 = engine->i915;
> +	struct intel_gt *gt = engine->gt;
>   
> -	add_render_compute_tuning_settings(engine->gt, wal);
> +	add_render_compute_tuning_settings(gt, wal);
>   
>   	if (GRAPHICS_VER(i915) >= 11) {
>   		/* This is not a Wa (although referred to as
> @@ -3030,13 +3032,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>   				 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>   	}
>   
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), B0, FOREVER) ||
> +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), B0, FOREVER))
>   		/* Wa_14017856879 */
>   		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
>   
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
> +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0))
>   		/*
>   		 * Wa_14017066071
>   		 * Wa_14017654203
> @@ -3044,13 +3046,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>   		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
>   				 MTL_DISABLE_SAMPLER_SC_OOO);
>   
> -	if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0))
>   		/* Wa_22015279794 */
>   		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>   				 DISABLE_PREFETCH_INTO_IC);
>   
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
> +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0) ||
>   	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>   	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>   		/* Wa_22013037850 */
> @@ -3058,16 +3060,16 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>   				DISABLE_128B_EVICTION_COMMAND_UDW);
>   	}
>   
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
> +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0) ||
>   	    IS_PONTEVECCHIO(i915) ||
>   	    IS_DG2(i915)) {
>   		/* Wa_22014226127 */
>   		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
>   	}
>   
> -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
> +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0) ||
>   	    IS_DG2(i915)) {
>   		/* Wa_18017747507 */
>   		wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 1e532981f74e..c733d43816f4 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>   		flags |= GUC_WA_GAM_CREDITS;
>   
>   	/* Wa_14014475959 */
> -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
>   	    IS_DG2(gt->i915))
>   		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
>   
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 1bd5d8f7c40b..01d6534dc7e8 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -4265,7 +4265,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
>   
>   	/* Wa_14014475959:dg2 */
>   	if (engine->class == COMPUTE_CLASS)
> -		if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> +		if (IS_GT_IP_STEP(GFX, engine->gt, IP_VER(12, 70), A0, B0) ||
>   		    IS_DG2(engine->i915))
>   			engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
>   
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6bb825d40451..687745550355 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -436,6 +436,9 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
>   #define __GT_VER_FULL(gt) (__IS_MEDIA_GT(gt) ? \
>   			   MEDIA_VER_FULL((gt)->i915) : \
>   			   GRAPHICS_VER_FULL((gt)->i915))
> +#define __GT_STEP(gt) (__IS_MEDIA_GT(gt) ? \
> +		       INTEL_MEDIA_STEP((gt)->i915) : \
> +		       INTEL_GRAPHICS_STEP((gt)->i915))
>   
>   /*
>    * Check that a GT contains IP of the specified type and within the specified
> @@ -454,6 +457,29 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
>   	 __GT_VER_FULL(gt) >= (from) && \
>   	 __GT_VER_FULL(gt) <= (until)))
>   
> +/*
> + * Check whether a GT contains the specific IP version and a stepping within
> + * the specified range [from, until).  The lower stepping bound is inclusive,
> + * the upper bound is exclusive (corresponding to the first hardware stepping
> + * at when the workaround is no longer needed).  E.g.,
> + *
> + *    IS_GT_IP_STEP(GFX, IP_VER(12, 70), A0, B0)
> + *    IS_GT_IP_STEP(MEDIA, IP_VER(13, 00), B1, D0)
> + *    IS_GT_IP_STEP(GFX, IP_VER(12, 71), B1, FOREVER)

Same as previous patch, I'd really like that we have the GT type split 
out from the macro.

Btw I found a way to implement optional macro arguments on Stack 
Overflow and we could have that too, with default stepping [FOREVER, 
FOREVER] if we wanted.

That way we could only have IS_GT_IP and call it as either IS_GT_IP(gt, 
IP_VER()) or IS_GT_IP(gt, IP_VER(), A0, B0).

But I think *only* if the compiler ends up smart enough not to pollute 
the code with impossible default forever-forever checks.

Possibly a step too far.

Regards,

Tvrtko

> + *
> + * "FOREVER" can be passed as the upper stepping bound for workarounds that
> + * have no upper bound on steppings of the specified IP version.
> + *
> + * Note that media version checks with this macro will only work on platforms
> + * with standalone media design (i.e., media version 13 and higher).
> + */
> +#define IS_GT_IP_STEP(type, gt, ipver, since, until) \
> +	(BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
> +	 (__IS_##type##_GT(gt) && \
> +	  __GT_VER_FULL(gt) == ipver && \
> +	  __GT_STEP(gt) >= STEP_##since && \
> +	  __GT_STEP(gt) <= STEP_##until))
> +
>   #define MEDIA_VER(i915)			(RUNTIME_INFO(i915)->media.ip.ver)
>   #define MEDIA_VER_FULL(i915)		IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
>   					       RUNTIME_INFO(i915)->media.ip.rel)
> @@ -710,10 +736,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>   #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
>   	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
>   
> -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
> -	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
> -	 IS_GRAPHICS_STEP(__i915, since, until))
> -
>   #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
>   	(IS_METEORLAKE(__i915) && \
>   	 IS_DISPLAY_STEP(__i915, since, until))

Re: [Intel-gfx] [PATCH v2 1/9] drm/i915: Consolidate condition for Wa_22011802037

[Matt Roper]

On Tue, Jul 25, 2023 at 11:21:34AM +0200, Andi Shyti wrote:
> Hi Matt,
> 
> > +/*
> > + * Wa_22011802037 requires that we (or the GuC) ensure that no command
> > + * streamers are executing MI_FORCE_WAKE while an engine reset is initiated.
> > + */
> > +bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
> 
> I've seen this format in a recent Jonathan's patch and I see it
> becoming a pattern in the future. Should we already agree on the
> naming? Would intel_needs_wa_22011802037() be sufficient? Or a

When a helper like this is static to one function, I usually just use
needs_wa_#####() as a name.  But when it's exported and used in several
files, I think it's best to give it a meaningful prefix where possible.
In this case intel_reset.c doesn't use a consistent namespace like some
of our other files, but intel_engine_reset_* seemed like an appropriate
prefix that clarifies where this code comes from and what it's general
scope is.

> prefix as intel_wa_* for all the similar functions?

I had a series a year or two ago that disassociated workaround bounds
from workaround implementations and changed all workaround conditions
into something like 'if (I915_WA(foo))' but we ultimately abandoned that
on i915 and shifted the effort over to the Xe driver instead (where the
"OOB" workarounds follow a somewhat similar idea).


Matt

> 
> Andi
> 
> > +{
> > +	if (GRAPHICS_VER(gt->i915) < 11)
> > +		return false;
> > +
> > +	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
> > +		return true;
> > +
> > +	if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
> > +		return false;
> > +
> > +	return true;
> > +}

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version

[Matt Roper]

On Tue, Jul 25, 2023 at 01:02:54PM +0100, Tvrtko Ursulin wrote:
> 
> On 25/07/2023 01:13, Matt Roper wrote:
> > Although some of our Xe_LPG workarounds were already being applied based
> > on IP version correctly, others were matching on MTL as a base platform,
> > which is incorrect.  Although MTL is the only platform right now that
> > uses Xe_LPG IP, this may not always be the case.  If a future platform
> > re-uses this graphics IP, the same workarounds should be applied, even
> > if it isn't a "MTL" platform.
> > 
> > We were also incorrectly applying Xe_LPG workarounds/tuning to the
> > Xe_LPM+ media IP in one or two places; we should make sure that we don't
> > try to apply graphics workarounds to the media GT and vice versa where
> > they don't belong.  A new helper macro IS_GT_IP_RANGE() is added to help
> > ensure this is handled properly -- it checks that the GT matches the IP
> > type being tested as well as the IP version falling in the proper range.
> > 
> > Note that many of the stepping-based workarounds are still incorrectly
> > checking for a MTL base platform; that will be remedied in a later
> > patch.
> > 
> > v2:
> >   - Rework macro into a slightly more generic IS_GT_IP_RANGE() that can
> >     be used for either GFX or MEDIA checks.
> > 
> > Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >   drivers/gpu/drm/i915/gt/intel_workarounds.c | 38 +++++++++++----------
> >   drivers/gpu/drm/i915/i915_drv.h             | 23 +++++++++++++
> >   2 files changed, 43 insertions(+), 18 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index d8a1eaa44e69..c4663541c5dd 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -805,8 +805,8 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> >   	wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
> >   }
> > -static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> > -				   struct i915_wa_list *wal)
> > +static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> > +				     struct i915_wa_list *wal)
> >   {
> >   	struct drm_i915_private *i915 = engine->i915;
> > @@ -817,12 +817,12 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> >   		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
> >   }
> > -static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > -				     struct i915_wa_list *wal)
> > +static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
> > +				       struct i915_wa_list *wal)
> >   {
> >   	struct drm_i915_private *i915 = engine->i915;
> > -	mtl_ctx_gt_tuning_init(engine, wal);
> > +	xelpg_ctx_gt_tuning_init(engine, wal);
> >   	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> >   	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> > @@ -931,8 +931,8 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
> >   	if (engine->class != RENDER_CLASS)
> >   		goto done;
> > -	if (IS_METEORLAKE(i915))
> > -		mtl_ctx_workarounds_init(engine, wal);
> > +	if (IS_GT_IP_RANGE(GFX, engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
> > +		xelpg_ctx_workarounds_init(engine, wal);
> >   	else if (IS_PONTEVECCHIO(i915))
> >   		; /* noop; none at this time */
> >   	else if (IS_DG2(i915))
> > @@ -1790,10 +1790,8 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> >    */
> >   static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
> >   {
> > -	if (IS_METEORLAKE(gt->i915)) {
> > -		if (gt->type != GT_MEDIA)
> > -			wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
> > -
> > +	if (IS_GT_IP_RANGE(GFX, gt, IP_VER(12, 70), IP_VER(12, 71))) {
> > +		wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
> >   		wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
> >   	}
> > @@ -1825,7 +1823,7 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
> >   		return;
> >   	}
> > -	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> > +	if (IS_GT_IP_RANGE(GFX, gt, IP_VER(12, 70), IP_VER(12, 71)))
> >   		xelpg_gt_workarounds_init(gt, wal);
> >   	else if (IS_PONTEVECCHIO(i915))
> >   		pvc_gt_workarounds_init(gt, wal);
> > @@ -2293,7 +2291,7 @@ static void pvc_whitelist_build(struct intel_engine_cs *engine)
> >   	blacklist_trtt(engine);
> >   }
> > -static void mtl_whitelist_build(struct intel_engine_cs *engine)
> > +static void xelpg_whitelist_build(struct intel_engine_cs *engine)
> >   {
> >   	struct i915_wa_list *w = &engine->whitelist;
> > @@ -2315,8 +2313,10 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> >   	wa_init_start(w, engine->gt, "whitelist", engine->name);
> > -	if (IS_METEORLAKE(i915))
> > -		mtl_whitelist_build(engine);
> > +	if (engine->gt->type == GT_MEDIA)
> > +		; /* none yet */
> > +	else if (IS_GT_IP_RANGE(GFX, engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
> > +		xelpg_whitelist_build(engine);
> >   	else if (IS_PONTEVECCHIO(i915))
> >   		pvc_whitelist_build(engine);
> >   	else if (IS_DG2(i915))
> > @@ -2974,10 +2974,12 @@ ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> >    * function invoked by __intel_engine_init_ctx_wa().
> >    */
> >   static void
> > -add_render_compute_tuning_settings(struct drm_i915_private *i915,
> > +add_render_compute_tuning_settings(struct intel_gt *gt,
> >   				   struct i915_wa_list *wal)
> >   {
> > -	if (IS_METEORLAKE(i915) || IS_DG2(i915))
> > +	struct drm_i915_private *i915 = gt->i915;
> > +
> > +	if (IS_GT_IP_RANGE(GFX, gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))
> >   		wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
> >   	/*
> > @@ -3007,7 +3009,7 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> >   {
> >   	struct drm_i915_private *i915 = engine->i915;
> > -	add_render_compute_tuning_settings(i915, wal);
> > +	add_render_compute_tuning_settings(engine->gt, wal);
> >   	if (GRAPHICS_VER(i915) >= 11) {
> >   		/* This is not a Wa (although referred to as
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 682ef2b5c7d5..6bb825d40451 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -431,6 +431,29 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
> >   #define IS_GRAPHICS_VER(i915, from, until) \
> >   	(GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
> > +#define __IS_MEDIA_GT(gt) ((gt)->type == GT_MEDIA)
> > +#define __IS_GFX_GT(gt) (!__IS_MEDIA_GT(gt))
> > +#define __GT_VER_FULL(gt) (__IS_MEDIA_GT(gt) ? \
> > +			   MEDIA_VER_FULL((gt)->i915) : \
> > +			   GRAPHICS_VER_FULL((gt)->i915))
> > +
> > +/*
> > + * Check that a GT contains IP of the specified type and within the specified
> > + * IP range.  E.g.,
> > + *
> > + *    IS_GT_IP_RANGE(GFX, IP_VER(12, 70), IP_VER(12, 71))
> > + *    IS_GT_IP_RANGE(MEDIA, IP_VER(13, 00), IP_VER(18, 02))
> 
> I think without the magic GFX/MEDIA first argument would be better and more
> readable. That is simply IS_GT_IP_RANGE(gt, IP_VER(), IP_VER). GT type
> checks feel would be more readable on the outside, and some of them will
> even probably come from a level above. Even when split out on the same line
> it reads more readable to me, like:
> 
>   if (IS_MEDIA_GT(gt) && IS_GT_IP_RANGE(gt, IP_VER(), IP_VER())
> 

Hmm, that's the kind of logic I was kind of hoping we could eliminate
with this macro.  With hardware going forward, any IS_GT_IP_RANGE
without an associated GT check is going to be a bug so I was really
hoping to make it non-optional and ensure that there's always context
directly associated with the version numbers (since the numbers are
meaningless on their own without being tied to a specific IP type).
While keeping the check separate means you might be able to move the
type check to a higher layer of the code, it also means you're going to
be left with a bunch of stuff like

        if (IS_GT_IP_RANGE(gt, IP_VER(17, 0), IP_VER(18, 2)))

and it may not be as clear what IP(s) this is supposed to match on.


Matt

> Regards,
> 
> Tvrtko
> 
> > + *
> > + * Note that media version checks with this macro will only work on platforms
> > + * with standalone media design (i.e., media version 13 and higher).
> > + */
> > +#define IS_GT_IP_RANGE(type, gt, from, until) ( \
> > +	BUILD_BUG_ON_ZERO(from < IP_VER(2, 0)) + \
> > +	BUILD_BUG_ON_ZERO(until < from) + \
> > +	(__IS_##type##_GT(gt) && \
> > +	 __GT_VER_FULL(gt) >= (from) && \
> > +	 __GT_VER_FULL(gt) <= (until)))
> > +
> >   #define MEDIA_VER(i915)			(RUNTIME_INFO(i915)->media.ip.ver)
> >   #define MEDIA_VER_FULL(i915)		IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
> >   					       RUNTIME_INFO(i915)->media.ip.rel)

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH v2 4/9] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP

[Matt Roper]

On Tue, Jul 25, 2023 at 12:04:43PM +0200, Andi Shyti wrote:
> Hi Matt,
> 
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -436,6 +436,9 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
> >  #define __GT_VER_FULL(gt) (__IS_MEDIA_GT(gt) ? \
> >  			   MEDIA_VER_FULL((gt)->i915) : \
> >  			   GRAPHICS_VER_FULL((gt)->i915))
> > +#define __GT_STEP(gt) (__IS_MEDIA_GT(gt) ? \
> > +		       INTEL_MEDIA_STEP((gt)->i915) : \
> > +		       INTEL_GRAPHICS_STEP((gt)->i915))
> >  
> >  /*
> >   * Check that a GT contains IP of the specified type and within the specified
> > @@ -454,6 +457,29 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
> >  	 __GT_VER_FULL(gt) >= (from) && \
> >  	 __GT_VER_FULL(gt) <= (until)))
> >  
> > +/*
> > + * Check whether a GT contains the specific IP version and a stepping within
> > + * the specified range [from, until).  The lower stepping bound is inclusive,
> > + * the upper bound is exclusive (corresponding to the first hardware stepping
> > + * at when the workaround is no longer needed).  E.g.,
> > + *
> > + *    IS_GT_IP_STEP(GFX, IP_VER(12, 70), A0, B0)
> > + *    IS_GT_IP_STEP(MEDIA, IP_VER(13, 00), B1, D0)
> > + *    IS_GT_IP_STEP(GFX, IP_VER(12, 71), B1, FOREVER)
> > + *
> > + * "FOREVER" can be passed as the upper stepping bound for workarounds that
> > + * have no upper bound on steppings of the specified IP version.
> > + *
> > + * Note that media version checks with this macro will only work on platforms
> > + * with standalone media design (i.e., media version 13 and higher).
> > + */
> > +#define IS_GT_IP_STEP(type, gt, ipver, since, until) \
> > +	(BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
> > +	 (__IS_##type##_GT(gt) && \
> > +	  __GT_VER_FULL(gt) == ipver && \
> > +	  __GT_STEP(gt) >= STEP_##since && \
> > +	  __GT_STEP(gt) <= STEP_##until))
> > +
> 
> Should this go in intel_gt.h?
> 
> >  #define MEDIA_VER(i915)			(RUNTIME_INFO(i915)->media.ip.ver)
> >  #define MEDIA_VER_FULL(i915)		IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
> >  					       RUNTIME_INFO(i915)->media.ip.rel)
> > @@ -710,10 +736,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >  #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
> >  	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
> >  
> > -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
> > -	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
> > -	 IS_GRAPHICS_STEP(__i915, since, until))
> > -
> 
> For completeness I would either leave this or remove all the
> above. Or I would make this a wrapper around IS_GT_IP_STEP() with
> a compile error if we are outside the MTL range.

If we leave this, then someone might try to use it in future patches.
Every single place this macro gets used will always be a driver bug,
which is the motivation for killing it off.

In contast, the ones for older platforms are correct and should remain.
Before the hardware switched to the disaggretated IP design, steppings
for each IP were directly tied to the base platform rather than the IP
version, and we inferred from the PCI revid.


Matt

> 
> Andi
> 
> >  #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
> >  	(IS_METEORLAKE(__i915) && \
> >  	 IS_DISPLAY_STEP(__i915, since, until))
> > -- 
> > 2.41.0

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version

[Tvrtko Ursulin]

On 25/07/2023 16:35, Matt Roper wrote:
> On Tue, Jul 25, 2023 at 01:02:54PM +0100, Tvrtko Ursulin wrote:
>>
>> On 25/07/2023 01:13, Matt Roper wrote:
>>> Although some of our Xe_LPG workarounds were already being applied based
>>> on IP version correctly, others were matching on MTL as a base platform,
>>> which is incorrect.  Although MTL is the only platform right now that
>>> uses Xe_LPG IP, this may not always be the case.  If a future platform
>>> re-uses this graphics IP, the same workarounds should be applied, even
>>> if it isn't a "MTL" platform.
>>>
>>> We were also incorrectly applying Xe_LPG workarounds/tuning to the
>>> Xe_LPM+ media IP in one or two places; we should make sure that we don't
>>> try to apply graphics workarounds to the media GT and vice versa where
>>> they don't belong.  A new helper macro IS_GT_IP_RANGE() is added to help
>>> ensure this is handled properly -- it checks that the GT matches the IP
>>> type being tested as well as the IP version falling in the proper range.
>>>
>>> Note that many of the stepping-based workarounds are still incorrectly
>>> checking for a MTL base platform; that will be remedied in a later
>>> patch.
>>>
>>> v2:
>>>    - Rework macro into a slightly more generic IS_GT_IP_RANGE() that can
>>>      be used for either GFX or MEDIA checks.
>>>
>>> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
>>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/gt/intel_workarounds.c | 38 +++++++++++----------
>>>    drivers/gpu/drm/i915/i915_drv.h             | 23 +++++++++++++
>>>    2 files changed, 43 insertions(+), 18 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> index d8a1eaa44e69..c4663541c5dd 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> @@ -805,8 +805,8 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
>>>    	wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
>>>    }
>>> -static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
>>> -				   struct i915_wa_list *wal)
>>> +static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
>>> +				     struct i915_wa_list *wal)
>>>    {
>>>    	struct drm_i915_private *i915 = engine->i915;
>>> @@ -817,12 +817,12 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
>>>    		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
>>>    }
>>> -static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
>>> -				     struct i915_wa_list *wal)
>>> +static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
>>> +				       struct i915_wa_list *wal)
>>>    {
>>>    	struct drm_i915_private *i915 = engine->i915;
>>> -	mtl_ctx_gt_tuning_init(engine, wal);
>>> +	xelpg_ctx_gt_tuning_init(engine, wal);
>>>    	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>    	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>>> @@ -931,8 +931,8 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>>>    	if (engine->class != RENDER_CLASS)
>>>    		goto done;
>>> -	if (IS_METEORLAKE(i915))
>>> -		mtl_ctx_workarounds_init(engine, wal);
>>> +	if (IS_GT_IP_RANGE(GFX, engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
>>> +		xelpg_ctx_workarounds_init(engine, wal);
>>>    	else if (IS_PONTEVECCHIO(i915))
>>>    		; /* noop; none at this time */
>>>    	else if (IS_DG2(i915))
>>> @@ -1790,10 +1790,8 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>>>     */
>>>    static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
>>>    {
>>> -	if (IS_METEORLAKE(gt->i915)) {
>>> -		if (gt->type != GT_MEDIA)
>>> -			wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
>>> -
>>> +	if (IS_GT_IP_RANGE(GFX, gt, IP_VER(12, 70), IP_VER(12, 71))) {
>>> +		wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
>>>    		wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
>>>    	}
>>> @@ -1825,7 +1823,7 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
>>>    		return;
>>>    	}
>>> -	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
>>> +	if (IS_GT_IP_RANGE(GFX, gt, IP_VER(12, 70), IP_VER(12, 71)))
>>>    		xelpg_gt_workarounds_init(gt, wal);
>>>    	else if (IS_PONTEVECCHIO(i915))
>>>    		pvc_gt_workarounds_init(gt, wal);
>>> @@ -2293,7 +2291,7 @@ static void pvc_whitelist_build(struct intel_engine_cs *engine)
>>>    	blacklist_trtt(engine);
>>>    }
>>> -static void mtl_whitelist_build(struct intel_engine_cs *engine)
>>> +static void xelpg_whitelist_build(struct intel_engine_cs *engine)
>>>    {
>>>    	struct i915_wa_list *w = &engine->whitelist;
>>> @@ -2315,8 +2313,10 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>>>    	wa_init_start(w, engine->gt, "whitelist", engine->name);
>>> -	if (IS_METEORLAKE(i915))
>>> -		mtl_whitelist_build(engine);
>>> +	if (engine->gt->type == GT_MEDIA)
>>> +		; /* none yet */
>>> +	else if (IS_GT_IP_RANGE(GFX, engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
>>> +		xelpg_whitelist_build(engine);
>>>    	else if (IS_PONTEVECCHIO(i915))
>>>    		pvc_whitelist_build(engine);
>>>    	else if (IS_DG2(i915))
>>> @@ -2974,10 +2974,12 @@ ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>>     * function invoked by __intel_engine_init_ctx_wa().
>>>     */
>>>    static void
>>> -add_render_compute_tuning_settings(struct drm_i915_private *i915,
>>> +add_render_compute_tuning_settings(struct intel_gt *gt,
>>>    				   struct i915_wa_list *wal)
>>>    {
>>> -	if (IS_METEORLAKE(i915) || IS_DG2(i915))
>>> +	struct drm_i915_private *i915 = gt->i915;
>>> +
>>> +	if (IS_GT_IP_RANGE(GFX, gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))
>>>    		wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
>>>    	/*
>>> @@ -3007,7 +3009,7 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>>>    {
>>>    	struct drm_i915_private *i915 = engine->i915;
>>> -	add_render_compute_tuning_settings(i915, wal);
>>> +	add_render_compute_tuning_settings(engine->gt, wal);
>>>    	if (GRAPHICS_VER(i915) >= 11) {
>>>    		/* This is not a Wa (although referred to as
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>> index 682ef2b5c7d5..6bb825d40451 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -431,6 +431,29 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
>>>    #define IS_GRAPHICS_VER(i915, from, until) \
>>>    	(GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
>>> +#define __IS_MEDIA_GT(gt) ((gt)->type == GT_MEDIA)
>>> +#define __IS_GFX_GT(gt) (!__IS_MEDIA_GT(gt))
>>> +#define __GT_VER_FULL(gt) (__IS_MEDIA_GT(gt) ? \
>>> +			   MEDIA_VER_FULL((gt)->i915) : \
>>> +			   GRAPHICS_VER_FULL((gt)->i915))
>>> +
>>> +/*
>>> + * Check that a GT contains IP of the specified type and within the specified
>>> + * IP range.  E.g.,
>>> + *
>>> + *    IS_GT_IP_RANGE(GFX, IP_VER(12, 70), IP_VER(12, 71))
>>> + *    IS_GT_IP_RANGE(MEDIA, IP_VER(13, 00), IP_VER(18, 02))
>>
>> I think without the magic GFX/MEDIA first argument would be better and more
>> readable. That is simply IS_GT_IP_RANGE(gt, IP_VER(), IP_VER). GT type
>> checks feel would be more readable on the outside, and some of them will
>> even probably come from a level above. Even when split out on the same line
>> it reads more readable to me, like:
>>
>>    if (IS_MEDIA_GT(gt) && IS_GT_IP_RANGE(gt, IP_VER(), IP_VER())
>>
> 
> Hmm, that's the kind of logic I was kind of hoping we could eliminate
> with this macro.  With hardware going forward, any IS_GT_IP_RANGE
> without an associated GT check is going to be a bug so I was really
> hoping to make it non-optional and ensure that there's always context
> directly associated with the version numbers (since the numbers are
> meaningless on their own without being tied to a specific IP type).
> While keeping the check separate means you might be able to move the
> type check to a higher layer of the code, it also means you're going to
> be left with a bunch of stuff like
> 
>          if (IS_GT_IP_RANGE(gt, IP_VER(17, 0), IP_VER(18, 2)))
> 
> and it may not be as clear what IP(s) this is supposed to match on.

I see.. how about IS_MEDIA_GT_IP_RANGE then? Or would that be going full 
circle by any chance? Just because I somehow find IS_GT_IP_RANGE(*GFX*, 
.. hard to parse. If this is not in a hurry perhaps wait for Jani to 
come back and provide a second opinion or another alternative.

Regards,

Tvrtko


> 
> Matt
> 
>> Regards,
>>
>> Tvrtko
>>
>>> + *
>>> + * Note that media version checks with this macro will only work on platforms
>>> + * with standalone media design (i.e., media version 13 and higher).
>>> + */
>>> +#define IS_GT_IP_RANGE(type, gt, from, until) ( \
>>> +	BUILD_BUG_ON_ZERO(from < IP_VER(2, 0)) + \
>>> +	BUILD_BUG_ON_ZERO(until < from) + \
>>> +	(__IS_##type##_GT(gt) && \
>>> +	 __GT_VER_FULL(gt) >= (from) && \
>>> +	 __GT_VER_FULL(gt) <= (until)))
>>> +
>>>    #define MEDIA_VER(i915)			(RUNTIME_INFO(i915)->media.ip.ver)
>>>    #define MEDIA_VER_FULL(i915)		IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
>>>    					       RUNTIME_INFO(i915)->media.ip.rel)
> 

Re: [Intel-gfx] [PATCH v2 4/9] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP

[Matt Roper]

On Tue, Jul 25, 2023 at 01:10:24PM +0100, Tvrtko Ursulin wrote:
> 
> On 25/07/2023 01:13, Matt Roper wrote:
> > Several workarounds are guarded by IS_MTL_GRAPHICS_STEP.  However none
> > of these workarounds are actually tied to MTL as a platform; they only
> > relate to the Xe_LPG graphics IP, regardless of what platform it appears
> > in.  At the moment MTL is the only platform that uses Xe_LPG with IP
> > versions 12.70 and 12.71, but we can't count on this being true in the
> > future.  Switch these to use a new IS_GT_IP_STEP() macro instead that is
> > purely based on IP version.  IS_GT_IP_STEP() is also GT-based rather
> > than device-based, which will help prevent mistakes where we
> > accidentally try to apply Xe_LPG graphics workarounds to the Xe_LPM+
> > media GT and vice-versa.
> > 
> > v2:
> >   - Switch to a more generic and shorter IS_GT_IP_STEP macro that can be
> >     used for both graphics and media IP (and any other kind of GTs that
> >     show up in the future).
> > 
> > Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >   .../drm/i915/display/skl_universal_plane.c    |  4 +-
> >   drivers/gpu/drm/i915/gt/gen8_engine_cs.c      |  9 ++--
> >   drivers/gpu/drm/i915/gt/intel_gt_mcr.c        |  4 +-
> >   drivers/gpu/drm/i915/gt/intel_lrc.c           |  4 +-
> >   drivers/gpu/drm/i915/gt/intel_reset.c         |  2 +-
> >   drivers/gpu/drm/i915/gt/intel_workarounds.c   | 52 ++++++++++---------
> >   drivers/gpu/drm/i915/gt/uc/intel_guc.c        |  2 +-
> >   .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  2 +-
> >   drivers/gpu/drm/i915/i915_drv.h               | 30 +++++++++--
> >   9 files changed, 67 insertions(+), 42 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 6b01a0b68b97..5fd8a42b3ec1 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
> >   				 enum pipe pipe, enum plane_id plane_id)
> >   {
> >   	/* Wa_14017240301 */
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > +	if (IS_GT_IP_STEP(GFX, to_gt(i915), IP_VER(12, 70), A0, B0) ||
> > +	    IS_GT_IP_STEP(GFX, to_gt(i915), IP_VER(12, 71), A0, B0))
> >   		return false;
> >   	/* Wa_22011186057 */
> > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > index 3ba20ea030e8..9d04591f3b4a 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
> >   static int mtl_dummy_pipe_control(struct i915_request *rq)
> >   {
> >   	/* Wa_14016712196 */
> > -	if (IS_MTL_GRAPHICS_STEP(rq->i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(rq->i915, P, STEP_A0, STEP_B0)) {
> > +	if (IS_GT_IP_STEP(GFX, rq->engine->gt, IP_VER(12, 70), A0, B0) ||
> > +	    IS_GT_IP_STEP(GFX, rq->engine->gt, IP_VER(12, 71), A0, B0)) {
> >   		u32 *cs;
> >   		/* dummy PIPE_CONTROL + depth flush */
> > @@ -755,6 +755,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
> >   u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> >   {
> >   	struct drm_i915_private *i915 = rq->i915;
> > +	struct intel_gt *gt = rq->engine->gt;
> >   	u32 flags = (PIPE_CONTROL_CS_STALL |
> >   		     PIPE_CONTROL_TLB_INVALIDATE |
> >   		     PIPE_CONTROL_TILE_CACHE_FLUSH |
> > @@ -765,8 +766,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> >   		     PIPE_CONTROL_FLUSH_ENABLE);
> >   	/* Wa_14016712196 */
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
> > +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0))
> >   		/* dummy PIPE_CONTROL + depth flush */
> >   		cs = gen12_emit_pipe_control(cs, 0,
> >   					     PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > index 0b414eae1683..c66373176f6c 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
> >   		gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
> >   	} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
> >   		/* Wa_14016747170 */
> > -		if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -		    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > +		if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
> > +		    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0))
> >   			fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
> >   					     intel_uncore_read(gt->uncore,
> >   							       MTL_GT_ACTIVITY_FACTOR));
> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > index 1b710102390b..8057cc5800b3 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > @@ -1377,8 +1377,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
> >   					      cs, GEN12_GFX_CCS_AUX_NV);
> >   	/* Wa_16014892111 */
> > -	if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
> > +	if (IS_GT_IP_STEP(GFX, ce->engine->gt, IP_VER(12, 70), A0, B0) ||
> > +	    IS_GT_IP_STEP(GFX, ce->engine->gt, IP_VER(12, 71), A0, B0) ||
> >   	    IS_DG2(ce->engine->i915))
> >   		cs = dg2_emit_draw_watermark_setting(cs);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> > index 1ff7b42521c9..efe83157ef78 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> > @@ -1641,7 +1641,7 @@ bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
> >   	if (GRAPHICS_VER(gt->i915) < 11)
> >   		return false;
> > -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
> > +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0))
> >   		return true;
> >   	if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index c4663541c5dd..b7cf1790c827 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -808,24 +808,24 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> >   static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> >   				     struct i915_wa_list *wal)
> >   {
> > -	struct drm_i915_private *i915 = engine->i915;
> > +	struct intel_gt *gt = engine->gt;
> >   	dg2_ctx_gt_tuning_init(engine, wal);
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> > +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), B0, FOREVER) ||
> > +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), B0, FOREVER))
> >   		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
> >   }
> >   static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
> >   				       struct i915_wa_list *wal)
> >   {
> > -	struct drm_i915_private *i915 = engine->i915;
> > +	struct intel_gt *gt = engine->gt;
> >   	xelpg_ctx_gt_tuning_init(engine, wal);
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> > +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
> > +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0)) {
> >   		/* Wa_14014947963 */
> >   		wa_masked_field_set(wal, VF_PREEMPTION,
> >   				    PREEMPTION_VERTEX_COUNT, 0x4000);
> > @@ -1746,8 +1746,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> >   	/* Wa_22016670082 */
> >   	wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
> > -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> > +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
> > +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0)) {
> >   		/* Wa_14014830051 */
> >   		wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
> > @@ -2424,16 +2424,17 @@ static void
> >   rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> >   {
> >   	struct drm_i915_private *i915 = engine->i915;
> > +	struct intel_gt *gt = engine->gt;
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> > +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
> > +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0)) {
> >   		/* Wa_22014600077 */
> >   		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> >   				 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
> >   	}
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
> > +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0) ||
> >   	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> >   	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> >   		/* Wa_1509727124 */
> > @@ -2443,7 +2444,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> >   	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> >   	    IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
> > +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0)) {
> >   		/* Wa_22012856258 */
> >   		wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
> >   				 GEN12_DISABLE_READ_SUPPRESSION);
> > @@ -3008,8 +3009,9 @@ static void
> >   general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> >   {
> >   	struct drm_i915_private *i915 = engine->i915;
> > +	struct intel_gt *gt = engine->gt;
> > -	add_render_compute_tuning_settings(engine->gt, wal);
> > +	add_render_compute_tuning_settings(gt, wal);
> >   	if (GRAPHICS_VER(i915) >= 11) {
> >   		/* This is not a Wa (although referred to as
> > @@ -3030,13 +3032,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> >   				 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
> >   	}
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> > +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), B0, FOREVER) ||
> > +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), B0, FOREVER))
> >   		/* Wa_14017856879 */
> >   		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
> > +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0))
> >   		/*
> >   		 * Wa_14017066071
> >   		 * Wa_14017654203
> > @@ -3044,13 +3046,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> >   		wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
> >   				 MTL_DISABLE_SAMPLER_SC_OOO);
> > -	if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0))
> >   		/* Wa_22015279794 */
> >   		wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> >   				 DISABLE_PREFETCH_INTO_IC);
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
> > +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0) ||
> >   	    IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> >   	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> >   		/* Wa_22013037850 */
> > @@ -3058,16 +3060,16 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> >   				DISABLE_128B_EVICTION_COMMAND_UDW);
> >   	}
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
> > +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0) ||
> >   	    IS_PONTEVECCHIO(i915) ||
> >   	    IS_DG2(i915)) {
> >   		/* Wa_22014226127 */
> >   		wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
> >   	}
> > -	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > -	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
> > +	    IS_GT_IP_STEP(GFX, gt, IP_VER(12, 71), A0, B0) ||
> >   	    IS_DG2(i915)) {
> >   		/* Wa_18017747507 */
> >   		wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > index 1e532981f74e..c733d43816f4 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
> >   		flags |= GUC_WA_GAM_CREDITS;
> >   	/* Wa_14014475959 */
> > -	if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> > +	if (IS_GT_IP_STEP(GFX, gt, IP_VER(12, 70), A0, B0) ||
> >   	    IS_DG2(gt->i915))
> >   		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index 1bd5d8f7c40b..01d6534dc7e8 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -4265,7 +4265,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
> >   	/* Wa_14014475959:dg2 */
> >   	if (engine->class == COMPUTE_CLASS)
> > -		if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> > +		if (IS_GT_IP_STEP(GFX, engine->gt, IP_VER(12, 70), A0, B0) ||
> >   		    IS_DG2(engine->i915))
> >   			engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 6bb825d40451..687745550355 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -436,6 +436,9 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
> >   #define __GT_VER_FULL(gt) (__IS_MEDIA_GT(gt) ? \
> >   			   MEDIA_VER_FULL((gt)->i915) : \
> >   			   GRAPHICS_VER_FULL((gt)->i915))
> > +#define __GT_STEP(gt) (__IS_MEDIA_GT(gt) ? \
> > +		       INTEL_MEDIA_STEP((gt)->i915) : \
> > +		       INTEL_GRAPHICS_STEP((gt)->i915))
> >   /*
> >    * Check that a GT contains IP of the specified type and within the specified
> > @@ -454,6 +457,29 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
> >   	 __GT_VER_FULL(gt) >= (from) && \
> >   	 __GT_VER_FULL(gt) <= (until)))
> > +/*
> > + * Check whether a GT contains the specific IP version and a stepping within
> > + * the specified range [from, until).  The lower stepping bound is inclusive,
> > + * the upper bound is exclusive (corresponding to the first hardware stepping
> > + * at when the workaround is no longer needed).  E.g.,
> > + *
> > + *    IS_GT_IP_STEP(GFX, IP_VER(12, 70), A0, B0)
> > + *    IS_GT_IP_STEP(MEDIA, IP_VER(13, 00), B1, D0)
> > + *    IS_GT_IP_STEP(GFX, IP_VER(12, 71), B1, FOREVER)
> 
> Same as previous patch, I'd really like that we have the GT type split out
> from the macro.
> 
> Btw I found a way to implement optional macro arguments on Stack Overflow
> and we could have that too, with default stepping [FOREVER, FOREVER] if we
> wanted.

Presumably we'd want [0, FOREVER) rather than [FOREVER, FOREVER],
otherwise we'd never match anything.

But I'm still questioning whether that would really help clarify
anything.  If we've lost the GT type check, then I don't see what
benefit a somewhat ambiguous IS_GT_IP() would provide over a more direct
"GRAPHICS_VER_FULL() == IP_VER()" that makes it clear what kind of
version we're checking for.  And we'd still need to handle version
ranges independently from stepping ranges since those need different
semantics.


Matt

> 
> That way we could only have IS_GT_IP and call it as either IS_GT_IP(gt,
> IP_VER()) or IS_GT_IP(gt, IP_VER(), A0, B0).
> 
> But I think *only* if the compiler ends up smart enough not to pollute the
> code with impossible default forever-forever checks.
> 
> Possibly a step too far.
> 
> Regards,
> 
> Tvrtko
> 
> > + *
> > + * "FOREVER" can be passed as the upper stepping bound for workarounds that
> > + * have no upper bound on steppings of the specified IP version.
> > + *
> > + * Note that media version checks with this macro will only work on platforms
> > + * with standalone media design (i.e., media version 13 and higher).
> > + */
> > +#define IS_GT_IP_STEP(type, gt, ipver, since, until) \
> > +	(BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
> > +	 (__IS_##type##_GT(gt) && \
> > +	  __GT_VER_FULL(gt) == ipver && \
> > +	  __GT_STEP(gt) >= STEP_##since && \
> > +	  __GT_STEP(gt) <= STEP_##until))
> > +
> >   #define MEDIA_VER(i915)			(RUNTIME_INFO(i915)->media.ip.ver)
> >   #define MEDIA_VER_FULL(i915)		IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
> >   					       RUNTIME_INFO(i915)->media.ip.rel)
> > @@ -710,10 +736,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >   #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
> >   	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
> > -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
> > -	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
> > -	 IS_GRAPHICS_STEP(__i915, since, until))
> > -
> >   #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
> >   	(IS_METEORLAKE(__i915) && \
> >   	 IS_DISPLAY_STEP(__i915, since, until))

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version

[Matt Roper]

On Tue, Jul 25, 2023 at 04:52:07PM +0100, Tvrtko Ursulin wrote:
> 
> On 25/07/2023 16:35, Matt Roper wrote:
> > On Tue, Jul 25, 2023 at 01:02:54PM +0100, Tvrtko Ursulin wrote:
> > > 
> > > On 25/07/2023 01:13, Matt Roper wrote:
> > > > Although some of our Xe_LPG workarounds were already being applied based
> > > > on IP version correctly, others were matching on MTL as a base platform,
> > > > which is incorrect.  Although MTL is the only platform right now that
> > > > uses Xe_LPG IP, this may not always be the case.  If a future platform
> > > > re-uses this graphics IP, the same workarounds should be applied, even
> > > > if it isn't a "MTL" platform.
> > > > 
> > > > We were also incorrectly applying Xe_LPG workarounds/tuning to the
> > > > Xe_LPM+ media IP in one or two places; we should make sure that we don't
> > > > try to apply graphics workarounds to the media GT and vice versa where
> > > > they don't belong.  A new helper macro IS_GT_IP_RANGE() is added to help
> > > > ensure this is handled properly -- it checks that the GT matches the IP
> > > > type being tested as well as the IP version falling in the proper range.
> > > > 
> > > > Note that many of the stepping-based workarounds are still incorrectly
> > > > checking for a MTL base platform; that will be remedied in a later
> > > > patch.
> > > > 
> > > > v2:
> > > >    - Rework macro into a slightly more generic IS_GT_IP_RANGE() that can
> > > >      be used for either GFX or MEDIA checks.
> > > > 
> > > > Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > > ---
> > > >    drivers/gpu/drm/i915/gt/intel_workarounds.c | 38 +++++++++++----------
> > > >    drivers/gpu/drm/i915/i915_drv.h             | 23 +++++++++++++
> > > >    2 files changed, 43 insertions(+), 18 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > index d8a1eaa44e69..c4663541c5dd 100644
> > > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > @@ -805,8 +805,8 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> > > >    	wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
> > > >    }
> > > > -static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> > > > -				   struct i915_wa_list *wal)
> > > > +static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> > > > +				     struct i915_wa_list *wal)
> > > >    {
> > > >    	struct drm_i915_private *i915 = engine->i915;
> > > > @@ -817,12 +817,12 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> > > >    		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
> > > >    }
> > > > -static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > > > -				     struct i915_wa_list *wal)
> > > > +static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
> > > > +				       struct i915_wa_list *wal)
> > > >    {
> > > >    	struct drm_i915_private *i915 = engine->i915;
> > > > -	mtl_ctx_gt_tuning_init(engine, wal);
> > > > +	xelpg_ctx_gt_tuning_init(engine, wal);
> > > >    	if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > > >    	    IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> > > > @@ -931,8 +931,8 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
> > > >    	if (engine->class != RENDER_CLASS)
> > > >    		goto done;
> > > > -	if (IS_METEORLAKE(i915))
> > > > -		mtl_ctx_workarounds_init(engine, wal);
> > > > +	if (IS_GT_IP_RANGE(GFX, engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
> > > > +		xelpg_ctx_workarounds_init(engine, wal);
> > > >    	else if (IS_PONTEVECCHIO(i915))
> > > >    		; /* noop; none at this time */
> > > >    	else if (IS_DG2(i915))
> > > > @@ -1790,10 +1790,8 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > > >     */
> > > >    static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
> > > >    {
> > > > -	if (IS_METEORLAKE(gt->i915)) {
> > > > -		if (gt->type != GT_MEDIA)
> > > > -			wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
> > > > -
> > > > +	if (IS_GT_IP_RANGE(GFX, gt, IP_VER(12, 70), IP_VER(12, 71))) {
> > > > +		wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
> > > >    		wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
> > > >    	}
> > > > @@ -1825,7 +1823,7 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
> > > >    		return;
> > > >    	}
> > > > -	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> > > > +	if (IS_GT_IP_RANGE(GFX, gt, IP_VER(12, 70), IP_VER(12, 71)))
> > > >    		xelpg_gt_workarounds_init(gt, wal);
> > > >    	else if (IS_PONTEVECCHIO(i915))
> > > >    		pvc_gt_workarounds_init(gt, wal);
> > > > @@ -2293,7 +2291,7 @@ static void pvc_whitelist_build(struct intel_engine_cs *engine)
> > > >    	blacklist_trtt(engine);
> > > >    }
> > > > -static void mtl_whitelist_build(struct intel_engine_cs *engine)
> > > > +static void xelpg_whitelist_build(struct intel_engine_cs *engine)
> > > >    {
> > > >    	struct i915_wa_list *w = &engine->whitelist;
> > > > @@ -2315,8 +2313,10 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> > > >    	wa_init_start(w, engine->gt, "whitelist", engine->name);
> > > > -	if (IS_METEORLAKE(i915))
> > > > -		mtl_whitelist_build(engine);
> > > > +	if (engine->gt->type == GT_MEDIA)
> > > > +		; /* none yet */
> > > > +	else if (IS_GT_IP_RANGE(GFX, engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
> > > > +		xelpg_whitelist_build(engine);
> > > >    	else if (IS_PONTEVECCHIO(i915))
> > > >    		pvc_whitelist_build(engine);
> > > >    	else if (IS_DG2(i915))
> > > > @@ -2974,10 +2974,12 @@ ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > >     * function invoked by __intel_engine_init_ctx_wa().
> > > >     */
> > > >    static void
> > > > -add_render_compute_tuning_settings(struct drm_i915_private *i915,
> > > > +add_render_compute_tuning_settings(struct intel_gt *gt,
> > > >    				   struct i915_wa_list *wal)
> > > >    {
> > > > -	if (IS_METEORLAKE(i915) || IS_DG2(i915))
> > > > +	struct drm_i915_private *i915 = gt->i915;
> > > > +
> > > > +	if (IS_GT_IP_RANGE(GFX, gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))
> > > >    		wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
> > > >    	/*
> > > > @@ -3007,7 +3009,7 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> > > >    {
> > > >    	struct drm_i915_private *i915 = engine->i915;
> > > > -	add_render_compute_tuning_settings(i915, wal);
> > > > +	add_render_compute_tuning_settings(engine->gt, wal);
> > > >    	if (GRAPHICS_VER(i915) >= 11) {
> > > >    		/* This is not a Wa (although referred to as
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > > index 682ef2b5c7d5..6bb825d40451 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > @@ -431,6 +431,29 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
> > > >    #define IS_GRAPHICS_VER(i915, from, until) \
> > > >    	(GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
> > > > +#define __IS_MEDIA_GT(gt) ((gt)->type == GT_MEDIA)
> > > > +#define __IS_GFX_GT(gt) (!__IS_MEDIA_GT(gt))
> > > > +#define __GT_VER_FULL(gt) (__IS_MEDIA_GT(gt) ? \
> > > > +			   MEDIA_VER_FULL((gt)->i915) : \
> > > > +			   GRAPHICS_VER_FULL((gt)->i915))
> > > > +
> > > > +/*
> > > > + * Check that a GT contains IP of the specified type and within the specified
> > > > + * IP range.  E.g.,
> > > > + *
> > > > + *    IS_GT_IP_RANGE(GFX, IP_VER(12, 70), IP_VER(12, 71))
> > > > + *    IS_GT_IP_RANGE(MEDIA, IP_VER(13, 00), IP_VER(18, 02))
> > > 
> > > I think without the magic GFX/MEDIA first argument would be better and more
> > > readable. That is simply IS_GT_IP_RANGE(gt, IP_VER(), IP_VER). GT type
> > > checks feel would be more readable on the outside, and some of them will
> > > even probably come from a level above. Even when split out on the same line
> > > it reads more readable to me, like:
> > > 
> > >    if (IS_MEDIA_GT(gt) && IS_GT_IP_RANGE(gt, IP_VER(), IP_VER())
> > > 
> > 
> > Hmm, that's the kind of logic I was kind of hoping we could eliminate
> > with this macro.  With hardware going forward, any IS_GT_IP_RANGE
> > without an associated GT check is going to be a bug so I was really
> > hoping to make it non-optional and ensure that there's always context
> > directly associated with the version numbers (since the numbers are
> > meaningless on their own without being tied to a specific IP type).
> > While keeping the check separate means you might be able to move the
> > type check to a higher layer of the code, it also means you're going to
> > be left with a bunch of stuff like
> > 
> >          if (IS_GT_IP_RANGE(gt, IP_VER(17, 0), IP_VER(18, 2)))
> > 
> > and it may not be as clear what IP(s) this is supposed to match on.
> 
> I see.. how about IS_MEDIA_GT_IP_RANGE then? Or would that be going full
> circle by any chance? Just because I somehow find IS_GT_IP_RANGE(*GFX*, ..
> hard to parse. If this is not in a hurry perhaps wait for Jani to come back
> and provide a second opinion or another alternative.

That's sort of going back to the design I had in v1 with
GT_GRAPHICS_RANGE() and GT_MEDIA_RANGE().

But yeah, there's no urgent rush on this, so I'm fine tabling this until
Jani gets back.


Matt

> 
> Regards,
> 
> Tvrtko
> 
> 
> > 
> > Matt
> > 
> > > Regards,
> > > 
> > > Tvrtko
> > > 
> > > > + *
> > > > + * Note that media version checks with this macro will only work on platforms
> > > > + * with standalone media design (i.e., media version 13 and higher).
> > > > + */
> > > > +#define IS_GT_IP_RANGE(type, gt, from, until) ( \
> > > > +	BUILD_BUG_ON_ZERO(from < IP_VER(2, 0)) + \
> > > > +	BUILD_BUG_ON_ZERO(until < from) + \
> > > > +	(__IS_##type##_GT(gt) && \
> > > > +	 __GT_VER_FULL(gt) >= (from) && \
> > > > +	 __GT_VER_FULL(gt) <= (until)))
> > > > +
> > > >    #define MEDIA_VER(i915)			(RUNTIME_INFO(i915)->media.ip.ver)
> > > >    #define MEDIA_VER_FULL(i915)		IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
> > > >    					       RUNTIME_INFO(i915)->media.ip.rel)
> > 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH v2 9/9] drm/i915: Replace several IS_METEORLAKE with proper IP version checks

[Matt Roper]

On Tue, Jul 25, 2023 at 12:10:18PM +0200, Andi Shyti wrote:
> Hi Matt,
> 
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> > @@ -470,9 +470,13 @@ enum i915_map_type i915_coherent_map_type(struct drm_i915_private *i915,
> >  					  bool always_coherent)
> >  {
> >  	/*
> > -	 * Wa_22016122933: always return I915_MAP_WC for MTL
> > +	 * Wa_22016122933: always return I915_MAP_WC for Xe_LPM+
> > +	 *
> > +	 * FIXME: The scope of this workaround is too wide right now and
> > +	 * is applying to objects used solely on the primary GT.  We need to
> > +	 * take into account which GT will be operating on the shared object.
> >  	 */
> > -	if (i915_gem_object_is_lmem(obj) || IS_METEORLAKE(i915))
> > +	if (i915_gem_object_is_lmem(obj) || MEDIA_VER_FULL(i915) == IP_VER(13, 0))
> >  		return I915_MAP_WC;
> >  	if (HAS_LLC(i915) || always_coherent)
> >  		return I915_MAP_WB;
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > index 21af0ec52223..24060278e7a2 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > @@ -21,7 +21,7 @@ static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine)
> >  {
> >  	struct drm_i915_private *i915 = engine->i915;
> >  
> > -	if (IS_METEORLAKE(i915) && engine->id == GSC0) {
> > +	if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) {
> 
> this is a bit in countertrend... why isn't this
> 
> 	MEDIA_VER_FULL(engine->i915) == IP_VER(13, 0)
> 
> Like all others?

Generally we always assume that future platforms will inherit the
behavior of the current platform.  The exceptions are things like
workarounds (for which every platform or IP has its own unique list and
we should never inherit) or things like TLB invalidation (where an
overlooked hardware change can go unnoticed in general system usage but
have serious consequences).


Matt

> 
> Andi

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH v2 8/9] drm/i915/display: Eliminate IS_METEORLAKE checks

[Lucas De Marchi]

On Mon, Jul 24, 2023 at 05:13:21PM -0700, Matt Roper wrote:
>diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c

for the phy checks what I have locally is:

>index 1b00ef2c6185..a42b3c4c0ed7 100644
>--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>@@ -31,7 +31,7 @@
>
> bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy)
> {
>-	if (IS_METEORLAKE(i915) && (phy < PHY_C))
>+	if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0) && phy < PHY_C)

	if (DISPLAY_VER(i915) >= 14 && !IS_DGFX(i915) && (phy < PHY_C))

> 		return true;
>
> 	return false;
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>index 43cba98f7753..85efd77f491b 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -1767,7 +1767,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
> 	if (IS_DG2(dev_priv))
> 		/* DG2's "TC1" output uses a SNPS PHY */
> 		return false;
>-	else if (IS_ALDERLAKE_P(dev_priv) || IS_METEORLAKE(dev_priv))
>+	else if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0))

	else if (DISPLAY_VER(dev_priv) >= 13 && !IS_DGFX(dev_priv))

> 		return phy >= PHY_F && phy <= PHY_I;
> 	else if (IS_TIGERLAKE(dev_priv))
> 		return phy >= PHY_D && phy <= PHY_I;


would that be better or do you have something else in mind?

Lucas De Marchi

Re: [Intel-gfx] [PATCH v2 8/9] drm/i915/display: Eliminate IS_METEORLAKE checks

[Matt Roper]

On Thu, Jul 27, 2023 at 03:38:46PM -0300, Lucas De Marchi wrote:
> On Mon, Jul 24, 2023 at 05:13:21PM -0700, Matt Roper wrote:
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> 
> for the phy checks what I have locally is:
> 
> > index 1b00ef2c6185..a42b3c4c0ed7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -31,7 +31,7 @@
> > 
> > bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy)
> > {
> > -	if (IS_METEORLAKE(i915) && (phy < PHY_C))
> > +	if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0) && phy < PHY_C)
> 
> 	if (DISPLAY_VER(i915) >= 14 && !IS_DGFX(i915) && (phy < PHY_C))

Why the !IS_DGFX check?  We can assume the PHYs will remain the same for
future platforms in general (at least until a platform shows up and
requires a change), but I don't think there's any reason yet to assume
that only igpu's will inherit the behavior and dgpu's won't.

> 
> > 		return true;
> > 
> > 	return false;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 43cba98f7753..85efd77f491b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1767,7 +1767,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
> > 	if (IS_DG2(dev_priv))
> > 		/* DG2's "TC1" output uses a SNPS PHY */
> > 		return false;
> > -	else if (IS_ALDERLAKE_P(dev_priv) || IS_METEORLAKE(dev_priv))
> > +	else if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0))
> 
> 	else if (DISPLAY_VER(dev_priv) >= 13 && !IS_DGFX(dev_priv))

Same here.  This is probably fine if we switch the IS_DGFX to IS_DG2 to
exclude the single existing platform that we know doesn't follow this,
but I don't think we should assume the same will be true on future
dgpus.


Matt

> 
> > 		return phy >= PHY_F && phy <= PHY_I;
> > 	else if (IS_TIGERLAKE(dev_priv))
> > 		return phy >= PHY_D && phy <= PHY_I;
> 
> 
> would that be better or do you have something else in mind?
> 
> Lucas De Marchi
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH v2 4/9] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP

[Jani Nikula]

On Mon, 24 Jul 2023, Matt Roper <matthew.d.roper@intel.com> wrote:
> +/*
> + * Check whether a GT contains the specific IP version and a stepping within
> + * the specified range [from, until).  The lower stepping bound is inclusive,
> + * the upper bound is exclusive (corresponding to the first hardware stepping
> + * at when the workaround is no longer needed).  E.g.,
> + *
> + *    IS_GT_IP_STEP(GFX, IP_VER(12, 70), A0, B0)
> + *    IS_GT_IP_STEP(MEDIA, IP_VER(13, 00), B1, D0)
> + *    IS_GT_IP_STEP(GFX, IP_VER(12, 71), B1, FOREVER)
> + *
> + * "FOREVER" can be passed as the upper stepping bound for workarounds that
> + * have no upper bound on steppings of the specified IP version.
> + *
> + * Note that media version checks with this macro will only work on platforms
> + * with standalone media design (i.e., media version 13 and higher).
> + */
> +#define IS_GT_IP_STEP(type, gt, ipver, since, until) \
> +	(BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
> +	 (__IS_##type##_GT(gt) && \
> +	  __GT_VER_FULL(gt) == ipver && \
> +	  __GT_STEP(gt) >= STEP_##since && \
> +	  __GT_STEP(gt) <= STEP_##until))
> +

I really dislike the type, since and until arguments here, passing in
something that becomes part of the name of another macro. That's
something we do in some of our macro spaghetti internally, but not as
part of an interface that gets called all over the place.

For function-like macros, I'd generally like to make them such that they
could be converted to regular (static inline) functions without changing
the call sites.

BR,
Jani.


>  #define MEDIA_VER(i915)			(RUNTIME_INFO(i915)->media.ip.ver)
>  #define MEDIA_VER_FULL(i915)		IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
>  					       RUNTIME_INFO(i915)->media.ip.rel)
> @@ -710,10 +736,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
>  	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
>  
> -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
> -	(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
> -	 IS_GRAPHICS_STEP(__i915, since, until))
> -
>  #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
>  	(IS_METEORLAKE(__i915) && \
>  	 IS_DISPLAY_STEP(__i915, since, until))

-- 
Jani Nikula, Intel Open Source Graphics Center