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From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: wayland-devel@lists.freedesktop.org
Subject: [Intel-gfx] [RFC 08/33] drm: Add color lut range structure
Date: Tue, 29 Aug 2023 21:33:57 +0530	[thread overview]
Message-ID: <20230829160422.1251087-9-uma.shankar@intel.com> (raw)
In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com>

Add color lut range structure which is to be used to advertize
the capabilities of pre-csc/post-csc color operation blocks.

Co-developed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 include/uapi/drm/drm_mode.h | 77 +++++++++++++++++++++++++++++++++++++
 1 file changed, 77 insertions(+)

diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 1cd656b0e994..6ce7bd0926e0 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -1091,6 +1091,83 @@ struct drm_color_pipeline {
 				  DRM_MODE_PAGE_FLIP_ASYNC | \
 				  DRM_MODE_PAGE_FLIP_TARGET)
 
+/**
+ * DRM_MODE_LUT_POST_CSC
+ *
+ * LUT is for post csc (after CTM)
+ */
+#define DRM_MODE_LUT_POST_CSC BIT(0)
+
+/**
+ * DRM_MODE_LUT_PRE_CSC
+ *
+ * LUT is for pre csc (before CTM)
+ */
+#define DRM_MODE_LUT_PRE_CSC BIT(1)
+
+/**
+ * DRM_MODE_LUT_INTERPOLATE
+ *
+ * linearly interpolate between the points
+ */
+#define DRM_MODE_LUT_INTERPOLATE BIT(2)
+
+/**
+ * DRM_MODE_LUT_REUSE_LAST
+ *
+ * the last value of the previous range is the
+ * first value of the current range.
+ */
+#define DRM_MODE_LUT_REUSE_LAST BIT(3)
+
+/**
+ * DRM_MODE_LUT_NON_DECREASING
+ *
+ * the curve must be non-decreasing
+ */
+#define DRM_MODE_LUT_NON_DECREASING BIT(4)
+
+/**
+ * DRM_MODE_LUT_REFLECT_NEGATIVE
+ *
+ *  the curve is reflected across origin for negative inputs
+ */
+#define DRM_MODE_LUT_REFLECT_NEGATIVE BIT(5)
+
+/**
+ * DRM_MODE_LUT_SINGLE_CHANNEL
+ *
+ * the same curve (red) is used for blue and green channels as well
+ */
+#define DRM_MODE_LUT_SINGLE_CHANNEL BIT(6)
+
+/**
+ * struct drm_color_lut_range
+ *
+ * structure to advertise capability of a color hardware
+ * block that accepts LUT values.  It can represent LUTs with
+ * varied number of entries and distributions
+ * (Multi segmented, Logarithmic etc).
+ */
+
+struct drm_color_lut_range {
+	/* DRM_MODE_LUT_* */
+	__u32 flags;
+	/* number of points on the curve */
+	__u16 count;
+	/* input/output bits per component */
+	__u8 input_bpc, output_bpc;
+	/* input start/end values */
+	__s32 start, end;
+	/* output min/max values */
+	__s32 min, max;
+};
+
+enum lut_type {
+	LUT_TYPE_PRE_CSC = 0,
+	LUT_TYPE_POST_CSC = 1,
+};
+
 /*
  * Request a page flip on the specified crtc.
  *
-- 
2.38.1


  parent reply	other threads:[~2023-08-29 15:59 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-29 16:03 [Intel-gfx] [RFC 00/33] Add Support for Plane Color Pipeline Uma Shankar
2023-08-29 16:03 ` [Intel-gfx] [RFC 01/33] drm/doc/rfc: Add RFC document for proposed " Uma Shankar
2023-08-29 19:40   ` Harry Wentland
2023-08-30  8:59     ` Shankar, Uma
2023-08-30 12:28       ` Pekka Paalanen
2023-09-04 13:44         ` Shankar, Uma
2023-09-05 11:32           ` Pekka Paalanen
2023-09-07 12:31             ` Shankar, Uma
2023-09-08  8:31               ` Pekka Paalanen
2023-09-07 20:08   ` Christopher Braga
2023-10-13  5:46     ` Shankar, Uma
2023-08-29 16:03 ` [Intel-gfx] [RFC 02/33] drm: Add color operation structure Uma Shankar
2023-08-30 13:00   ` Pekka Paalanen
2023-09-04 14:10     ` Shankar, Uma
2023-09-05 11:33       ` Pekka Paalanen
2023-08-29 16:03 ` [Intel-gfx] [RFC 03/33] drm: Add plane get color pipeline property Uma Shankar
2023-08-29 16:03 ` [Intel-gfx] [RFC 04/33] drm: Add helper to add color pipeline Uma Shankar
2023-08-29 16:03 ` [Intel-gfx] [RFC 05/33] drm: Add structures for setting " Uma Shankar
2023-08-29 16:03 ` [Intel-gfx] [RFC 06/33] drm: Add set colorpipeline property Uma Shankar
2023-08-29 16:03 ` [Intel-gfx] [RFC 07/33] drm: Add Enhanced Gamma LUT precision structure Uma Shankar
2023-08-29 16:03 ` Uma Shankar [this message]
2023-08-29 16:03 ` [Intel-gfx] [RFC 09/33] drm: Add color information to plane state Uma Shankar
2023-08-29 16:03 ` [Intel-gfx] [RFC 10/33] drm: Manage color blob states Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 11/33] drm: Replace individual color blobs Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 12/33] drm: Reset pipeline when user sends NULL blob Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 13/33] drm: Reset plane color state on pipeline switch request Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 14/33] drm/i915/color: Add lut range for SDR planes Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 15/33] drm/i915/color: Add lut range for HDR planes Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 16/33] drm/i915/color: Add color pipeline " Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 17/33] drm/i915/color: Add color pipeline for SDR planes Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 18/33] drm/i915/color: Add HDR plane LUT range data to color pipeline Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 19/33] drm/i915/color: Add SDR " Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 20/33] drm/i915/color: Add color pipelines to plane Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 21/33] drm/i915/color: Create and attach set color pipeline property Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 22/33] drm/i915/color: Add plane color callbacks Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 23/33] drm/i915/color: Load plane color luts from atomic flip Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 24/33] drm/i915/xelpd: Add plane color check to glk_plane_color_ctl Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 25/33] drm/i915/xelpd: Add register definitions for Plane Degamma Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 26/33] drm/i915/color: Add color functions for ADL Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 27/33] drm/i915/color: Program Plane Pre-CSC Registers Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 28/33] drm/i915/xelpd: Add register definitions for Plane Post CSC Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 29/33] drm/i915/xelpd: Program Plane Post CSC Registers Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 30/33] drm/i915/color: Enable Plane CSC Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 31/33] drm/i915/color: Enable plane color features Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 32/33] drm/i915/color: Add a dummy pipeline with 3D LUT Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 33/33] drm/i915/color: Add example implementation for vendor specific color operation Uma Shankar
2023-08-29 19:26 ` [Intel-gfx] [RFC 00/33] Add Support for Plane Color Pipeline Harry Wentland
2023-08-30  8:47   ` Shankar, Uma
2023-08-30 21:15     ` Sebastian Wick
2023-09-04 14:29       ` Shankar, Uma
2023-09-05 11:33         ` Pekka Paalanen
2023-09-05 12:33           ` Sebastian Wick
2023-09-05 12:57             ` Sebastian Wick
2023-08-29 20:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2023-08-29 20:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-08-29 20:17 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

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