Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Pekka Paalanen <ppaalanen@gmail.com>
To: Uma Shankar <uma.shankar@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
	wayland-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFC 02/33] drm: Add color operation structure
Date: Wed, 30 Aug 2023 16:00:19 +0300	[thread overview]
Message-ID: <20230830160019.19e67519@eldfell> (raw)
In-Reply-To: <20230829160422.1251087-3-uma.shankar@intel.com>

[-- Attachment #1: Type: text/plain, Size: 5209 bytes --]

On Tue, 29 Aug 2023 21:33:51 +0530
Uma Shankar <uma.shankar@intel.com> wrote:

> From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> 
> Each Color Hardware block will be represented uniquely
> in the color pipeline. Define the structure to represent
> the same.
> 
> These color operations will form the building blocks of
> a color pipeline which best represents the underlying
> Hardware. Color operations can be re-arranged, substracted
> or added to create distinct color pipelines to accurately
> describe the Hardware blocks present in the display engine.
> 
> Co-developed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> ---
>  include/uapi/drm/drm_mode.h | 72 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 72 insertions(+)
> 
> diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
> index ea1b639bcb28..882479f41745 100644
> --- a/include/uapi/drm/drm_mode.h
> +++ b/include/uapi/drm/drm_mode.h
> @@ -943,6 +943,78 @@ struct hdr_output_metadata {
>  	};
>  };
>  
> +/**
> + * enum color_op_block
> + *
> + * Enums to identify hardware color blocks.
> + *
> + * @DRM_CB_PRE_CSC: LUT before the CTM unit
> + * @DRM_CB_CSC: CTM hardware supporting 3x3 matrix
> + * @DRM_CB_POST_CSC: LUT after the CTM unit
> + * @DRM_CB_3D_LUT: LUT hardware with coefficients for all
> + *                 color components
> + * @DRM_CB_PRIVATE: Vendor specific hardware unit. Vendor
> + *                  can expose a custom hardware by defining a
> + *                  color operation block with this name as
> + *                  identifier

This naming scheme does not seem to work. It assumes a far too rigid
pipeline, just like the old KMS property design. What if you have two
other operations between PRE_CSC and CSC?

What sense do PRE_CSC and POST_CSC make if you don't happen to have a
CSC operation?

What if a driver put POST_CSC before PRE_CSC in its pipeline?

What if your CSC is actually a series of three independent operations,
and in addition you have PRE_CSC and POST_CSC?

3D_LUT is an operation category, not a name. The same could be said
about private.

Given that all these are also UAPI, do we also need protect old
userspace from seeing values it does not understand?

> + */
> +enum color_op_block {
> +	DRM_CB_INVAL = -1,
> +
> +	DRM_CB_PRE_CSC = 0,
> +	DRM_CB_CSC,
> +	DRM_CB_POST_CSC,
> +	DRM_CB_3D_LUT,
> +
> +	/* Any new generic hardware block can be updated here */
> +
> +	/*
> +	 * PRIVATE is kept at 255 to make it future proof and leave
> +	 * scope for any new addition
> +	 */
> +	DRM_CB_PRIVATE = 255,
> +	DRM_CB_MAX = DRM_CB_PRIVATE,
> +};
> +
> +/**
> + * enum color_op_type
> + *
> + * These enums are to identify the mathematical operation that
> + * a hardware block is capable of.
> + * @CURVE_1D: It represents a one dimensional lookup table
> + * @CURVE_3D: Represents lut value for each color component for 3d lut capable hardware
> + * @MATRIX: It represents co-efficients for a CSC/CTM matrix hardware
> + * @FIXED_FUNCTION: To enable and program any custom fixed function hardware unit
> + */
> +enum color_op_type {
> +	CURVE_1D,
> +	CURVE_3D,
> +	MATRIX,
> +	FIXED_FUNCTION,

My assumption was that a color_op_type would clearly and uniquely
define the mathematical model of the operation and the UABI structure
of the parameter blob. That means we need different values for uniform
vs. exponentially vs. programmable distributed 1D LUT, etc.

If there is a 1D curve with pre-programmed (fixed and named) curves, we
need to enumerate all the curve types somehow. Probably each fixed
curve type should not be a different operation type, because that would
explode the number of alternative pipelines.

A 3D curve in my mind is a function {x,y,z} = f(t), while I suspect you
meant a 3D LUT which is a {x,y,z} = f(t,u,v) - a 3-vector field in
three dimensional space.

A matrix element could be with or without an offset vector I guess.

FIXED_FUNCTION would need to be replaced with e.g. your example
VENDORXXX_BT602_TO_BT2020 to work.

Have I missed something, how did you intend this to work?


Thanks,
pq

> +};
> +
> +/**
> + * @struct drm_color_op
> + *
> + * This structure is used to represent the capability of
> + * individual color hardware blocks.
> + *
> + * @name: a standardized enum to identify the color hardware block
> + * @type: The type of mathematical operation it can perform
> + * @blob_id: Id pointing to a blob containing information about
> + *          the hardware block which advertizes its capabilities
> + *          to the userspace. It can be an optional field depending
> + *          on the members "name" and "type".
> + * @private_flags: This can be used to provide vendor specific hints
> + *                 to user space
> + */
> +struct drm_color_op {
> +	enum color_op_block name;
> +	enum color_op_type type;
> +	__u32 blob_id;
> +	__u32 private_flags;
> +};
> +
>  /**
>   * DRM_MODE_PAGE_FLIP_EVENT
>   *


[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

  reply	other threads:[~2023-08-30 13:00 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-29 16:03 [Intel-gfx] [RFC 00/33] Add Support for Plane Color Pipeline Uma Shankar
2023-08-29 16:03 ` [Intel-gfx] [RFC 01/33] drm/doc/rfc: Add RFC document for proposed " Uma Shankar
2023-08-29 19:40   ` Harry Wentland
2023-08-30  8:59     ` Shankar, Uma
2023-08-30 12:28       ` Pekka Paalanen
2023-09-04 13:44         ` Shankar, Uma
2023-09-05 11:32           ` Pekka Paalanen
2023-09-07 12:31             ` Shankar, Uma
2023-09-08  8:31               ` Pekka Paalanen
2023-09-07 20:08   ` Christopher Braga
2023-10-13  5:46     ` Shankar, Uma
2023-08-29 16:03 ` [Intel-gfx] [RFC 02/33] drm: Add color operation structure Uma Shankar
2023-08-30 13:00   ` Pekka Paalanen [this message]
2023-09-04 14:10     ` Shankar, Uma
2023-09-05 11:33       ` Pekka Paalanen
2023-08-29 16:03 ` [Intel-gfx] [RFC 03/33] drm: Add plane get color pipeline property Uma Shankar
2023-08-29 16:03 ` [Intel-gfx] [RFC 04/33] drm: Add helper to add color pipeline Uma Shankar
2023-08-29 16:03 ` [Intel-gfx] [RFC 05/33] drm: Add structures for setting " Uma Shankar
2023-08-29 16:03 ` [Intel-gfx] [RFC 06/33] drm: Add set colorpipeline property Uma Shankar
2023-08-29 16:03 ` [Intel-gfx] [RFC 07/33] drm: Add Enhanced Gamma LUT precision structure Uma Shankar
2023-08-29 16:03 ` [Intel-gfx] [RFC 08/33] drm: Add color lut range structure Uma Shankar
2023-08-29 16:03 ` [Intel-gfx] [RFC 09/33] drm: Add color information to plane state Uma Shankar
2023-08-29 16:03 ` [Intel-gfx] [RFC 10/33] drm: Manage color blob states Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 11/33] drm: Replace individual color blobs Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 12/33] drm: Reset pipeline when user sends NULL blob Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 13/33] drm: Reset plane color state on pipeline switch request Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 14/33] drm/i915/color: Add lut range for SDR planes Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 15/33] drm/i915/color: Add lut range for HDR planes Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 16/33] drm/i915/color: Add color pipeline " Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 17/33] drm/i915/color: Add color pipeline for SDR planes Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 18/33] drm/i915/color: Add HDR plane LUT range data to color pipeline Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 19/33] drm/i915/color: Add SDR " Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 20/33] drm/i915/color: Add color pipelines to plane Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 21/33] drm/i915/color: Create and attach set color pipeline property Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 22/33] drm/i915/color: Add plane color callbacks Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 23/33] drm/i915/color: Load plane color luts from atomic flip Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 24/33] drm/i915/xelpd: Add plane color check to glk_plane_color_ctl Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 25/33] drm/i915/xelpd: Add register definitions for Plane Degamma Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 26/33] drm/i915/color: Add color functions for ADL Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 27/33] drm/i915/color: Program Plane Pre-CSC Registers Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 28/33] drm/i915/xelpd: Add register definitions for Plane Post CSC Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 29/33] drm/i915/xelpd: Program Plane Post CSC Registers Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 30/33] drm/i915/color: Enable Plane CSC Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 31/33] drm/i915/color: Enable plane color features Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 32/33] drm/i915/color: Add a dummy pipeline with 3D LUT Uma Shankar
2023-08-29 16:04 ` [Intel-gfx] [RFC 33/33] drm/i915/color: Add example implementation for vendor specific color operation Uma Shankar
2023-08-29 19:26 ` [Intel-gfx] [RFC 00/33] Add Support for Plane Color Pipeline Harry Wentland
2023-08-30  8:47   ` Shankar, Uma
2023-08-30 21:15     ` Sebastian Wick
2023-09-04 14:29       ` Shankar, Uma
2023-09-05 11:33         ` Pekka Paalanen
2023-09-05 12:33           ` Sebastian Wick
2023-09-05 12:57             ` Sebastian Wick
2023-08-29 20:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2023-08-29 20:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-08-29 20:17 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230830160019.19e67519@eldfell \
    --to=ppaalanen@gmail.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=uma.shankar@intel.com \
    --cc=wayland-devel@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox