* [Intel-gfx] [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp prescision
2023-09-11 5:05 [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support Mitul Golani
@ 2023-09-11 5:05 ` Mitul Golani
2023-09-11 8:53 ` Kandpal, Suraj
2023-09-11 5:05 ` [Intel-gfx] [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format Mitul Golani
` (9 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Mitul Golani @ 2023-09-11 5:05 UTC (permalink / raw)
To: intel-gfx
From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Add helper to get the DSC bits_per_pixel precision for the DP sink.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/display/drm_dp_helper.c | 27 +++++++++++++++++++++++++
include/drm/display/drm_dp_helper.h | 1 +
2 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index 8a1b64c57dfd..5c23d5b8fc50 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2323,6 +2323,33 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
}
EXPORT_SYMBOL(drm_dp_read_desc);
+/**
+ * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
+ * @dsc_dpcd: DSC capabilities from DPCD
+ *
+ * Returns the bpp precision supported by the DP sink.
+ */
+u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+ u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT];
+
+ switch (bpp_increment_dpcd) {
+ case DP_DSC_BITS_PER_PIXEL_1_16:
+ return 16;
+ case DP_DSC_BITS_PER_PIXEL_1_8:
+ return 8;
+ case DP_DSC_BITS_PER_PIXEL_1_4:
+ return 4;
+ case DP_DSC_BITS_PER_PIXEL_1_2:
+ return 2;
+ case DP_DSC_BITS_PER_PIXEL_1_1:
+ return 1;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);
+
/**
* drm_dp_dsc_sink_max_slice_count() - Get the max slice count
* supported by the DSC sink.
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index 3369104e2d25..6968d4d87931 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -164,6 +164,7 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
}
/* DP/eDP DSC support */
+u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
bool is_edp);
u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp prescision
2023-09-11 5:05 ` [Intel-gfx] [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp prescision Mitul Golani
@ 2023-09-11 8:53 ` Kandpal, Suraj
0 siblings, 0 replies; 27+ messages in thread
From: Kandpal, Suraj @ 2023-09-11 8:53 UTC (permalink / raw)
To: Golani, Mitulkumar Ajitkumar, intel-gfx@lists.freedesktop.org
> Subject: [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp
> prescision
>
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>
> Add helper to get the DSC bits_per_pixel precision for the DP sink.
I think this should also be floated in drm-devel mailing list.
Regards,
Suraj Kandpal
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/display/drm_dp_helper.c | 27 +++++++++++++++++++++++++
> include/drm/display/drm_dp_helper.h | 1 +
> 2 files changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c
> b/drivers/gpu/drm/display/drm_dp_helper.c
> index 8a1b64c57dfd..5c23d5b8fc50 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -2323,6 +2323,33 @@ int drm_dp_read_desc(struct drm_dp_aux *aux,
> struct drm_dp_desc *desc, } EXPORT_SYMBOL(drm_dp_read_desc);
>
> +/**
> + * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
> + * @dsc_dpcd: DSC capabilities from DPCD
> + *
> + * Returns the bpp precision supported by the DP sink.
> + */
> +u8 drm_dp_dsc_sink_bpp_incr(const u8
> +dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
> +{
> + u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC -
> +DP_DSC_SUPPORT];
> +
> + switch (bpp_increment_dpcd) {
> + case DP_DSC_BITS_PER_PIXEL_1_16:
> + return 16;
> + case DP_DSC_BITS_PER_PIXEL_1_8:
> + return 8;
> + case DP_DSC_BITS_PER_PIXEL_1_4:
> + return 4;
> + case DP_DSC_BITS_PER_PIXEL_1_2:
> + return 2;
> + case DP_DSC_BITS_PER_PIXEL_1_1:
> + return 1;
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);
> +
> /**
> * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
> * supported by the DSC sink.
> diff --git a/include/drm/display/drm_dp_helper.h
> b/include/drm/display/drm_dp_helper.h
> index 3369104e2d25..6968d4d87931 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -164,6 +164,7 @@ drm_dp_is_branch(const u8
> dpcd[DP_RECEIVER_CAP_SIZE]) }
>
> /* DP/eDP DSC support */
> +u8 drm_dp_dsc_sink_bpp_incr(const u8
> +dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
> u8 drm_dp_dsc_sink_max_slice_count(const u8
> dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
> bool is_edp);
> u8 drm_dp_dsc_sink_line_buf_depth(const u8
> dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
> --
> 2.25.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format
2023-09-11 5:05 [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support Mitul Golani
2023-09-11 5:05 ` [Intel-gfx] [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp prescision Mitul Golani
@ 2023-09-11 5:05 ` Mitul Golani
2023-09-11 9:13 ` Kandpal, Suraj
2023-09-11 11:36 ` Jani Nikula
2023-09-11 5:05 ` [Intel-gfx] [PATCH 3/8] drm/i915/display: Consider fractional vdsc bpp while computing m_n values Mitul Golani
` (8 subsequent siblings)
10 siblings, 2 replies; 27+ messages in thread
From: Mitul Golani @ 2023-09-11 5:05 UTC (permalink / raw)
To: intel-gfx
From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
DSC parameter bits_per_pixel is stored in U6.4 format.
The 4 bits represent the fractional part of the bpp.
Currently we use compressed_bpp member of dsc structure to store
only the integral part of the bits_per_pixel.
To store the full bits_per_pixel along with the fractional part,
compressed_bpp is changed to store bpp in U6.4 formats. Intergral
part is retrieved by simply right shifting the member compressed_bpp by 4.
v2:
-Use to_bpp_int, to_bpp_frac_dec, to_bpp_x16 helpers while dealing
with compressed bpp. (Suraj)
-Fix comment styling. (Suraj)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 10 ++++----
drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
drivers/gpu/drm/i915/display/intel_bios.c | 4 +--
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
.../drm/i915/display/intel_display_types.h | 18 ++++++++++++-
drivers/gpu/drm/i915/display/intel_dp.c | 25 +++++++++++--------
drivers/gpu/drm/i915/display/intel_dp_mst.c | 18 ++++++-------
drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +--
9 files changed, 52 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index ad6488e9c2b2..df98f35bbcda 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -330,7 +330,7 @@ static int afe_clk(struct intel_encoder *encoder,
int bpp;
if (crtc_state->dsc.compression_enable)
- bpp = crtc_state->dsc.compressed_bpp;
+ bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
else
bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
@@ -860,7 +860,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
* compressed and non-compressed bpp.
*/
if (crtc_state->dsc.compression_enable) {
- mul = crtc_state->dsc.compressed_bpp;
+ mul = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
}
@@ -884,7 +884,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
int bpp, line_time_us, byte_clk_period_ns;
if (crtc_state->dsc.compression_enable)
- bpp = crtc_state->dsc.compressed_bpp;
+ bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
else
bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
@@ -1451,8 +1451,8 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
- if (pipe_config->dsc.compressed_bpp) {
- int div = pipe_config->dsc.compressed_bpp;
+ if (pipe_config->dsc.compressed_bpp_x16) {
+ int div = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
adjusted_mode->crtc_htotal =
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 19605264a35c..aa93ccd6c2aa 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -528,7 +528,7 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
- vdsc_bpp = crtc_state->dsc.compressed_bpp;
+ vdsc_bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
cdclk = i915->display.cdclk.hw.cdclk;
/* fec= 0.972261, using rounding multiplier of 1000000 */
fec_coeff = 972261;
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 858c959f7bab..7b6d299fbcf2 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -3384,8 +3384,8 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
crtc_state->pipe_bpp = bpc * 3;
- crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
- VBT_DSC_MAX_BPP(dsc->max_bpp));
+ crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(min(crtc_state->pipe_bpp,
+ VBT_DSC_MAX_BPP(dsc->max_bpp)));
/*
* FIXME: This is ugly, and slice count should take DSC engine
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ad5251ba6fe1..06a1e99a2762 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2567,7 +2567,7 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
* => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
*/
int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;
- int min_cdclk_bj = (crtc_state->dsc.compressed_bpp * pixel_clock) /
+ int min_cdclk_bj = (to_bpp_int(crtc_state->dsc.compressed_bpp_x16) * pixel_clock) /
(2 * bigjoiner_interface_bits);
min_cdclk = max(min_cdclk, min_cdclk_bj);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 83e1bc858b9f..afcbdd4f105a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5365,7 +5365,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(dsc.compression_enable);
PIPE_CONF_CHECK_I(dsc.dsc_split);
- PIPE_CONF_CHECK_I(dsc.compressed_bpp);
+ PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
PIPE_CONF_CHECK_BOOL(splitter.enable);
PIPE_CONF_CHECK_I(splitter.link_count);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c21064794f32..9eb7b8912076 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1353,7 +1353,8 @@ struct intel_crtc_state {
struct {
bool compression_enable;
bool dsc_split;
- u16 compressed_bpp;
+ /* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
+ u16 compressed_bpp_x16;
u8 slice_count;
struct drm_dsc_config config;
} dsc;
@@ -2108,4 +2109,19 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
}
+static inline int to_bpp_int(int bpp_x16)
+{
+ return bpp_x16 >> 4;
+}
+
+static inline int to_bpp_frac_dec(int bpp_x16)
+{
+ return (bpp_x16 & 0xf) * 625;
+}
+
+static inline int to_bpp_x16(int bpp)
+{
+ return bpp << 4;
+}
+
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2206b45bc78c..9b88ac3a73c7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1863,7 +1863,7 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
valid_dsc_bpp[i],
timeslots);
if (ret == 0) {
- pipe_config->dsc.compressed_bpp = valid_dsc_bpp[i];
+ pipe_config->dsc.compressed_bpp_x16 = to_bpp_x16(valid_dsc_bpp[i]);
return 0;
}
}
@@ -1901,7 +1901,7 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
compressed_bpp,
timeslots);
if (ret == 0) {
- pipe_config->dsc.compressed_bpp = compressed_bpp;
+ pipe_config->dsc.compressed_bpp_x16 = to_bpp_x16(compressed_bpp);
return 0;
}
}
@@ -2085,7 +2085,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
/* Compressed BPP should be less than the Input DSC bpp */
dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
- pipe_config->dsc.compressed_bpp = max(dsc_min_bpp, dsc_max_bpp);
+ pipe_config->dsc.compressed_bpp_x16 = to_bpp_x16(max(dsc_min_bpp, dsc_max_bpp));
pipe_config->pipe_bpp = pipe_bpp;
@@ -2172,17 +2172,19 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (ret < 0) {
drm_dbg_kms(&dev_priv->drm,
"Cannot compute valid DSC parameters for Input Bpp = %d "
- "Compressed BPP = %d\n",
+ "Compressed BPP = %d.%d\n",
pipe_config->pipe_bpp,
- pipe_config->dsc.compressed_bpp);
+ to_bpp_int(pipe_config->dsc.compressed_bpp_x16),
+ to_bpp_frac_dec(pipe_config->dsc.compressed_bpp_x16));
return ret;
}
pipe_config->dsc.compression_enable = true;
drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
- "Compressed Bpp = %d Slice Count = %d\n",
+ "Compressed Bpp = %d.%d Slice Count = %d\n",
pipe_config->pipe_bpp,
- pipe_config->dsc.compressed_bpp,
+ to_bpp_int(pipe_config->dsc.compressed_bpp_x16),
+ to_bpp_frac_dec(pipe_config->dsc.compressed_bpp_x16),
pipe_config->dsc.slice_count);
return 0;
@@ -2261,15 +2263,16 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
if (pipe_config->dsc.compression_enable) {
drm_dbg_kms(&i915->drm,
- "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
+ "DP lane count %d clock %d Input bpp %d Compressed bpp %d.%d\n",
pipe_config->lane_count, pipe_config->port_clock,
pipe_config->pipe_bpp,
- pipe_config->dsc.compressed_bpp);
+ to_bpp_int(pipe_config->dsc.compressed_bpp_x16),
+ to_bpp_frac_dec(pipe_config->dsc.compressed_bpp_x16));
drm_dbg_kms(&i915->drm,
"DP link rate required %i available %i\n",
intel_dp_link_required(adjusted_mode->crtc_clock,
- pipe_config->dsc.compressed_bpp),
+ to_bpp_int(pipe_config->dsc.compressed_bpp_x16)),
intel_dp_max_data_rate(pipe_config->port_clock,
pipe_config->lane_count));
} else {
@@ -2702,7 +2705,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_dp_limited_color_range(pipe_config, conn_state);
if (pipe_config->dsc.compression_enable)
- link_bpp = pipe_config->dsc.compressed_bpp;
+ link_bpp = pipe_config->dsc.compressed_bpp_x16;
else
link_bpp = intel_dp_output_bpp(pipe_config->output_format,
pipe_config->pipe_bpp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 2d1c42a5e684..68a81f10e772 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -140,7 +140,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
if (!dsc)
crtc_state->pipe_bpp = bpp;
else
- crtc_state->dsc.compressed_bpp = bpp;
+ crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(bpp);
drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);
}
@@ -238,13 +238,13 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
if (slots < 0)
return slots;
- last_compressed_bpp = crtc_state->dsc.compressed_bpp;
+ last_compressed_bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
- crtc_state->dsc.compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915,
- last_compressed_bpp,
- crtc_state->pipe_bpp);
+ crtc_state->dsc.compressed_bpp_x16 =
+ to_bpp_x16(intel_dp_dsc_nearest_valid_bpp(i915, last_compressed_bpp,
+ crtc_state->pipe_bpp));
- if (crtc_state->dsc.compressed_bpp != last_compressed_bpp)
+ if (crtc_state->dsc.compressed_bpp_x16 != to_bpp_x16(last_compressed_bpp))
need_timeslot_recalc = true;
/*
@@ -253,14 +253,14 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
*/
if (need_timeslot_recalc) {
slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
- crtc_state->dsc.compressed_bpp,
- crtc_state->dsc.compressed_bpp,
+ to_bpp_int(crtc_state->dsc.compressed_bpp_x16),
+ to_bpp_int(crtc_state->dsc.compressed_bpp_x16),
limits, conn_state, 2 * 3, true);
if (slots < 0)
return slots;
}
- intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
+ intel_link_compute_m_n(to_bpp_int(crtc_state->dsc.compressed_bpp_x16),
crtc_state->lane_count,
adjusted_mode->crtc_clock,
crtc_state->port_clock,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index b24601d0b2c5..bfc41972a0bb 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -248,7 +248,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
- u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
+ u16 compressed_bpp = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
int err;
int ret;
@@ -878,7 +878,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
if (vdsc_cfg->native_420)
vdsc_cfg->bits_per_pixel >>= 1;
- crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
+ crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;
/* PPS_2 */
intel_dsc_read_and_verify_pps_reg(crtc_state, 2, &pps_temp);
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format
2023-09-11 5:05 ` [Intel-gfx] [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format Mitul Golani
@ 2023-09-11 9:13 ` Kandpal, Suraj
2023-09-11 9:17 ` Kandpal, Suraj
2023-09-11 11:36 ` Jani Nikula
1 sibling, 1 reply; 27+ messages in thread
From: Kandpal, Suraj @ 2023-09-11 9:13 UTC (permalink / raw)
To: Golani, Mitulkumar Ajitkumar, intel-gfx@lists.freedesktop.org
> Subject: [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format
>
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>
> DSC parameter bits_per_pixel is stored in U6.4 format.
> The 4 bits represent the fractional part of the bpp.
> Currently we use compressed_bpp member of dsc structure to store only the
> integral part of the bits_per_pixel.
> To store the full bits_per_pixel along with the fractional part, compressed_bpp
> is changed to store bpp in U6.4 formats. Intergral part is retrieved by simply
> right shifting the member compressed_bpp by 4.
>
> v2:
> -Use to_bpp_int, to_bpp_frac_dec, to_bpp_x16 helpers while dealing with
> compressed bpp. (Suraj) -Fix comment styling. (Suraj)
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 10 ++++----
> drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
> drivers/gpu/drm/i915/display/intel_bios.c | 4 +--
> drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> .../drm/i915/display/intel_display_types.h | 18 ++++++++++++-
> drivers/gpu/drm/i915/display/intel_dp.c | 25 +++++++++++--------
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 18 ++++++-------
> drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +--
> 9 files changed, 52 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index ad6488e9c2b2..df98f35bbcda 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -330,7 +330,7 @@ static int afe_clk(struct intel_encoder *encoder,
> int bpp;
>
> if (crtc_state->dsc.compression_enable)
> - bpp = crtc_state->dsc.compressed_bpp;
> + bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
> else
> bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
>
> @@ -860,7 +860,7 @@ gen11_dsi_set_transcoder_timings(struct
> intel_encoder *encoder,
> * compressed and non-compressed bpp.
> */
> if (crtc_state->dsc.compression_enable) {
> - mul = crtc_state->dsc.compressed_bpp;
> + mul = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
> div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
> }
>
> @@ -884,7 +884,7 @@ gen11_dsi_set_transcoder_timings(struct
> intel_encoder *encoder,
> int bpp, line_time_us, byte_clk_period_ns;
>
> if (crtc_state->dsc.compression_enable)
> - bpp = crtc_state->dsc.compressed_bpp;
> + bpp = to_bpp_int(crtc_state-
> >dsc.compressed_bpp_x16);
> else
> bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi-
> >pixel_format);
>
> @@ -1451,8 +1451,8 @@ static void gen11_dsi_get_timings(struct
> intel_encoder *encoder,
> struct drm_display_mode *adjusted_mode =
> &pipe_config->hw.adjusted_mode;
>
> - if (pipe_config->dsc.compressed_bpp) {
> - int div = pipe_config->dsc.compressed_bpp;
> + if (pipe_config->dsc.compressed_bpp_x16) {
> + int div = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
> int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi-
> >pixel_format);
>
> adjusted_mode->crtc_htotal =
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> b/drivers/gpu/drm/i915/display/intel_audio.c
> index 19605264a35c..aa93ccd6c2aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -528,7 +528,7 @@ static unsigned int calc_hblank_early_prog(struct
> intel_encoder *encoder,
> h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
> pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
> - vdsc_bpp = crtc_state->dsc.compressed_bpp;
> + vdsc_bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
> cdclk = i915->display.cdclk.hw.cdclk;
> /* fec= 0.972261, using rounding multiplier of 1000000 */
> fec_coeff = 972261;
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 858c959f7bab..7b6d299fbcf2 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -3384,8 +3384,8 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
>
> crtc_state->pipe_bpp = bpc * 3;
>
> - crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
> - VBT_DSC_MAX_BPP(dsc-
> >max_bpp));
> + crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(min(crtc_state-
> >pipe_bpp,
> +
> VBT_DSC_MAX_BPP(dsc->max_bpp)));
>
> /*
> * FIXME: This is ugly, and slice count should take DSC engine diff --git
> a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index ad5251ba6fe1..06a1e99a2762 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2567,7 +2567,7 @@ static int intel_vdsc_min_cdclk(const struct
> intel_crtc_state *crtc_state)
> * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner
> Interface bits
> */
> int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;
> - int min_cdclk_bj = (crtc_state->dsc.compressed_bpp *
> pixel_clock) /
> + int min_cdclk_bj = (to_bpp_int(crtc_state-
> >dsc.compressed_bpp_x16) *
> +pixel_clock) /
> (2 * bigjoiner_interface_bits);
>
> min_cdclk = max(min_cdclk, min_cdclk_bj); diff --git
> a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 83e1bc858b9f..afcbdd4f105a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5365,7 +5365,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>
> PIPE_CONF_CHECK_I(dsc.compression_enable);
> PIPE_CONF_CHECK_I(dsc.dsc_split);
> - PIPE_CONF_CHECK_I(dsc.compressed_bpp);
> + PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
>
> PIPE_CONF_CHECK_BOOL(splitter.enable);
> PIPE_CONF_CHECK_I(splitter.link_count);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c21064794f32..9eb7b8912076 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1353,7 +1353,8 @@ struct intel_crtc_state {
> struct {
> bool compression_enable;
> bool dsc_split;
> - u16 compressed_bpp;
> + /* Compressed Bpp in U6.4 format (first 4 bits for fractional
> part) */
> + u16 compressed_bpp_x16;
> u8 slice_count;
> struct drm_dsc_config config;
> } dsc;
> @@ -2108,4 +2109,19 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
> return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL; }
>
> +static inline int to_bpp_int(int bpp_x16) {
> + return bpp_x16 >> 4;
> +}
> +
> +static inline int to_bpp_frac_dec(int bpp_x16) {
> + return (bpp_x16 & 0xf) * 625;
> +}
Let's add a comment on top on why we apply the mask and where the value 625 comes from
Something like:
"Since compressed bpp is now fractional such that last 4 bits represent fractional bits we get the
fractional part by multiplying by 10000 then dividing it by 16 as we initially left shift compressed bpp by 4,
to get 4 bits for the fractional part"
Otherwise,
LGTM.
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com
> +
> +static inline int to_bpp_x16(int bpp)
> +{
> + return bpp << 4;
> +}
> +
> #endif /* __INTEL_DISPLAY_TYPES_H__ */ diff --git
> a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2206b45bc78c..9b88ac3a73c7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1863,7 +1863,7 @@ icl_dsc_compute_link_config(struct intel_dp
> *intel_dp,
> valid_dsc_bpp[i],
> timeslots);
> if (ret == 0) {
> - pipe_config->dsc.compressed_bpp = valid_dsc_bpp[i];
> + pipe_config->dsc.compressed_bpp_x16 =
> to_bpp_x16(valid_dsc_bpp[i]);
> return 0;
> }
> }
> @@ -1901,7 +1901,7 @@ xelpd_dsc_compute_link_config(struct intel_dp
> *intel_dp,
> compressed_bpp,
> timeslots);
> if (ret == 0) {
> - pipe_config->dsc.compressed_bpp =
> compressed_bpp;
> + pipe_config->dsc.compressed_bpp_x16 =
> to_bpp_x16(compressed_bpp);
> return 0;
> }
> }
> @@ -2085,7 +2085,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct
> intel_dp *intel_dp,
> /* Compressed BPP should be less than the Input DSC bpp */
> dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
>
> - pipe_config->dsc.compressed_bpp = max(dsc_min_bpp,
> dsc_max_bpp);
> + pipe_config->dsc.compressed_bpp_x16 =
> to_bpp_x16(max(dsc_min_bpp,
> +dsc_max_bpp));
>
> pipe_config->pipe_bpp = pipe_bpp;
>
> @@ -2172,17 +2172,19 @@ int intel_dp_dsc_compute_config(struct intel_dp
> *intel_dp,
> if (ret < 0) {
> drm_dbg_kms(&dev_priv->drm,
> "Cannot compute valid DSC parameters for Input
> Bpp = %d "
> - "Compressed BPP = %d\n",
> + "Compressed BPP = %d.%d\n",
> pipe_config->pipe_bpp,
> - pipe_config->dsc.compressed_bpp);
> + to_bpp_int(pipe_config->dsc.compressed_bpp_x16),
> + to_bpp_frac_dec(pipe_config-
> >dsc.compressed_bpp_x16));
> return ret;
> }
>
> pipe_config->dsc.compression_enable = true;
> drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp =
> %d "
> - "Compressed Bpp = %d Slice Count = %d\n",
> + "Compressed Bpp = %d.%d Slice Count = %d\n",
> pipe_config->pipe_bpp,
> - pipe_config->dsc.compressed_bpp,
> + to_bpp_int(pipe_config->dsc.compressed_bpp_x16),
> + to_bpp_frac_dec(pipe_config->dsc.compressed_bpp_x16),
> pipe_config->dsc.slice_count);
>
> return 0;
> @@ -2261,15 +2263,16 @@ intel_dp_compute_link_config(struct
> intel_encoder *encoder,
>
> if (pipe_config->dsc.compression_enable) {
> drm_dbg_kms(&i915->drm,
> - "DP lane count %d clock %d Input bpp %d
> Compressed bpp %d\n",
> + "DP lane count %d clock %d Input bpp %d
> Compressed bpp %d.%d\n",
> pipe_config->lane_count, pipe_config->port_clock,
> pipe_config->pipe_bpp,
> - pipe_config->dsc.compressed_bpp);
> + to_bpp_int(pipe_config->dsc.compressed_bpp_x16),
> + to_bpp_frac_dec(pipe_config-
> >dsc.compressed_bpp_x16));
>
> drm_dbg_kms(&i915->drm,
> "DP link rate required %i available %i\n",
> intel_dp_link_required(adjusted_mode->crtc_clock,
> - pipe_config-
> >dsc.compressed_bpp),
> + to_bpp_int(pipe_config-
> >dsc.compressed_bpp_x16)),
> intel_dp_max_data_rate(pipe_config->port_clock,
> pipe_config->lane_count));
> } else {
> @@ -2702,7 +2705,7 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
> intel_dp_limited_color_range(pipe_config, conn_state);
>
> if (pipe_config->dsc.compression_enable)
> - link_bpp = pipe_config->dsc.compressed_bpp;
> + link_bpp = pipe_config->dsc.compressed_bpp_x16;
> else
> link_bpp = intel_dp_output_bpp(pipe_config->output_format,
> pipe_config->pipe_bpp);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 2d1c42a5e684..68a81f10e772 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -140,7 +140,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct
> intel_encoder *encoder,
> if (!dsc)
> crtc_state->pipe_bpp = bpp;
> else
> - crtc_state->dsc.compressed_bpp = bpp;
> + crtc_state->dsc.compressed_bpp_x16 =
> to_bpp_x16(bpp);
> drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc
> %d\n", slots, bpp, dsc);
> }
>
> @@ -238,13 +238,13 @@ static int
> intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> if (slots < 0)
> return slots;
>
> - last_compressed_bpp = crtc_state->dsc.compressed_bpp;
> + last_compressed_bpp = to_bpp_int(crtc_state-
> >dsc.compressed_bpp_x16);
>
> - crtc_state->dsc.compressed_bpp =
> intel_dp_dsc_nearest_valid_bpp(i915,
> -
> last_compressed_bpp,
> -
> crtc_state->pipe_bpp);
> + crtc_state->dsc.compressed_bpp_x16 =
> +
> to_bpp_x16(intel_dp_dsc_nearest_valid_bpp(i915,
> last_compressed_bpp,
> +
> crtc_state->pipe_bpp));
>
> - if (crtc_state->dsc.compressed_bpp != last_compressed_bpp)
> + if (crtc_state->dsc.compressed_bpp_x16 !=
> +to_bpp_x16(last_compressed_bpp))
> need_timeslot_recalc = true;
>
> /*
> @@ -253,14 +253,14 @@ static int
> intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> */
> if (need_timeslot_recalc) {
> slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder,
> crtc_state,
> - crtc_state-
> >dsc.compressed_bpp,
> - crtc_state-
> >dsc.compressed_bpp,
> +
> to_bpp_int(crtc_state->dsc.compressed_bpp_x16),
> +
> to_bpp_int(crtc_state->dsc.compressed_bpp_x16),
> limits, conn_state,
> 2 * 3, true);
> if (slots < 0)
> return slots;
> }
>
> - intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
> + intel_link_compute_m_n(to_bpp_int(crtc_state-
> >dsc.compressed_bpp_x16),
> crtc_state->lane_count,
> adjusted_mode->crtc_clock,
> crtc_state->port_clock,
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index b24601d0b2c5..bfc41972a0bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -248,7 +248,7 @@ int intel_dsc_compute_params(struct intel_crtc_state
> *pipe_config)
> struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
> - u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
> + u16 compressed_bpp = to_bpp_int(pipe_config-
> >dsc.compressed_bpp_x16);
> int err;
> int ret;
>
> @@ -878,7 +878,7 @@ static void intel_dsc_get_pps_config(struct
> intel_crtc_state *crtc_state)
> if (vdsc_cfg->native_420)
> vdsc_cfg->bits_per_pixel >>= 1;
>
> - crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> + crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;
>
> /* PPS_2 */
> intel_dsc_read_and_verify_pps_reg(crtc_state, 2, &pps_temp);
> --
> 2.25.1
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format
2023-09-11 9:13 ` Kandpal, Suraj
@ 2023-09-11 9:17 ` Kandpal, Suraj
0 siblings, 0 replies; 27+ messages in thread
From: Kandpal, Suraj @ 2023-09-11 9:17 UTC (permalink / raw)
To: Golani, Mitulkumar Ajitkumar, intel-gfx@lists.freedesktop.org
> Subject: RE: [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4
> format
>
> > Subject: [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4
> > format
> >
> > From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >
> > DSC parameter bits_per_pixel is stored in U6.4 format.
> > The 4 bits represent the fractional part of the bpp.
> > Currently we use compressed_bpp member of dsc structure to store only
> > the integral part of the bits_per_pixel.
> > To store the full bits_per_pixel along with the fractional part,
> > compressed_bpp is changed to store bpp in U6.4 formats. Intergral part
> > is retrieved by simply right shifting the member compressed_bpp by 4.
> >
> > v2:
> > -Use to_bpp_int, to_bpp_frac_dec, to_bpp_x16 helpers while dealing
> > with compressed bpp. (Suraj) -Fix comment styling. (Suraj)
> >
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/icl_dsi.c | 10 ++++----
> > drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_bios.c | 4 +--
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> > .../drm/i915/display/intel_display_types.h | 18 ++++++++++++-
> > drivers/gpu/drm/i915/display/intel_dp.c | 25 +++++++++++--------
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 18 ++++++-------
> > drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +--
> > 9 files changed, 52 insertions(+), 33 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index ad6488e9c2b2..df98f35bbcda 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -330,7 +330,7 @@ static int afe_clk(struct intel_encoder *encoder,
> > int bpp;
> >
> > if (crtc_state->dsc.compression_enable)
> > - bpp = crtc_state->dsc.compressed_bpp;
> > + bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
> > else
> > bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
> >
> > @@ -860,7 +860,7 @@ gen11_dsi_set_transcoder_timings(struct
> > intel_encoder *encoder,
> > * compressed and non-compressed bpp.
> > */
> > if (crtc_state->dsc.compression_enable) {
> > - mul = crtc_state->dsc.compressed_bpp;
> > + mul = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
> > div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
> > }
> >
> > @@ -884,7 +884,7 @@ gen11_dsi_set_transcoder_timings(struct
> > intel_encoder *encoder,
> > int bpp, line_time_us, byte_clk_period_ns;
> >
> > if (crtc_state->dsc.compression_enable)
> > - bpp = crtc_state->dsc.compressed_bpp;
> > + bpp = to_bpp_int(crtc_state-
> > >dsc.compressed_bpp_x16);
> > else
> > bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi-
> > >pixel_format);
> >
> > @@ -1451,8 +1451,8 @@ static void gen11_dsi_get_timings(struct
> > intel_encoder *encoder,
> > struct drm_display_mode *adjusted_mode =
> > &pipe_config->hw.adjusted_mode;
> >
> > - if (pipe_config->dsc.compressed_bpp) {
> > - int div = pipe_config->dsc.compressed_bpp;
> > + if (pipe_config->dsc.compressed_bpp_x16) {
> > + int div = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
> > int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi-
> > >pixel_format);
> >
> > adjusted_mode->crtc_htotal =
> > diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> > b/drivers/gpu/drm/i915/display/intel_audio.c
> > index 19605264a35c..aa93ccd6c2aa 100644
> > --- a/drivers/gpu/drm/i915/display/intel_audio.c
> > +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> > @@ -528,7 +528,7 @@ static unsigned int calc_hblank_early_prog(struct
> > intel_encoder *encoder,
> > h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> > h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
> > pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
> > - vdsc_bpp = crtc_state->dsc.compressed_bpp;
> > + vdsc_bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
> > cdclk = i915->display.cdclk.hw.cdclk;
> > /* fec= 0.972261, using rounding multiplier of 1000000 */
> > fec_coeff = 972261;
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > b/drivers/gpu/drm/i915/display/intel_bios.c
> > index 858c959f7bab..7b6d299fbcf2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > @@ -3384,8 +3384,8 @@ static void fill_dsc(struct intel_crtc_state
> > *crtc_state,
> >
> > crtc_state->pipe_bpp = bpc * 3;
> >
> > - crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
> > - VBT_DSC_MAX_BPP(dsc-
> > >max_bpp));
> > + crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(min(crtc_state-
> > >pipe_bpp,
> > +
> > VBT_DSC_MAX_BPP(dsc->max_bpp)));
> >
> > /*
> > * FIXME: This is ugly, and slice count should take DSC engine diff
> > --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index ad5251ba6fe1..06a1e99a2762 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -2567,7 +2567,7 @@ static int intel_vdsc_min_cdclk(const struct
> > intel_crtc_state *crtc_state)
> > * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner
> > Interface bits
> > */
> > int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;
> > - int min_cdclk_bj = (crtc_state->dsc.compressed_bpp *
> > pixel_clock) /
> > + int min_cdclk_bj = (to_bpp_int(crtc_state-
> > >dsc.compressed_bpp_x16) *
> > +pixel_clock) /
> > (2 * bigjoiner_interface_bits);
> >
> > min_cdclk = max(min_cdclk, min_cdclk_bj); diff --git
> > a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 83e1bc858b9f..afcbdd4f105a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -5365,7 +5365,7 @@ intel_pipe_config_compare(const struct
> > intel_crtc_state *current_config,
> >
> > PIPE_CONF_CHECK_I(dsc.compression_enable);
> > PIPE_CONF_CHECK_I(dsc.dsc_split);
> > - PIPE_CONF_CHECK_I(dsc.compressed_bpp);
> > + PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
> >
> > PIPE_CONF_CHECK_BOOL(splitter.enable);
> > PIPE_CONF_CHECK_I(splitter.link_count);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index c21064794f32..9eb7b8912076 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1353,7 +1353,8 @@ struct intel_crtc_state {
> > struct {
> > bool compression_enable;
> > bool dsc_split;
> > - u16 compressed_bpp;
> > + /* Compressed Bpp in U6.4 format (first 4 bits for fractional
> > part) */
> > + u16 compressed_bpp_x16;
> > u8 slice_count;
> > struct drm_dsc_config config;
> > } dsc;
> > @@ -2108,4 +2109,19 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
> > return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL; }
> >
> > +static inline int to_bpp_int(int bpp_x16) {
> > + return bpp_x16 >> 4;
> > +}
> > +
> > +static inline int to_bpp_frac_dec(int bpp_x16) {
> > + return (bpp_x16 & 0xf) * 625;
> > +}
>
> Let's add a comment on top on why we apply the mask and where the value
> 625 comes from Something like:
> "Since compressed bpp is now fractional such that last 4 bits represent
> fractional bits we get the fractional part by multiplying by 10000 then dividing it
> by 16 as we initially left shift compressed bpp by 4, to get 4 bits for the
> fractional part"
>
> Otherwise,
> LGTM.
>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com
>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > +
> > +static inline int to_bpp_x16(int bpp) {
> > + return bpp << 4;
> > +}
> > +
> > #endif /* __INTEL_DISPLAY_TYPES_H__ */ diff --git
> > a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 2206b45bc78c..9b88ac3a73c7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1863,7 +1863,7 @@ icl_dsc_compute_link_config(struct intel_dp
> > *intel_dp,
> > valid_dsc_bpp[i],
> > timeslots);
> > if (ret == 0) {
> > - pipe_config->dsc.compressed_bpp = valid_dsc_bpp[i];
> > + pipe_config->dsc.compressed_bpp_x16 =
> > to_bpp_x16(valid_dsc_bpp[i]);
> > return 0;
> > }
> > }
> > @@ -1901,7 +1901,7 @@ xelpd_dsc_compute_link_config(struct intel_dp
> > *intel_dp,
> > compressed_bpp,
> > timeslots);
> > if (ret == 0) {
> > - pipe_config->dsc.compressed_bpp =
> > compressed_bpp;
> > + pipe_config->dsc.compressed_bpp_x16 =
> > to_bpp_x16(compressed_bpp);
> > return 0;
> > }
> > }
> > @@ -2085,7 +2085,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct
> > intel_dp *intel_dp,
> > /* Compressed BPP should be less than the Input DSC bpp */
> > dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
> >
> > - pipe_config->dsc.compressed_bpp = max(dsc_min_bpp,
> > dsc_max_bpp);
> > + pipe_config->dsc.compressed_bpp_x16 =
> > to_bpp_x16(max(dsc_min_bpp,
> > +dsc_max_bpp));
> >
> > pipe_config->pipe_bpp = pipe_bpp;
> >
> > @@ -2172,17 +2172,19 @@ int intel_dp_dsc_compute_config(struct
> > intel_dp *intel_dp,
> > if (ret < 0) {
> > drm_dbg_kms(&dev_priv->drm,
> > "Cannot compute valid DSC parameters for Input
> Bpp = %d "
> > - "Compressed BPP = %d\n",
> > + "Compressed BPP = %d.%d\n",
> > pipe_config->pipe_bpp,
> > - pipe_config->dsc.compressed_bpp);
> > + to_bpp_int(pipe_config->dsc.compressed_bpp_x16),
> > + to_bpp_frac_dec(pipe_config-
> > >dsc.compressed_bpp_x16));
> > return ret;
> > }
> >
> > pipe_config->dsc.compression_enable = true;
> > drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp =
> %d "
> > - "Compressed Bpp = %d Slice Count = %d\n",
> > + "Compressed Bpp = %d.%d Slice Count = %d\n",
> > pipe_config->pipe_bpp,
> > - pipe_config->dsc.compressed_bpp,
> > + to_bpp_int(pipe_config->dsc.compressed_bpp_x16),
> > + to_bpp_frac_dec(pipe_config->dsc.compressed_bpp_x16),
> > pipe_config->dsc.slice_count);
> >
> > return 0;
> > @@ -2261,15 +2263,16 @@ intel_dp_compute_link_config(struct
> > intel_encoder *encoder,
> >
> > if (pipe_config->dsc.compression_enable) {
> > drm_dbg_kms(&i915->drm,
> > - "DP lane count %d clock %d Input bpp %d
> > Compressed bpp %d\n",
> > + "DP lane count %d clock %d Input bpp %d
> > Compressed bpp %d.%d\n",
> > pipe_config->lane_count, pipe_config->port_clock,
> > pipe_config->pipe_bpp,
> > - pipe_config->dsc.compressed_bpp);
> > + to_bpp_int(pipe_config->dsc.compressed_bpp_x16),
> > + to_bpp_frac_dec(pipe_config-
> > >dsc.compressed_bpp_x16));
> >
> > drm_dbg_kms(&i915->drm,
> > "DP link rate required %i available %i\n",
> > intel_dp_link_required(adjusted_mode->crtc_clock,
> > - pipe_config-
> > >dsc.compressed_bpp),
> > + to_bpp_int(pipe_config-
> > >dsc.compressed_bpp_x16)),
> > intel_dp_max_data_rate(pipe_config->port_clock,
> > pipe_config->lane_count));
> > } else {
> > @@ -2702,7 +2705,7 @@ intel_dp_compute_config(struct intel_encoder
> > *encoder,
> > intel_dp_limited_color_range(pipe_config, conn_state);
> >
> > if (pipe_config->dsc.compression_enable)
> > - link_bpp = pipe_config->dsc.compressed_bpp;
> > + link_bpp = pipe_config->dsc.compressed_bpp_x16;
> > else
> > link_bpp = intel_dp_output_bpp(pipe_config->output_format,
> > pipe_config->pipe_bpp);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 2d1c42a5e684..68a81f10e772 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -140,7 +140,7 @@ static int
> > intel_dp_mst_find_vcpi_slots_for_bpp(struct
> > intel_encoder *encoder,
> > if (!dsc)
> > crtc_state->pipe_bpp = bpp;
> > else
> > - crtc_state->dsc.compressed_bpp = bpp;
> > + crtc_state->dsc.compressed_bpp_x16 =
> > to_bpp_x16(bpp);
> > drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc
> %d\n",
> > slots, bpp, dsc);
> > }
> >
> > @@ -238,13 +238,13 @@ static int
> > intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> > if (slots < 0)
> > return slots;
> >
> > - last_compressed_bpp = crtc_state->dsc.compressed_bpp;
> > + last_compressed_bpp = to_bpp_int(crtc_state-
> > >dsc.compressed_bpp_x16);
> >
> > - crtc_state->dsc.compressed_bpp =
> > intel_dp_dsc_nearest_valid_bpp(i915,
> > -
> > last_compressed_bpp,
> > -
> > crtc_state->pipe_bpp);
> > + crtc_state->dsc.compressed_bpp_x16 =
> > +
> > to_bpp_x16(intel_dp_dsc_nearest_valid_bpp(i915,
> > last_compressed_bpp,
> > +
> > crtc_state->pipe_bpp));
> >
> > - if (crtc_state->dsc.compressed_bpp != last_compressed_bpp)
> > + if (crtc_state->dsc.compressed_bpp_x16 !=
> > +to_bpp_x16(last_compressed_bpp))
> > need_timeslot_recalc = true;
> >
> > /*
> > @@ -253,14 +253,14 @@ static int
> > intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> > */
> > if (need_timeslot_recalc) {
> > slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder,
> > crtc_state,
> > - crtc_state-
> > >dsc.compressed_bpp,
> > - crtc_state-
> > >dsc.compressed_bpp,
> > +
> > to_bpp_int(crtc_state->dsc.compressed_bpp_x16),
> > +
> > to_bpp_int(crtc_state->dsc.compressed_bpp_x16),
> > limits, conn_state,
> > 2 * 3, true);
> > if (slots < 0)
> > return slots;
> > }
> >
> > - intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
> > + intel_link_compute_m_n(to_bpp_int(crtc_state-
> > >dsc.compressed_bpp_x16),
> > crtc_state->lane_count,
> > adjusted_mode->crtc_clock,
> > crtc_state->port_clock,
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index b24601d0b2c5..bfc41972a0bb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -248,7 +248,7 @@ int intel_dsc_compute_params(struct
> > intel_crtc_state
> > *pipe_config)
> > struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
> > - u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
> > + u16 compressed_bpp = to_bpp_int(pipe_config-
> > >dsc.compressed_bpp_x16);
> > int err;
> > int ret;
> >
> > @@ -878,7 +878,7 @@ static void intel_dsc_get_pps_config(struct
> > intel_crtc_state *crtc_state)
> > if (vdsc_cfg->native_420)
> > vdsc_cfg->bits_per_pixel >>= 1;
> >
> > - crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> > + crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;
> >
> > /* PPS_2 */
> > intel_dsc_read_and_verify_pps_reg(crtc_state, 2, &pps_temp);
> > --
> > 2.25.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format
2023-09-11 5:05 ` [Intel-gfx] [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format Mitul Golani
2023-09-11 9:13 ` Kandpal, Suraj
@ 2023-09-11 11:36 ` Jani Nikula
2023-09-11 12:03 ` Golani, Mitulkumar Ajitkumar
1 sibling, 1 reply; 27+ messages in thread
From: Jani Nikula @ 2023-09-11 11:36 UTC (permalink / raw)
To: Mitul Golani, intel-gfx
On Mon, 11 Sep 2023, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> wrote:
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>
> DSC parameter bits_per_pixel is stored in U6.4 format.
> The 4 bits represent the fractional part of the bpp.
> Currently we use compressed_bpp member of dsc structure to store
> only the integral part of the bits_per_pixel.
> To store the full bits_per_pixel along with the fractional part,
> compressed_bpp is changed to store bpp in U6.4 formats. Intergral
> part is retrieved by simply right shifting the member compressed_bpp by 4.
>
> v2:
> -Use to_bpp_int, to_bpp_frac_dec, to_bpp_x16 helpers while dealing
> with compressed bpp. (Suraj)
> -Fix comment styling. (Suraj)
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 10 ++++----
> drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
> drivers/gpu/drm/i915/display/intel_bios.c | 4 +--
> drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> .../drm/i915/display/intel_display_types.h | 18 ++++++++++++-
> drivers/gpu/drm/i915/display/intel_dp.c | 25 +++++++++++--------
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 18 ++++++-------
> drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +--
> 9 files changed, 52 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index ad6488e9c2b2..df98f35bbcda 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -330,7 +330,7 @@ static int afe_clk(struct intel_encoder *encoder,
> int bpp;
>
> if (crtc_state->dsc.compression_enable)
> - bpp = crtc_state->dsc.compressed_bpp;
> + bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
> else
> bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
>
> @@ -860,7 +860,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
> * compressed and non-compressed bpp.
> */
> if (crtc_state->dsc.compression_enable) {
> - mul = crtc_state->dsc.compressed_bpp;
> + mul = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
> div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
> }
>
> @@ -884,7 +884,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
> int bpp, line_time_us, byte_clk_period_ns;
>
> if (crtc_state->dsc.compression_enable)
> - bpp = crtc_state->dsc.compressed_bpp;
> + bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
> else
> bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
>
> @@ -1451,8 +1451,8 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
> struct drm_display_mode *adjusted_mode =
> &pipe_config->hw.adjusted_mode;
>
> - if (pipe_config->dsc.compressed_bpp) {
> - int div = pipe_config->dsc.compressed_bpp;
> + if (pipe_config->dsc.compressed_bpp_x16) {
> + int div = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
> int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
>
> adjusted_mode->crtc_htotal =
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> index 19605264a35c..aa93ccd6c2aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -528,7 +528,7 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
> h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
> pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
> - vdsc_bpp = crtc_state->dsc.compressed_bpp;
> + vdsc_bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
> cdclk = i915->display.cdclk.hw.cdclk;
> /* fec= 0.972261, using rounding multiplier of 1000000 */
> fec_coeff = 972261;
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 858c959f7bab..7b6d299fbcf2 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -3384,8 +3384,8 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
>
> crtc_state->pipe_bpp = bpc * 3;
>
> - crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
> - VBT_DSC_MAX_BPP(dsc->max_bpp));
> + crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(min(crtc_state->pipe_bpp,
> + VBT_DSC_MAX_BPP(dsc->max_bpp)));
>
> /*
> * FIXME: This is ugly, and slice count should take DSC engine
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index ad5251ba6fe1..06a1e99a2762 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2567,7 +2567,7 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
> * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
> */
> int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;
> - int min_cdclk_bj = (crtc_state->dsc.compressed_bpp * pixel_clock) /
> + int min_cdclk_bj = (to_bpp_int(crtc_state->dsc.compressed_bpp_x16) * pixel_clock) /
> (2 * bigjoiner_interface_bits);
>
> min_cdclk = max(min_cdclk, min_cdclk_bj);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 83e1bc858b9f..afcbdd4f105a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5365,7 +5365,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>
> PIPE_CONF_CHECK_I(dsc.compression_enable);
> PIPE_CONF_CHECK_I(dsc.dsc_split);
> - PIPE_CONF_CHECK_I(dsc.compressed_bpp);
> + PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
>
> PIPE_CONF_CHECK_BOOL(splitter.enable);
> PIPE_CONF_CHECK_I(splitter.link_count);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c21064794f32..9eb7b8912076 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1353,7 +1353,8 @@ struct intel_crtc_state {
> struct {
> bool compression_enable;
> bool dsc_split;
> - u16 compressed_bpp;
> + /* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
> + u16 compressed_bpp_x16;
> u8 slice_count;
> struct drm_dsc_config config;
> } dsc;
> @@ -2108,4 +2109,19 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
> return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
> }
>
> +static inline int to_bpp_int(int bpp_x16)
> +{
> + return bpp_x16 >> 4;
> +}
> +
> +static inline int to_bpp_frac_dec(int bpp_x16)
> +{
> + return (bpp_x16 & 0xf) * 625;
> +}
> +
> +static inline int to_bpp_x16(int bpp)
> +{
> + return bpp << 4;
> +}
> +
This file is not the place for random helpers.
It could even be a separate file for 6.4 fixed point.
At some point we might want to move this to drm core even, and perhaps
it could even be a struct so there are no misuses, but gotta start
somewhere.
(There's an include/drm/drm_fixed.h for 20.12, for instance.)
BR,
Jani.
> #endif /* __INTEL_DISPLAY_TYPES_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2206b45bc78c..9b88ac3a73c7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1863,7 +1863,7 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
> valid_dsc_bpp[i],
> timeslots);
> if (ret == 0) {
> - pipe_config->dsc.compressed_bpp = valid_dsc_bpp[i];
> + pipe_config->dsc.compressed_bpp_x16 = to_bpp_x16(valid_dsc_bpp[i]);
> return 0;
> }
> }
> @@ -1901,7 +1901,7 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
> compressed_bpp,
> timeslots);
> if (ret == 0) {
> - pipe_config->dsc.compressed_bpp = compressed_bpp;
> + pipe_config->dsc.compressed_bpp_x16 = to_bpp_x16(compressed_bpp);
> return 0;
> }
> }
> @@ -2085,7 +2085,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
> /* Compressed BPP should be less than the Input DSC bpp */
> dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
>
> - pipe_config->dsc.compressed_bpp = max(dsc_min_bpp, dsc_max_bpp);
> + pipe_config->dsc.compressed_bpp_x16 = to_bpp_x16(max(dsc_min_bpp, dsc_max_bpp));
>
> pipe_config->pipe_bpp = pipe_bpp;
>
> @@ -2172,17 +2172,19 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> if (ret < 0) {
> drm_dbg_kms(&dev_priv->drm,
> "Cannot compute valid DSC parameters for Input Bpp = %d "
> - "Compressed BPP = %d\n",
> + "Compressed BPP = %d.%d\n",
> pipe_config->pipe_bpp,
> - pipe_config->dsc.compressed_bpp);
> + to_bpp_int(pipe_config->dsc.compressed_bpp_x16),
> + to_bpp_frac_dec(pipe_config->dsc.compressed_bpp_x16));
> return ret;
> }
>
> pipe_config->dsc.compression_enable = true;
> drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
> - "Compressed Bpp = %d Slice Count = %d\n",
> + "Compressed Bpp = %d.%d Slice Count = %d\n",
> pipe_config->pipe_bpp,
> - pipe_config->dsc.compressed_bpp,
> + to_bpp_int(pipe_config->dsc.compressed_bpp_x16),
> + to_bpp_frac_dec(pipe_config->dsc.compressed_bpp_x16),
> pipe_config->dsc.slice_count);
>
> return 0;
> @@ -2261,15 +2263,16 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>
> if (pipe_config->dsc.compression_enable) {
> drm_dbg_kms(&i915->drm,
> - "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
> + "DP lane count %d clock %d Input bpp %d Compressed bpp %d.%d\n",
> pipe_config->lane_count, pipe_config->port_clock,
> pipe_config->pipe_bpp,
> - pipe_config->dsc.compressed_bpp);
> + to_bpp_int(pipe_config->dsc.compressed_bpp_x16),
> + to_bpp_frac_dec(pipe_config->dsc.compressed_bpp_x16));
>
> drm_dbg_kms(&i915->drm,
> "DP link rate required %i available %i\n",
> intel_dp_link_required(adjusted_mode->crtc_clock,
> - pipe_config->dsc.compressed_bpp),
> + to_bpp_int(pipe_config->dsc.compressed_bpp_x16)),
> intel_dp_max_data_rate(pipe_config->port_clock,
> pipe_config->lane_count));
> } else {
> @@ -2702,7 +2705,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> intel_dp_limited_color_range(pipe_config, conn_state);
>
> if (pipe_config->dsc.compression_enable)
> - link_bpp = pipe_config->dsc.compressed_bpp;
> + link_bpp = pipe_config->dsc.compressed_bpp_x16;
> else
> link_bpp = intel_dp_output_bpp(pipe_config->output_format,
> pipe_config->pipe_bpp);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 2d1c42a5e684..68a81f10e772 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -140,7 +140,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> if (!dsc)
> crtc_state->pipe_bpp = bpp;
> else
> - crtc_state->dsc.compressed_bpp = bpp;
> + crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(bpp);
> drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);
> }
>
> @@ -238,13 +238,13 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> if (slots < 0)
> return slots;
>
> - last_compressed_bpp = crtc_state->dsc.compressed_bpp;
> + last_compressed_bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
>
> - crtc_state->dsc.compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915,
> - last_compressed_bpp,
> - crtc_state->pipe_bpp);
> + crtc_state->dsc.compressed_bpp_x16 =
> + to_bpp_x16(intel_dp_dsc_nearest_valid_bpp(i915, last_compressed_bpp,
> + crtc_state->pipe_bpp));
>
> - if (crtc_state->dsc.compressed_bpp != last_compressed_bpp)
> + if (crtc_state->dsc.compressed_bpp_x16 != to_bpp_x16(last_compressed_bpp))
> need_timeslot_recalc = true;
>
> /*
> @@ -253,14 +253,14 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> */
> if (need_timeslot_recalc) {
> slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
> - crtc_state->dsc.compressed_bpp,
> - crtc_state->dsc.compressed_bpp,
> + to_bpp_int(crtc_state->dsc.compressed_bpp_x16),
> + to_bpp_int(crtc_state->dsc.compressed_bpp_x16),
> limits, conn_state, 2 * 3, true);
> if (slots < 0)
> return slots;
> }
>
> - intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
> + intel_link_compute_m_n(to_bpp_int(crtc_state->dsc.compressed_bpp_x16),
> crtc_state->lane_count,
> adjusted_mode->crtc_clock,
> crtc_state->port_clock,
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index b24601d0b2c5..bfc41972a0bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -248,7 +248,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
> - u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
> + u16 compressed_bpp = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
> int err;
> int ret;
>
> @@ -878,7 +878,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
> if (vdsc_cfg->native_420)
> vdsc_cfg->bits_per_pixel >>= 1;
>
> - crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> + crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;
>
> /* PPS_2 */
> intel_dsc_read_and_verify_pps_reg(crtc_state, 2, &pps_temp);
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format
2023-09-11 11:36 ` Jani Nikula
@ 2023-09-11 12:03 ` Golani, Mitulkumar Ajitkumar
0 siblings, 0 replies; 27+ messages in thread
From: Golani, Mitulkumar Ajitkumar @ 2023-09-11 12:03 UTC (permalink / raw)
To: Jani Nikula, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: 11 September 2023 17:07
> To: Golani, Mitulkumar Ajitkumar <mitulkumar.ajitkumar.golani@intel.com>;
> intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 2/8] drm/i915/display: Store compressed bpp
> in U6.4 format
>
> On Mon, 11 Sep 2023, Mitul Golani
> <mitulkumar.ajitkumar.golani@intel.com> wrote:
> > From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >
> > DSC parameter bits_per_pixel is stored in U6.4 format.
> > The 4 bits represent the fractional part of the bpp.
> > Currently we use compressed_bpp member of dsc structure to store only
> > the integral part of the bits_per_pixel.
> > To store the full bits_per_pixel along with the fractional part,
> > compressed_bpp is changed to store bpp in U6.4 formats. Intergral part
> > is retrieved by simply right shifting the member compressed_bpp by 4.
> >
> > v2:
> > -Use to_bpp_int, to_bpp_frac_dec, to_bpp_x16 helpers while dealing
> > with compressed bpp. (Suraj) -Fix comment styling. (Suraj)
> >
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/icl_dsi.c | 10 ++++----
> > drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_bios.c | 4 +--
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> > .../drm/i915/display/intel_display_types.h | 18 ++++++++++++-
> > drivers/gpu/drm/i915/display/intel_dp.c | 25 +++++++++++--------
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 18 ++++++-------
> > drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +--
> > 9 files changed, 52 insertions(+), 33 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index ad6488e9c2b2..df98f35bbcda 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -330,7 +330,7 @@ static int afe_clk(struct intel_encoder *encoder,
> > int bpp;
> >
> > if (crtc_state->dsc.compression_enable)
> > - bpp = crtc_state->dsc.compressed_bpp;
> > + bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
> > else
> > bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi-
> >pixel_format);
> >
> > @@ -860,7 +860,7 @@ gen11_dsi_set_transcoder_timings(struct
> intel_encoder *encoder,
> > * compressed and non-compressed bpp.
> > */
> > if (crtc_state->dsc.compression_enable) {
> > - mul = crtc_state->dsc.compressed_bpp;
> > + mul = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
> > div = mipi_dsi_pixel_format_to_bpp(intel_dsi-
> >pixel_format);
> > }
> >
> > @@ -884,7 +884,7 @@ gen11_dsi_set_transcoder_timings(struct
> intel_encoder *encoder,
> > int bpp, line_time_us, byte_clk_period_ns;
> >
> > if (crtc_state->dsc.compression_enable)
> > - bpp = crtc_state->dsc.compressed_bpp;
> > + bpp = to_bpp_int(crtc_state-
> >dsc.compressed_bpp_x16);
> > else
> > bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi-
> >pixel_format);
> >
> > @@ -1451,8 +1451,8 @@ static void gen11_dsi_get_timings(struct
> intel_encoder *encoder,
> > struct drm_display_mode *adjusted_mode =
> > &pipe_config->hw.adjusted_mode;
> >
> > - if (pipe_config->dsc.compressed_bpp) {
> > - int div = pipe_config->dsc.compressed_bpp;
> > + if (pipe_config->dsc.compressed_bpp_x16) {
> > + int div = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
> > int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi-
> >pixel_format);
> >
> > adjusted_mode->crtc_htotal =
> > diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> > b/drivers/gpu/drm/i915/display/intel_audio.c
> > index 19605264a35c..aa93ccd6c2aa 100644
> > --- a/drivers/gpu/drm/i915/display/intel_audio.c
> > +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> > @@ -528,7 +528,7 @@ static unsigned int calc_hblank_early_prog(struct
> intel_encoder *encoder,
> > h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> > h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
> > pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
> > - vdsc_bpp = crtc_state->dsc.compressed_bpp;
> > + vdsc_bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
> > cdclk = i915->display.cdclk.hw.cdclk;
> > /* fec= 0.972261, using rounding multiplier of 1000000 */
> > fec_coeff = 972261;
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > b/drivers/gpu/drm/i915/display/intel_bios.c
> > index 858c959f7bab..7b6d299fbcf2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > @@ -3384,8 +3384,8 @@ static void fill_dsc(struct intel_crtc_state
> > *crtc_state,
> >
> > crtc_state->pipe_bpp = bpc * 3;
> >
> > - crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
> > - VBT_DSC_MAX_BPP(dsc-
> >max_bpp));
> > + crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(min(crtc_state-
> >pipe_bpp,
> > +
> VBT_DSC_MAX_BPP(dsc->max_bpp)));
> >
> > /*
> > * FIXME: This is ugly, and slice count should take DSC engine diff
> > --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index ad5251ba6fe1..06a1e99a2762 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -2567,7 +2567,7 @@ static int intel_vdsc_min_cdclk(const struct
> intel_crtc_state *crtc_state)
> > * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner
> Interface bits
> > */
> > int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 :
> 24;
> > - int min_cdclk_bj = (crtc_state->dsc.compressed_bpp *
> pixel_clock) /
> > + int min_cdclk_bj = (to_bpp_int(crtc_state-
> >dsc.compressed_bpp_x16)
> > +* pixel_clock) /
> > (2 * bigjoiner_interface_bits);
> >
> > min_cdclk = max(min_cdclk, min_cdclk_bj); diff --git
> > a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 83e1bc858b9f..afcbdd4f105a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -5365,7 +5365,7 @@ intel_pipe_config_compare(const struct
> > intel_crtc_state *current_config,
> >
> > PIPE_CONF_CHECK_I(dsc.compression_enable);
> > PIPE_CONF_CHECK_I(dsc.dsc_split);
> > - PIPE_CONF_CHECK_I(dsc.compressed_bpp);
> > + PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
> >
> > PIPE_CONF_CHECK_BOOL(splitter.enable);
> > PIPE_CONF_CHECK_I(splitter.link_count);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index c21064794f32..9eb7b8912076 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1353,7 +1353,8 @@ struct intel_crtc_state {
> > struct {
> > bool compression_enable;
> > bool dsc_split;
> > - u16 compressed_bpp;
> > + /* Compressed Bpp in U6.4 format (first 4 bits for fractional
> part) */
> > + u16 compressed_bpp_x16;
> > u8 slice_count;
> > struct drm_dsc_config config;
> > } dsc;
> > @@ -2108,4 +2109,19 @@ to_intel_frontbuffer(struct drm_framebuffer
> *fb)
> > return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL; }
> >
> > +static inline int to_bpp_int(int bpp_x16) {
> > + return bpp_x16 >> 4;
> > +}
> > +
> > +static inline int to_bpp_frac_dec(int bpp_x16) {
> > + return (bpp_x16 & 0xf) * 625;
> > +}
> > +
> > +static inline int to_bpp_x16(int bpp) {
> > + return bpp << 4;
> > +}
> > +
>
> This file is not the place for random helpers.
>
> It could even be a separate file for 6.4 fixed point.
>
> At some point we might want to move this to drm core even, and perhaps it
Hi Jani,
Do you have any naming suggestions for the new file and the helpers that will
defined in it.
Regards,
Mitul
> could even be a struct so there are no misuses, but gotta start somewhere.
>
> (There's an include/drm/drm_fixed.h for 20.12, for instance.)
>
>
> BR,
> Jani.
>
>
>
> > #endif /* __INTEL_DISPLAY_TYPES_H__ */ diff --git
> > a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 2206b45bc78c..9b88ac3a73c7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1863,7 +1863,7 @@ icl_dsc_compute_link_config(struct intel_dp
> *intel_dp,
> > valid_dsc_bpp[i],
> > timeslots);
> > if (ret == 0) {
> > - pipe_config->dsc.compressed_bpp =
> valid_dsc_bpp[i];
> > + pipe_config->dsc.compressed_bpp_x16 =
> > +to_bpp_x16(valid_dsc_bpp[i]);
> > return 0;
> > }
> > }
> > @@ -1901,7 +1901,7 @@ xelpd_dsc_compute_link_config(struct intel_dp
> *intel_dp,
> > compressed_bpp,
> > timeslots);
> > if (ret == 0) {
> > - pipe_config->dsc.compressed_bpp =
> compressed_bpp;
> > + pipe_config->dsc.compressed_bpp_x16 =
> to_bpp_x16(compressed_bpp);
> > return 0;
> > }
> > }
> > @@ -2085,7 +2085,7 @@ static int
> intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
> > /* Compressed BPP should be less than the Input DSC bpp */
> > dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
> >
> > - pipe_config->dsc.compressed_bpp = max(dsc_min_bpp,
> dsc_max_bpp);
> > + pipe_config->dsc.compressed_bpp_x16 =
> to_bpp_x16(max(dsc_min_bpp,
> > +dsc_max_bpp));
> >
> > pipe_config->pipe_bpp = pipe_bpp;
> >
> > @@ -2172,17 +2172,19 @@ int intel_dp_dsc_compute_config(struct
> intel_dp *intel_dp,
> > if (ret < 0) {
> > drm_dbg_kms(&dev_priv->drm,
> > "Cannot compute valid DSC parameters for Input
> Bpp = %d "
> > - "Compressed BPP = %d\n",
> > + "Compressed BPP = %d.%d\n",
> > pipe_config->pipe_bpp,
> > - pipe_config->dsc.compressed_bpp);
> > + to_bpp_int(pipe_config-
> >dsc.compressed_bpp_x16),
> > + to_bpp_frac_dec(pipe_config-
> >dsc.compressed_bpp_x16));
> > return ret;
> > }
> >
> > pipe_config->dsc.compression_enable = true;
> > drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp =
> %d "
> > - "Compressed Bpp = %d Slice Count = %d\n",
> > + "Compressed Bpp = %d.%d Slice Count = %d\n",
> > pipe_config->pipe_bpp,
> > - pipe_config->dsc.compressed_bpp,
> > + to_bpp_int(pipe_config->dsc.compressed_bpp_x16),
> > + to_bpp_frac_dec(pipe_config->dsc.compressed_bpp_x16),
> > pipe_config->dsc.slice_count);
> >
> > return 0;
> > @@ -2261,15 +2263,16 @@ intel_dp_compute_link_config(struct
> > intel_encoder *encoder,
> >
> > if (pipe_config->dsc.compression_enable) {
> > drm_dbg_kms(&i915->drm,
> > - "DP lane count %d clock %d Input bpp %d
> Compressed bpp %d\n",
> > + "DP lane count %d clock %d Input bpp %d
> Compressed bpp
> > +%d.%d\n",
> > pipe_config->lane_count, pipe_config->port_clock,
> > pipe_config->pipe_bpp,
> > - pipe_config->dsc.compressed_bpp);
> > + to_bpp_int(pipe_config-
> >dsc.compressed_bpp_x16),
> > + to_bpp_frac_dec(pipe_config-
> >dsc.compressed_bpp_x16));
> >
> > drm_dbg_kms(&i915->drm,
> > "DP link rate required %i available %i\n",
> > intel_dp_link_required(adjusted_mode-
> >crtc_clock,
> > - pipe_config-
> >dsc.compressed_bpp),
> > + to_bpp_int(pipe_config-
> >dsc.compressed_bpp_x16)),
> > intel_dp_max_data_rate(pipe_config->port_clock,
> > pipe_config->lane_count));
> > } else {
> > @@ -2702,7 +2705,7 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
> > intel_dp_limited_color_range(pipe_config, conn_state);
> >
> > if (pipe_config->dsc.compression_enable)
> > - link_bpp = pipe_config->dsc.compressed_bpp;
> > + link_bpp = pipe_config->dsc.compressed_bpp_x16;
> > else
> > link_bpp = intel_dp_output_bpp(pipe_config-
> >output_format,
> > pipe_config->pipe_bpp);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 2d1c42a5e684..68a81f10e772 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -140,7 +140,7 @@ static int
> intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> > if (!dsc)
> > crtc_state->pipe_bpp = bpp;
> > else
> > - crtc_state->dsc.compressed_bpp = bpp;
> > + crtc_state->dsc.compressed_bpp_x16 =
> to_bpp_x16(bpp);
> > drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d
> dsc %d\n", slots, bpp, dsc);
> > }
> >
> > @@ -238,13 +238,13 @@ static int
> intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> > if (slots < 0)
> > return slots;
> >
> > - last_compressed_bpp = crtc_state->dsc.compressed_bpp;
> > + last_compressed_bpp =
> > +to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
> >
> > - crtc_state->dsc.compressed_bpp =
> intel_dp_dsc_nearest_valid_bpp(i915,
> > -
> last_compressed_bpp,
> > -
> crtc_state->pipe_bpp);
> > + crtc_state->dsc.compressed_bpp_x16 =
> > +
> to_bpp_x16(intel_dp_dsc_nearest_valid_bpp(i915,
> last_compressed_bpp,
> > +
> crtc_state->pipe_bpp));
> >
> > - if (crtc_state->dsc.compressed_bpp != last_compressed_bpp)
> > + if (crtc_state->dsc.compressed_bpp_x16 !=
> > +to_bpp_x16(last_compressed_bpp))
> > need_timeslot_recalc = true;
> >
> > /*
> > @@ -253,14 +253,14 @@ static int
> intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
> > */
> > if (need_timeslot_recalc) {
> > slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder,
> crtc_state,
> > - crtc_state-
> >dsc.compressed_bpp,
> > - crtc_state-
> >dsc.compressed_bpp,
> > +
> to_bpp_int(crtc_state->dsc.compressed_bpp_x16),
> > +
> to_bpp_int(crtc_state->dsc.compressed_bpp_x16),
> > limits, conn_state,
> 2 * 3, true);
> > if (slots < 0)
> > return slots;
> > }
> >
> > - intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
> > +
> > +intel_link_compute_m_n(to_bpp_int(crtc_state-
> >dsc.compressed_bpp_x16)
> > +,
> > crtc_state->lane_count,
> > adjusted_mode->crtc_clock,
> > crtc_state->port_clock,
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index b24601d0b2c5..bfc41972a0bb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -248,7 +248,7 @@ int intel_dsc_compute_params(struct
> intel_crtc_state *pipe_config)
> > struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
> > - u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
> > + u16 compressed_bpp =
> > +to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
> > int err;
> > int ret;
> >
> > @@ -878,7 +878,7 @@ static void intel_dsc_get_pps_config(struct
> intel_crtc_state *crtc_state)
> > if (vdsc_cfg->native_420)
> > vdsc_cfg->bits_per_pixel >>= 1;
> >
> > - crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
> > + crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;
> >
> > /* PPS_2 */
> > intel_dsc_read_and_verify_pps_reg(crtc_state, 2, &pps_temp);
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 3/8] drm/i915/display: Consider fractional vdsc bpp while computing m_n values
2023-09-11 5:05 [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support Mitul Golani
2023-09-11 5:05 ` [Intel-gfx] [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp prescision Mitul Golani
2023-09-11 5:05 ` [Intel-gfx] [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format Mitul Golani
@ 2023-09-11 5:05 ` Mitul Golani
2023-09-11 9:15 ` Kandpal, Suraj
2023-09-11 5:05 ` [Intel-gfx] [PATCH 4/8] drm/i915/audio : Consider fractional vdsc bpp while computing tu_data Mitul Golani
` (7 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Mitul Golani @ 2023-09-11 5:05 UTC (permalink / raw)
To: intel-gfx
From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate this precision while computing m_n values.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++++-
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 5 +++--
drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 ++++--
drivers/gpu/drm/i915/display/intel_fdi.c | 2 +-
5 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index afcbdd4f105a..b37aeac961f4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2380,10 +2380,14 @@ void
intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
- bool fec_enable)
+ bool fec_enable,
+ bool is_dsc_fractional_bpp)
{
u32 data_clock = bits_per_pixel * pixel_clock;
+ if (is_dsc_fractional_bpp)
+ data_clock = DIV_ROUND_UP(bits_per_pixel * pixel_clock, 16);
+
if (fec_enable)
data_clock = intel_dp_mode_to_fec_clock(data_clock);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 49ac8473b988..a4c4ca3cad65 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -398,7 +398,7 @@ u8 intel_calc_active_pipes(struct intel_atomic_state *state,
void intel_link_compute_m_n(u16 bpp, int nlanes,
int pixel_clock, int link_clock,
struct intel_link_m_n *m_n,
- bool fec_enable);
+ bool fec_enable, bool is_dsc_fractional_bpp);
u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier);
enum drm_mode_status
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9b88ac3a73c7..d13fa2749eaf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2558,7 +2558,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock,
pipe_config->port_clock, &pipe_config->dp_m2_n2,
- pipe_config->fec_enable);
+ pipe_config->fec_enable, false);
/* FIXME: abstract this better */
if (pipe_config->splitter.enable)
@@ -2737,7 +2737,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
adjusted_mode->crtc_clock,
pipe_config->port_clock,
&pipe_config->dp_m_n,
- pipe_config->fec_enable);
+ pipe_config->fec_enable,
+ pipe_config->dsc.compression_enable);
/* FIXME: abstract this better */
if (pipe_config->splitter.enable)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 68a81f10e772..68630925a0b9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -171,7 +171,8 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
adjusted_mode->crtc_clock,
crtc_state->port_clock,
&crtc_state->dp_m_n,
- crtc_state->fec_enable);
+ crtc_state->fec_enable,
+ false);
crtc_state->dp_m_n.tu = slots;
return 0;
@@ -265,7 +266,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
adjusted_mode->crtc_clock,
crtc_state->port_clock,
&crtc_state->dp_m_n,
- crtc_state->fec_enable);
+ crtc_state->fec_enable,
+ crtc_state->dsc.compression_enable);
crtc_state->dp_m_n.tu = slots;
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index e12b46a84fa1..15fddabf7c2e 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -259,7 +259,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
pipe_config->fdi_lanes = lane;
intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
- link_bw, &pipe_config->fdi_m_n, false);
+ link_bw, &pipe_config->fdi_m_n, false, false);
ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config);
if (ret == -EDEADLK)
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 3/8] drm/i915/display: Consider fractional vdsc bpp while computing m_n values
2023-09-11 5:05 ` [Intel-gfx] [PATCH 3/8] drm/i915/display: Consider fractional vdsc bpp while computing m_n values Mitul Golani
@ 2023-09-11 9:15 ` Kandpal, Suraj
0 siblings, 0 replies; 27+ messages in thread
From: Kandpal, Suraj @ 2023-09-11 9:15 UTC (permalink / raw)
To: Golani, Mitulkumar Ajitkumar, intel-gfx@lists.freedesktop.org
> Subject: [PATCH 3/8] drm/i915/display: Consider fractional vdsc bpp while
> computing m_n values
>
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>
> MTL+ supports fractional compressed bits_per_pixel, with precision of
> 1/16. This compressed bpp is stored in U6.4 format.
> Accommodate this precision while computing m_n values.
>
LGTM.
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 6 +++++-
> drivers/gpu/drm/i915/display/intel_display.h | 2 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 5 +++--
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 ++++--
> drivers/gpu/drm/i915/display/intel_fdi.c | 2 +-
> 5 files changed, 14 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index afcbdd4f105a..b37aeac961f4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2380,10 +2380,14 @@ void
> intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
> int pixel_clock, int link_clock,
> struct intel_link_m_n *m_n,
> - bool fec_enable)
> + bool fec_enable,
> + bool is_dsc_fractional_bpp)
> {
> u32 data_clock = bits_per_pixel * pixel_clock;
>
> + if (is_dsc_fractional_bpp)
> + data_clock = DIV_ROUND_UP(bits_per_pixel * pixel_clock, 16);
> +
> if (fec_enable)
> data_clock = intel_dp_mode_to_fec_clock(data_clock);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 49ac8473b988..a4c4ca3cad65 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -398,7 +398,7 @@ u8 intel_calc_active_pipes(struct intel_atomic_state
> *state, void intel_link_compute_m_n(u16 bpp, int nlanes,
> int pixel_clock, int link_clock,
> struct intel_link_m_n *m_n,
> - bool fec_enable);
> + bool fec_enable, bool is_dsc_fractional_bpp);
> u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> u32 pixel_format, u64 modifier); enum
> drm_mode_status diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9b88ac3a73c7..d13fa2749eaf 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2558,7 +2558,7 @@ intel_dp_drrs_compute_config(struct
> intel_connector *connector,
>
> intel_link_compute_m_n(link_bpp, pipe_config->lane_count,
> pixel_clock,
> pipe_config->port_clock, &pipe_config-
> >dp_m2_n2,
> - pipe_config->fec_enable);
> + pipe_config->fec_enable, false);
>
> /* FIXME: abstract this better */
> if (pipe_config->splitter.enable)
> @@ -2737,7 +2737,8 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
> adjusted_mode->crtc_clock,
> pipe_config->port_clock,
> &pipe_config->dp_m_n,
> - pipe_config->fec_enable);
> + pipe_config->fec_enable,
> + pipe_config->dsc.compression_enable);
>
> /* FIXME: abstract this better */
> if (pipe_config->splitter.enable)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 68a81f10e772..68630925a0b9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -171,7 +171,8 @@ static int intel_dp_mst_compute_link_config(struct
> intel_encoder *encoder,
> adjusted_mode->crtc_clock,
> crtc_state->port_clock,
> &crtc_state->dp_m_n,
> - crtc_state->fec_enable);
> + crtc_state->fec_enable,
> + false);
> crtc_state->dp_m_n.tu = slots;
>
> return 0;
> @@ -265,7 +266,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct
> intel_encoder *encoder,
> adjusted_mode->crtc_clock,
> crtc_state->port_clock,
> &crtc_state->dp_m_n,
> - crtc_state->fec_enable);
> + crtc_state->fec_enable,
> + crtc_state->dsc.compression_enable);
> crtc_state->dp_m_n.tu = slots;
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
> b/drivers/gpu/drm/i915/display/intel_fdi.c
> index e12b46a84fa1..15fddabf7c2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -259,7 +259,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
> pipe_config->fdi_lanes = lane;
>
> intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> - link_bw, &pipe_config->fdi_m_n, false);
> + link_bw, &pipe_config->fdi_m_n, false, false);
>
> ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config);
> if (ret == -EDEADLK)
> --
> 2.25.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 4/8] drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
2023-09-11 5:05 [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support Mitul Golani
` (2 preceding siblings ...)
2023-09-11 5:05 ` [Intel-gfx] [PATCH 3/8] drm/i915/display: Consider fractional vdsc bpp while computing m_n values Mitul Golani
@ 2023-09-11 5:05 ` Mitul Golani
2023-09-11 9:16 ` Kandpal, Suraj
2023-09-11 5:05 ` [Intel-gfx] [PATCH 5/8] drm/i915/dsc/mtl: Add support for fractional bpp Mitul Golani
` (6 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Mitul Golani @ 2023-09-11 5:05 UTC (permalink / raw)
To: intel-gfx
From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
MTL+ supports fractional compressed bits_per_pixel, with precision of
1/16. This compressed bpp is stored in U6.4 format.
Accommodate the precision during calculation of transfer unit data
for hblank_early calculation.
v2:
-Fixed tu_data calculation while dealing with U6.4 format. (Stan)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_audio.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index aa93ccd6c2aa..cfbaa7006905 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -521,14 +521,14 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
unsigned int link_clks_available, link_clks_required;
unsigned int tu_data, tu_line, link_clks_active;
unsigned int h_active, h_total, hblank_delta, pixel_clk;
- unsigned int fec_coeff, cdclk, vdsc_bpp;
+ unsigned int fec_coeff, cdclk, vdsc_bppx16;
unsigned int link_clk, lanes;
unsigned int hblank_rise;
h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
- vdsc_bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
+ vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16;
cdclk = i915->display.cdclk.hw.cdclk;
/* fec= 0.972261, using rounding multiplier of 1000000 */
fec_coeff = 972261;
@@ -536,10 +536,10 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
lanes = crtc_state->lane_count;
drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :"
- "lanes = %u vdsc_bpp = %u cdclk = %u\n",
- h_active, link_clk, lanes, vdsc_bpp, cdclk);
+ "lanes = %u vdsc_bppx16 = %u cdclk = %u\n",
+ h_active, link_clk, lanes, vdsc_bppx16, cdclk);
- if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk))
+ if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk))
return 0;
link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28;
@@ -551,8 +551,8 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk),
mul_u32_u32(link_clk, cdclk));
- tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 1000000),
- mul_u32_u32(link_clk * lanes, fec_coeff));
+ tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000),
+ mul_u32_u32(link_clk * lanes * 16, fec_coeff));
tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff),
mul_u32_u32(64 * pixel_clk, 1000000));
link_clks_active = (tu_line - 1) * 64 + tu_data;
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 4/8] drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
2023-09-11 5:05 ` [Intel-gfx] [PATCH 4/8] drm/i915/audio : Consider fractional vdsc bpp while computing tu_data Mitul Golani
@ 2023-09-11 9:16 ` Kandpal, Suraj
0 siblings, 0 replies; 27+ messages in thread
From: Kandpal, Suraj @ 2023-09-11 9:16 UTC (permalink / raw)
To: Golani, Mitulkumar Ajitkumar, intel-gfx@lists.freedesktop.org
> Subject: [PATCH 4/8] drm/i915/audio : Consider fractional vdsc bpp while
> computing tu_data
>
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>
> MTL+ supports fractional compressed bits_per_pixel, with precision of
> 1/16. This compressed bpp is stored in U6.4 format.
> Accommodate the precision during calculation of transfer unit data for
> hblank_early calculation.
>
> v2:
> -Fixed tu_data calculation while dealing with U6.4 format. (Stan)
>
LGTM.
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_audio.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> b/drivers/gpu/drm/i915/display/intel_audio.c
> index aa93ccd6c2aa..cfbaa7006905 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -521,14 +521,14 @@ static unsigned int calc_hblank_early_prog(struct
> intel_encoder *encoder,
> unsigned int link_clks_available, link_clks_required;
> unsigned int tu_data, tu_line, link_clks_active;
> unsigned int h_active, h_total, hblank_delta, pixel_clk;
> - unsigned int fec_coeff, cdclk, vdsc_bpp;
> + unsigned int fec_coeff, cdclk, vdsc_bppx16;
> unsigned int link_clk, lanes;
> unsigned int hblank_rise;
>
> h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
> h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
> pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
> - vdsc_bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
> + vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16;
> cdclk = i915->display.cdclk.hw.cdclk;
> /* fec= 0.972261, using rounding multiplier of 1000000 */
> fec_coeff = 972261;
> @@ -536,10 +536,10 @@ static unsigned int calc_hblank_early_prog(struct
> intel_encoder *encoder,
> lanes = crtc_state->lane_count;
>
> drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :"
> - "lanes = %u vdsc_bpp = %u cdclk = %u\n",
> - h_active, link_clk, lanes, vdsc_bpp, cdclk);
> + "lanes = %u vdsc_bppx16 = %u cdclk = %u\n",
> + h_active, link_clk, lanes, vdsc_bppx16, cdclk);
>
> - if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bpp || !cdclk))
> + if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 ||
> +!cdclk))
> return 0;
>
> link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28; @@
> -551,8 +551,8 @@ static unsigned int calc_hblank_early_prog(struct
> intel_encoder *encoder,
> hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 *
> (link_clk + cdclk), pixel_clk),
> mul_u32_u32(link_clk,
> cdclk));
>
> - tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bpp * 8, 1000000),
> - mul_u32_u32(link_clk * lanes, fec_coeff));
> + tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8,
> 1000000),
> + mul_u32_u32(link_clk * lanes * 16, fec_coeff));
> tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff),
> mul_u32_u32(64 * pixel_clk, 1000000));
> link_clks_active = (tu_line - 1) * 64 + tu_data;
> --
> 2.25.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 5/8] drm/i915/dsc/mtl: Add support for fractional bpp
2023-09-11 5:05 [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support Mitul Golani
` (3 preceding siblings ...)
2023-09-11 5:05 ` [Intel-gfx] [PATCH 4/8] drm/i915/audio : Consider fractional vdsc bpp while computing tu_data Mitul Golani
@ 2023-09-11 5:05 ` Mitul Golani
2023-09-11 9:28 ` Kandpal, Suraj
2023-09-11 5:05 ` [Intel-gfx] [PATCH 6/8] drm/i915/dp: Iterate over output bpp with fractional step size Mitul Golani
` (5 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Mitul Golani @ 2023-09-11 5:05 UTC (permalink / raw)
To: intel-gfx
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
Consider the fractional bpp while reading the qp values.
v2: Use helpers for fractional, integral bits of bits_per_pixel. (Suraj)
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
.../gpu/drm/i915/display/intel_qp_tables.c | 3 ---
drivers/gpu/drm/i915/display/intel_vdsc.c | 25 +++++++++++++++----
2 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c b/drivers/gpu/drm/i915/display/intel_qp_tables.c
index 543cdc46aa1d..600c815e37e4 100644
--- a/drivers/gpu/drm/i915/display/intel_qp_tables.c
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
@@ -34,9 +34,6 @@
* These qp tables are as per the C model
* and it has the rows pointing to bpps which increment
* in steps of 0.5
- * We do not support fractional bpps as of today,
- * hence we would skip the fractional bpps during
- * our references for qp calclulations.
*/
static const u8 rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index bfc41972a0bb..d7cfb2446c13 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -77,8 +77,8 @@ intel_vdsc_set_min_max_qp(struct drm_dsc_config *vdsc_cfg, int buf,
static void
calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
{
+ int bpp = to_bpp_int(vdsc_cfg->bits_per_pixel);
int bpc = vdsc_cfg->bits_per_component;
- int bpp = vdsc_cfg->bits_per_pixel >> 4;
int qp_bpc_modifier = (bpc - 8) * 2;
int uncompressed_bpg_rate;
int first_line_bpg_offset;
@@ -148,7 +148,13 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
static const s8 ofs_und8[] = {
10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
};
-
+ /*
+ * For 420 format since bits_per_pixel (bpp) is set to target bpp * 2,
+ * QP table values for target bpp 4.0 to 4.4375 (rounded to 4.0) are
+ * actually for bpp 8 to 8.875 (rounded to 4.0 * 2 i.e 8).
+ * Similarly values for target bpp 4.5 to 4.8375 (rounded to 4.5)
+ * are for bpp 9 to 9.875 (rounded to 4.5 * 2 i.e 9), and so on.
+ */
bpp_i = bpp - 8;
for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
u8 range_bpg_offset;
@@ -178,6 +184,9 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
}
} else {
+ /* fractional bpp part * 10000 (for precision up to 4 decimal places) */
+ int fractional_bits = to_bpp_frac_dec(vdsc_cfg->bits_per_pixel);
+
static const s8 ofs_und6[] = {
0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
};
@@ -191,7 +200,14 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
};
- bpp_i = (2 * (bpp - 6));
+ /*
+ * QP table rows have values in increment of 0.5.
+ * So 6.0 bpp to 6.4375 will have index 0, 6.5 to 6.9375 will have index 1,
+ * and so on.
+ * 0.5 fractional part with 4 decimal precision becomes 5000
+ */
+ bpp_i = ((bpp - 6) + (fractional_bits < 5000 ? 0 : 1));
+
for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
u8 range_bpg_offset;
@@ -279,8 +295,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
/* Gen 11 does not support VBR */
vdsc_cfg->vbr_enable = false;
- /* Gen 11 only supports integral values of bpp */
- vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
+ vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp_x16;
/*
* According to DSC 1.2 specs in Section 4.1 if native_420 is set
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 5/8] drm/i915/dsc/mtl: Add support for fractional bpp
2023-09-11 5:05 ` [Intel-gfx] [PATCH 5/8] drm/i915/dsc/mtl: Add support for fractional bpp Mitul Golani
@ 2023-09-11 9:28 ` Kandpal, Suraj
0 siblings, 0 replies; 27+ messages in thread
From: Kandpal, Suraj @ 2023-09-11 9:28 UTC (permalink / raw)
To: Golani, Mitulkumar Ajitkumar, intel-gfx@lists.freedesktop.org
> Subject: [PATCH 5/8] drm/i915/dsc/mtl: Add support for fractional bpp
>
> From: Vandita Kulkarni <vandita.kulkarni@intel.com>
>
> Consider the fractional bpp while reading the qp values.
>
> v2: Use helpers for fractional, integral bits of bits_per_pixel. (Suraj)
>
LGTM.
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> .../gpu/drm/i915/display/intel_qp_tables.c | 3 ---
> drivers/gpu/drm/i915/display/intel_vdsc.c | 25 +++++++++++++++----
> 2 files changed, 20 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c
> b/drivers/gpu/drm/i915/display/intel_qp_tables.c
> index 543cdc46aa1d..600c815e37e4 100644
> --- a/drivers/gpu/drm/i915/display/intel_qp_tables.c
> +++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
> @@ -34,9 +34,6 @@
> * These qp tables are as per the C model
> * and it has the rows pointing to bpps which increment
> * in steps of 0.5
> - * We do not support fractional bpps as of today,
> - * hence we would skip the fractional bpps during
> - * our references for qp calclulations.
> */
> static const u8
> rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC
> _MAX_NUM_BPP] = {
> { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, diff --git
> a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index bfc41972a0bb..d7cfb2446c13 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -77,8 +77,8 @@ intel_vdsc_set_min_max_qp(struct drm_dsc_config
> *vdsc_cfg, int buf, static void calculate_rc_params(struct drm_dsc_config
> *vdsc_cfg) {
> + int bpp = to_bpp_int(vdsc_cfg->bits_per_pixel);
> int bpc = vdsc_cfg->bits_per_component;
> - int bpp = vdsc_cfg->bits_per_pixel >> 4;
> int qp_bpc_modifier = (bpc - 8) * 2;
> int uncompressed_bpg_rate;
> int first_line_bpg_offset;
> @@ -148,7 +148,13 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
> static const s8 ofs_und8[] = {
> 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
> };
> -
> + /*
> + * For 420 format since bits_per_pixel (bpp) is set to target bpp
> * 2,
> + * QP table values for target bpp 4.0 to 4.4375 (rounded to 4.0)
> are
> + * actually for bpp 8 to 8.875 (rounded to 4.0 * 2 i.e 8).
> + * Similarly values for target bpp 4.5 to 4.8375 (rounded to 4.5)
> + * are for bpp 9 to 9.875 (rounded to 4.5 * 2 i.e 9), and so on.
> + */
> bpp_i = bpp - 8;
> for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
> u8 range_bpg_offset;
> @@ -178,6 +184,9 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
> range_bpg_offset &
> DSC_RANGE_BPG_OFFSET_MASK;
> }
> } else {
> + /* fractional bpp part * 10000 (for precision up to 4 decimal
> places) */
> + int fractional_bits = to_bpp_frac_dec(vdsc_cfg-
> >bits_per_pixel);
> +
> static const s8 ofs_und6[] = {
> 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
> };
> @@ -191,7 +200,14 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
> 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
> };
>
> - bpp_i = (2 * (bpp - 6));
> + /*
> + * QP table rows have values in increment of 0.5.
> + * So 6.0 bpp to 6.4375 will have index 0, 6.5 to 6.9375 will
> have index 1,
> + * and so on.
> + * 0.5 fractional part with 4 decimal precision becomes 5000
> + */
> + bpp_i = ((bpp - 6) + (fractional_bits < 5000 ? 0 : 1));
> +
> for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
> u8 range_bpg_offset;
>
> @@ -279,8 +295,7 @@ int intel_dsc_compute_params(struct intel_crtc_state
> *pipe_config)
> /* Gen 11 does not support VBR */
> vdsc_cfg->vbr_enable = false;
>
> - /* Gen 11 only supports integral values of bpp */
> - vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
> + vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp_x16;
>
> /*
> * According to DSC 1.2 specs in Section 4.1 if native_420 is set
> --
> 2.25.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 6/8] drm/i915/dp: Iterate over output bpp with fractional step size
2023-09-11 5:05 [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support Mitul Golani
` (4 preceding siblings ...)
2023-09-11 5:05 ` [Intel-gfx] [PATCH 5/8] drm/i915/dsc/mtl: Add support for fractional bpp Mitul Golani
@ 2023-09-11 5:05 ` Mitul Golani
2023-09-11 9:32 ` Kandpal, Suraj
2023-09-11 5:05 ` [Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp Mitul Golani
` (4 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Mitul Golani @ 2023-09-11 5:05 UTC (permalink / raw)
To: intel-gfx
From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
This patch adds support to iterate over compressed output bpp as per the
fractional step, supported by DP sink.
v2:
-Avoid ending up with compressed bpp, same as pipe bpp. (Stan)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 37 +++++++++++++++----------
1 file changed, 23 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d13fa2749eaf..90c92f3dc62a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1715,15 +1715,15 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
}
-static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock,
+static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock,
u32 lane_count, u32 mode_clock,
enum intel_output_format output_format,
int timeslots)
{
u32 available_bw, required_bw;
- available_bw = (link_clock * lane_count * timeslots) / 8;
- required_bw = compressed_bpp * (intel_dp_mode_to_fec_clock(mode_clock));
+ available_bw = (link_clock * lane_count * timeslots * 16) / 8;
+ required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock));
return available_bw > required_bw;
}
@@ -1731,7 +1731,7 @@ static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock,
static int dsc_compute_link_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct link_config_limits *limits,
- u16 compressed_bpp,
+ u16 compressed_bppx16,
int timeslots)
{
const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
@@ -1746,8 +1746,8 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
for (lane_count = limits->min_lane_count;
lane_count <= limits->max_lane_count;
lane_count <<= 1) {
- if (!is_bw_sufficient_for_dsc_config(compressed_bpp, link_rate, lane_count,
- adjusted_mode->clock,
+ if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate,
+ lane_count, adjusted_mode->clock,
pipe_config->output_format,
timeslots))
continue;
@@ -1860,7 +1860,7 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
ret = dsc_compute_link_config(intel_dp,
pipe_config,
limits,
- valid_dsc_bpp[i],
+ valid_dsc_bpp[i] << 4,
timeslots);
if (ret == 0) {
pipe_config->dsc.compressed_bpp_x16 = to_bpp_x16(valid_dsc_bpp[i]);
@@ -1886,22 +1886,31 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
int pipe_bpp,
int timeslots)
{
- u16 compressed_bpp;
+ u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u16 compressed_bppx16;
+ u8 bppx16_step;
int ret;
+ if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1)
+ bppx16_step = 16;
+ else
+ bppx16_step = 16 / bppx16_incr;
+
/* Compressed BPP should be less than the Input DSC bpp */
- dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
+ dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step);
+ dsc_min_bpp = dsc_min_bpp << 4;
- for (compressed_bpp = dsc_max_bpp;
- compressed_bpp >= dsc_min_bpp;
- compressed_bpp--) {
+ for (compressed_bppx16 = dsc_max_bpp;
+ compressed_bppx16 >= dsc_min_bpp;
+ compressed_bppx16 -= bppx16_step) {
ret = dsc_compute_link_config(intel_dp,
pipe_config,
limits,
- compressed_bpp,
+ compressed_bppx16,
timeslots);
if (ret == 0) {
- pipe_config->dsc.compressed_bpp_x16 = to_bpp_x16(compressed_bpp);
+ pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
return 0;
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 6/8] drm/i915/dp: Iterate over output bpp with fractional step size
2023-09-11 5:05 ` [Intel-gfx] [PATCH 6/8] drm/i915/dp: Iterate over output bpp with fractional step size Mitul Golani
@ 2023-09-11 9:32 ` Kandpal, Suraj
0 siblings, 0 replies; 27+ messages in thread
From: Kandpal, Suraj @ 2023-09-11 9:32 UTC (permalink / raw)
To: Golani, Mitulkumar Ajitkumar, intel-gfx@lists.freedesktop.org
> Subject: [PATCH 6/8] drm/i915/dp: Iterate over output bpp with fractional step
> size
>
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>
> This patch adds support to iterate over compressed output bpp as per the
> fractional step, supported by DP sink.
>
> v2:
> -Avoid ending up with compressed bpp, same as pipe bpp. (Stan)
>
LGTM.
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 37 +++++++++++++++----------
> 1 file changed, 23 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index d13fa2749eaf..90c92f3dc62a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1715,15 +1715,15 @@ static bool intel_dp_dsc_supports_format(struct
> intel_dp *intel_dp,
> return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
> sink_dsc_format); }
>
> -static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32
> link_clock,
> +static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32
> +link_clock,
> u32 lane_count, u32 mode_clock,
> enum intel_output_format
> output_format,
> int timeslots)
> {
> u32 available_bw, required_bw;
>
> - available_bw = (link_clock * lane_count * timeslots) / 8;
> - required_bw = compressed_bpp *
> (intel_dp_mode_to_fec_clock(mode_clock));
> + available_bw = (link_clock * lane_count * timeslots * 16) / 8;
> + required_bw = compressed_bppx16 *
> +(intel_dp_mode_to_fec_clock(mode_clock));
>
> return available_bw > required_bw;
> }
> @@ -1731,7 +1731,7 @@ static bool is_bw_sufficient_for_dsc_config(u16
> compressed_bpp, u32 link_clock, static int dsc_compute_link_config(struct
> intel_dp *intel_dp,
> struct intel_crtc_state *pipe_config,
> struct link_config_limits *limits,
> - u16 compressed_bpp,
> + u16 compressed_bppx16,
> int timeslots)
> {
> const struct drm_display_mode *adjusted_mode = &pipe_config-
> >hw.adjusted_mode; @@ -1746,8 +1746,8 @@ static int
> dsc_compute_link_config(struct intel_dp *intel_dp,
> for (lane_count = limits->min_lane_count;
> lane_count <= limits->max_lane_count;
> lane_count <<= 1) {
> - if (!is_bw_sufficient_for_dsc_config(compressed_bpp,
> link_rate, lane_count,
> - adjusted_mode-
> >clock,
> + if
> (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate,
> + lane_count,
> adjusted_mode->clock,
> pipe_config-
> >output_format,
> timeslots))
> continue;
> @@ -1860,7 +1860,7 @@ icl_dsc_compute_link_config(struct intel_dp
> *intel_dp,
> ret = dsc_compute_link_config(intel_dp,
> pipe_config,
> limits,
> - valid_dsc_bpp[i],
> + valid_dsc_bpp[i] << 4,
> timeslots);
> if (ret == 0) {
> pipe_config->dsc.compressed_bpp_x16 =
> to_bpp_x16(valid_dsc_bpp[i]); @@ -1886,22 +1886,31 @@
> xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
> int pipe_bpp,
> int timeslots)
> {
> - u16 compressed_bpp;
> + u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd);
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + u16 compressed_bppx16;
> + u8 bppx16_step;
> int ret;
>
> + if (DISPLAY_VER(i915) < 14 || bppx16_incr <= 1)
> + bppx16_step = 16;
> + else
> + bppx16_step = 16 / bppx16_incr;
> +
> /* Compressed BPP should be less than the Input DSC bpp */
> - dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
> + dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) -
> bppx16_step);
> + dsc_min_bpp = dsc_min_bpp << 4;
>
> - for (compressed_bpp = dsc_max_bpp;
> - compressed_bpp >= dsc_min_bpp;
> - compressed_bpp--) {
> + for (compressed_bppx16 = dsc_max_bpp;
> + compressed_bppx16 >= dsc_min_bpp;
> + compressed_bppx16 -= bppx16_step) {
> ret = dsc_compute_link_config(intel_dp,
> pipe_config,
> limits,
> - compressed_bpp,
> + compressed_bppx16,
> timeslots);
> if (ret == 0) {
> - pipe_config->dsc.compressed_bpp_x16 =
> to_bpp_x16(compressed_bpp);
> + pipe_config->dsc.compressed_bpp_x16 =
> compressed_bppx16;
> return 0;
> }
> }
> --
> 2.25.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
2023-09-11 5:05 [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support Mitul Golani
` (5 preceding siblings ...)
2023-09-11 5:05 ` [Intel-gfx] [PATCH 6/8] drm/i915/dp: Iterate over output bpp with fractional step size Mitul Golani
@ 2023-09-11 5:05 ` Mitul Golani
2023-09-11 9:43 ` Kandpal, Suraj
2023-09-11 5:05 ` [Intel-gfx] [PATCH 8/8] drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs Mitul Golani
` (3 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Mitul Golani @ 2023-09-11 5:05 UTC (permalink / raw)
To: intel-gfx
From: Swati Sharma <swati2.sharma@intel.com>
DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show
to depict sink's precision.
Also, new debugfs entry is created to enforce fractional bpp.
If Force_DSC_Fractional_BPP_en is set then while iterating over
output bpp with fractional step size we will continue if output_bpp is
computed as integer. With this approach, we will be able to validate
DSC with fractional bpp.
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 82 +++++++++++++++++++
.../drm/i915/display/intel_display_types.h | 1 +
2 files changed, 83 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index f05b52381a83..d1b202e14e5f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1244,6 +1244,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
DP_DSC_YCbCr420_Native)),
str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
DP_DSC_YCbCr444)));
+ seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
+ drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
seq_printf(m, "Force_DSC_Enable: %s\n",
str_yes_no(intel_dp->force_dsc_en));
if (!intel_dp_is_edp(intel_dp))
@@ -1436,6 +1438,83 @@ static const struct file_operations i915_dsc_output_format_fops = {
.write = i915_dsc_output_format_write
};
+static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
+{
+ struct drm_connector *connector = m->private;
+ struct drm_device *dev = connector->dev;
+ struct drm_crtc *crtc;
+ struct intel_dp *intel_dp;
+ struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+ int ret;
+
+ if (!encoder)
+ return -ENODEV;
+
+ ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
+ if (ret)
+ return ret;
+
+ crtc = connector->state->crtc;
+ if (connector->status != connector_status_connected || !crtc) {
+ ret = -ENODEV;
+ goto out;
+ }
+
+ intel_dp = intel_attached_dp(to_intel_connector(connector));
+ seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
+ str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
+
+out: drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+ return ret;
+}
+
+static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
+ const char __user *ubuf,
+ size_t len, loff_t *offp)
+{
+ struct drm_connector *connector =
+ ((struct seq_file *)file->private_data)->private;
+ struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ bool dsc_fractional_bpp_enable = false;
+ int ret;
+
+ if (len == 0)
+ return 0;
+
+ drm_dbg(&i915->drm,
+ "Copied %zu bytes from user to force fractional bpp for DSC\n", len);
+
+ ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
+ if (ret < 0)
+ return ret;
+
+ drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
+ (dsc_fractional_bpp_enable) ? "true" : "false");
+ intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
+
+ *offp += len;
+
+ return len;
+}
+
+static int i915_dsc_fractional_bpp_open(struct inode *inode,
+ struct file *file)
+{
+ return single_open(file, i915_dsc_fractional_bpp_show, inode->i_private);
+}
+
+static const struct file_operations i915_dsc_fractional_bpp_fops = {
+ .owner = THIS_MODULE,
+ .open = i915_dsc_fractional_bpp_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+ .write = i915_dsc_fractional_bpp_write
+};
+
/*
* Returns the Current CRTC's bpc.
* Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
@@ -1513,6 +1592,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
debugfs_create_file("i915_dsc_output_format", 0644, root,
connector, &i915_dsc_output_format_fops);
+
+ debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
+ connector, &i915_dsc_fractional_bpp_fops);
}
if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9eb7b8912076..6e76f1274b0c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1797,6 +1797,7 @@ struct intel_dp {
/* Display stream compression testing */
bool force_dsc_en;
int force_dsc_output_format;
+ bool force_dsc_fractional_bpp_en;
int force_dsc_bpc;
bool hobl_failed;
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
2023-09-11 5:05 ` [Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp Mitul Golani
@ 2023-09-11 9:43 ` Kandpal, Suraj
0 siblings, 0 replies; 27+ messages in thread
From: Kandpal, Suraj @ 2023-09-11 9:43 UTC (permalink / raw)
To: Golani, Mitulkumar Ajitkumar, intel-gfx@lists.freedesktop.org
> Subject: [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional
> bpp
>
> From: Swati Sharma <swati2.sharma@intel.com>
>
> DSC_Sink_BPP_Precision entry is added to i915_dsc_fec_support_show to
> depict sink's precision.
> Also, new debugfs entry is created to enforce fractional bpp.
> If Force_DSC_Fractional_BPP_en is set then while iterating over output bpp
> with fractional step size we will continue if output_bpp is computed as integer.
> With this approach, we will be able to validate DSC with fractional bpp.
>
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> .../drm/i915/display/intel_display_debugfs.c | 82 +++++++++++++++++++
> .../drm/i915/display/intel_display_types.h | 1 +
> 2 files changed, 83 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index f05b52381a83..d1b202e14e5f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -1244,6 +1244,8 @@ static int i915_dsc_fec_support_show(struct seq_file
> *m, void *data)
>
> DP_DSC_YCbCr420_Native)),
>
> str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
>
> DP_DSC_YCbCr444)));
> + seq_printf(m, "DSC_Sink_BPP_Precision: %d\n",
> + drm_dp_dsc_sink_bpp_incr(intel_dp->dsc_dpcd));
> seq_printf(m, "Force_DSC_Enable: %s\n",
> str_yes_no(intel_dp->force_dsc_en));
> if (!intel_dp_is_edp(intel_dp))
> @@ -1436,6 +1438,83 @@ static const struct file_operations
> i915_dsc_output_format_fops = {
> .write = i915_dsc_output_format_write
> };
>
> +static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
> +{
> + struct drm_connector *connector = m->private;
> + struct drm_device *dev = connector->dev;
> + struct drm_crtc *crtc;
> + struct intel_dp *intel_dp;
> + struct intel_encoder *encoder =
> intel_attached_encoder(to_intel_connector(connector));
> + int ret;
> +
> + if (!encoder)
> + return -ENODEV;
> +
> + ret = drm_modeset_lock_single_interruptible(&dev-
> >mode_config.connection_mutex);
> + if (ret)
> + return ret;
> +
> + crtc = connector->state->crtc;
> + if (connector->status != connector_status_connected || !crtc) {
> + ret = -ENODEV;
> + goto out;
> + }
> +
> + intel_dp = intel_attached_dp(to_intel_connector(connector));
> + seq_printf(m, "Force_DSC_Fractional_BPP_Enable: %s\n",
> + str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
> +
> +out: drm_modeset_unlock(&dev->mode_config.connection_mutex);
> +
The above function should be on a new line and the extra new line can be removed
return and modeset_unlock
With that fixed
LGTM.
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> + return ret;
> +}
> +
> +static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
> + const char __user *ubuf,
> + size_t len, loff_t *offp)
> +{
> + struct drm_connector *connector =
> + ((struct seq_file *)file->private_data)->private;
> + struct intel_encoder *encoder =
> intel_attached_encoder(to_intel_connector(connector));
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> + bool dsc_fractional_bpp_enable = false;
> + int ret;
> +
> + if (len == 0)
> + return 0;
> +
> + drm_dbg(&i915->drm,
> + "Copied %zu bytes from user to force fractional bpp for
> DSC\n", len);
> +
> + ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
> + if (ret < 0)
> + return ret;
> +
> + drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
> + (dsc_fractional_bpp_enable) ? "true" : "false");
> + intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
> +
> + *offp += len;
> +
> + return len;
> +}
> +
> +static int i915_dsc_fractional_bpp_open(struct inode *inode,
> + struct file *file)
> +{
> + return single_open(file, i915_dsc_fractional_bpp_show,
> +inode->i_private); }
> +
> +static const struct file_operations i915_dsc_fractional_bpp_fops = {
> + .owner = THIS_MODULE,
> + .open = i915_dsc_fractional_bpp_open,
> + .read = seq_read,
> + .llseek = seq_lseek,
> + .release = single_release,
> + .write = i915_dsc_fractional_bpp_write };
> +
> /*
> * Returns the Current CRTC's bpc.
> * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
> @@ -1513,6 +1592,9 @@ void intel_connector_debugfs_add(struct
> intel_connector *intel_connector)
>
> debugfs_create_file("i915_dsc_output_format", 0644, root,
> connector, &i915_dsc_output_format_fops);
> +
> + debugfs_create_file("i915_dsc_fractional_bpp", 0644, root,
> + connector, &i915_dsc_fractional_bpp_fops);
> }
>
> if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9eb7b8912076..6e76f1274b0c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1797,6 +1797,7 @@ struct intel_dp {
> /* Display stream compression testing */
> bool force_dsc_en;
> int force_dsc_output_format;
> + bool force_dsc_fractional_bpp_en;
> int force_dsc_bpc;
>
> bool hobl_failed;
> --
> 2.25.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 8/8] drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs
2023-09-11 5:05 [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support Mitul Golani
` (6 preceding siblings ...)
2023-09-11 5:05 ` [Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp Mitul Golani
@ 2023-09-11 5:05 ` Mitul Golani
2023-09-11 9:45 ` Kandpal, Suraj
2023-09-11 5:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC fractional bpp support (rev5) Patchwork
` (2 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Mitul Golani @ 2023-09-11 5:05 UTC (permalink / raw)
To: intel-gfx
From: Swati Sharma <swati2.sharma@intel.com>
If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff
compressed bpp is fractional. Continue if the computed compressed bpp
turns out to be a integer.
v2:
-Use helpers for fractional, integral bits of bits_per_pixel. (Suraj)
-Fix comment (Suraj)
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 90c92f3dc62a..f6bfbd89bc3f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1904,6 +1904,9 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
for (compressed_bppx16 = dsc_max_bpp;
compressed_bppx16 >= dsc_min_bpp;
compressed_bppx16 -= bppx16_step) {
+ if (intel_dp->force_dsc_fractional_bpp_en &&
+ !to_bpp_frac_dec(compressed_bppx16))
+ continue;
ret = dsc_compute_link_config(intel_dp,
pipe_config,
limits,
@@ -1911,6 +1914,10 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
timeslots);
if (ret == 0) {
pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;
+ if (intel_dp->force_dsc_fractional_bpp_en &&
+ to_bpp_frac_dec(compressed_bppx16))
+ drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n");
+
return 0;
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 8/8] drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs
2023-09-11 5:05 ` [Intel-gfx] [PATCH 8/8] drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs Mitul Golani
@ 2023-09-11 9:45 ` Kandpal, Suraj
0 siblings, 0 replies; 27+ messages in thread
From: Kandpal, Suraj @ 2023-09-11 9:45 UTC (permalink / raw)
To: Golani, Mitulkumar Ajitkumar, intel-gfx@lists.freedesktop.org
> Subject: [PATCH 8/8] drm/i915/dsc: Allow DSC only with fractional bpp when
> forced from debugfs
>
> From: Swati Sharma <swati2.sharma@intel.com>
>
> If force_dsc_fractional_bpp_en is set through debugfs allow DSC iff
> compressed bpp is fractional. Continue if the computed compressed bpp turns
> out to be a integer.
>
> v2:
> -Use helpers for fractional, integral bits of bits_per_pixel. (Suraj) -Fix comment
> (Suraj)
>
LGTM.
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 90c92f3dc62a..f6bfbd89bc3f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1904,6 +1904,9 @@ xelpd_dsc_compute_link_config(struct intel_dp
> *intel_dp,
> for (compressed_bppx16 = dsc_max_bpp;
> compressed_bppx16 >= dsc_min_bpp;
> compressed_bppx16 -= bppx16_step) {
> + if (intel_dp->force_dsc_fractional_bpp_en &&
> + !to_bpp_frac_dec(compressed_bppx16))
> + continue;
> ret = dsc_compute_link_config(intel_dp,
> pipe_config,
> limits,
> @@ -1911,6 +1914,10 @@ xelpd_dsc_compute_link_config(struct intel_dp
> *intel_dp,
> timeslots);
> if (ret == 0) {
> pipe_config->dsc.compressed_bpp_x16 =
> compressed_bppx16;
> + if (intel_dp->force_dsc_fractional_bpp_en &&
> + to_bpp_frac_dec(compressed_bppx16))
> + drm_dbg_kms(&i915->drm, "Forcing DSC
> fractional bpp\n");
> +
> return 0;
> }
> }
> --
> 2.25.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC fractional bpp support (rev5)
2023-09-11 5:05 [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support Mitul Golani
` (7 preceding siblings ...)
2023-09-11 5:05 ` [Intel-gfx] [PATCH 8/8] drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs Mitul Golani
@ 2023-09-11 5:43 ` Patchwork
2023-09-11 5:43 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-09-11 5:59 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
10 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2023-09-11 5:43 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
== Series Details ==
Series: Add DSC fractional bpp support (rev5)
URL : https://patchwork.freedesktop.org/series/111391/
State : warning
== Summary ==
Error: dim checkpatch failed
212219eebdff drm/display/dp: Add helper function to get DSC bpp prescision
8ca519027e97 drm/i915/display: Store compressed bpp in U6.4 format
-:273: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#273: FILE: drivers/gpu/drm/i915/display/intel_dp_mst.c:256:
+ to_bpp_int(crtc_state->dsc.compressed_bpp_x16),
-:274: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#274: FILE: drivers/gpu/drm/i915/display/intel_dp_mst.c:257:
+ to_bpp_int(crtc_state->dsc.compressed_bpp_x16),
total: 0 errors, 2 warnings, 0 checks, 229 lines checked
1f6e8b3da485 drm/i915/display: Consider fractional vdsc bpp while computing m_n values
8e22f6b5fd3d drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
63d0e6f944c3 drm/i915/dsc/mtl: Add support for fractional bpp
87d13694719f drm/i915/dp: Iterate over output bpp with fractional step size
4e1c6710e89f drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
afa236fc4570 drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs
^ permalink raw reply [flat|nested] 27+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add DSC fractional bpp support (rev5)
2023-09-11 5:05 [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support Mitul Golani
` (8 preceding siblings ...)
2023-09-11 5:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC fractional bpp support (rev5) Patchwork
@ 2023-09-11 5:43 ` Patchwork
2023-09-11 5:59 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
10 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2023-09-11 5:43 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
== Series Details ==
Series: Add DSC fractional bpp support (rev5)
URL : https://patchwork.freedesktop.org/series/111391/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 27+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for Add DSC fractional bpp support (rev5)
2023-09-11 5:05 [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support Mitul Golani
` (9 preceding siblings ...)
2023-09-11 5:43 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-09-11 5:59 ` Patchwork
10 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2023-09-11 5:59 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 10695 bytes --]
== Series Details ==
Series: Add DSC fractional bpp support (rev5)
URL : https://patchwork.freedesktop.org/series/111391/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13617 -> Patchwork_111391v5
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_111391v5 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_111391v5, please notify your bug team (lgci.bug.filing@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/index.html
Participating hosts (38 -> 39)
------------------------------
Additional (2): fi-kbl-soraka bat-dg2-8
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_111391v5:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_suspend@basic-s0@smem:
- bat-dg2-8: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/bat-dg2-8/igt@gem_exec_suspend@basic-s0@smem.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_pm_backlight@basic-brightness}:
- bat-dg2-8: NOTRUN -> [SKIP][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/bat-dg2-8/igt@kms_pm_backlight@basic-brightness.html
Known issues
------------
Here are the changes found in Patchwork_111391v5 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@gem_mmap@basic:
- bat-dg2-8: NOTRUN -> [SKIP][5] ([i915#4083])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/bat-dg2-8/igt@gem_mmap@basic.html
* igt@gem_mmap_gtt@basic:
- bat-dg2-8: NOTRUN -> [SKIP][6] ([i915#4077]) +2 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/bat-dg2-8/igt@gem_mmap_gtt@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg2-8: NOTRUN -> [SKIP][7] ([i915#4079]) +1 other test skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/bat-dg2-8/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rps@basic-api:
- bat-dg2-8: NOTRUN -> [SKIP][8] ([i915#6621])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/bat-dg2-8/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][9] ([i915#1886] / [i915#7913])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-dg2-8: NOTRUN -> [SKIP][10] ([i915#6645])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/bat-dg2-8/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-dg2-8: NOTRUN -> [SKIP][11] ([i915#5190])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/bat-dg2-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg2-8: NOTRUN -> [SKIP][12] ([i915#4215] / [i915#5190])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/bat-dg2-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- bat-dg2-8: NOTRUN -> [SKIP][13] ([i915#4212]) +7 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/bat-dg2-8/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-kbl-soraka: NOTRUN -> [SKIP][14] ([fdo#109271]) +8 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/fi-kbl-soraka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-dg2-8: NOTRUN -> [SKIP][15] ([i915#4103] / [i915#4213]) +1 other test skip
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/bat-dg2-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg2-8: NOTRUN -> [SKIP][16] ([fdo#109285])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/bat-dg2-8/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-dg2-8: NOTRUN -> [SKIP][17] ([i915#5274])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/bat-dg2-8/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_frontbuffer_tracking@basic:
- fi-bsw-nick: [PASS][18] -> [FAIL][19] ([i915#9276])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13617/fi-bsw-nick/igt@kms_frontbuffer_tracking@basic.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/fi-bsw-nick/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [PASS][20] -> [FAIL][21] ([IGT#3] / [i915#6121])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13617/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_psr@cursor_plane_move:
- bat-dg2-8: NOTRUN -> [SKIP][22] ([i915#1072]) +3 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/bat-dg2-8/igt@kms_psr@cursor_plane_move.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-dg2-8: NOTRUN -> [SKIP][23] ([i915#3555])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/bat-dg2-8/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-dg2-8: NOTRUN -> [SKIP][24] ([i915#3708])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/bat-dg2-8/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-dg2-8: NOTRUN -> [SKIP][25] ([i915#3708] / [i915#4077]) +1 other test skip
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/bat-dg2-8/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-write:
- bat-dg2-8: NOTRUN -> [SKIP][26] ([i915#3291] / [i915#3708]) +2 other tests skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/bat-dg2-8/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [ABORT][27] ([i915#8668]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13617/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#9276]: https://gitlab.freedesktop.org/drm/intel/issues/9276
Build changes
-------------
* Linux: CI_DRM_13617 -> Patchwork_111391v5
CI-20190529: 20190529
CI_DRM_13617: 232c052bbad9247620eb164d559c1e0a9eae0353 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7478: 605d1288086602b23d0d73fee5022dcd329d9d3e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111391v5: 232c052bbad9247620eb164d559c1e0a9eae0353 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
83f55c785eb9 drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs
bf5775149689 drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp
9b3697dfa298 drm/i915/dp: Iterate over output bpp with fractional step size
89d88297a613 drm/i915/dsc/mtl: Add support for fractional bpp
ac736a081b81 drm/i915/audio : Consider fractional vdsc bpp while computing tu_data
0d9f9d0fce76 drm/i915/display: Consider fractional vdsc bpp while computing m_n values
1a765e6a92ae drm/i915/display: Store compressed bpp in U6.4 format
48ad3c8048eb drm/display/dp: Add helper function to get DSC bpp prescision
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111391v5/index.html
[-- Attachment #2: Type: text/html, Size: 12396 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread