From: Jonathan Cavitt <jonathan.cavitt@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: janusz.krzysztofik@intel.com, andi.shyti@intel.com,
matthew.d.roper@intel.com, jonathan.cavitt@intel.com,
saurabhg.gupta@intel.com, chris.p.wilson@linux.intel.com,
nirmoy.das@intel.com
Subject: [Intel-gfx] [PATCH v17 1/7] drm/i915: Add GuC TLB Invalidation device info flags
Date: Tue, 17 Oct 2023 11:08:00 -0700 [thread overview]
Message-ID: <20231017180806.3054290-2-jonathan.cavitt@intel.com> (raw)
In-Reply-To: <20231017180806.3054290-1-jonathan.cavitt@intel.com>
Add device info flags for if GuC TLB Invalidation is enabled.
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cb60fc9cf8737..6a2a78c61f212 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -794,6 +794,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_GUC_DEPRIVILEGE(i915) \
(INTEL_INFO(i915)->has_guc_deprivilege)
+#define HAS_GUC_TLB_INVALIDATION(i915) (INTEL_INFO(i915)->has_guc_tlb_invalidation)
+
#define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 39817490b13fd..eba2f0b919c87 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -153,6 +153,7 @@ enum intel_ppgtt_type {
func(has_heci_pxp); \
func(has_heci_gscfi); \
func(has_guc_deprivilege); \
+ func(has_guc_tlb_invalidation); \
func(has_l3_ccs_read); \
func(has_l3_dpf); \
func(has_llc); \
--
2.25.1
next prev parent reply other threads:[~2023-10-17 18:19 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-17 18:07 [Intel-gfx] [PATCH v17 0/7] drm/i915: Define and use GuC and CTB TLB invalidation routines Jonathan Cavitt
2023-10-17 18:08 ` Jonathan Cavitt [this message]
2023-10-17 18:08 ` [Intel-gfx] [PATCH v17 2/7] drm/i915/guc: Add CT size delay helper Jonathan Cavitt
2023-10-17 18:08 ` [Intel-gfx] [PATCH v17 3/7] drm/i915: Define and use GuC and CTB TLB invalidation routines Jonathan Cavitt
2023-10-17 18:08 ` [Intel-gfx] [PATCH v17 4/7] drm/i915: No TLB invalidation on suspended GT Jonathan Cavitt
2023-10-17 18:08 ` [Intel-gfx] [PATCH v17 5/7] drm/i915: No TLB invalidation on wedged GT Jonathan Cavitt
2023-10-17 18:08 ` [Intel-gfx] [PATCH v17 6/7] drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck Jonathan Cavitt
2023-10-17 18:08 ` [Intel-gfx] [PATCH v17 7/7] drm/i915: Enable GuC TLB invalidations for MTL Jonathan Cavitt
2023-10-17 19:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Define and use GuC and CTB TLB invalidation routines Patchwork
2023-10-17 19:07 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-17 19:25 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-10-17 20:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Define and use GuC and CTB TLB invalidation routines (rev2) Patchwork
2023-10-17 20:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-17 20:20 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-10-17 21:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Define and use GuC and CTB TLB invalidation routines (rev3) Patchwork
2023-10-17 21:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-17 21:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-10-18 2:40 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-10-18 3:28 ` Andi Shyti
2023-10-18 3:51 ` Andi Shyti
2023-10-18 4:18 ` [Intel-gfx] [PATCH v17 0/7] drm/i915: Define and use GuC and CTB TLB invalidation routines Andi Shyti
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