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From: Jonathan Cavitt <jonathan.cavitt@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: janusz.krzysztofik@intel.com, andi.shyti@intel.com,
	matthew.d.roper@intel.com, jonathan.cavitt@intel.com,
	saurabhg.gupta@intel.com, chris.p.wilson@linux.intel.com,
	nirmoy.das@intel.com
Subject: [Intel-gfx] [PATCH v17 6/7] drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck
Date: Tue, 17 Oct 2023 11:08:05 -0700	[thread overview]
Message-ID: <20231017180806.3054290-7-jonathan.cavitt@intel.com> (raw)
In-Reply-To: <20231017180806.3054290-1-jonathan.cavitt@intel.com>

For the gt_tlb live selftest, when operating on the GSC engine,
increase the timeout from 10 ms to 200 ms because the GSC
engine is a bit slower than the rest.

Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
---
 drivers/gpu/drm/i915/gt/selftest_tlb.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_tlb.c b/drivers/gpu/drm/i915/gt/selftest_tlb.c
index 7e41f69fc818f..00b872b6380b1 100644
--- a/drivers/gpu/drm/i915/gt/selftest_tlb.c
+++ b/drivers/gpu/drm/i915/gt/selftest_tlb.c
@@ -136,8 +136,15 @@ pte_tlbinv(struct intel_context *ce,
 	i915_request_get(rq);
 	i915_request_add(rq);
 
-	/* Short sleep to sanitycheck the batch is spinning before we begin */
-	msleep(10);
+	/*
+	 * Short sleep to sanitycheck the batch is spinning before we begin.
+	 * FIXME: Why is GSC so slow?
+	 */
+	if (ce->engine->class == OTHER_CLASS)
+		msleep(200);
+	else
+		msleep(10);
+
 	if (va == vb) {
 		if (!i915_request_completed(rq)) {
 			pr_err("%s(%s): Semaphore sanitycheck failed %llx, with alignment %llx, using PTE size %x (phys %x, sg %x)\n",
-- 
2.25.1


  parent reply	other threads:[~2023-10-17 18:19 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-17 18:07 [Intel-gfx] [PATCH v17 0/7] drm/i915: Define and use GuC and CTB TLB invalidation routines Jonathan Cavitt
2023-10-17 18:08 ` [Intel-gfx] [PATCH v17 1/7] drm/i915: Add GuC TLB Invalidation device info flags Jonathan Cavitt
2023-10-17 18:08 ` [Intel-gfx] [PATCH v17 2/7] drm/i915/guc: Add CT size delay helper Jonathan Cavitt
2023-10-17 18:08 ` [Intel-gfx] [PATCH v17 3/7] drm/i915: Define and use GuC and CTB TLB invalidation routines Jonathan Cavitt
2023-10-17 18:08 ` [Intel-gfx] [PATCH v17 4/7] drm/i915: No TLB invalidation on suspended GT Jonathan Cavitt
2023-10-17 18:08 ` [Intel-gfx] [PATCH v17 5/7] drm/i915: No TLB invalidation on wedged GT Jonathan Cavitt
2023-10-17 18:08 ` Jonathan Cavitt [this message]
2023-10-17 18:08 ` [Intel-gfx] [PATCH v17 7/7] drm/i915: Enable GuC TLB invalidations for MTL Jonathan Cavitt
2023-10-17 19:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Define and use GuC and CTB TLB invalidation routines Patchwork
2023-10-17 19:07 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-17 19:25 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-10-17 20:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Define and use GuC and CTB TLB invalidation routines (rev2) Patchwork
2023-10-17 20:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-17 20:20 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-10-17 21:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Define and use GuC and CTB TLB invalidation routines (rev3) Patchwork
2023-10-17 21:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-17 21:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-10-18  2:40 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-10-18  3:28   ` Andi Shyti
2023-10-18  3:51     ` Andi Shyti
2023-10-18  4:18 ` [Intel-gfx] [PATCH v17 0/7] drm/i915: Define and use GuC and CTB TLB invalidation routines Andi Shyti

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