* [PATCH v15 0/9] Implement CMRR Support
@ 2024-06-10 2:48 Mitul Golani
2024-06-10 2:48 ` [PATCH v15 1/9] gpu/drm/i915: Update indentation for VRR registers and bits Mitul Golani
` (13 more replies)
0 siblings, 14 replies; 17+ messages in thread
From: Mitul Golani @ 2024-06-10 2:48 UTC (permalink / raw)
To: intel-gfx; +Cc: ankit.k.nautiyal
CMRR is a display feature that uses adaptive sync
framework to vary Vtotal slightly to match the
content rate exactly without frame drops. This
feature is a variation of VRR where it varies Vtotal
slightly (between additional 0 and 1 Vtotal scanlines)
to match content rate exactly without frame drops
using the adaptive sync framework.
enable this feature by programing new registers for
CMRR enable, CMRR_M, CMRR_N, vmin=vmax=flipline.The
CMRR_M/CMRR_N ratio represents the fractional part
in (actual refresh rate/target refresh rate) * origVTotal.
--v6:
- CMRR handling in co-existatnce of LRR and DRRS
- Correct vtotal paramas accuracy and add 2 digit precision.
--v7:
- Rebased patches in-accordance to AS SDP merge.
- Add neccessary gaurd to prevent crtc_state mismatch
during intel_vrr_get_config.
-v8:
- Add support for AS SDP for CMRR.
- update palce holder for CMRR register(Jani).
- Make CMRR as subset of FAVT, as per comments in patch#3.
-v9:
- Add CMRR register definitions to separate intel_vrr_reg.h.
- Remove cmrr_enabling/disabling, use vrr.enable instead.
- Update AS SDP pack function to accomodate target_rr_divider.
- Remove duplicated lines to compute vrr_vsync params.
- Set cmrr.enable with a separate patch at last.
-v10:
- Separate VRR related register definitions.
- Add dependency header intel_display_reg_defs.h.
- Rename file name to intel_vrr_regs.h instead of reg.h.
- Revert removed line.
- Since vrr.enable and cmrr.enable are not mutually exclusive,
handle accordingly.
- is_edp is not required inside is_cmrr_frac_required function.
- Add video_mode_required flag for future enhancement.
- Correct cmrr_m/cmrr_n calculation.
- target_rr_divider is bools so handle accordingly.
-v11:
- Move VRR related register and bits to separate file
intel_vrr_regs.h.
- Correct file header macro to intel_vrr_regs.h.
- Remove adding CMRR flag to vrr_ctl register during
set_transcoder_timing.
- Replace vrr.enable flag to cmrr.enable where added mistakenly.
- Move cmrr computation patch to last and set other other required
params before computing cmrr.enable.
-v12:
- Add patch to fix check patch issues for VRR related registers
in i915_reg.h then move them to intel_vrr_regs.h with separate
patch.
-v13:
- Reverted unrelated patches while rebase.
-v14:
- Fix all indentations for VRR related registes in Patch#1
-v15:
- Rebase.
Mitul Golani (9):
gpu/drm/i915: Update indentation for VRR registers and bits
drm/i915: Separate VRR related register definitions
drm/i915: Define and compute Transcoder CMRR registers
drm/i915: Update trans_vrr_ctl flag when cmrr is computed
drm/dp: Add refresh rate divider to struct representing AS SDP
drm/i915/display: Add support for pack and unpack
drm/i915/display: Compute Adaptive sync SDP params
drm/i915/display: Compute vrr vsync params
drm/i915: Compute CMRR and calculate vtotal
drivers/gpu/drm/i915/display/intel_display.c | 24 +++-
.../drm/i915/display/intel_display_device.h | 1 +
.../drm/i915/display/intel_display_types.h | 6 +
drivers/gpu/drm/i915/display/intel_dp.c | 18 ++-
drivers/gpu/drm/i915/display/intel_vrr.c | 128 ++++++++++++++++--
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 127 +++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 100 --------------
include/drm/display/drm_dp_helper.h | 1 +
8 files changed, 286 insertions(+), 119 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_vrr_regs.h
--
2.25.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v15 1/9] gpu/drm/i915: Update indentation for VRR registers and bits
2024-06-10 2:48 [PATCH v15 0/9] Implement CMRR Support Mitul Golani
@ 2024-06-10 2:48 ` Mitul Golani
2024-06-10 4:19 ` Nautiyal, Ankit K
2024-06-10 2:48 ` [PATCH v15 2/9] drm/i915: Separate VRR related register definitions Mitul Golani
` (12 subsequent siblings)
13 siblings, 1 reply; 17+ messages in thread
From: Mitul Golani @ 2024-06-10 2:48 UTC (permalink / raw)
To: intel-gfx; +Cc: ankit.k.nautiyal
Update the indentation for the VRR register definition and
its bits, and fix checkpatch issues to ensure smooth movement
of registers and bits.
--v2:
- Keep XELPD_VRR_CTL_VRR_GUARDBAND(x) to avoid readability (Ankit).
- Fix all indentation related VRR registers and bits instead of
checkpatch one.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 174 ++++++++++++++++----------------
1 file changed, 87 insertions(+), 87 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7daf902772e4..a10591424338 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1148,104 +1148,104 @@
#define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
/* VRR registers */
-#define _TRANS_VRR_CTL_A 0x60420
-#define _TRANS_VRR_CTL_B 0x61420
-#define _TRANS_VRR_CTL_C 0x62420
-#define _TRANS_VRR_CTL_D 0x63420
-#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
-#define VRR_CTL_VRR_ENABLE REG_BIT(31)
-#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
-#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
-#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
-#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
-#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
-#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
-#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
-
-#define _TRANS_VRR_VMAX_A 0x60424
-#define _TRANS_VRR_VMAX_B 0x61424
-#define _TRANS_VRR_VMAX_C 0x62424
-#define _TRANS_VRR_VMAX_D 0x63424
+#define _TRANS_VRR_CTL_A 0x60420
+#define _TRANS_VRR_CTL_B 0x61420
+#define _TRANS_VRR_CTL_C 0x62420
+#define _TRANS_VRR_CTL_D 0x63420
+#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
+#define VRR_CTL_VRR_ENABLE REG_BIT(31)
+#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
+#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
+#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
+#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
+#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
+#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
+#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
+
+#define _TRANS_VRR_VMAX_A 0x60424
+#define _TRANS_VRR_VMAX_B 0x61424
+#define _TRANS_VRR_VMAX_C 0x62424
+#define _TRANS_VRR_VMAX_D 0x63424
#define TRANS_VRR_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A)
-#define VRR_VMAX_MASK REG_GENMASK(19, 0)
+#define VRR_VMAX_MASK REG_GENMASK(19, 0)
-#define _TRANS_VRR_VMIN_A 0x60434
-#define _TRANS_VRR_VMIN_B 0x61434
-#define _TRANS_VRR_VMIN_C 0x62434
-#define _TRANS_VRR_VMIN_D 0x63434
+#define _TRANS_VRR_VMIN_A 0x60434
+#define _TRANS_VRR_VMIN_B 0x61434
+#define _TRANS_VRR_VMIN_C 0x62434
+#define _TRANS_VRR_VMIN_D 0x63434
#define TRANS_VRR_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A)
-#define VRR_VMIN_MASK REG_GENMASK(15, 0)
+#define VRR_VMIN_MASK REG_GENMASK(15, 0)
-#define _TRANS_VRR_VMAXSHIFT_A 0x60428
-#define _TRANS_VRR_VMAXSHIFT_B 0x61428
-#define _TRANS_VRR_VMAXSHIFT_C 0x62428
-#define _TRANS_VRR_VMAXSHIFT_D 0x63428
+#define _TRANS_VRR_VMAXSHIFT_A 0x60428
+#define _TRANS_VRR_VMAXSHIFT_B 0x61428
+#define _TRANS_VRR_VMAXSHIFT_C 0x62428
+#define _TRANS_VRR_VMAXSHIFT_D 0x63428
#define TRANS_VRR_VMAXSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
- _TRANS_VRR_VMAXSHIFT_A)
-#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
-#define VRR_VMAXSHIFT_DEC REG_BIT(16)
-#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
-
-#define _TRANS_VRR_STATUS_A 0x6042C
-#define _TRANS_VRR_STATUS_B 0x6142C
-#define _TRANS_VRR_STATUS_C 0x6242C
-#define _TRANS_VRR_STATUS_D 0x6342C
-#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
-#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
-#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
-#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
-#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
-#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
-#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
-#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
-#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
-#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
-#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
-#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
-#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
-#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
-#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
-
-#define _TRANS_VRR_VTOTAL_PREV_A 0x60480
-#define _TRANS_VRR_VTOTAL_PREV_B 0x61480
-#define _TRANS_VRR_VTOTAL_PREV_C 0x62480
-#define _TRANS_VRR_VTOTAL_PREV_D 0x63480
+ _TRANS_VRR_VMAXSHIFT_A)
+#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
+#define VRR_VMAXSHIFT_DEC REG_BIT(16)
+#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
+
+#define _TRANS_VRR_STATUS_A 0x6042c
+#define _TRANS_VRR_STATUS_B 0x6142c
+#define _TRANS_VRR_STATUS_C 0x6242c
+#define _TRANS_VRR_STATUS_D 0x6342c
+#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
+#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
+#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
+#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
+#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
+#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
+#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
+#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
+#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
+#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
+#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
+#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
+#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
+#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
+#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
+
+#define _TRANS_VRR_VTOTAL_PREV_A 0x60480
+#define _TRANS_VRR_VTOTAL_PREV_B 0x61480
+#define _TRANS_VRR_VTOTAL_PREV_C 0x62480
+#define _TRANS_VRR_VTOTAL_PREV_D 0x63480
#define TRANS_VRR_VTOTAL_PREV(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
- _TRANS_VRR_VTOTAL_PREV_A)
-#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
-#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
-#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
-#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
-
-#define _TRANS_VRR_FLIPLINE_A 0x60438
-#define _TRANS_VRR_FLIPLINE_B 0x61438
-#define _TRANS_VRR_FLIPLINE_C 0x62438
-#define _TRANS_VRR_FLIPLINE_D 0x63438
+ _TRANS_VRR_VTOTAL_PREV_A)
+#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
+#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
+#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
+#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
+
+#define _TRANS_VRR_FLIPLINE_A 0x60438
+#define _TRANS_VRR_FLIPLINE_B 0x61438
+#define _TRANS_VRR_FLIPLINE_C 0x62438
+#define _TRANS_VRR_FLIPLINE_D 0x63438
#define TRANS_VRR_FLIPLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
- _TRANS_VRR_FLIPLINE_A)
-#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
+ _TRANS_VRR_FLIPLINE_A)
+#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
-#define _TRANS_VRR_STATUS2_A 0x6043C
-#define _TRANS_VRR_STATUS2_B 0x6143C
-#define _TRANS_VRR_STATUS2_C 0x6243C
-#define _TRANS_VRR_STATUS2_D 0x6343C
+#define _TRANS_VRR_STATUS2_A 0x6043c
+#define _TRANS_VRR_STATUS2_B 0x6143c
+#define _TRANS_VRR_STATUS2_C 0x6243c
+#define _TRANS_VRR_STATUS2_D 0x6343c
#define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A)
-#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
+#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
-#define _TRANS_PUSH_A 0x60A70
-#define _TRANS_PUSH_B 0x61A70
-#define _TRANS_PUSH_C 0x62A70
-#define _TRANS_PUSH_D 0x63A70
+#define _TRANS_PUSH_A 0x60a70
+#define _TRANS_PUSH_B 0x61a70
+#define _TRANS_PUSH_C 0x62a70
+#define _TRANS_PUSH_D 0x63a70
#define TRANS_PUSH(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A)
-#define TRANS_PUSH_EN REG_BIT(31)
-#define TRANS_PUSH_SEND REG_BIT(30)
-
-#define _TRANS_VRR_VSYNC_A 0x60078
-#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A)
-#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
-#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end))
-#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
-#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
+#define TRANS_PUSH_EN REG_BIT(31)
+#define TRANS_PUSH_SEND REG_BIT(30)
+
+#define _TRANS_VRR_VSYNC_A 0x60078
+#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A)
+#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
+#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end))
+#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
+#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
/* VGA port control */
#define ADPA _MMIO(0x61100)
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v15 2/9] drm/i915: Separate VRR related register definitions
2024-06-10 2:48 [PATCH v15 0/9] Implement CMRR Support Mitul Golani
2024-06-10 2:48 ` [PATCH v15 1/9] gpu/drm/i915: Update indentation for VRR registers and bits Mitul Golani
@ 2024-06-10 2:48 ` Mitul Golani
2024-06-10 4:46 ` Nautiyal, Ankit K
2024-06-10 2:48 ` [PATCH v15 3/9] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani
` (11 subsequent siblings)
13 siblings, 1 reply; 17+ messages in thread
From: Mitul Golani @ 2024-06-10 2:48 UTC (permalink / raw)
To: intel-gfx; +Cc: ankit.k.nautiyal
Move VRR related register definitions to a separate file called
intel_vrr_regs.h.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 111 ++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 100 ----------------
3 files changed, 112 insertions(+), 100 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_vrr_regs.h
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5f3657aa8313..871e6e6a184a 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -9,6 +9,7 @@
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_vrr.h"
+#include "intel_vrr_regs.h"
#include "intel_dp.h"
bool intel_vrr_is_capable(struct intel_connector *connector)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
new file mode 100644
index 000000000000..c3237d5c38df
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __INTEL_VRR_REGS_H__
+#define __INTEL_VRR_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+/* VRR registers */
+#define _TRANS_VRR_CTL_A 0x60420
+#define _TRANS_VRR_CTL_B 0x61420
+#define _TRANS_VRR_CTL_C 0x62420
+#define _TRANS_VRR_CTL_D 0x63420
+#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
+#define VRR_CTL_VRR_ENABLE REG_BIT(31)
+#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
+#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
+#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
+#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
+#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
+#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
+#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
+
+#define _TRANS_VRR_VMAX_A 0x60424
+#define _TRANS_VRR_VMAX_B 0x61424
+#define _TRANS_VRR_VMAX_C 0x62424
+#define _TRANS_VRR_VMAX_D 0x63424
+#define TRANS_VRR_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A)
+#define VRR_VMAX_MASK REG_GENMASK(19, 0)
+
+#define _TRANS_VRR_VMIN_A 0x60434
+#define _TRANS_VRR_VMIN_B 0x61434
+#define _TRANS_VRR_VMIN_C 0x62434
+#define _TRANS_VRR_VMIN_D 0x63434
+#define TRANS_VRR_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A)
+#define VRR_VMIN_MASK REG_GENMASK(15, 0)
+
+#define _TRANS_VRR_VMAXSHIFT_A 0x60428
+#define _TRANS_VRR_VMAXSHIFT_B 0x61428
+#define _TRANS_VRR_VMAXSHIFT_C 0x62428
+#define _TRANS_VRR_VMAXSHIFT_D 0x63428
+#define TRANS_VRR_VMAXSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
+ _TRANS_VRR_VMAXSHIFT_A)
+#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
+#define VRR_VMAXSHIFT_DEC REG_BIT(16)
+#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
+
+#define _TRANS_VRR_STATUS_A 0x6042c
+#define _TRANS_VRR_STATUS_B 0x6142c
+#define _TRANS_VRR_STATUS_C 0x6242c
+#define _TRANS_VRR_STATUS_D 0x6342c
+#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
+#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
+#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
+#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
+#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
+#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
+#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
+#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
+#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
+#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
+#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
+#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
+#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
+#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
+#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
+
+#define _TRANS_VRR_VTOTAL_PREV_A 0x60480
+#define _TRANS_VRR_VTOTAL_PREV_B 0x61480
+#define _TRANS_VRR_VTOTAL_PREV_C 0x62480
+#define _TRANS_VRR_VTOTAL_PREV_D 0x63480
+#define TRANS_VRR_VTOTAL_PREV(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
+ _TRANS_VRR_VTOTAL_PREV_A)
+#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
+#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
+#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
+#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
+
+#define _TRANS_VRR_FLIPLINE_A 0x60438
+#define _TRANS_VRR_FLIPLINE_B 0x61438
+#define _TRANS_VRR_FLIPLINE_C 0x62438
+#define _TRANS_VRR_FLIPLINE_D 0x63438
+#define TRANS_VRR_FLIPLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
+ _TRANS_VRR_FLIPLINE_A)
+#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
+
+#define _TRANS_VRR_STATUS2_A 0x6043c
+#define _TRANS_VRR_STATUS2_B 0x6143c
+#define _TRANS_VRR_STATUS2_C 0x6243c
+#define _TRANS_VRR_STATUS2_D 0x6343c
+#define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A)
+#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
+
+#define _TRANS_PUSH_A 0x60a70
+#define _TRANS_PUSH_B 0x61a70
+#define _TRANS_PUSH_C 0x62a70
+#define _TRANS_PUSH_D 0x63a70
+#define TRANS_PUSH(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A)
+#define TRANS_PUSH_EN REG_BIT(31)
+#define TRANS_PUSH_SEND REG_BIT(30)
+
+#define _TRANS_VRR_VSYNC_A 0x60078
+#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A)
+#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
+#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end))
+#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
+#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
+
+#endif /* __INTEL_VRR_REGS__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a10591424338..df58cf38e144 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1147,106 +1147,6 @@
#define PIPESRC(dev_priv, pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
#define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
-/* VRR registers */
-#define _TRANS_VRR_CTL_A 0x60420
-#define _TRANS_VRR_CTL_B 0x61420
-#define _TRANS_VRR_CTL_C 0x62420
-#define _TRANS_VRR_CTL_D 0x63420
-#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
-#define VRR_CTL_VRR_ENABLE REG_BIT(31)
-#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
-#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
-#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
-#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
-#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
-#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
-#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
-
-#define _TRANS_VRR_VMAX_A 0x60424
-#define _TRANS_VRR_VMAX_B 0x61424
-#define _TRANS_VRR_VMAX_C 0x62424
-#define _TRANS_VRR_VMAX_D 0x63424
-#define TRANS_VRR_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A)
-#define VRR_VMAX_MASK REG_GENMASK(19, 0)
-
-#define _TRANS_VRR_VMIN_A 0x60434
-#define _TRANS_VRR_VMIN_B 0x61434
-#define _TRANS_VRR_VMIN_C 0x62434
-#define _TRANS_VRR_VMIN_D 0x63434
-#define TRANS_VRR_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A)
-#define VRR_VMIN_MASK REG_GENMASK(15, 0)
-
-#define _TRANS_VRR_VMAXSHIFT_A 0x60428
-#define _TRANS_VRR_VMAXSHIFT_B 0x61428
-#define _TRANS_VRR_VMAXSHIFT_C 0x62428
-#define _TRANS_VRR_VMAXSHIFT_D 0x63428
-#define TRANS_VRR_VMAXSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
- _TRANS_VRR_VMAXSHIFT_A)
-#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
-#define VRR_VMAXSHIFT_DEC REG_BIT(16)
-#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
-
-#define _TRANS_VRR_STATUS_A 0x6042c
-#define _TRANS_VRR_STATUS_B 0x6142c
-#define _TRANS_VRR_STATUS_C 0x6242c
-#define _TRANS_VRR_STATUS_D 0x6342c
-#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
-#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
-#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
-#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
-#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
-#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
-#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
-#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
-#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
-#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
-#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
-#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
-#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
-#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
-#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
-
-#define _TRANS_VRR_VTOTAL_PREV_A 0x60480
-#define _TRANS_VRR_VTOTAL_PREV_B 0x61480
-#define _TRANS_VRR_VTOTAL_PREV_C 0x62480
-#define _TRANS_VRR_VTOTAL_PREV_D 0x63480
-#define TRANS_VRR_VTOTAL_PREV(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
- _TRANS_VRR_VTOTAL_PREV_A)
-#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
-#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
-#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
-#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
-
-#define _TRANS_VRR_FLIPLINE_A 0x60438
-#define _TRANS_VRR_FLIPLINE_B 0x61438
-#define _TRANS_VRR_FLIPLINE_C 0x62438
-#define _TRANS_VRR_FLIPLINE_D 0x63438
-#define TRANS_VRR_FLIPLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
- _TRANS_VRR_FLIPLINE_A)
-#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
-
-#define _TRANS_VRR_STATUS2_A 0x6043c
-#define _TRANS_VRR_STATUS2_B 0x6143c
-#define _TRANS_VRR_STATUS2_C 0x6243c
-#define _TRANS_VRR_STATUS2_D 0x6343c
-#define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A)
-#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
-
-#define _TRANS_PUSH_A 0x60a70
-#define _TRANS_PUSH_B 0x61a70
-#define _TRANS_PUSH_C 0x62a70
-#define _TRANS_PUSH_D 0x63a70
-#define TRANS_PUSH(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A)
-#define TRANS_PUSH_EN REG_BIT(31)
-#define TRANS_PUSH_SEND REG_BIT(30)
-
-#define _TRANS_VRR_VSYNC_A 0x60078
-#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A)
-#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
-#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end))
-#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
-#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
-
/* VGA port control */
#define ADPA _MMIO(0x61100)
#define PCH_ADPA _MMIO(0xe1100)
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v15 3/9] drm/i915: Define and compute Transcoder CMRR registers
2024-06-10 2:48 [PATCH v15 0/9] Implement CMRR Support Mitul Golani
2024-06-10 2:48 ` [PATCH v15 1/9] gpu/drm/i915: Update indentation for VRR registers and bits Mitul Golani
2024-06-10 2:48 ` [PATCH v15 2/9] drm/i915: Separate VRR related register definitions Mitul Golani
@ 2024-06-10 2:48 ` Mitul Golani
2024-06-10 2:48 ` [PATCH v15 4/9] drm/i915: Update trans_vrr_ctl flag when cmrr is computed Mitul Golani
` (10 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Mitul Golani @ 2024-06-10 2:48 UTC (permalink / raw)
To: intel-gfx; +Cc: ankit.k.nautiyal
Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.
--v2:
- Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
- Fix indent and order based on register offset. [Jani]
--v3:
- Removing RFC tag.
--v4:
- Update place holder for CMRR register definition. (Jani)
--v5:
- Add CMRR register definitions to a separate file intel_vrr_reg.h.
--v6:
- Fixed indentation. (Jani)
- Add dependency header intel_display_reg_defs.h. (Jani)
- Rename file name to intel_vrr_regs.h instead of reg.h (Jani)
--v7:
- Remove adding CMRR flag to vrr_ctl register during set_transcoder_timing,
as it is already being done during intel_vrr_enable. (Ankit)
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 23 ++++++++++++++++++-
.../drm/i915/display/intel_display_types.h | 6 +++++
drivers/gpu/drm/i915/display/intel_vrr.c | 20 ++++++++++++++++
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 14 +++++++++++
4 files changed, 62 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c608329dac42..33f5a3ef2e94 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1006,6 +1006,13 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
}
+static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
+ const struct intel_crtc_state *new_crtc_state)
+{
+ return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
+ old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
+}
+
static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
const struct intel_crtc_state *new_crtc_state)
{
@@ -5078,6 +5085,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
} \
} while (0)
+#define PIPE_CONF_CHECK_LLI(name) do { \
+ if (current_config->name != pipe_config->name) { \
+ pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
+ "(expected %lli, found %lli)", \
+ current_config->name, \
+ pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
+
#define PIPE_CONF_CHECK_BOOL(name) do { \
if (current_config->name != pipe_config->name) { \
BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
@@ -5456,10 +5473,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(vrr.guardband);
PIPE_CONF_CHECK_I(vrr.vsync_start);
PIPE_CONF_CHECK_I(vrr.vsync_end);
+ PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
+ PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
}
#undef PIPE_CONF_CHECK_X
#undef PIPE_CONF_CHECK_I
+#undef PIPE_CONF_CHECK_LLI
#undef PIPE_CONF_CHECK_BOOL
#undef PIPE_CONF_CHECK_P
#undef PIPE_CONF_CHECK_FLAGS
@@ -6848,7 +6868,8 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state,
intel_crtc_needs_fastset(new_crtc_state))
icl_set_pipe_chicken(new_crtc_state);
- if (vrr_params_changed(old_crtc_state, new_crtc_state))
+ if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
+ cmrr_params_changed(old_crtc_state, new_crtc_state))
intel_vrr_set_transcoder_timings(new_crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 83d6a3d901fd..098cabc15c7f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1402,6 +1402,12 @@ struct intel_crtc_state {
u32 vsync_end, vsync_start;
} vrr;
+ /* Content Match Refresh Rate state */
+ struct {
+ bool enable;
+ u64 cmrr_n, cmrr_m;
+ } cmrr;
+
/* Stream Splitter for eDP MSO */
struct {
bool enable;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 871e6e6a184a..d2f854d9d18b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -219,6 +219,17 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
return;
}
+ if (crtc_state->cmrr.enable) {
+ intel_de_write(dev_priv, TRANS_CMRR_M_HI(dev_priv, cpu_transcoder),
+ upper_32_bits(crtc_state->cmrr.cmrr_m));
+ intel_de_write(dev_priv, TRANS_CMRR_M_LO(dev_priv, cpu_transcoder),
+ lower_32_bits(crtc_state->cmrr.cmrr_m));
+ intel_de_write(dev_priv, TRANS_CMRR_N_HI(dev_priv, cpu_transcoder),
+ upper_32_bits(crtc_state->cmrr.cmrr_n));
+ intel_de_write(dev_priv, TRANS_CMRR_N_LO(dev_priv, cpu_transcoder),
+ lower_32_bits(crtc_state->cmrr.cmrr_n));
+ }
+
intel_de_write(dev_priv, TRANS_VRR_VMIN(dev_priv, cpu_transcoder),
crtc_state->vrr.vmin - 1);
intel_de_write(dev_priv, TRANS_VRR_VMAX(dev_priv, cpu_transcoder),
@@ -307,6 +318,15 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
+ if (crtc_state->cmrr.enable) {
+ crtc_state->cmrr.cmrr_n =
+ intel_de_read64_2x32(dev_priv, TRANS_CMRR_N_LO(dev_priv, cpu_transcoder),
+ TRANS_CMRR_N_HI(dev_priv, cpu_transcoder));
+ crtc_state->cmrr.cmrr_m =
+ intel_de_read64_2x32(dev_priv, TRANS_CMRR_M_LO(dev_priv, cpu_transcoder),
+ TRANS_CMRR_M_HI(dev_priv, cpu_transcoder));
+ }
+
if (DISPLAY_VER(dev_priv) >= 13)
crtc_state->vrr.guardband =
REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index c3237d5c38df..20267ec12f5a 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -108,4 +108,18 @@
#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
+/*CMRR Registers*/
+
+#define _TRANS_CMRR_M_LO_A 0x604F0
+#define TRANS_CMRR_M_LO(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_LO_A)
+
+#define _TRANS_CMRR_M_HI_A 0x604F4
+#define TRANS_CMRR_M_HI(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_HI_A)
+
+#define _TRANS_CMRR_N_LO_A 0x604F8
+#define TRANS_CMRR_N_LO(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_LO_A)
+
+#define _TRANS_CMRR_N_HI_A 0x604FC
+#define TRANS_CMRR_N_HI(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_HI_A)
+
#endif /* __INTEL_VRR_REGS__ */
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v15 4/9] drm/i915: Update trans_vrr_ctl flag when cmrr is computed
2024-06-10 2:48 [PATCH v15 0/9] Implement CMRR Support Mitul Golani
` (2 preceding siblings ...)
2024-06-10 2:48 ` [PATCH v15 3/9] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani
@ 2024-06-10 2:48 ` Mitul Golani
2024-06-10 2:48 ` [PATCH v15 5/9] drm/dp: Add refresh rate divider to struct representing AS SDP Mitul Golani
` (9 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Mitul Golani @ 2024-06-10 2:48 UTC (permalink / raw)
To: intel-gfx; +Cc: ankit.k.nautiyal
Add/update trans_vrr_ctl flag when crtc_state->cmrr.enable
is set, With this commit setting the stage for subsequent
CMRR enablement.
--v2:
- Check pipe active state in cmrr enabling. [Jani]
- Remove usage of bitwise OR on booleans. [Jani]
- Revert unrelated changes. [Jani]
- Update intel_vrr_enable, vrr and cmrr enable conditions. [Jani]
- Simplify whole if-ladder in intel_vrr_enable. [Jani]
- Revert patch restructuring mistakes in intel_vrr_get_config. [Jani]
--v3:
- Check pipe active state in cmrr disabling.[Jani]
- Correct messed up condition in intel_vrr_enable. [Jani]
--v4:
- Removing RFC tag.
--v5:
- CMRR handling in co-existatnce of LRR and DRRS.
--v7:
- Rebase on top of AS SDP merge.
--v8:
- Remove cmrr_enabling/disabling and update commit message. (Ankit)
--v9:
- Revert removed line(Ankit).
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 10 ++++++++--
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 2 ++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index d2f854d9d18b..19b364074de0 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -282,8 +282,14 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
VRR_VSYNC_START(crtc_state->vrr.vsync_start));
- intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
- VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
+ if (crtc_state->cmrr.enable) {
+ intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
+ VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
+ trans_vrr_ctl(crtc_state));
+ } else {
+ intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
+ VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
+ }
}
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index 20267ec12f5a..6ed0e0dc97e7 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -122,4 +122,6 @@
#define _TRANS_CMRR_N_HI_A 0x604FC
#define TRANS_CMRR_N_HI(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_HI_A)
+#define VRR_CTL_CMRR_ENABLE REG_BIT(27)
+
#endif /* __INTEL_VRR_REGS__ */
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v15 5/9] drm/dp: Add refresh rate divider to struct representing AS SDP
2024-06-10 2:48 [PATCH v15 0/9] Implement CMRR Support Mitul Golani
` (3 preceding siblings ...)
2024-06-10 2:48 ` [PATCH v15 4/9] drm/i915: Update trans_vrr_ctl flag when cmrr is computed Mitul Golani
@ 2024-06-10 2:48 ` Mitul Golani
2024-06-10 2:48 ` [PATCH v15 6/9] drm/i915/display: Add support for pack and unpack Mitul Golani
` (8 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Mitul Golani @ 2024-06-10 2:48 UTC (permalink / raw)
To: intel-gfx; +Cc: ankit.k.nautiyal
Add target_rr_divider to structure representing AS SDP.
It is valid only in FAVT mode, sink device ignores the bit in AVT
mode.
--v2:
- Update commit header and send patch to dri-devel.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
---
include/drm/display/drm_dp_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index 8defcc399f42..ea03e1dd26ba 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -122,6 +122,7 @@ struct drm_dp_as_sdp {
int target_rr;
int duration_incr_ms;
int duration_decr_ms;
+ bool target_rr_divider;
enum operation_mode mode;
};
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v15 6/9] drm/i915/display: Add support for pack and unpack
2024-06-10 2:48 [PATCH v15 0/9] Implement CMRR Support Mitul Golani
` (4 preceding siblings ...)
2024-06-10 2:48 ` [PATCH v15 5/9] drm/dp: Add refresh rate divider to struct representing AS SDP Mitul Golani
@ 2024-06-10 2:48 ` Mitul Golani
2024-06-10 2:48 ` [PATCH v15 7/9] drm/i915/display: Compute Adaptive sync SDP params Mitul Golani
` (7 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Mitul Golani @ 2024-06-10 2:48 UTC (permalink / raw)
To: intel-gfx; +Cc: ankit.k.nautiyal
Add support of pack and unpack for target_rr_divider.
--v2:
- Set Target Refresh Rate Divider bit when related
AS SDP bit is set (Ankit).
--v3:
- target_rr_divider is bools so set accordingly (Ankit).
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index fd054e16850d..ac81b172b1ec 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4232,6 +4232,9 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
sdp->db[3] = as_sdp->target_rr & 0xFF;
sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3;
+ if (as_sdp->target_rr_divider)
+ sdp->db[4] |= 0x20;
+
return length;
}
@@ -4413,6 +4416,7 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;
as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
+ as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
return 0;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v15 7/9] drm/i915/display: Compute Adaptive sync SDP params
2024-06-10 2:48 [PATCH v15 0/9] Implement CMRR Support Mitul Golani
` (5 preceding siblings ...)
2024-06-10 2:48 ` [PATCH v15 6/9] drm/i915/display: Add support for pack and unpack Mitul Golani
@ 2024-06-10 2:48 ` Mitul Golani
2024-06-10 2:48 ` [PATCH v15 8/9] drm/i915/display: Compute vrr vsync params Mitul Golani
` (6 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Mitul Golani @ 2024-06-10 2:48 UTC (permalink / raw)
To: intel-gfx; +Cc: ankit.k.nautiyal
Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.
--v2:
Since vrr.enable is set in case of cmrr also, handle accordingly(Ankit).
--v3:
- Since vrr.enable is set in case of cmrr also, handle
accordingly(Ankit).
- check cmrr.enable when CMRR flags are set during intel_dp_compute_as_sdp.
--v4:
- Use drm_mode_vrefresh instead of manual calculation (Ankit).
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ac81b172b1ec..b5915c23302f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2637,11 +2637,19 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
/* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */
as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
as_sdp->length = 0x9;
- as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
- as_sdp->vtotal = adjusted_mode->vtotal;
- as_sdp->target_rr = 0;
as_sdp->duration_incr_ms = 0;
as_sdp->duration_incr_ms = 0;
+
+ if (crtc_state->cmrr.enable) {
+ as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
+ as_sdp->vtotal = adjusted_mode->vtotal;
+ as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
+ as_sdp->target_rr_divider = true;
+ } else {
+ as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
+ as_sdp->vtotal = adjusted_mode->vtotal;
+ as_sdp->target_rr = 0;
+ }
}
static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v15 8/9] drm/i915/display: Compute vrr vsync params
2024-06-10 2:48 [PATCH v15 0/9] Implement CMRR Support Mitul Golani
` (6 preceding siblings ...)
2024-06-10 2:48 ` [PATCH v15 7/9] drm/i915/display: Compute Adaptive sync SDP params Mitul Golani
@ 2024-06-10 2:48 ` Mitul Golani
2024-06-10 2:48 ` [PATCH v15 9/9] drm/i915: Compute CMRR and calculate vtotal Mitul Golani
` (5 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Mitul Golani @ 2024-06-10 2:48 UTC (permalink / raw)
To: intel-gfx; +Cc: ankit.k.nautiyal
Compute vrr vsync params in case of FAVT as well instead of
only to AVT mode of operation.
--v2:
- Remove redundant computation for vrr_vsync_start
and vrr_vsync_end(Ankit).
--v3:
- vrr.enable and cmrr.enable check together is not required as both
will be true at the same point in time. (Ankit)
- Replace vrr.enable flag to cmrr.enable, mistakenly added. (Ankit)
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 19b364074de0..4ad99a54aa83 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -175,14 +175,15 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
if (crtc_state->uapi.vrr_enabled) {
crtc_state->vrr.enable = true;
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
- if (intel_dp_as_sdp_supported(intel_dp)) {
- crtc_state->vrr.vsync_start =
- (crtc_state->hw.adjusted_mode.crtc_vtotal -
- crtc_state->hw.adjusted_mode.vsync_start);
- crtc_state->vrr.vsync_end =
- (crtc_state->hw.adjusted_mode.crtc_vtotal -
- crtc_state->hw.adjusted_mode.vsync_end);
- }
+ }
+
+ if (intel_dp_as_sdp_supported(intel_dp)) {
+ crtc_state->vrr.vsync_start =
+ (crtc_state->hw.adjusted_mode.crtc_vtotal -
+ crtc_state->hw.adjusted_mode.vsync_start);
+ crtc_state->vrr.vsync_end =
+ (crtc_state->hw.adjusted_mode.crtc_vtotal -
+ crtc_state->hw.adjusted_mode.vsync_end);
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v15 9/9] drm/i915: Compute CMRR and calculate vtotal
2024-06-10 2:48 [PATCH v15 0/9] Implement CMRR Support Mitul Golani
` (7 preceding siblings ...)
2024-06-10 2:48 ` [PATCH v15 8/9] drm/i915/display: Compute vrr vsync params Mitul Golani
@ 2024-06-10 2:48 ` Mitul Golani
2024-06-10 3:25 ` ✗ Fi.CI.CHECKPATCH: warning for Implement CMRR Support (rev16) Patchwork
` (4 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Mitul Golani @ 2024-06-10 2:48 UTC (permalink / raw)
To: intel-gfx; +Cc: ankit.k.nautiyal
Compute Fixed Average Vtotal/CMRR with resepect to
userspace VRR enablement. Also calculate required
parameters in case of CMRR is enabled. During
intel_vrr_compute_config, CMRR is getting enabled
based on userspace has enabled Variable refresh mode
with VRR timing generator or not. Make CMRR as small subset of
FAVT mode, when Panel is running on Fixed refresh rate
and on VRR framework then only enable CMRR to match with
actual refresh rate.
--v2:
- Update is_cmrr_frac_required function return as bool, not int. [Jani]
- Use signed int math instead of unsigned in cmrr_get_vtotal2. [Jani]
- Fix typo and usage of camel case in cmrr_get_vtotal. [Jani]
- Use do_div in cmrr_get_vtotalwhile calculating cmrr_m. [ Jani]
- Simplify cmrr and vrr compute config in intel_vrr_compute_config. [Jani]
- Correct valiable name usage in is_cmrr_frac_required. [Ville]
--v3:
- Removing RFC tag.
--v4:
- Added edp check to address edp usecase for now. (ville)
- Updated is_cmrr_fraction_required to more simplified calculation.
- on longterm goal to be worked upon uapi as suggestion from ville.
--v5:
- Correct vtotal paramas accuracy and add 2 digit precision.
- Avoid using DIV_ROUND_UP and improve scanline precision.
--v6:
- Make CMRR a small subset of FAVT mode.
--v7:
- Update commit message to avoid confusion with Legacy VRR (Ankit).
- Add cmrr.enable in last, so remove from this patch.
--v8:
- Set cmrr.enable in current patch instead of separate patch (Ankit).
- Since vrr.enable and cmrr.enable are not mutually exclusive,
handle accordingly (Ankit).
- is_edp is not required inside is_cmrr_frac_required function (Ankit).
- Add video_mode_required flag for future enhancement.
- Correct cmrr_m/cmrr_n calculation.
--v9:
- Move patch to last and set other bits before computing
cmrr.enable.(Ankit)
- Add TODO: for to address target refresh rate precision as future
enhancement.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915/display/intel_display_device.h | 1 +
drivers/gpu/drm/i915/display/intel_vrr.c | 92 ++++++++++++++++---
3 files changed, 83 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 33f5a3ef2e94..5a91f67a8c9f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5475,6 +5475,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(vrr.vsync_end);
PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
+ PIPE_CONF_CHECK_BOOL(cmrr.enable);
}
#undef PIPE_CONF_CHECK_X
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 44cda6c3e4d8..13453ea4daea 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -154,6 +154,7 @@ enum intel_display_subplatform {
BIT(trans)) != 0)
#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
#define HAS_AS_SDP(i915) (DISPLAY_VER(i915) >= 13)
+#define HAS_CMRR(i915) (DISPLAY_VER(i915) >= 20)
#define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
#define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug)
#define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 4ad99a54aa83..05f67dc9d98d 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -12,6 +12,9 @@
#include "intel_vrr_regs.h"
#include "intel_dp.h"
+#define FIXED_POINT_PRECISION 100
+#define CMRR_PRECISION_TOLERANCE 10
+
bool intel_vrr_is_capable(struct intel_connector *connector)
{
const struct drm_display_info *info = &connector->base.display_info;
@@ -107,6 +110,52 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state);
}
+static bool
+is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
+{
+ int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
+ struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+
+ if (!HAS_CMRR(i915))
+ return false;
+
+ actual_refresh_k =
+ drm_mode_vrefresh(adjusted_mode) * FIXED_POINT_PRECISION;
+ pixel_clock_per_line =
+ adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal;
+ calculated_refresh_k =
+ pixel_clock_per_line * FIXED_POINT_PRECISION / adjusted_mode->crtc_vtotal;
+
+ if ((actual_refresh_k - calculated_refresh_k) < CMRR_PRECISION_TOLERANCE)
+ return false;
+
+ return true;
+}
+
+static unsigned int
+cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
+{
+ int multiplier_m = 1, multiplier_n = 1, vtotal, desired_refresh_rate;
+ long long adjusted_pixel_rate;
+ struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+
+ desired_refresh_rate = drm_mode_vrefresh(adjusted_mode);
+
+ if (video_mode_required) {
+ multiplier_m = 1001;
+ multiplier_n = 1000;
+ }
+
+ crtc_state->cmrr.cmrr_n =
+ desired_refresh_rate * adjusted_mode->crtc_htotal * multiplier_n;
+ vtotal = (adjusted_mode->crtc_clock * 1000 * multiplier_n) / crtc_state->cmrr.cmrr_n;
+ adjusted_pixel_rate = adjusted_mode->crtc_clock * 1000 * multiplier_m;
+ crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n);
+
+ return vtotal;
+}
+
void
intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
@@ -116,6 +165,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
struct intel_dp *intel_dp = intel_attached_dp(connector);
+ bool is_edp = intel_dp_is_edp(intel_dp);
struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
const struct drm_display_info *info = &connector->base.display_info;
int vmin, vmax;
@@ -160,21 +210,26 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1;
/*
- * For XE_LPD+, we use guardband and pipeline override
- * is deprecated.
+ * When panel is VRR capable and userspace has
+ * not enabled adaptive sync mode then Fixed Average
+ * Vtotal mode should be enabled.
*/
- if (DISPLAY_VER(i915) >= 13) {
- crtc_state->vrr.guardband =
- crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start;
- } else {
- crtc_state->vrr.pipeline_full =
- min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start -
- crtc_state->framestart_delay - 1);
- }
-
if (crtc_state->uapi.vrr_enabled) {
crtc_state->vrr.enable = true;
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+ } else if (is_cmrr_frac_required(crtc_state) && is_edp) {
+ crtc_state->vrr.enable = true;
+ crtc_state->cmrr.enable = true;
+ /*
+ * TODO: Compute precise target refresh rate to determine
+ * if video_mode_required should be true. Currently set to
+ * false due to uncertainty about the precise target
+ * refresh Rate.
+ */
+ crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false);
+ crtc_state->vrr.vmin = crtc_state->vrr.vmax;
+ crtc_state->vrr.flipline = crtc_state->vrr.vmin;
+ crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
}
if (intel_dp_as_sdp_supported(intel_dp)) {
@@ -185,6 +240,19 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
(crtc_state->hw.adjusted_mode.crtc_vtotal -
crtc_state->hw.adjusted_mode.vsync_end);
}
+
+ /*
+ * For XE_LPD+, we use guardband and pipeline override
+ * is deprecated.
+ */
+ if (DISPLAY_VER(i915) >= 13) {
+ crtc_state->vrr.guardband =
+ crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start;
+ } else {
+ crtc_state->vrr.pipeline_full =
+ min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start -
+ crtc_state->framestart_delay - 1);
+ }
}
static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
@@ -324,6 +392,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
TRANS_VRR_CTL(dev_priv, cpu_transcoder));
crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
+ if (HAS_CMRR(dev_priv))
+ crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
if (crtc_state->cmrr.enable) {
crtc_state->cmrr.cmrr_n =
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Implement CMRR Support (rev16)
2024-06-10 2:48 [PATCH v15 0/9] Implement CMRR Support Mitul Golani
` (8 preceding siblings ...)
2024-06-10 2:48 ` [PATCH v15 9/9] drm/i915: Compute CMRR and calculate vtotal Mitul Golani
@ 2024-06-10 3:25 ` Patchwork
2024-06-10 3:25 ` ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2024-06-10 3:25 UTC (permalink / raw)
To: Mitul Golani; +Cc: intel-gfx
== Series Details ==
Series: Implement CMRR Support (rev16)
URL : https://patchwork.freedesktop.org/series/126443/
State : warning
== Summary ==
Error: dim checkpatch failed
b8cc2eb5f1b3 gpu/drm/i915: Update indentation for VRR registers and bits
-:56: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#56: FILE: drivers/gpu/drm/i915/i915_reg.h:1163:
+#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
total: 0 errors, 1 warnings, 0 checks, 191 lines checked
7741c9db9350 drm/i915: Separate VRR related register definitions
-:24: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#24:
new file mode 100644
-:52: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#52: FILE: drivers/gpu/drm/i915/display/intel_vrr_regs.h:24:
+#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
total: 0 errors, 2 warnings, 0 checks, 224 lines checked
44cea8d41519 drm/i915: Define and compute Transcoder CMRR registers
-:58: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#58: FILE: drivers/gpu/drm/i915/display/intel_display.c:5088:
+#define PIPE_CONF_CHECK_LLI(name) do { \
+ if (current_config->name != pipe_config->name) { \
+ pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
+ "(expected %lli, found %lli)", \
+ current_config->name, \
+ pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
-:58: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues
#58: FILE: drivers/gpu/drm/i915/display/intel_display.c:5088:
+#define PIPE_CONF_CHECK_LLI(name) do { \
+ if (current_config->name != pipe_config->name) { \
+ pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
+ "(expected %lli, found %lli)", \
+ current_config->name, \
+ pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
total: 0 errors, 0 warnings, 2 checks, 113 lines checked
db37dc341b7a drm/i915: Update trans_vrr_ctl flag when cmrr is computed
c4d451d75652 drm/dp: Add refresh rate divider to struct representing AS SDP
7ca4826c4e55 drm/i915/display: Add support for pack and unpack
faef2ab5539c drm/i915/display: Compute Adaptive sync SDP params
65adee246cc0 drm/i915/display: Compute vrr vsync params
613540a63c0e drm/i915: Compute CMRR and calculate vtotal
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✗ Fi.CI.SPARSE: warning for Implement CMRR Support (rev16)
2024-06-10 2:48 [PATCH v15 0/9] Implement CMRR Support Mitul Golani
` (9 preceding siblings ...)
2024-06-10 3:25 ` ✗ Fi.CI.CHECKPATCH: warning for Implement CMRR Support (rev16) Patchwork
@ 2024-06-10 3:25 ` Patchwork
2024-06-10 3:31 ` ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2024-06-10 3:25 UTC (permalink / raw)
To: Mitul Golani; +Cc: intel-gfx
== Series Details ==
Series: Implement CMRR Support (rev16)
URL : https://patchwork.freedesktop.org/series/126443/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✓ Fi.CI.BAT: success for Implement CMRR Support (rev16)
2024-06-10 2:48 [PATCH v15 0/9] Implement CMRR Support Mitul Golani
` (10 preceding siblings ...)
2024-06-10 3:25 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2024-06-10 3:31 ` Patchwork
2024-06-10 4:53 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-06-11 4:34 ` [PATCH v15 0/9] Implement CMRR Support Kandpal, Suraj
13 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2024-06-10 3:31 UTC (permalink / raw)
To: Mitul Golani; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8758 bytes --]
== Series Details ==
Series: Implement CMRR Support (rev16)
URL : https://patchwork.freedesktop.org/series/126443/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14904 -> Patchwork_126443v16
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/index.html
Participating hosts (44 -> 42)
------------------------------
Additional (2): bat-kbl-2 bat-jsl-3
Missing (4): bat-dg2-11 bat-atsm-1 fi-snb-2520m bat-adlp-6
Known issues
------------
Here are the changes found in Patchwork_126443v16 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-jsl-3: NOTRUN -> [SKIP][1] ([i915#9318])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/bat-jsl-3/igt@debugfs_test@basic-hwmon.html
* igt@fbdev@info:
- bat-kbl-2: NOTRUN -> [SKIP][2] ([i915#1849])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/bat-kbl-2/igt@fbdev@info.html
- bat-arls-3: [PASS][3] -> [SKIP][4] ([i915#1849])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/bat-arls-3/igt@fbdev@info.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/bat-arls-3/igt@fbdev@info.html
* igt@fbdev@nullptr:
- bat-arls-3: [PASS][5] -> [SKIP][6] ([i915#11191]) +3 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/bat-arls-3/igt@fbdev@nullptr.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/bat-arls-3/igt@fbdev@nullptr.html
* igt@gem_huc_copy@huc-copy:
- bat-jsl-3: NOTRUN -> [SKIP][7] ([i915#2190])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/bat-jsl-3/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- bat-jsl-3: NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/bat-jsl-3/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2: NOTRUN -> [SKIP][9] +39 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/bat-kbl-2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-jsl-3: NOTRUN -> [SKIP][10] ([i915#4103]) +1 other test skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/bat-jsl-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
- bat-arls-3: [PASS][11] -> [SKIP][12] ([i915#11190] / [i915#11204]) +5 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/bat-arls-3/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/bat-arls-3/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
* igt@kms_dsc@dsc-basic:
- bat-jsl-3: NOTRUN -> [SKIP][13] ([i915#3555] / [i915#9886])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/bat-jsl-3/igt@kms_dsc@dsc-basic.html
* igt@kms_flip@basic-flip-vs-wf_vblank:
- bat-arls-3: NOTRUN -> [SKIP][14] ([i915#3637]) +3 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/bat-arls-3/igt@kms_flip@basic-flip-vs-wf_vblank.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-jsl-3: NOTRUN -> [SKIP][15]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/bat-jsl-3/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- bat-arls-3: [PASS][16] -> [SKIP][17] ([i915#4342] / [i915#5354])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/bat-arls-3/igt@kms_frontbuffer_tracking@basic.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/bat-arls-3/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence:
- bat-arls-3: NOTRUN -> [SKIP][18] ([i915#11190] / [i915#11204]) +7 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/bat-arls-3/igt@kms_pipe_crc_basic@read-crc-frame-sequence.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-jsl-3: NOTRUN -> [SKIP][19] ([i915#3555])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/bat-jsl-3/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-arls-3: [PASS][20] -> [SKIP][21] ([i915#11204] / [i915#3708])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/bat-arls-3/igt@prime_vgem@basic-fence-flip.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/bat-arls-3/igt@prime_vgem@basic-fence-flip.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_lrc:
- bat-adln-1: [INCOMPLETE][22] ([i915#9413]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/bat-adln-1/igt@i915_selftest@live@gt_lrc.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/bat-adln-1/igt@i915_selftest@live@gt_lrc.html
* igt@kms_flip@basic-flip-vs-dpms@d-dp7:
- {bat-mtlp-9}: [DMESG-WARN][24] ([i915#11009]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/bat-mtlp-9/igt@kms_flip@basic-flip-vs-dpms@d-dp7.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/bat-mtlp-9/igt@kms_flip@basic-flip-vs-dpms@d-dp7.html
#### Warnings ####
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-arls-3: [SKIP][26] ([i915#10202]) -> [SKIP][27] ([i915#11190] / [i915#11204]) +1 other test skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/bat-arls-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/bat-arls-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_dsc@dsc-basic:
- bat-arls-3: [SKIP][28] ([i915#9886]) -> [SKIP][29] ([i915#11190] / [i915#11204])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/bat-arls-3/igt@kms_dsc@dsc-basic.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/bat-arls-3/igt@kms_dsc@dsc-basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10202]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10202
[i915#10580]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10580
[i915#10911]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10911
[i915#11009]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11009
[i915#11190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11190
[i915#11191]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11191
[i915#11204]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11204
[i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4342]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4342
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#6121]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6121
[i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
[i915#9413]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9413
[i915#9886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9886
Build changes
-------------
* Linux: CI_DRM_14904 -> Patchwork_126443v16
CI-20190529: 20190529
CI_DRM_14904: 2bea08bd31298d60d416b2a6ed346bb53dd28037 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7880: 73618605b4370cf902267aaf1d25666ff5e26112 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_126443v16: 2bea08bd31298d60d416b2a6ed346bb53dd28037 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/index.html
[-- Attachment #2: Type: text/html, Size: 10367 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v15 1/9] gpu/drm/i915: Update indentation for VRR registers and bits
2024-06-10 2:48 ` [PATCH v15 1/9] gpu/drm/i915: Update indentation for VRR registers and bits Mitul Golani
@ 2024-06-10 4:19 ` Nautiyal, Ankit K
0 siblings, 0 replies; 17+ messages in thread
From: Nautiyal, Ankit K @ 2024-06-10 4:19 UTC (permalink / raw)
To: Mitul Golani, intel-gfx
Subject: drm/i915 should suffice.
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
On 6/10/2024 8:18 AM, Mitul Golani wrote:
> Update the indentation for the VRR register definition and
> its bits, and fix checkpatch issues to ensure smooth movement
> of registers and bits.
>
> --v2:
> - Keep XELPD_VRR_CTL_VRR_GUARDBAND(x) to avoid readability (Ankit).
> - Fix all indentation related VRR registers and bits instead of
> checkpatch one.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 174 ++++++++++++++++----------------
> 1 file changed, 87 insertions(+), 87 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7daf902772e4..a10591424338 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1148,104 +1148,104 @@
> #define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
>
> /* VRR registers */
> -#define _TRANS_VRR_CTL_A 0x60420
> -#define _TRANS_VRR_CTL_B 0x61420
> -#define _TRANS_VRR_CTL_C 0x62420
> -#define _TRANS_VRR_CTL_D 0x63420
> -#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
> -#define VRR_CTL_VRR_ENABLE REG_BIT(31)
> -#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
> -#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
> -#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
> -#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
> -#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
> -#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
> -#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
> -
> -#define _TRANS_VRR_VMAX_A 0x60424
> -#define _TRANS_VRR_VMAX_B 0x61424
> -#define _TRANS_VRR_VMAX_C 0x62424
> -#define _TRANS_VRR_VMAX_D 0x63424
> +#define _TRANS_VRR_CTL_A 0x60420
> +#define _TRANS_VRR_CTL_B 0x61420
> +#define _TRANS_VRR_CTL_C 0x62420
> +#define _TRANS_VRR_CTL_D 0x63420
> +#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
> +#define VRR_CTL_VRR_ENABLE REG_BIT(31)
> +#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
> +#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
> +#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
> +#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
> +#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
> +#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
> +#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
> +
> +#define _TRANS_VRR_VMAX_A 0x60424
> +#define _TRANS_VRR_VMAX_B 0x61424
> +#define _TRANS_VRR_VMAX_C 0x62424
> +#define _TRANS_VRR_VMAX_D 0x63424
> #define TRANS_VRR_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A)
> -#define VRR_VMAX_MASK REG_GENMASK(19, 0)
> +#define VRR_VMAX_MASK REG_GENMASK(19, 0)
>
> -#define _TRANS_VRR_VMIN_A 0x60434
> -#define _TRANS_VRR_VMIN_B 0x61434
> -#define _TRANS_VRR_VMIN_C 0x62434
> -#define _TRANS_VRR_VMIN_D 0x63434
> +#define _TRANS_VRR_VMIN_A 0x60434
> +#define _TRANS_VRR_VMIN_B 0x61434
> +#define _TRANS_VRR_VMIN_C 0x62434
> +#define _TRANS_VRR_VMIN_D 0x63434
> #define TRANS_VRR_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A)
> -#define VRR_VMIN_MASK REG_GENMASK(15, 0)
> +#define VRR_VMIN_MASK REG_GENMASK(15, 0)
>
> -#define _TRANS_VRR_VMAXSHIFT_A 0x60428
> -#define _TRANS_VRR_VMAXSHIFT_B 0x61428
> -#define _TRANS_VRR_VMAXSHIFT_C 0x62428
> -#define _TRANS_VRR_VMAXSHIFT_D 0x63428
> +#define _TRANS_VRR_VMAXSHIFT_A 0x60428
> +#define _TRANS_VRR_VMAXSHIFT_B 0x61428
> +#define _TRANS_VRR_VMAXSHIFT_C 0x62428
> +#define _TRANS_VRR_VMAXSHIFT_D 0x63428
> #define TRANS_VRR_VMAXSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
> - _TRANS_VRR_VMAXSHIFT_A)
> -#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
> -#define VRR_VMAXSHIFT_DEC REG_BIT(16)
> -#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
> -
> -#define _TRANS_VRR_STATUS_A 0x6042C
> -#define _TRANS_VRR_STATUS_B 0x6142C
> -#define _TRANS_VRR_STATUS_C 0x6242C
> -#define _TRANS_VRR_STATUS_D 0x6342C
> -#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
> -#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
> -#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
> -#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
> -#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
> -#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
> -#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
> -#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
> -#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
> -#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
> -#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
> -#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
> -#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
> -#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
> -#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
> -
> -#define _TRANS_VRR_VTOTAL_PREV_A 0x60480
> -#define _TRANS_VRR_VTOTAL_PREV_B 0x61480
> -#define _TRANS_VRR_VTOTAL_PREV_C 0x62480
> -#define _TRANS_VRR_VTOTAL_PREV_D 0x63480
> + _TRANS_VRR_VMAXSHIFT_A)
> +#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
> +#define VRR_VMAXSHIFT_DEC REG_BIT(16)
> +#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
> +
> +#define _TRANS_VRR_STATUS_A 0x6042c
> +#define _TRANS_VRR_STATUS_B 0x6142c
> +#define _TRANS_VRR_STATUS_C 0x6242c
> +#define _TRANS_VRR_STATUS_D 0x6342c
> +#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
> +#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
> +#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
> +#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
> +#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
> +#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
> +#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
> +#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
> +#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
> +#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
> +#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
> +#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
> +#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
> +#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
> +#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
> +
> +#define _TRANS_VRR_VTOTAL_PREV_A 0x60480
> +#define _TRANS_VRR_VTOTAL_PREV_B 0x61480
> +#define _TRANS_VRR_VTOTAL_PREV_C 0x62480
> +#define _TRANS_VRR_VTOTAL_PREV_D 0x63480
> #define TRANS_VRR_VTOTAL_PREV(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
> - _TRANS_VRR_VTOTAL_PREV_A)
> -#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
> -#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
> -#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
> -#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
> -
> -#define _TRANS_VRR_FLIPLINE_A 0x60438
> -#define _TRANS_VRR_FLIPLINE_B 0x61438
> -#define _TRANS_VRR_FLIPLINE_C 0x62438
> -#define _TRANS_VRR_FLIPLINE_D 0x63438
> + _TRANS_VRR_VTOTAL_PREV_A)
> +#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
> +#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
> +#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
> +#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
> +
> +#define _TRANS_VRR_FLIPLINE_A 0x60438
> +#define _TRANS_VRR_FLIPLINE_B 0x61438
> +#define _TRANS_VRR_FLIPLINE_C 0x62438
> +#define _TRANS_VRR_FLIPLINE_D 0x63438
> #define TRANS_VRR_FLIPLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
> - _TRANS_VRR_FLIPLINE_A)
> -#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
> + _TRANS_VRR_FLIPLINE_A)
> +#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
>
> -#define _TRANS_VRR_STATUS2_A 0x6043C
> -#define _TRANS_VRR_STATUS2_B 0x6143C
> -#define _TRANS_VRR_STATUS2_C 0x6243C
> -#define _TRANS_VRR_STATUS2_D 0x6343C
> +#define _TRANS_VRR_STATUS2_A 0x6043c
> +#define _TRANS_VRR_STATUS2_B 0x6143c
> +#define _TRANS_VRR_STATUS2_C 0x6243c
> +#define _TRANS_VRR_STATUS2_D 0x6343c
> #define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A)
> -#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
> +#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
>
> -#define _TRANS_PUSH_A 0x60A70
> -#define _TRANS_PUSH_B 0x61A70
> -#define _TRANS_PUSH_C 0x62A70
> -#define _TRANS_PUSH_D 0x63A70
> +#define _TRANS_PUSH_A 0x60a70
> +#define _TRANS_PUSH_B 0x61a70
> +#define _TRANS_PUSH_C 0x62a70
> +#define _TRANS_PUSH_D 0x63a70
> #define TRANS_PUSH(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A)
> -#define TRANS_PUSH_EN REG_BIT(31)
> -#define TRANS_PUSH_SEND REG_BIT(30)
> -
> -#define _TRANS_VRR_VSYNC_A 0x60078
> -#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A)
> -#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
> -#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end))
> -#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
> -#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
> +#define TRANS_PUSH_EN REG_BIT(31)
> +#define TRANS_PUSH_SEND REG_BIT(30)
> +
> +#define _TRANS_VRR_VSYNC_A 0x60078
> +#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A)
> +#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
> +#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end))
> +#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
> +#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
>
> /* VGA port control */
> #define ADPA _MMIO(0x61100)
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v15 2/9] drm/i915: Separate VRR related register definitions
2024-06-10 2:48 ` [PATCH v15 2/9] drm/i915: Separate VRR related register definitions Mitul Golani
@ 2024-06-10 4:46 ` Nautiyal, Ankit K
0 siblings, 0 replies; 17+ messages in thread
From: Nautiyal, Ankit K @ 2024-06-10 4:46 UTC (permalink / raw)
To: Mitul Golani, intel-gfx
On 6/10/2024 8:18 AM, Mitul Golani wrote:
> Move VRR related register definitions to a separate file called
> intel_vrr_regs.h.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 1 +
> drivers/gpu/drm/i915/display/intel_vrr_regs.h | 111 ++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 100 ----------------
> 3 files changed, 112 insertions(+), 100 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_vrr_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 5f3657aa8313..871e6e6a184a 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -9,6 +9,7 @@
> #include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_vrr.h"
> +#include "intel_vrr_regs.h"
> #include "intel_dp.h"
>
> bool intel_vrr_is_capable(struct intel_connector *connector)
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> new file mode 100644
> index 000000000000..c3237d5c38df
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> @@ -0,0 +1,111 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
> +
> +#ifndef __INTEL_VRR_REGS_H__
> +#define __INTEL_VRR_REGS_H__
> +
> +#include "intel_display_reg_defs.h"
> +
> +/* VRR registers */
> +#define _TRANS_VRR_CTL_A 0x60420
> +#define _TRANS_VRR_CTL_B 0x61420
> +#define _TRANS_VRR_CTL_C 0x62420
> +#define _TRANS_VRR_CTL_D 0x63420
> +#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
> +#define VRR_CTL_VRR_ENABLE REG_BIT(31)
> +#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
> +#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
> +#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
> +#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
> +#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
> +#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
> +#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
The above 2 lines seem to have some change in space, as per git show
--color-moved.
But other than that, patch looks good to me.
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> +
> +#define _TRANS_VRR_VMAX_A 0x60424
> +#define _TRANS_VRR_VMAX_B 0x61424
> +#define _TRANS_VRR_VMAX_C 0x62424
> +#define _TRANS_VRR_VMAX_D 0x63424
> +#define TRANS_VRR_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A)
> +#define VRR_VMAX_MASK REG_GENMASK(19, 0)
> +
> +#define _TRANS_VRR_VMIN_A 0x60434
> +#define _TRANS_VRR_VMIN_B 0x61434
> +#define _TRANS_VRR_VMIN_C 0x62434
> +#define _TRANS_VRR_VMIN_D 0x63434
> +#define TRANS_VRR_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A)
> +#define VRR_VMIN_MASK REG_GENMASK(15, 0)
> +
> +#define _TRANS_VRR_VMAXSHIFT_A 0x60428
> +#define _TRANS_VRR_VMAXSHIFT_B 0x61428
> +#define _TRANS_VRR_VMAXSHIFT_C 0x62428
> +#define _TRANS_VRR_VMAXSHIFT_D 0x63428
> +#define TRANS_VRR_VMAXSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
> + _TRANS_VRR_VMAXSHIFT_A)
> +#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
> +#define VRR_VMAXSHIFT_DEC REG_BIT(16)
> +#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
> +
> +#define _TRANS_VRR_STATUS_A 0x6042c
> +#define _TRANS_VRR_STATUS_B 0x6142c
> +#define _TRANS_VRR_STATUS_C 0x6242c
> +#define _TRANS_VRR_STATUS_D 0x6342c
> +#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
> +#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
> +#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
> +#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
> +#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
> +#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
> +#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
> +#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
> +#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
> +#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
> +#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
> +#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
> +#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
> +#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
> +#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
> +
> +#define _TRANS_VRR_VTOTAL_PREV_A 0x60480
> +#define _TRANS_VRR_VTOTAL_PREV_B 0x61480
> +#define _TRANS_VRR_VTOTAL_PREV_C 0x62480
> +#define _TRANS_VRR_VTOTAL_PREV_D 0x63480
> +#define TRANS_VRR_VTOTAL_PREV(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
> + _TRANS_VRR_VTOTAL_PREV_A)
> +#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
> +#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
> +#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
> +#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
> +
> +#define _TRANS_VRR_FLIPLINE_A 0x60438
> +#define _TRANS_VRR_FLIPLINE_B 0x61438
> +#define _TRANS_VRR_FLIPLINE_C 0x62438
> +#define _TRANS_VRR_FLIPLINE_D 0x63438
> +#define TRANS_VRR_FLIPLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
> + _TRANS_VRR_FLIPLINE_A)
> +#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
> +
> +#define _TRANS_VRR_STATUS2_A 0x6043c
> +#define _TRANS_VRR_STATUS2_B 0x6143c
> +#define _TRANS_VRR_STATUS2_C 0x6243c
> +#define _TRANS_VRR_STATUS2_D 0x6343c
> +#define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A)
> +#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
> +
> +#define _TRANS_PUSH_A 0x60a70
> +#define _TRANS_PUSH_B 0x61a70
> +#define _TRANS_PUSH_C 0x62a70
> +#define _TRANS_PUSH_D 0x63a70
> +#define TRANS_PUSH(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A)
> +#define TRANS_PUSH_EN REG_BIT(31)
> +#define TRANS_PUSH_SEND REG_BIT(30)
> +
> +#define _TRANS_VRR_VSYNC_A 0x60078
> +#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A)
> +#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
> +#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end))
> +#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
> +#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
> +
> +#endif /* __INTEL_VRR_REGS__ */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a10591424338..df58cf38e144 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1147,106 +1147,6 @@
> #define PIPESRC(dev_priv, pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
> #define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
>
> -/* VRR registers */
> -#define _TRANS_VRR_CTL_A 0x60420
> -#define _TRANS_VRR_CTL_B 0x61420
> -#define _TRANS_VRR_CTL_C 0x62420
> -#define _TRANS_VRR_CTL_D 0x63420
> -#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
> -#define VRR_CTL_VRR_ENABLE REG_BIT(31)
> -#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
> -#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
> -#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
> -#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
> -#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
> -#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
> -#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
> -
> -#define _TRANS_VRR_VMAX_A 0x60424
> -#define _TRANS_VRR_VMAX_B 0x61424
> -#define _TRANS_VRR_VMAX_C 0x62424
> -#define _TRANS_VRR_VMAX_D 0x63424
> -#define TRANS_VRR_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A)
> -#define VRR_VMAX_MASK REG_GENMASK(19, 0)
> -
> -#define _TRANS_VRR_VMIN_A 0x60434
> -#define _TRANS_VRR_VMIN_B 0x61434
> -#define _TRANS_VRR_VMIN_C 0x62434
> -#define _TRANS_VRR_VMIN_D 0x63434
> -#define TRANS_VRR_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A)
> -#define VRR_VMIN_MASK REG_GENMASK(15, 0)
> -
> -#define _TRANS_VRR_VMAXSHIFT_A 0x60428
> -#define _TRANS_VRR_VMAXSHIFT_B 0x61428
> -#define _TRANS_VRR_VMAXSHIFT_C 0x62428
> -#define _TRANS_VRR_VMAXSHIFT_D 0x63428
> -#define TRANS_VRR_VMAXSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
> - _TRANS_VRR_VMAXSHIFT_A)
> -#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
> -#define VRR_VMAXSHIFT_DEC REG_BIT(16)
> -#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
> -
> -#define _TRANS_VRR_STATUS_A 0x6042c
> -#define _TRANS_VRR_STATUS_B 0x6142c
> -#define _TRANS_VRR_STATUS_C 0x6242c
> -#define _TRANS_VRR_STATUS_D 0x6342c
> -#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
> -#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
> -#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
> -#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
> -#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
> -#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
> -#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
> -#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
> -#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
> -#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
> -#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
> -#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
> -#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
> -#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
> -#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
> -
> -#define _TRANS_VRR_VTOTAL_PREV_A 0x60480
> -#define _TRANS_VRR_VTOTAL_PREV_B 0x61480
> -#define _TRANS_VRR_VTOTAL_PREV_C 0x62480
> -#define _TRANS_VRR_VTOTAL_PREV_D 0x63480
> -#define TRANS_VRR_VTOTAL_PREV(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
> - _TRANS_VRR_VTOTAL_PREV_A)
> -#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
> -#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
> -#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
> -#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
> -
> -#define _TRANS_VRR_FLIPLINE_A 0x60438
> -#define _TRANS_VRR_FLIPLINE_B 0x61438
> -#define _TRANS_VRR_FLIPLINE_C 0x62438
> -#define _TRANS_VRR_FLIPLINE_D 0x63438
> -#define TRANS_VRR_FLIPLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
> - _TRANS_VRR_FLIPLINE_A)
> -#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
> -
> -#define _TRANS_VRR_STATUS2_A 0x6043c
> -#define _TRANS_VRR_STATUS2_B 0x6143c
> -#define _TRANS_VRR_STATUS2_C 0x6243c
> -#define _TRANS_VRR_STATUS2_D 0x6343c
> -#define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A)
> -#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
> -
> -#define _TRANS_PUSH_A 0x60a70
> -#define _TRANS_PUSH_B 0x61a70
> -#define _TRANS_PUSH_C 0x62a70
> -#define _TRANS_PUSH_D 0x63a70
> -#define TRANS_PUSH(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A)
> -#define TRANS_PUSH_EN REG_BIT(31)
> -#define TRANS_PUSH_SEND REG_BIT(30)
> -
> -#define _TRANS_VRR_VSYNC_A 0x60078
> -#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A)
> -#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
> -#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end))
> -#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
> -#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
> -
> /* VGA port control */
> #define ADPA _MMIO(0x61100)
> #define PCH_ADPA _MMIO(0xe1100)
^ permalink raw reply [flat|nested] 17+ messages in thread
* ✗ Fi.CI.IGT: failure for Implement CMRR Support (rev16)
2024-06-10 2:48 [PATCH v15 0/9] Implement CMRR Support Mitul Golani
` (11 preceding siblings ...)
2024-06-10 3:31 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2024-06-10 4:53 ` Patchwork
2024-06-11 4:34 ` [PATCH v15 0/9] Implement CMRR Support Kandpal, Suraj
13 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2024-06-10 4:53 UTC (permalink / raw)
To: Mitul Golani; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 91987 bytes --]
== Series Details ==
Series: Implement CMRR Support (rev16)
URL : https://patchwork.freedesktop.org/series/126443/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14904_full -> Patchwork_126443v16_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_126443v16_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_126443v16_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 10)
------------------------------
Additional (1): shard-snb-0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_126443v16_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip@dpms-off-confusion@c-hdmi-a1:
- shard-glk: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-glk9/igt@kms_flip@dpms-off-confusion@c-hdmi-a1.html
* igt@kms_flip@dpms-off-confusion@c-hdmi-a4:
- shard-dg1: [PASS][2] -> [INCOMPLETE][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg1-16/igt@kms_flip@dpms-off-confusion@c-hdmi-a4.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-17/igt@kms_flip@dpms-off-confusion@c-hdmi-a4.html
* igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [INCOMPLETE][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-5/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-pixel-format@pipe-a-hdmi-a-3.html
New tests
---------
New tests have been introduced between CI_DRM_14904_full and Patchwork_126443v16_full:
### New IGT tests (2) ###
* igt@kms_tiled_display@basic-test-pattern:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_126443v16_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@crc32:
- shard-rkl: NOTRUN -> [SKIP][5] ([i915#6230])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-3/igt@api_intel_bb@crc32.html
* igt@debugfs_test@basic-hwmon:
- shard-tglu: NOTRUN -> [SKIP][6] ([i915#9318])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-tglu-6/igt@debugfs_test@basic-hwmon.html
* igt@device_reset@unbind-cold-reset-rebind:
- shard-rkl: NOTRUN -> [SKIP][7] ([i915#11078])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-1/igt@device_reset@unbind-cold-reset-rebind.html
* igt@drm_fdinfo@idle@rcs0:
- shard-rkl: [PASS][8] -> [FAIL][9] ([i915#7742]) +1 other test fail
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-rkl-5/igt@drm_fdinfo@idle@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-4/igt@drm_fdinfo@idle@rcs0.html
* igt@drm_fdinfo@isolation@vcs1:
- shard-dg2: NOTRUN -> [SKIP][10] ([i915#8414]) +6 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@drm_fdinfo@isolation@vcs1.html
* igt@drm_fdinfo@virtual-busy-idle-all:
- shard-dg1: NOTRUN -> [SKIP][11] ([i915#8414])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-18/igt@drm_fdinfo@virtual-busy-idle-all.html
* igt@drm_fdinfo@virtual-idle:
- shard-rkl: NOTRUN -> [FAIL][12] ([i915#7742])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-1/igt@drm_fdinfo@virtual-idle.html
* igt@gem_basic@multigpu-create-close:
- shard-rkl: NOTRUN -> [SKIP][13] ([i915#7697])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-1/igt@gem_basic@multigpu-create-close.html
- shard-dg1: NOTRUN -> [SKIP][14] ([i915#7697])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-15/igt@gem_basic@multigpu-create-close.html
* igt@gem_busy@semaphore:
- shard-dg1: NOTRUN -> [SKIP][15] ([i915#3936])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@gem_busy@semaphore.html
* igt@gem_ccs@block-copy-compressed:
- shard-dg1: NOTRUN -> [SKIP][16] ([i915#3555] / [i915#9323])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@gem_ccs@block-copy-compressed.html
* igt@gem_ccs@ctrl-surf-copy:
- shard-rkl: NOTRUN -> [SKIP][17] ([i915#3555] / [i915#9323])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-5/igt@gem_ccs@ctrl-surf-copy.html
* igt@gem_ccs@suspend-resume:
- shard-rkl: NOTRUN -> [SKIP][18] ([i915#9323])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-1/igt@gem_ccs@suspend-resume.html
* igt@gem_close_race@multigpu-basic-process:
- shard-dg2: NOTRUN -> [SKIP][19] ([i915#7697])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-mtlp: NOTRUN -> [SKIP][20] ([i915#6335])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_create@create-ext-cpu-access-sanity-check:
- shard-rkl: NOTRUN -> [SKIP][21] ([i915#6335])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-1/igt@gem_create@create-ext-cpu-access-sanity-check.html
* igt@gem_create@create-ext-set-pat:
- shard-dg1: NOTRUN -> [SKIP][22] ([i915#8562])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-dg1: NOTRUN -> [FAIL][23] ([i915#10086] / [i915#11279]) +3 other tests fail
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_ctx_isolation@preservation-s3@vcs1:
- shard-dg1: NOTRUN -> [FAIL][24] ([i915#10086])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@gem_ctx_isolation@preservation-s3@vcs1.html
* igt@gem_ctx_persistence@hang:
- shard-mtlp: NOTRUN -> [SKIP][25] ([i915#8555])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@gem_ctx_persistence@hang.html
* igt@gem_ctx_persistence@heartbeat-close:
- shard-dg1: NOTRUN -> [SKIP][26] ([i915#8555]) +1 other test skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-15/igt@gem_ctx_persistence@heartbeat-close.html
* igt@gem_ctx_persistence@heartbeat-many:
- shard-dg2: NOTRUN -> [SKIP][27] ([i915#8555])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-5/igt@gem_ctx_persistence@heartbeat-many.html
* igt@gem_ctx_persistence@saturated-hostile-nopreempt@vcs0:
- shard-mtlp: NOTRUN -> [SKIP][28] ([i915#5882]) +5 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@gem_ctx_persistence@saturated-hostile-nopreempt@vcs0.html
* igt@gem_ctx_sseu@engines:
- shard-rkl: NOTRUN -> [SKIP][29] ([i915#280])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-3/igt@gem_ctx_sseu@engines.html
* igt@gem_eio@hibernate:
- shard-rkl: NOTRUN -> [ABORT][30] ([i915#7975] / [i915#8213])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-5/igt@gem_eio@hibernate.html
* igt@gem_eio@in-flight-suspend:
- shard-dg2: NOTRUN -> [FAIL][31] ([i915#11269])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@gem_eio@in-flight-suspend.html
* igt@gem_eio@kms:
- shard-dg1: NOTRUN -> [FAIL][32] ([i915#5784])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@gem_eio@kms.html
* igt@gem_exec_balancer@bonded-semaphore:
- shard-mtlp: NOTRUN -> [SKIP][33] ([i915#4812])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-2/igt@gem_exec_balancer@bonded-semaphore.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-rkl: NOTRUN -> [SKIP][34] ([i915#4525]) +3 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-5/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_capture@capture-invisible@smem0:
- shard-rkl: NOTRUN -> [SKIP][35] ([i915#6334])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-3/igt@gem_exec_capture@capture-invisible@smem0.html
* igt@gem_exec_endless@dispatch@bcs0:
- shard-dg2: [PASS][36] -> [TIMEOUT][37] ([i915#3778] / [i915#7016])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg2-2/igt@gem_exec_endless@dispatch@bcs0.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-6/igt@gem_exec_endless@dispatch@bcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: NOTRUN -> [FAIL][38] ([i915#2842])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-glk1/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-tglu: NOTRUN -> [FAIL][39] ([i915#2842])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-tglu-6/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace:
- shard-dg1: NOTRUN -> [SKIP][40] ([i915#3539]) +1 other test skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-15/igt@gem_exec_fair@basic-pace.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-rkl: NOTRUN -> [FAIL][41] ([i915#2842])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-1/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-sync:
- shard-mtlp: NOTRUN -> [SKIP][42] ([i915#4473] / [i915#4771])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-2/igt@gem_exec_fair@basic-sync.html
* igt@gem_exec_flush@basic-batch-kernel-default-uc:
- shard-dg2: NOTRUN -> [SKIP][43] ([i915#3539] / [i915#4852])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@gem_exec_flush@basic-batch-kernel-default-uc.html
* igt@gem_exec_flush@basic-uc-rw-default:
- shard-dg1: NOTRUN -> [SKIP][44] ([i915#3539] / [i915#4852]) +4 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-15/igt@gem_exec_flush@basic-uc-rw-default.html
* igt@gem_exec_reloc@basic-cpu-wc-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][45] ([i915#3281]) +4 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@gem_exec_reloc@basic-cpu-wc-noreloc.html
* igt@gem_exec_reloc@basic-wc-read-noreloc:
- shard-rkl: NOTRUN -> [SKIP][46] ([i915#3281]) +7 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-5/igt@gem_exec_reloc@basic-wc-read-noreloc.html
* igt@gem_exec_reloc@basic-write-gtt-active:
- shard-dg1: NOTRUN -> [SKIP][47] ([i915#3281]) +3 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@gem_exec_reloc@basic-write-gtt-active.html
* igt@gem_exec_reloc@basic-write-wc-noreloc:
- shard-dg2: NOTRUN -> [SKIP][48] ([i915#3281]) +2 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@gem_exec_reloc@basic-write-wc-noreloc.html
* igt@gem_exec_schedule@reorder-wide:
- shard-mtlp: NOTRUN -> [SKIP][49] ([i915#4537] / [i915#4812])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@gem_exec_schedule@reorder-wide.html
* igt@gem_fence_thrash@bo-write-verify-threaded-none:
- shard-dg1: NOTRUN -> [SKIP][50] ([i915#4860]) +3 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@gem_fence_thrash@bo-write-verify-threaded-none.html
* igt@gem_huc_copy@huc-copy:
- shard-rkl: NOTRUN -> [SKIP][51] ([i915#2190])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-5/igt@gem_huc_copy@huc-copy.html
- shard-glk: NOTRUN -> [SKIP][52] ([i915#2190])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-glk1/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@heavy-random@lmem0:
- shard-dg1: [PASS][53] -> [FAIL][54] ([i915#10378])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg1-14/igt@gem_lmem_swapping@heavy-random@lmem0.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-15/igt@gem_lmem_swapping@heavy-random@lmem0.html
* igt@gem_lmem_swapping@heavy-verify-multi@lmem0:
- shard-dg1: NOTRUN -> [FAIL][55] ([i915#10378])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-15/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html
* igt@gem_lmem_swapping@random-engines:
- shard-mtlp: NOTRUN -> [SKIP][56] ([i915#4613])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@verify:
- shard-rkl: NOTRUN -> [SKIP][57] ([i915#4613]) +3 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-3/igt@gem_lmem_swapping@verify.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-tglu: NOTRUN -> [SKIP][58] ([i915#4613])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-tglu-6/igt@gem_lmem_swapping@verify-ccs.html
* igt@gem_lmem_swapping@verify-random-ccs:
- shard-glk: NOTRUN -> [SKIP][59] ([i915#4613]) +1 other test skip
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-glk1/igt@gem_lmem_swapping@verify-random-ccs.html
* igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
- shard-mtlp: NOTRUN -> [SKIP][60] ([i915#4077]) +5 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy-odd:
- shard-dg1: NOTRUN -> [SKIP][61] ([i915#4077]) +8 other tests skip
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-18/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html
* igt@gem_mmap_gtt@cpuset-medium-copy-odd:
- shard-dg2: NOTRUN -> [SKIP][62] ([i915#4077]) +2 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@gem_mmap_gtt@cpuset-medium-copy-odd.html
* igt@gem_mmap_wc@read-write:
- shard-mtlp: NOTRUN -> [SKIP][63] ([i915#4083]) +1 other test skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-3/igt@gem_mmap_wc@read-write.html
* igt@gem_mmap_wc@write-wc-read-gtt:
- shard-dg1: NOTRUN -> [SKIP][64] ([i915#4083]) +2 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@gem_mmap_wc@write-wc-read-gtt.html
* igt@gem_partial_pwrite_pread@write:
- shard-dg2: NOTRUN -> [SKIP][65] ([i915#3282]) +2 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@gem_partial_pwrite_pread@write.html
* igt@gem_pwrite_snooped:
- shard-rkl: NOTRUN -> [SKIP][66] ([i915#3282]) +4 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-3/igt@gem_pwrite_snooped.html
* igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
- shard-rkl: NOTRUN -> [SKIP][67] ([i915#4270]) +1 other test skip
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-1/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
* igt@gem_pxp@reject-modify-context-protection-on:
- shard-dg2: NOTRUN -> [SKIP][68] ([i915#4270])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@gem_pxp@reject-modify-context-protection-on.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-tglu: NOTRUN -> [SKIP][69] ([i915#4270])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-tglu-6/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_pxp@verify-pxp-stale-buf-execution:
- shard-dg1: NOTRUN -> [SKIP][70] ([i915#4270])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@gem_pxp@verify-pxp-stale-buf-execution.html
* igt@gem_pxp@verify-pxp-stale-buf-optout-execution:
- shard-mtlp: NOTRUN -> [SKIP][71] ([i915#4270]) +1 other test skip
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html
* igt@gem_readwrite@beyond-eob:
- shard-dg1: NOTRUN -> [SKIP][72] ([i915#3282]) +1 other test skip
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-18/igt@gem_readwrite@beyond-eob.html
* igt@gem_readwrite@read-write:
- shard-mtlp: NOTRUN -> [SKIP][73] ([i915#3282]) +2 other tests skip
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@gem_readwrite@read-write.html
* igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs:
- shard-mtlp: NOTRUN -> [SKIP][74] ([i915#8428]) +1 other test skip
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs.html
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled:
- shard-dg2: NOTRUN -> [SKIP][75] ([i915#5190] / [i915#8428]) +1 other test skip
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled.html
* igt@gem_softpin@evict-snoop:
- shard-mtlp: NOTRUN -> [SKIP][76] ([i915#4885])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@gem_softpin@evict-snoop.html
* igt@gem_tiled_pread_pwrite:
- shard-dg1: NOTRUN -> [SKIP][77] ([i915#4079]) +1 other test skip
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@gem_tiled_pread_pwrite.html
* igt@gem_userptr_blits@coherency-sync:
- shard-rkl: NOTRUN -> [SKIP][78] ([i915#3297])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-1/igt@gem_userptr_blits@coherency-sync.html
* igt@gem_userptr_blits@unsync-unmap:
- shard-mtlp: NOTRUN -> [SKIP][79] ([i915#3297])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@gem_userptr_blits@unsync-unmap.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-dg2: NOTRUN -> [SKIP][80] ([i915#3297])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-dg1: NOTRUN -> [FAIL][81] ([i915#10177] / [i915#11279])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-18/igt@gem_workarounds@suspend-resume-fd.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-tglu: NOTRUN -> [SKIP][82] ([i915#2527] / [i915#2856])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-tglu-6/igt@gen9_exec_parse@batch-invalid-length.html
* igt@gen9_exec_parse@bb-chained:
- shard-rkl: NOTRUN -> [SKIP][83] ([i915#2527]) +3 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-1/igt@gen9_exec_parse@bb-chained.html
* igt@gen9_exec_parse@bb-secure:
- shard-dg1: NOTRUN -> [SKIP][84] ([i915#2527]) +2 other tests skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@gen9_exec_parse@bb-secure.html
- shard-mtlp: NOTRUN -> [SKIP][85] ([i915#2856])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-3/igt@gen9_exec_parse@bb-secure.html
* igt@gen9_exec_parse@cmd-crossing-page:
- shard-dg2: NOTRUN -> [SKIP][86] ([i915#2856]) +1 other test skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@gen9_exec_parse@cmd-crossing-page.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg1: NOTRUN -> [INCOMPLETE][87] ([i915#1982] / [i915#9820] / [i915#9849])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-15/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_freq_api@freq-basic-api:
- shard-rkl: NOTRUN -> [SKIP][88] ([i915#8399])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-1/igt@i915_pm_freq_api@freq-basic-api.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0:
- shard-dg1: [PASS][89] -> [FAIL][90] ([i915#3591])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-mtlp: NOTRUN -> [SKIP][91] +5 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@i915_pm_rpm@system-suspend:
- shard-dg1: NOTRUN -> [FAIL][92] ([i915#11279]) +1 other test fail
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@i915_pm_rpm@system-suspend.html
* igt@i915_pm_rps@basic-api:
- shard-dg1: NOTRUN -> [SKIP][93] ([i915#6621])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-18/igt@i915_pm_rps@basic-api.html
* igt@i915_power@sanity:
- shard-rkl: NOTRUN -> [SKIP][94] ([i915#7984])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-1/igt@i915_power@sanity.html
* igt@i915_suspend@debugfs-reader:
- shard-dg1: NOTRUN -> [FAIL][95] ([i915#10031] / [i915#11279]) +2 other tests fail
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-18/igt@i915_suspend@debugfs-reader.html
* igt@i915_suspend@sysfs-reader:
- shard-dg2: NOTRUN -> [FAIL][96] ([i915#10031] / [i915#11279])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@i915_suspend@sysfs-reader.html
* igt@intel_hwmon@hwmon-read:
- shard-mtlp: NOTRUN -> [SKIP][97] ([i915#7707])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@intel_hwmon@hwmon-read.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- shard-dg2: NOTRUN -> [SKIP][98] ([i915#4212])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
- shard-tglu: NOTRUN -> [SKIP][99] ([i915#3826])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-tglu-6/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-4-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][100] ([i915#8709]) +11 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-10/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-4-mc-ccs.html
* igt@kms_async_flips@test-cursor:
- shard-mtlp: NOTRUN -> [SKIP][101] ([i915#10333])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-2/igt@kms_async_flips@test-cursor.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-rkl: NOTRUN -> [SKIP][102] ([i915#9531])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-3/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-dg1: NOTRUN -> [SKIP][103] ([i915#1769] / [i915#3555])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-180:
- shard-tglu: NOTRUN -> [SKIP][104] ([i915#5286])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-tglu-6/igt@kms_big_fb@4-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
- shard-dg1: NOTRUN -> [SKIP][105] ([i915#5286])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-rkl: NOTRUN -> [SKIP][106] ([i915#5286]) +4 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-dg1: NOTRUN -> [SKIP][107] ([i915#4538] / [i915#5286]) +4 other tests skip
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-15/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][108] +5 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][109] ([i915#3638]) +1 other test skip
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-3/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-90:
- shard-dg1: NOTRUN -> [SKIP][110] ([i915#3638]) +3 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-18/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-addfb:
- shard-dg2: NOTRUN -> [SKIP][111] ([i915#5190])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@kms_big_fb@y-tiled-addfb.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180:
- shard-dg1: NOTRUN -> [SKIP][112] ([i915#4538]) +5 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
- shard-dg2: NOTRUN -> [SKIP][113] ([i915#4538] / [i915#5190]) +2 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_joiner@basic:
- shard-dg2: NOTRUN -> [SKIP][114] ([i915#10656]) +1 other test skip
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-5/igt@kms_big_joiner@basic.html
- shard-tglu: NOTRUN -> [SKIP][115] ([i915#10656]) +1 other test skip
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-tglu-6/igt@kms_big_joiner@basic.html
* igt@kms_big_joiner@basic-force-joiner:
- shard-dg1: NOTRUN -> [SKIP][116] ([i915#10656])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@kms_big_joiner@basic-force-joiner.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][117] ([i915#10307] / [i915#10434] / [i915#6095]) +3 other tests skip
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1.html
* igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][118] ([i915#10307] / [i915#6095]) +211 other tests skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-7/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-3.html
* igt@kms_ccs@ccs-on-another-bo-yf-tiled-ccs@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][119] ([i915#6095]) +63 other tests skip
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-15/igt@kms_ccs@ccs-on-another-bo-yf-tiled-ccs@pipe-c-hdmi-a-4.html
* igt@kms_ccs@crc-primary-basic-4-tiled-xe2-ccs:
- shard-mtlp: NOTRUN -> [SKIP][120] ([i915#10278])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@kms_ccs@crc-primary-basic-4-tiled-xe2-ccs.html
* igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][121] ([i915#6095]) +19 other tests skip
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-2/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc@pipe-d-edp-1.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][122] ([i915#6095]) +85 other tests skip
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-3/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][123] ([i915#6095]) +11 other tests skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-tglu-6/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@random-ccs-data-y-tiled-ccs:
- shard-snb: NOTRUN -> [SKIP][124] +26 other tests skip
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-snb4/igt@kms_ccs@random-ccs-data-y-tiled-ccs.html
* igt@kms_cdclk@mode-transition:
- shard-rkl: NOTRUN -> [SKIP][125] ([i915#3742])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-5/igt@kms_cdclk@mode-transition.html
* igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][126] ([i915#4087]) +3 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-6/igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3.html
* igt@kms_chamelium_audio@dp-audio:
- shard-tglu: NOTRUN -> [SKIP][127] ([i915#7828]) +2 other tests skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-tglu-6/igt@kms_chamelium_audio@dp-audio.html
* igt@kms_chamelium_frames@dp-crc-fast:
- shard-dg2: NOTRUN -> [SKIP][128] ([i915#7828]) +2 other tests skip
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@kms_chamelium_frames@dp-crc-fast.html
* igt@kms_chamelium_hpd@dp-hpd:
- shard-rkl: NOTRUN -> [SKIP][129] ([i915#7828]) +7 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-5/igt@kms_chamelium_hpd@dp-hpd.html
* igt@kms_chamelium_hpd@dp-hpd-after-suspend:
- shard-dg1: NOTRUN -> [SKIP][130] ([i915#7828]) +4 other tests skip
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-15/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html
* igt@kms_chamelium_hpd@hdmi-hpd-fast:
- shard-mtlp: NOTRUN -> [SKIP][131] ([i915#7828]) +2 other tests skip
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@kms_chamelium_hpd@hdmi-hpd-fast.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-rkl: NOTRUN -> [SKIP][132] ([i915#3116]) +2 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-3/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@legacy:
- shard-dg2: NOTRUN -> [SKIP][133] ([i915#7118] / [i915#9424])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@lic-type-0:
- shard-dg1: NOTRUN -> [SKIP][134] ([i915#9424])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-18/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@mei-interface:
- shard-tglu: NOTRUN -> [SKIP][135] ([i915#6944] / [i915#9424])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-tglu-6/igt@kms_content_protection@mei-interface.html
* igt@kms_cursor_crc@cursor-offscreen-32x10:
- shard-mtlp: NOTRUN -> [SKIP][136] ([i915#3555] / [i915#8814])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-2/igt@kms_cursor_crc@cursor-offscreen-32x10.html
* igt@kms_cursor_crc@cursor-offscreen-512x512:
- shard-rkl: NOTRUN -> [SKIP][137] ([i915#3359])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-1/igt@kms_cursor_crc@cursor-offscreen-512x512.html
* igt@kms_cursor_crc@cursor-offscreen-64x21:
- shard-mtlp: NOTRUN -> [SKIP][138] ([i915#8814])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@kms_cursor_crc@cursor-offscreen-64x21.html
* igt@kms_cursor_crc@cursor-onscreen-32x10:
- shard-dg2: NOTRUN -> [SKIP][139] ([i915#3555]) +2 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@kms_cursor_crc@cursor-onscreen-32x10.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-mtlp: NOTRUN -> [SKIP][140] ([i915#3359])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-tglu: NOTRUN -> [SKIP][141] ([i915#3359])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-tglu-6/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_crc@cursor-sliding-32x32:
- shard-tglu: NOTRUN -> [SKIP][142] ([i915#3555])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-tglu-6/igt@kms_cursor_crc@cursor-sliding-32x32.html
* igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1:
- shard-dg2: NOTRUN -> [FAIL][143] ([i915#11279] / [i915#11298])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1.html
* igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [FAIL][144] ([i915#11298])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-1.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
- shard-mtlp: NOTRUN -> [SKIP][145] ([i915#9809])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-3/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
- shard-dg2: NOTRUN -> [SKIP][146] ([i915#5354]) +10 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
- shard-tglu: NOTRUN -> [SKIP][147] ([i915#4103])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-tglu-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
- shard-dg2: NOTRUN -> [SKIP][148] ([i915#4103] / [i915#4213]) +1 other test skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][149] ([i915#9723])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-6/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-2.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][150] ([i915#9227])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-6/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-3.html
* igt@kms_display_modes@mst-extended-mode-negative:
- shard-rkl: NOTRUN -> [SKIP][151] ([i915#8588])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-1/igt@kms_display_modes@mst-extended-mode-negative.html
* igt@kms_dp_aux_dev:
- shard-rkl: NOTRUN -> [SKIP][152] ([i915#1257])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-5/igt@kms_dp_aux_dev.html
* igt@kms_dsc@dsc-with-bpc:
- shard-dg1: NOTRUN -> [SKIP][153] ([i915#3555] / [i915#3840])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-rkl: NOTRUN -> [SKIP][154] ([i915#3555] / [i915#3840])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-1/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_feature_discovery@chamelium:
- shard-tglu: NOTRUN -> [SKIP][155] ([i915#2065] / [i915#4854])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-tglu-6/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@display-4x:
- shard-rkl: NOTRUN -> [SKIP][156] ([i915#1839]) +1 other test skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-1/igt@kms_feature_discovery@display-4x.html
- shard-mtlp: NOTRUN -> [SKIP][157] ([i915#1839])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-2/igt@kms_feature_discovery@display-4x.html
* igt@kms_feature_discovery@dp-mst:
- shard-mtlp: NOTRUN -> [SKIP][158] ([i915#9337])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@kms_feature_discovery@dp-mst.html
* igt@kms_feature_discovery@psr2:
- shard-dg2: NOTRUN -> [SKIP][159] ([i915#658])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@kms_feature_discovery@psr2.html
* igt@kms_fence_pin_leak:
- shard-dg1: NOTRUN -> [SKIP][160] ([i915#4881])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@kms_fence_pin_leak.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-mtlp: NOTRUN -> [SKIP][161] ([i915#8381])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-2/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@2x-nonexisting-fb-interruptible:
- shard-tglu: NOTRUN -> [SKIP][162] ([i915#3637]) +1 other test skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-tglu-6/igt@kms_flip@2x-nonexisting-fb-interruptible.html
* igt@kms_flip@2x-plain-flip:
- shard-dg1: NOTRUN -> [SKIP][163] ([i915#9934]) +4 other tests skip
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][164] ([i915#3637]) +1 other test skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip@flip-vs-fences:
- shard-dg1: NOTRUN -> [SKIP][165] ([i915#8381])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-18/igt@kms_flip@flip-vs-fences.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a4:
- shard-dg1: NOTRUN -> [FAIL][166] ([i915#11275] / [i915#11279]) +1 other test fail
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a4.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1:
- shard-dg2: NOTRUN -> [FAIL][167] ([i915#11275]) +1 other test fail
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1:
- shard-dg2: NOTRUN -> [FAIL][168] ([i915#10545] / [i915#11279]) +1 other test fail
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a4:
- shard-dg1: NOTRUN -> [FAIL][169] ([i915#10545] / [i915#11279])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a4.html
* igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a4:
- shard-dg1: NOTRUN -> [FAIL][170] ([i915#10545])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a4.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][171] ([i915#2587] / [i915#2672]) +2 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][172] ([i915#2672])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][173] ([i915#2672]) +1 other test skip
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][174] ([i915#2672]) +2 other tests skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff:
- shard-mtlp: NOTRUN -> [SKIP][175] ([i915#1825]) +9 other tests skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
- shard-dg1: NOTRUN -> [SKIP][176] +34 other tests skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][177] +42 other tests skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][178] ([i915#8708]) +4 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
- shard-rkl: NOTRUN -> [SKIP][179] ([i915#1825]) +40 other tests skip
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-fullscreen:
- shard-tglu: NOTRUN -> [SKIP][180] +20 other tests skip
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-tglu-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-rkl: NOTRUN -> [SKIP][181] ([i915#5439])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
- shard-dg1: NOTRUN -> [SKIP][182] ([i915#3458]) +13 other tests skip
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-18/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][183] ([i915#8708]) +10 other tests skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render:
- shard-rkl: NOTRUN -> [SKIP][184] ([i915#3023]) +25 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary:
- shard-dg2: NOTRUN -> [SKIP][185] ([i915#3458]) +7 other tests skip
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-5/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][186] ([i915#8708]) +6 other tests skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html
* igt@kms_hdmi_inject@inject-audio:
- shard-tglu: NOTRUN -> [SKIP][187] ([i915#433])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-tglu-6/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-dg2: NOTRUN -> [SKIP][188] ([i915#3555] / [i915#8228])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-3/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-rkl: NOTRUN -> [SKIP][189] ([i915#3555] / [i915#8228])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-5/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_hdr@static-swap:
- shard-dg1: NOTRUN -> [SKIP][190] ([i915#3555] / [i915#8228])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@kms_hdr@static-swap.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-dg2: NOTRUN -> [SKIP][191] ([i915#4816])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_panel_fitting@legacy:
- shard-rkl: NOTRUN -> [SKIP][192] ([i915#6301])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-1/igt@kms_panel_fitting@legacy.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [FAIL][193] ([i915#11274] / [i915#11279]) +3 other tests fail
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-1.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a:
- shard-dg1: NOTRUN -> [FAIL][194] ([i915#11279] / [i915#11284])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-18/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a.html
* igt@kms_plane_multiple@tiling-yf:
- shard-rkl: NOTRUN -> [SKIP][195] ([i915#3555]) +7 other tests skip
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-3/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-3:
- shard-dg1: NOTRUN -> [FAIL][196] ([i915#8292])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-13/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-3.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-1:
- shard-glk: NOTRUN -> [SKIP][197] +75 other tests skip
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-glk1/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-b-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][198] ([i915#9423]) +7 other tests skip
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-3/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][199] ([i915#9423]) +7 other tests skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-4/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][200] ([i915#9423]) +7 other tests skip
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-hdmi-a-4.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][201] ([i915#5176] / [i915#9423]) +3 other tests skip
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-15/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-hdmi-a-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][202] ([i915#5235] / [i915#9423] / [i915#9728]) +3 other tests skip
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-3/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-d-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][203] ([i915#5235]) +3 other tests skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-3/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-dp-4:
- shard-dg2: NOTRUN -> [SKIP][204] ([i915#5235] / [i915#9423]) +23 other tests skip
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-11/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-dp-4.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-d-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][205] ([i915#5235]) +3 other tests skip
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-d-hdmi-a-4.html
* igt@kms_pm_backlight@bad-brightness:
- shard-rkl: NOTRUN -> [SKIP][206] ([i915#5354])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-5/igt@kms_pm_backlight@bad-brightness.html
* igt@kms_pm_backlight@basic-brightness:
- shard-dg1: NOTRUN -> [SKIP][207] ([i915#5354])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-rkl: NOTRUN -> [SKIP][208] ([i915#9685])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-1/igt@kms_pm_dc@dc3co-vpb-simulation.html
- shard-dg1: NOTRUN -> [SKIP][209] ([i915#9685])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-15/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_pm_dc@dc6-dpms:
- shard-dg1: NOTRUN -> [SKIP][210] ([i915#3361])
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-18/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_dc@dc6-psr:
- shard-dg2: NOTRUN -> [SKIP][211] ([i915#9685])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-tglu: NOTRUN -> [SKIP][212] ([i915#9519])
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-tglu-6/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@dpms-non-lpsp:
- shard-dg2: [PASS][213] -> [SKIP][214] ([i915#9519]) +1 other test skip
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg2-5/igt@kms_pm_rpm@dpms-non-lpsp.html
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@kms_pm_rpm@dpms-non-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-dg1: NOTRUN -> [SKIP][215] ([i915#9519]) +1 other test skip
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-rkl: NOTRUN -> [SKIP][216] ([i915#9519]) +2 other tests skip
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_prime@basic-crc-hybrid:
- shard-mtlp: NOTRUN -> [SKIP][217] ([i915#6524])
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-rkl: NOTRUN -> [SKIP][218] ([i915#9683])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-1/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-pr-dpms:
- shard-mtlp: NOTRUN -> [SKIP][219] ([i915#9688]) +3 other tests skip
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@kms_psr@fbc-pr-dpms.html
* igt@kms_psr@fbc-psr2-sprite-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][220] ([i915#1072] / [i915#9732]) +17 other tests skip
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-18/igt@kms_psr@fbc-psr2-sprite-mmap-gtt.html
* igt@kms_psr@psr-sprite-mmap-cpu:
- shard-tglu: NOTRUN -> [SKIP][221] ([i915#9732]) +4 other tests skip
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-tglu-6/igt@kms_psr@psr-sprite-mmap-cpu.html
* igt@kms_psr@psr2-primary-blt:
- shard-dg2: NOTRUN -> [SKIP][222] ([i915#1072] / [i915#9732]) +5 other tests skip
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@kms_psr@psr2-primary-blt.html
* igt@kms_psr@psr2-suspend:
- shard-rkl: NOTRUN -> [SKIP][223] ([i915#1072] / [i915#9732]) +20 other tests skip
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-3/igt@kms_psr@psr2-suspend.html
* igt@kms_rotation_crc@primary-rotation-90:
- shard-dg2: NOTRUN -> [SKIP][224] ([i915#4235])
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-5/igt@kms_rotation_crc@primary-rotation-90.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-dg1: NOTRUN -> [SKIP][225] ([i915#5289]) +1 other test skip
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_rotation_crc@sprite-rotation-270:
- shard-mtlp: NOTRUN -> [SKIP][226] ([i915#4235])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@kms_rotation_crc@sprite-rotation-270.html
* igt@kms_scaling_modes@scaling-mode-center:
- shard-dg1: NOTRUN -> [SKIP][227] ([i915#3555]) +5 other tests skip
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@kms_scaling_modes@scaling-mode-center.html
* igt@kms_scaling_modes@scaling-mode-none@pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][228] ([i915#5030]) +2 other tests skip
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-2/igt@kms_scaling_modes@scaling-mode-none@pipe-a-edp-1.html
* igt@kms_scaling_modes@scaling-mode-none@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][229] ([i915#5030] / [i915#9041])
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-2/igt@kms_scaling_modes@scaling-mode-none@pipe-d-edp-1.html
* igt@kms_setmode@basic@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [FAIL][230] ([i915#5465]) +1 other test fail
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-18/igt@kms_setmode@basic@pipe-a-hdmi-a-4.html
* igt@kms_vblank@query-forked-busy-hang@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [INCOMPLETE][231] ([i915#9508])
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-5/igt@kms_vblank@query-forked-busy-hang@pipe-a-hdmi-a-1.html
* igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-2:
- shard-dg2: NOTRUN -> [FAIL][232] ([i915#10305] / [i915#11279]) +1 other test fail
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-2/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-2.html
* igt@kms_vblank@ts-continuation-suspend@pipe-d-hdmi-a-4:
- shard-dg1: NOTRUN -> [FAIL][233] ([i915#10305] / [i915#11279]) +1 other test fail
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-17/igt@kms_vblank@ts-continuation-suspend@pipe-d-hdmi-a-4.html
* igt@kms_writeback@writeback-check-output:
- shard-dg1: NOTRUN -> [SKIP][234] ([i915#2437])
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-dg1: NOTRUN -> [SKIP][235] ([i915#2437] / [i915#9412])
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@perf@global-sseu-config:
- shard-mtlp: NOTRUN -> [SKIP][236] ([i915#7387])
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@perf@global-sseu-config.html
* igt@perf@mi-rpc:
- shard-rkl: NOTRUN -> [SKIP][237] ([i915#2434])
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-1/igt@perf@mi-rpc.html
- shard-dg1: NOTRUN -> [SKIP][238] ([i915#2434])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-15/igt@perf@mi-rpc.html
* igt@perf@unprivileged-single-ctx-counters:
- shard-rkl: NOTRUN -> [SKIP][239] ([i915#2433])
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-3/igt@perf@unprivileged-single-ctx-counters.html
* igt@perf_pmu@rc6@other-idle-gt0:
- shard-rkl: NOTRUN -> [SKIP][240] ([i915#8516])
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-5/igt@perf_pmu@rc6@other-idle-gt0.html
* igt@prime_vgem@basic-read:
- shard-rkl: NOTRUN -> [SKIP][241] ([i915#3291] / [i915#3708])
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-5/igt@prime_vgem@basic-read.html
* igt@prime_vgem@fence-flip-hang:
- shard-dg1: NOTRUN -> [SKIP][242] ([i915#3708])
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-18/igt@prime_vgem@fence-flip-hang.html
* igt@prime_vgem@fence-read-hang:
- shard-dg2: NOTRUN -> [SKIP][243] ([i915#3708])
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@prime_vgem@fence-read-hang.html
* igt@sriov_basic@enable-vfs-autoprobe-on:
- shard-dg2: NOTRUN -> [SKIP][244] ([i915#9917])
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@sriov_basic@enable-vfs-autoprobe-on.html
* igt@syncobj_wait@invalid-wait-zero-handles:
- shard-dg1: NOTRUN -> [FAIL][245] ([i915#9779])
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@syncobj_wait@invalid-wait-zero-handles.html
* igt@v3d/v3d_create_bo@create-bo-zeroed:
- shard-tglu: NOTRUN -> [SKIP][246] ([i915#2575]) +4 other tests skip
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-tglu-6/igt@v3d/v3d_create_bo@create-bo-zeroed.html
* igt@v3d/v3d_job_submission@array-job-submission:
- shard-dg2: NOTRUN -> [SKIP][247] ([i915#2575]) +2 other tests skip
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@v3d/v3d_job_submission@array-job-submission.html
* igt@v3d/v3d_perfmon@get-values-invalid-perfmon:
- shard-dg1: NOTRUN -> [SKIP][248] ([i915#2575]) +9 other tests skip
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-18/igt@v3d/v3d_perfmon@get-values-invalid-perfmon.html
* igt@v3d/v3d_submit_csd@multi-and-single-sync:
- shard-mtlp: NOTRUN -> [SKIP][249] ([i915#2575]) +4 other tests skip
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-7/igt@v3d/v3d_submit_csd@multi-and-single-sync.html
* igt@vc4/vc4_label_bo@set-label:
- shard-dg1: NOTRUN -> [SKIP][250] ([i915#7711]) +4 other tests skip
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-18/igt@vc4/vc4_label_bo@set-label.html
* igt@vc4/vc4_perfmon@get-values-invalid-pointer:
- shard-mtlp: NOTRUN -> [SKIP][251] ([i915#7711]) +1 other test skip
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-2/igt@vc4/vc4_perfmon@get-values-invalid-pointer.html
* igt@vc4/vc4_purgeable_bo@mark-unpurgeable-check-retained:
- shard-dg2: NOTRUN -> [SKIP][252] ([i915#7711]) +1 other test skip
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@vc4/vc4_purgeable_bo@mark-unpurgeable-check-retained.html
* igt@vc4/vc4_tiling@get-bad-modifier:
- shard-rkl: NOTRUN -> [SKIP][253] ([i915#7711]) +6 other tests skip
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-3/igt@vc4/vc4_tiling@get-bad-modifier.html
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [FAIL][254] ([i915#7742]) -> [PASS][255]
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-rkl-6/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-1/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@drm_read@short-buffer-block:
- shard-dg1: [DMESG-WARN][256] ([i915#4423]) -> [PASS][257]
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg1-13/igt@drm_read@short-buffer-block.html
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-17/igt@drm_read@short-buffer-block.html
* igt@gem_eio@unwedge-stress:
- shard-dg2: [FAIL][258] ([i915#5784]) -> [PASS][259]
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg2-11/igt@gem_eio@unwedge-stress.html
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-7/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglu: [FAIL][260] ([i915#2842]) -> [PASS][261]
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-tglu-5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-tglu-9/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0:
- shard-dg2: [FAIL][262] ([i915#10446]) -> [PASS][263]
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg2-11/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-3/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html
* igt@gem_lmem_swapping@heavy-verify-random@lmem0:
- shard-dg2: [FAIL][264] ([i915#10378]) -> [PASS][265]
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg2-2/igt@gem_lmem_swapping@heavy-verify-random@lmem0.html
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-10/igt@gem_lmem_swapping@heavy-verify-random@lmem0.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-snb: [INCOMPLETE][266] ([i915#9849]) -> [PASS][267]
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-snb2/igt@i915_module_load@reload-with-fault-injection.html
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-snb4/igt@i915_module_load@reload-with-fault-injection.html
- shard-mtlp: [ABORT][268] ([i915#10131] / [i915#10887] / [i915#9820]) -> [PASS][269]
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-mtlp-7/igt@i915_module_load@reload-with-fault-injection.html
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-2/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rpm@system-suspend:
- shard-rkl: [FAIL][270] ([i915#11279]) -> [PASS][271]
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-rkl-6/igt@i915_pm_rpm@system-suspend.html
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-4/igt@i915_pm_rpm@system-suspend.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-rkl: [FAIL][272] ([i915#10031] / [i915#11279]) -> [PASS][273] +1 other test pass
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-rkl-6/igt@i915_suspend@basic-s3-without-i915.html
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-4/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_cursor_legacy@torture-bo@pipe-a:
- shard-snb: [DMESG-WARN][274] ([i915#10166]) -> [PASS][275]
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-snb2/igt@kms_cursor_legacy@torture-bo@pipe-a.html
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-snb4/igt@kms_cursor_legacy@torture-bo@pipe-a.html
* igt@kms_flip@flip-vs-rmfb-interruptible@a-hdmi-a2:
- shard-glk: [INCOMPLETE][276] -> [PASS][277]
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-glk4/igt@kms_flip@flip-vs-rmfb-interruptible@a-hdmi-a2.html
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-glk9/igt@kms_flip@flip-vs-rmfb-interruptible@a-hdmi-a2.html
* igt@kms_flip@wf_vblank-ts-check@a-edp1:
- shard-mtlp: [INCOMPLETE][278] -> [PASS][279]
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-mtlp-2/igt@kms_flip@wf_vblank-ts-check@a-edp1.html
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-3/igt@kms_flip@wf_vblank-ts-check@a-edp1.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-dg2: [SKIP][280] ([i915#9519]) -> [PASS][281] +2 other tests pass
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg2-5/igt@kms_pm_rpm@modeset-lpsp.html
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@kms_pm_rpm@modeset-lpsp.html
- shard-rkl: [SKIP][282] ([i915#9519]) -> [PASS][283] +2 other tests pass
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-rkl-6/igt@kms_pm_rpm@modeset-lpsp.html
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1:
- shard-snb: [FAIL][284] ([i915#9196]) -> [PASS][285] +1 other test pass
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-snb7/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-snb4/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1:
- shard-mtlp: [FAIL][286] ([i915#9196]) -> [PASS][287]
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-mtlp-4/igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1.html
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-mtlp-1/igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1.html
#### Warnings ####
* igt@device_reset@unbind-reset-rebind:
- shard-dg1: [INCOMPLETE][288] ([i915#1982] / [i915#9408]) -> [INCOMPLETE][289] ([i915#9408])
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg1-16/igt@device_reset@unbind-reset-rebind.html
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-16/igt@device_reset@unbind-reset-rebind.html
* igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-lmem0-lmem0:
- shard-dg2: [FAIL][290] ([i915#11265]) -> [FAIL][291] ([i915#11265] / [i915#11279])
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg2-4/igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-lmem0-lmem0.html
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-6/igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-lmem0-lmem0.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-dg2: [ABORT][292] ([i915#9846]) -> [INCOMPLETE][293] ([i915#9364])
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg2-3/igt@gem_create@create-ext-cpu-access-big.html
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-4/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_ctx_isolation@preservation-s3@vcs1:
- shard-dg2: [FAIL][294] ([i915#10086] / [i915#11279]) -> [FAIL][295] ([i915#10086]) +1 other test fail
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg2-5/igt@gem_ctx_isolation@preservation-s3@vcs1.html
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@gem_ctx_isolation@preservation-s3@vcs1.html
* igt@gem_ctx_isolation@preservation-s3@vecs1:
- shard-dg2: [FAIL][296] ([i915#10086]) -> [FAIL][297] ([i915#10086] / [i915#11279])
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg2-5/igt@gem_ctx_isolation@preservation-s3@vecs1.html
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@gem_ctx_isolation@preservation-s3@vecs1.html
* igt@gem_exec_suspend@basic-s3@smem:
- shard-dg2: [FAIL][298] -> [FAIL][299] ([i915#11279])
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg2-4/igt@gem_exec_suspend@basic-s3@smem.html
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-6/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_pm_rps@waitboost:
- shard-dg2: [FAIL][300] ([i915#11295]) -> [FAIL][301] ([i915#8346])
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg2-2/igt@i915_pm_rps@waitboost.html
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-6/igt@i915_pm_rps@waitboost.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-dg2: [FAIL][302] ([i915#10031]) -> [FAIL][303] ([i915#10031] / [i915#11279])
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg2-5/igt@i915_suspend@basic-s3-without-i915.html
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-8/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-90:
- shard-dg1: [SKIP][304] ([i915#4423] / [i915#4538]) -> [SKIP][305] ([i915#4538])
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg1-13/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-17/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html
* igt@kms_content_protection@type1:
- shard-dg2: [SKIP][306] ([i915#7118] / [i915#9424]) -> [SKIP][307] ([i915#7118] / [i915#7162] / [i915#9424])
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg2-10/igt@kms_content_protection@type1.html
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-11/igt@kms_content_protection@type1.html
* igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-4:
- shard-dg1: [FAIL][308] ([i915#11298]) -> [FAIL][309] ([i915#11279] / [i915#11298])
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg1-17/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-4.html
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-18/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-4.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-dg2: [FAIL][310] ([i915#11280]) -> [FAIL][311] ([i915#11279] / [i915#11280])
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-suspend.html
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt:
- shard-dg2: [SKIP][312] ([i915#3458]) -> [SKIP][313] ([i915#10433] / [i915#3458]) +2 other tests skip
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg2-3/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt.html
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite:
- shard-dg2: [SKIP][314] ([i915#10433] / [i915#3458]) -> [SKIP][315] ([i915#3458]) +4 other tests skip
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite.html
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-7/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_pm_rpm@system-suspend-modeset:
- shard-dg2: [FAIL][316] ([i915#11273]) -> [FAIL][317] ([i915#11273] / [i915#11279])
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg2-8/igt@kms_pm_rpm@system-suspend-modeset.html
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-2/igt@kms_pm_rpm@system-suspend-modeset.html
* igt@kms_psr@fbc-psr-cursor-mmap-cpu:
- shard-dg2: [SKIP][318] ([i915#1072] / [i915#9732]) -> [SKIP][319] ([i915#1072] / [i915#9673] / [i915#9732]) +5 other tests skip
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg2-10/igt@kms_psr@fbc-psr-cursor-mmap-cpu.html
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-11/igt@kms_psr@fbc-psr-cursor-mmap-cpu.html
* igt@kms_psr@fbc-psr-primary-mmap-gtt:
- shard-dg2: [SKIP][320] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][321] ([i915#1072] / [i915#9732]) +9 other tests skip
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg2-11/igt@kms_psr@fbc-psr-primary-mmap-gtt.html
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-7/igt@kms_psr@fbc-psr-primary-mmap-gtt.html
* igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-4:
- shard-dg1: [FAIL][322] ([i915#10305]) -> [FAIL][323] ([i915#10305] / [i915#11279])
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg1-15/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-4.html
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg1-15/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-4.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: [FAIL][324] ([i915#9100]) -> [FAIL][325] ([i915#7484])
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14904/shard-dg2-1/igt@perf@non-zero-reason@0-rcs0.html
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/shard-dg2-2/igt@perf@non-zero-reason@0-rcs0.html
[i915#10031]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10031
[i915#10086]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10086
[i915#10131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10131
[i915#10166]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10166
[i915#10177]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10177
[i915#10278]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10278
[i915#10305]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10305
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10333]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10333
[i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10446]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10446
[i915#10545]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10545
[i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#10887]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10887
[i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
[i915#11265]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11265
[i915#11269]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11269
[i915#11273]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11273
[i915#11274]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11274
[i915#11275]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11275
[i915#11279]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11279
[i915#11280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11280
[i915#11284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11284
[i915#11295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11295
[i915#11298]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11298
[i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
[i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#2065]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2065
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#2433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
[i915#3778]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3778
[i915#3826]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3826
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#3936]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3936
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4087
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/433
[i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
[i915#4473]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4473
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4854
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#4881]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4881
[i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
[i915#5030]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5030
[i915#5176]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
[i915#5465]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5465
[i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
[i915#5882]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5882
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6230]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6230
[i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
[i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
[i915#7016]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7016
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7162]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7162
[i915#7387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7387
[i915#7484]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7484
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
[i915#7711]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
[i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
[i915#8213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8292]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8292
[i915#8346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8346
[i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
[i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
[i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
[i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
[i915#8588]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8588
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
[i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
[i915#9041]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9041
[i915#9100]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9100
[i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
[i915#9227]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9227
[i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
[i915#9364]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9364
[i915#9408]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9408
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9508]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9508
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
[i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
[i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
[i915#9728]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9728
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9779]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9779
[i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
[i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
[i915#9846]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9846
[i915#9849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9849
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_14904 -> Patchwork_126443v16
CI-20190529: 20190529
CI_DRM_14904: 2bea08bd31298d60d416b2a6ed346bb53dd28037 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7880: 73618605b4370cf902267aaf1d25666ff5e26112 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_126443v16: 2bea08bd31298d60d416b2a6ed346bb53dd28037 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126443v16/index.html
[-- Attachment #2: Type: text/html, Size: 114200 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [PATCH v15 0/9] Implement CMRR Support
2024-06-10 2:48 [PATCH v15 0/9] Implement CMRR Support Mitul Golani
` (12 preceding siblings ...)
2024-06-10 4:53 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2024-06-11 4:34 ` Kandpal, Suraj
13 siblings, 0 replies; 17+ messages in thread
From: Kandpal, Suraj @ 2024-06-11 4:34 UTC (permalink / raw)
To: Golani, Mitulkumar Ajitkumar, intel-gfx@lists.freedesktop.org
Cc: Nautiyal, Ankit K
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Mitul
> Golani
> Sent: Monday, June 10, 2024 8:18 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Subject: [PATCH v15 0/9] Implement CMRR Support
>
> CMRR is a display feature that uses adaptive sync framework to vary Vtotal
> slightly to match the content rate exactly without frame drops. This feature is a
> variation of VRR where it varies Vtotal slightly (between additional 0 and 1
> Vtotal scanlines) to match content rate exactly without frame drops using the
> adaptive sync framework.
>
> enable this feature by programing new registers for CMRR enable, CMRR_M,
> CMRR_N, vmin=vmax=flipline.The CMRR_M/CMRR_N ratio represents the
> fractional part in (actual refresh rate/target refresh rate) * origVTotal.
>
> --v6:
> - CMRR handling in co-existatnce of LRR and DRRS
> - Correct vtotal paramas accuracy and add 2 digit precision.
>
> --v7:
> - Rebased patches in-accordance to AS SDP merge.
> - Add neccessary gaurd to prevent crtc_state mismatch during
> intel_vrr_get_config.
>
> -v8:
> - Add support for AS SDP for CMRR.
> - update palce holder for CMRR register(Jani).
> - Make CMRR as subset of FAVT, as per comments in patch#3.
>
> -v9:
> - Add CMRR register definitions to separate intel_vrr_reg.h.
> - Remove cmrr_enabling/disabling, use vrr.enable instead.
> - Update AS SDP pack function to accomodate target_rr_divider.
> - Remove duplicated lines to compute vrr_vsync params.
> - Set cmrr.enable with a separate patch at last.
>
> -v10:
> - Separate VRR related register definitions.
> - Add dependency header intel_display_reg_defs.h.
> - Rename file name to intel_vrr_regs.h instead of reg.h.
> - Revert removed line.
> - Since vrr.enable and cmrr.enable are not mutually exclusive, handle
> accordingly.
> - is_edp is not required inside is_cmrr_frac_required function.
> - Add video_mode_required flag for future enhancement.
> - Correct cmrr_m/cmrr_n calculation.
> - target_rr_divider is bools so handle accordingly.
>
> -v11:
> - Move VRR related register and bits to separate file intel_vrr_regs.h.
> - Correct file header macro to intel_vrr_regs.h.
> - Remove adding CMRR flag to vrr_ctl register during set_transcoder_timing.
> - Replace vrr.enable flag to cmrr.enable where added mistakenly.
> - Move cmrr computation patch to last and set other other required
> params before computing cmrr.enable.
>
> -v12:
> - Add patch to fix check patch issues for VRR related registers in i915_reg.h
> then move them to intel_vrr_regs.h with separate patch.
>
> -v13:
> - Reverted unrelated patches while rebase.
>
> -v14:
> - Fix all indentations for VRR related registes in Patch#1
>
> -v15:
> - Rebase.
>
Thanks for the patches and reviews everyone
Pushed-to drm-intel-next
> Mitul Golani (9):
> gpu/drm/i915: Update indentation for VRR registers and bits
> drm/i915: Separate VRR related register definitions
> drm/i915: Define and compute Transcoder CMRR registers
> drm/i915: Update trans_vrr_ctl flag when cmrr is computed
> drm/dp: Add refresh rate divider to struct representing AS SDP
> drm/i915/display: Add support for pack and unpack
> drm/i915/display: Compute Adaptive sync SDP params
> drm/i915/display: Compute vrr vsync params
> drm/i915: Compute CMRR and calculate vtotal
>
> drivers/gpu/drm/i915/display/intel_display.c | 24 +++-
> .../drm/i915/display/intel_display_device.h | 1 +
> .../drm/i915/display/intel_display_types.h | 6 +
> drivers/gpu/drm/i915/display/intel_dp.c | 18 ++-
> drivers/gpu/drm/i915/display/intel_vrr.c | 128 ++++++++++++++++--
> drivers/gpu/drm/i915/display/intel_vrr_regs.h | 127 +++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 100 --------------
> include/drm/display/drm_dp_helper.h | 1 +
> 8 files changed, 286 insertions(+), 119 deletions(-) create mode 100644
> drivers/gpu/drm/i915/display/intel_vrr_regs.h
>
> --
> 2.25.1
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2024-06-11 4:34 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-06-10 2:48 [PATCH v15 0/9] Implement CMRR Support Mitul Golani
2024-06-10 2:48 ` [PATCH v15 1/9] gpu/drm/i915: Update indentation for VRR registers and bits Mitul Golani
2024-06-10 4:19 ` Nautiyal, Ankit K
2024-06-10 2:48 ` [PATCH v15 2/9] drm/i915: Separate VRR related register definitions Mitul Golani
2024-06-10 4:46 ` Nautiyal, Ankit K
2024-06-10 2:48 ` [PATCH v15 3/9] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani
2024-06-10 2:48 ` [PATCH v15 4/9] drm/i915: Update trans_vrr_ctl flag when cmrr is computed Mitul Golani
2024-06-10 2:48 ` [PATCH v15 5/9] drm/dp: Add refresh rate divider to struct representing AS SDP Mitul Golani
2024-06-10 2:48 ` [PATCH v15 6/9] drm/i915/display: Add support for pack and unpack Mitul Golani
2024-06-10 2:48 ` [PATCH v15 7/9] drm/i915/display: Compute Adaptive sync SDP params Mitul Golani
2024-06-10 2:48 ` [PATCH v15 8/9] drm/i915/display: Compute vrr vsync params Mitul Golani
2024-06-10 2:48 ` [PATCH v15 9/9] drm/i915: Compute CMRR and calculate vtotal Mitul Golani
2024-06-10 3:25 ` ✗ Fi.CI.CHECKPATCH: warning for Implement CMRR Support (rev16) Patchwork
2024-06-10 3:25 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-06-10 3:31 ` ✓ Fi.CI.BAT: success " Patchwork
2024-06-10 4:53 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-06-11 4:34 ` [PATCH v15 0/9] Implement CMRR Support Kandpal, Suraj
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