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From: Arun R Murthy <arun.r.murthy@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: Arun R Murthy <arun.r.murthy@intel.com>,
	Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
Subject: [PATCH 3/3] drm/i915/dp: Include the time taken by AUX Tx for timeout
Date: Thu, 12 Sep 2024 10:35:52 +0530	[thread overview]
Message-ID: <20240912050552.779356-4-arun.r.murthy@intel.com> (raw)
In-Reply-To: <20240912050552.779356-1-arun.r.murthy@intel.com>

As per DP spec the timeout for LANE_CHANNEL_EQ_DONE is 400ms. But this
timeout value is exclusively for the Aux RD Interval and excludes the
time consumed for the AUX Tx (i.e reading/writing FFE presets). Add
another 50ms for these AUX Tx to the 400ms timeout.

Signed-off-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index ca179bed46ad..b6573934c6dd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1414,7 +1414,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
 	}
 
 	/* Time budget for the LANEx_EQ_DONE Sequence */
-	deadline = jiffies + msecs_to_jiffies_timeout(400);
+	deadline = jiffies + msecs_to_jiffies_timeout(450);
 
 	for (try = 0; try < max_tries; try++) {
 		fsleep(delay_us);
-- 
2.25.1


  parent reply	other threads:[~2024-09-12  5:15 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-12  5:05 [PATCH 0/3] Some correction in the DP Link Training dequence Arun R Murthy
2024-09-12  5:05 ` [PATCH 1/3] drm/i915/dp: use fsleep instead of usleep_rage for LT Arun R Murthy
2024-09-12  9:01   ` Jani Nikula
2024-09-12 10:04     ` Murthy, Arun R
2024-09-12 12:01       ` Srikanth V, NagaVenkata
2024-09-23 10:23       ` Jani Nikula
2024-09-12  9:05   ` Jani Nikula
2024-09-12 10:57     ` Murthy, Arun R
2024-09-23 10:32       ` Jani Nikula
2024-09-23 10:24   ` Jani Nikula
2024-09-23 12:59     ` Francois Dugast
2024-09-23 13:51       ` Jani Nikula
2024-09-12  5:05 ` [PATCH 2/3] drm/i915/dp: read Aux RD interval after reading the FFE preset Arun R Murthy
2024-09-12  9:04   ` Jani Nikula
2024-09-12 10:54     ` Murthy, Arun R
2024-09-12 11:58       ` Srikanth V, NagaVenkata
2024-09-23  6:21   ` Kandpal, Suraj
2024-09-23  6:28     ` Srikanth V, NagaVenkata
2024-09-23  6:32       ` Kandpal, Suraj
2024-09-23  6:56       ` Kandpal, Suraj
2024-09-24  5:58         ` Murthy, Arun R
2024-09-23 11:09   ` Jani Nikula
2024-09-24  6:00     ` Murthy, Arun R
2024-09-12  5:05 ` Arun R Murthy [this message]
2024-09-23  6:23   ` [PATCH 3/3] drm/i915/dp: Include the time taken by AUX Tx for timeout Kandpal, Suraj
2024-09-23  6:31     ` Srikanth V, NagaVenkata
2024-09-23  6:58       ` Kandpal, Suraj
2024-09-23 11:45       ` Jani Nikula
2024-09-12  6:12 ` ✓ Fi.CI.BAT: success for Some correction in the DP Link Training dequence Patchwork
2024-09-13  0:00 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-09-23  6:26 ` [PATCH 0/3] " Kandpal, Suraj

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