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From: Francois Dugast <francois.dugast@intel.com>
To: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Arun R Murthy <arun.r.murthy@intel.com>,
	<intel-xe@lists.freedesktop.org>,
	 <intel-gfx@lists.freedesktop.org>,
	Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
Subject: Re: [PATCH 1/3] drm/i915/dp: use fsleep instead of usleep_rage for LT
Date: Mon, 23 Sep 2024 14:59:42 +0200	[thread overview]
Message-ID: <ZvFmM3FIdY4DS3AS@fdugast-desk> (raw)
In-Reply-To: <87tte6652c.fsf@intel.com>

On Mon, Sep 23, 2024 at 01:24:27PM +0300, Jani Nikula wrote:
> On Thu, 12 Sep 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> > Aux RD Interval value depends on the value read from the dpcd register
> > which is updated from the sink device use flseep thereby we adhere to
> > the Documentation/timers/timers-howto.rst
> >
> > Signed-off-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
> > Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> 
> With the commit message updated to explain why,

While at it, please also fix the typo s/usleep_rage/usleep_range/.

Francois

> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp_link_training.c | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > index 397cc4ebae52..f41b69840ad9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> > @@ -898,7 +898,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
> >  
> >  	voltage_tries = 1;
> >  	for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
> > -		usleep_range(delay_us, 2 * delay_us);
> > +		fsleep(delay_us);
> >  
> >  		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
> >  						     link_status) < 0) {
> > @@ -1040,7 +1040,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
> >  	}
> >  
> >  	for (tries = 0; tries < 5; tries++) {
> > -		usleep_range(delay_us, 2 * delay_us);
> > +		fsleep(delay_us);
> >  
> >  		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
> >  						     link_status) < 0) {
> > @@ -1417,7 +1417,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
> >  	deadline = jiffies + msecs_to_jiffies_timeout(400);
> >  
> >  	for (try = 0; try < max_tries; try++) {
> > -		usleep_range(delay_us, 2 * delay_us);
> > +		fsleep(delay_us);
> >  
> >  		/*
> >  		 * The delay may get updated. The transmitter shall read the
> 
> -- 
> Jani Nikula, Intel

  reply	other threads:[~2024-09-23 13:00 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-12  5:05 [PATCH 0/3] Some correction in the DP Link Training dequence Arun R Murthy
2024-09-12  5:05 ` [PATCH 1/3] drm/i915/dp: use fsleep instead of usleep_rage for LT Arun R Murthy
2024-09-12  9:01   ` Jani Nikula
2024-09-12 10:04     ` Murthy, Arun R
2024-09-12 12:01       ` Srikanth V, NagaVenkata
2024-09-23 10:23       ` Jani Nikula
2024-09-12  9:05   ` Jani Nikula
2024-09-12 10:57     ` Murthy, Arun R
2024-09-23 10:32       ` Jani Nikula
2024-09-23 10:24   ` Jani Nikula
2024-09-23 12:59     ` Francois Dugast [this message]
2024-09-23 13:51       ` Jani Nikula
2024-09-12  5:05 ` [PATCH 2/3] drm/i915/dp: read Aux RD interval after reading the FFE preset Arun R Murthy
2024-09-12  9:04   ` Jani Nikula
2024-09-12 10:54     ` Murthy, Arun R
2024-09-12 11:58       ` Srikanth V, NagaVenkata
2024-09-23  6:21   ` Kandpal, Suraj
2024-09-23  6:28     ` Srikanth V, NagaVenkata
2024-09-23  6:32       ` Kandpal, Suraj
2024-09-23  6:56       ` Kandpal, Suraj
2024-09-24  5:58         ` Murthy, Arun R
2024-09-23 11:09   ` Jani Nikula
2024-09-24  6:00     ` Murthy, Arun R
2024-09-12  5:05 ` [PATCH 3/3] drm/i915/dp: Include the time taken by AUX Tx for timeout Arun R Murthy
2024-09-23  6:23   ` Kandpal, Suraj
2024-09-23  6:31     ` Srikanth V, NagaVenkata
2024-09-23  6:58       ` Kandpal, Suraj
2024-09-23 11:45       ` Jani Nikula
2024-09-12  6:12 ` ✓ Fi.CI.BAT: success for Some correction in the DP Link Training dequence Patchwork
2024-09-13  0:00 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-09-23  6:26 ` [PATCH 0/3] " Kandpal, Suraj

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