From: Jani Nikula <jani.nikula@linux.intel.com>
To: Arun R Murthy <arun.r.murthy@intel.com>,
intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: Arun R Murthy <arun.r.murthy@intel.com>,
Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
Subject: Re: [PATCH 2/3] drm/i915/dp: read Aux RD interval after reading the FFE preset
Date: Thu, 12 Sep 2024 12:04:26 +0300 [thread overview]
Message-ID: <87frq5i6p1.fsf@intel.com> (raw)
In-Reply-To: <20240912050552.779356-3-arun.r.murthy@intel.com>
On Thu, 12 Sep 2024, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> DP Source should be reading AUX_RD interval after we get adjusted
> TX_FFE_PRESET_VALUE from the DP Sink. (before actually adjusting
> in DP Source)
Please explain why.
BR,
Jani.
>
> Signed-off-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
> .../gpu/drm/i915/display/intel_dp_link_training.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index f41b69840ad9..ca179bed46ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -1419,12 +1419,6 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
> for (try = 0; try < max_tries; try++) {
> fsleep(delay_us);
>
> - /*
> - * The delay may get updated. The transmitter shall read the
> - * delay before link status during link training.
> - */
> - delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
> -
> if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
> lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
> return false;
> @@ -1457,6 +1451,12 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
> lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n");
> return false;
> }
> +
> + /*
> + * The delay may get updated. The transmitter shall read the
> + * delay before link status during link training.
> + */
> + delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
> }
>
> if (try == max_tries) {
--
Jani Nikula, Intel
next prev parent reply other threads:[~2024-09-12 9:04 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-12 5:05 [PATCH 0/3] Some correction in the DP Link Training dequence Arun R Murthy
2024-09-12 5:05 ` [PATCH 1/3] drm/i915/dp: use fsleep instead of usleep_rage for LT Arun R Murthy
2024-09-12 9:01 ` Jani Nikula
2024-09-12 10:04 ` Murthy, Arun R
2024-09-12 12:01 ` Srikanth V, NagaVenkata
2024-09-23 10:23 ` Jani Nikula
2024-09-12 9:05 ` Jani Nikula
2024-09-12 10:57 ` Murthy, Arun R
2024-09-23 10:32 ` Jani Nikula
2024-09-23 10:24 ` Jani Nikula
2024-09-23 12:59 ` Francois Dugast
2024-09-23 13:51 ` Jani Nikula
2024-09-12 5:05 ` [PATCH 2/3] drm/i915/dp: read Aux RD interval after reading the FFE preset Arun R Murthy
2024-09-12 9:04 ` Jani Nikula [this message]
2024-09-12 10:54 ` Murthy, Arun R
2024-09-12 11:58 ` Srikanth V, NagaVenkata
2024-09-23 6:21 ` Kandpal, Suraj
2024-09-23 6:28 ` Srikanth V, NagaVenkata
2024-09-23 6:32 ` Kandpal, Suraj
2024-09-23 6:56 ` Kandpal, Suraj
2024-09-24 5:58 ` Murthy, Arun R
2024-09-23 11:09 ` Jani Nikula
2024-09-24 6:00 ` Murthy, Arun R
2024-09-12 5:05 ` [PATCH 3/3] drm/i915/dp: Include the time taken by AUX Tx for timeout Arun R Murthy
2024-09-23 6:23 ` Kandpal, Suraj
2024-09-23 6:31 ` Srikanth V, NagaVenkata
2024-09-23 6:58 ` Kandpal, Suraj
2024-09-23 11:45 ` Jani Nikula
2024-09-12 6:12 ` ✓ Fi.CI.BAT: success for Some correction in the DP Link Training dequence Patchwork
2024-09-13 0:00 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-09-23 6:26 ` [PATCH 0/3] " Kandpal, Suraj
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