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From: Uma Shankar <uma.shankar@intel.com>
To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
	intel-xe@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, harry.wentland@amd.com,
	pekka.paalanen@haloniitty.fi, sebastian.wick@redhat.com,
	jadahl@redhat.com, mwen@igalia.com, contact@emersion.fr,
	naveen1.kumar@intel.com,
	Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>,
	Uma Shankar <uma.shankar@intel.com>
Subject: [v2 07/25] drm: Add 1D LUT multi-segmented color op
Date: Tue, 26 Nov 2024 18:57:12 +0530	[thread overview]
Message-ID: <20241126132730.1192571-8-uma.shankar@intel.com> (raw)
In-Reply-To: <20241126132730.1192571-1-uma.shankar@intel.com>

From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>

Add support for color ops that can be programmed
by 1 dimensional multi segmented Look Up Tables.

Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/drm_atomic.c      | 4 ++++
 drivers/gpu/drm/drm_atomic_uapi.c | 3 +++
 include/uapi/drm/drm_mode.h       | 8 ++++++++
 3 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index 8a75f4a0637a..f344d64d42ce 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -802,6 +802,10 @@ static void drm_atomic_colorop_print_state(struct drm_printer *p,
 		drm_printf(p, "\tinterpolation=%s\n", drm_get_colorop_lut1d_interpolation_name(colorop->lut1d_interpolation));
 		drm_printf(p, "\tdata blob id=%d\n", state->data ? state->data->base.id : 0);
 		break;
+	case DRM_COLOROP_1D_LUT_MULTSEG:
+		drm_printf(p, "\thw cap blob id=%d\n", state->hw_caps ? state->hw_caps->base.id : 0);
+		drm_printf(p, "\tdata blob id=%d\n", state->data ? state->data->base.id : 0);
+		break;
 	case DRM_COLOROP_CTM_3X3:
 		drm_printf(p, "\tdata blob id=%d\n", state->data ? state->data->base.id : 0);
 		break;
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c
index 46cc7b0df6e8..326159bff91c 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -720,6 +720,9 @@ static int drm_atomic_color_set_data_property(struct drm_colorop *colorop,
 		size = modes[index].lut_stride[0] * modes[index].lut_stride[1] * modes[index].lut_stride[2] *
 		       sizeof(struct drm_color_lut);
 		break;
+	case DRM_COLOROP_1D_LUT_MULTSEG:
+		elem_size = sizeof(struct drm_color_lut_32);
+		break;
 	default:
 		/* should never get here */
 		return -EINVAL;
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 9ed8b1b1357a..d126a5410eea 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -923,6 +923,14 @@ enum drm_colorop_type {
 	 */
 	DRM_COLOROP_CTM_3X4,
 
+	/**
+	 * @DRM_COLOROP_1D_LUT_MULTSEG:
+	 *
+	 * A 3x4 matrix. Its values are specified via the
+	 * &drm_color_ctm_3x4 struct provided via the DATA property.
+	 */
+	DRM_COLOROP_1D_LUT_MULTSEG,
+
 	/**
 	 * @DRM_COLOROP_CTM_3X3:
 	 *
-- 
2.42.0


  parent reply	other threads:[~2024-11-26 13:20 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-26 13:27 [v2 00/25] Plane Color Pipeline support for Intel platforms Uma Shankar
2024-11-26 13:27 ` [v2 01/25] [NOT FOR REVIEW] drm: color pipeline base work Uma Shankar
2024-11-26 13:27 ` [v2 02/25] drm: Add support for 3x3 CTM Uma Shankar
2024-11-30  9:38   ` Dmitry Baryshkov
2024-12-03  9:03     ` Shankar, Uma
2024-11-26 13:27 ` [v2 03/25] drm: Add Enhanced LUT precision structure Uma Shankar
2024-11-26 13:27 ` [v2 04/25] drm: Add Color lut range attributes Uma Shankar
2024-11-26 13:27 ` [v2 05/25] drm: Add Color ops capability property Uma Shankar
2024-11-30  9:43   ` Dmitry Baryshkov
2024-12-03  9:09     ` Shankar, Uma
2024-11-26 13:27 ` [v2 06/25] drm: Define helper to create color " Uma Shankar
2024-11-26 13:27 ` Uma Shankar [this message]
2024-11-30  9:44   ` [v2 07/25] drm: Add 1D LUT multi-segmented color op Dmitry Baryshkov
2024-12-03  9:11     ` Shankar, Uma
2024-11-26 13:27 ` [v2 08/25] drm: Define helper for adding capability property for 1D LUT MULTSEG Uma Shankar
2024-11-26 13:27 ` [v2 09/25] drm: Add helper to initialize segmented 1D LUT Uma Shankar
2024-11-30  9:46   ` Dmitry Baryshkov
2024-12-03  9:14     ` Shankar, Uma
2024-12-05 23:38       ` Dmitry Baryshkov
2024-11-26 13:27 ` [v2 10/25] drm/i915: Add identifiers for intel color blocks Uma Shankar
2024-11-26 13:27 ` [v2 11/25] drm/i915: Add intel_color_op Uma Shankar
2024-11-26 13:27 ` [v2 12/25] drm/i915/color: Add helper to create intel colorop Uma Shankar
2024-11-26 13:27 ` [v2 13/25] drm/i915/color: Create a transfer function color pipeline Uma Shankar
2024-11-26 13:27 ` [v2 14/25] drm/i915/color: Add and attach COLORPIPELINE plane property Uma Shankar
2024-11-26 13:27 ` [v2 15/25] drm/i915/color: Add framework to set colorop Uma Shankar
2024-11-26 13:27 ` [v2 16/25] drm/i915/color: Add callbacks to set plane CTM Uma Shankar
2024-11-26 13:27 ` [v2 17/25] drm/i915/color: Add new color callbacks for Xelpd Uma Shankar
2024-11-26 13:27 ` [v2 18/25] drm/i915/color: Add plane CTM callback for D13 and beyond Uma Shankar
2024-11-26 13:27 ` [v2 19/25] drm/i915: Add register definitions for Plane Degamma Uma Shankar
2024-11-26 13:27 ` [v2 20/25] drm/i915/color: Add framework to program PRE/POST CSC LUT Uma Shankar
2024-11-26 13:27 ` [v2 21/25] drm/i915: Add register definitions for Plane Post CSC Uma Shankar
2024-11-26 13:27 ` [v2 22/25] drm/i915/color: Program Pre-CSC registers Uma Shankar
2024-11-26 13:27 ` [v2 23/25] drm/i915/xelpd: Program Plane Post CSC Registers Uma Shankar
2024-11-26 13:27 ` [v2 24/25] drm/i915/color: Enable Plane Color Pipelines Uma Shankar
2024-11-26 13:27 ` [v2 25/25] drm/doc/rfc: Add documentation for multi-segmented 1D LUT Uma Shankar
2024-11-26 14:54 ` ✗ Fi.CI.CHECKPATCH: warning for Plane Color Pipeline support for Intel platforms (rev2) Patchwork
2024-11-26 14:54 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-11-26 15:09 ` ✗ i915.CI.BAT: failure " Patchwork

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