From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: ankit.k.nautiyal@intel.com, ville.syrjala@intel.com
Subject: [PATCH v5 12/17] drm/i915/dsb: Add pipedmc dc balance enable/disable
Date: Tue, 13 May 2025 10:46:55 +0530 [thread overview]
Message-ID: <20250513051700.507389-13-mitulkumar.ajitkumar.golani@intel.com> (raw)
In-Reply-To: <20250513051700.507389-1-mitulkumar.ajitkumar.golani@intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add function to control DC balance enable/disable bit via DSB.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc.c | 18 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dmc.h | 5 +++++
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index b58189d24e7e..593f5140475b 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -30,6 +30,7 @@
#include "intel_de.h"
#include "intel_display_rpm.h"
#include "intel_display_power_well.h"
+#include "intel_display_types.h"
#include "intel_dmc.h"
#include "intel_dmc_regs.h"
#include "intel_step.h"
@@ -1403,3 +1404,20 @@ void intel_dmc_debugfs_register(struct intel_display *display)
debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root,
display, &intel_dmc_debugfs_status_fops);
}
+
+void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc)
+{
+ struct intel_display *display = to_intel_display(crtc);
+ enum pipe pipe = crtc->pipe;
+
+ intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe),
+ PIPEDMC_ADAPTIVE_DCB_ENABLE);
+}
+
+void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc)
+{
+ struct intel_display *display = to_intel_display(crtc);
+ enum pipe pipe = crtc->pipe;
+
+ intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 0);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index bd1c459b0075..48869f19079a 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -9,9 +9,11 @@
#include <linux/types.h>
enum pipe;
+struct intel_crtc;
struct drm_printer;
struct intel_display;
struct intel_dmc_snapshot;
+struct intel_dsb;
void intel_dmc_init(struct intel_display *display);
void intel_dmc_load_program(struct intel_display *display);
@@ -34,4 +36,7 @@ void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool star
void assert_dmc_loaded(struct intel_display *display);
+void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc);
+void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc);
+
#endif /* __INTEL_DMC_H__ */
--
2.48.1
next prev parent reply other threads:[~2025-05-13 5:19 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-13 5:16 [PATCH v5 00/17] Enable/Disable DC balance along with VRR DSB Mitul Golani
2025-05-13 5:16 ` [PATCH v5 01/17] drm/i915/vrr: Refactor vmin/vmax stuff Mitul Golani
2025-05-13 5:16 ` [PATCH v5 02/17] drm/i915/display: Add source param for dc balance Mitul Golani
2025-05-13 5:16 ` [PATCH v5 03/17] drm/i915/display: Add pipe dmc registers and bits for DC Balance Mitul Golani
2025-05-30 6:22 ` Nautiyal, Ankit K
2025-05-13 5:16 ` [PATCH v5 04/17] drm/i915/display: Add VRR DC balance registers Mitul Golani
2025-05-13 7:15 ` Jani Nikula
2025-05-13 5:16 ` [PATCH v5 05/17] drm/i915/vrr: Add functions to read out vmin/vmax stuff Mitul Golani
2025-05-13 5:16 ` [PATCH v5 06/17] drm/i915/vrr: Add DC Balance params to crtc_state Mitul Golani
2025-05-13 5:16 ` [PATCH v5 07/17] drm/i915/vrr: Add state dump for DC Balance params Mitul Golani
2025-05-13 5:16 ` [PATCH v5 08/17] drm/i915/vrr: Add compute config " Mitul Golani
2025-05-13 5:16 ` [PATCH v5 09/17] drm/i915/vrr: Write DC balance params to hw registers Mitul Golani
2025-05-27 6:17 ` Nautiyal, Ankit K
2025-05-13 5:16 ` [PATCH v5 10/17] drm/i915: Extract vrr_vblank_start() Mitul Golani
2025-05-13 5:16 ` [PATCH v5 11/17] drm/i915/vrr: Implement vblank evasion with DC balancing Mitul Golani
2025-05-13 5:16 ` Mitul Golani [this message]
2025-05-13 5:16 ` [PATCH v5 13/17] drm/i915/vrr: Restructure VRR enablement bit Mitul Golani
2025-05-13 5:16 ` [PATCH v5 14/17] drm/i915/vrr: Pause DC Balancing for DSB commits Mitul Golani
2025-05-13 5:16 ` [PATCH v5 15/17] drm/i915/vrr: Add function to check if DC Balance Possible Mitul Golani
2025-05-13 5:16 ` [PATCH v5 16/17] drm/i915/display: Add function to configure PIPEDMC_EVT_CTL Mitul Golani
2025-05-13 5:17 ` [PATCH v5 17/17] drm/i915/vrr: Enable DC Balance bit Mitul Golani
2025-05-13 6:02 ` ✗ Fi.CI.CHECKPATCH: warning for Enable/Disable DC balance along with VRR DSB (rev5) Patchwork
2025-05-13 6:02 ` ✗ Fi.CI.SPARSE: " Patchwork
2025-05-13 6:26 ` ✗ i915.CI.BAT: failure " Patchwork
2025-05-15 7:55 ` Golani, Mitulkumar Ajitkumar
2025-05-15 8:20 ` ✓ i915.CI.BAT: success " Patchwork
2025-05-15 9:56 ` ✗ i915.CI.Full: failure " Patchwork
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