From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
Cc: chaitanya.kumar.borah@intel.com, ville.syrjala@linux.intel.com,
pekka.paalanen@collabora.com, contact@emersion.fr,
harry.wentland@amd.com, mwen@igalia.com, jadahl@redhat.com,
sebastian.wick@redhat.com, shashank.sharma@amd.com,
swati2.sharma@intel.com, alex.hung@amd.com,
jani.nikula@intel.com, Uma Shankar <uma.shankar@intel.com>
Subject: [v6 10/16] drm/i915/color: Add framework to program PRE/POST CSC LUT
Date: Wed, 5 Nov 2025 18:04:06 +0530 [thread overview]
Message-ID: <20251105123413.2671075-11-uma.shankar@intel.com> (raw)
In-Reply-To: <20251105123413.2671075-1-uma.shankar@intel.com>
Add framework that will help in loading LUT to Pre/Post CSC color
blocks.
v2: Add dsb support
v3: Align enum names
v4: Propagate change in lut data to crtc_state
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 16 ++++++++++++++++
.../gpu/drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_plane.c | 4 ++++
3 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index fd3c6b7b0f38..83b0cb519e44 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -93,6 +93,10 @@ struct intel_color_funcs {
/* Plane CSC*/
void (*load_plane_csc_matrix)(struct intel_dsb *dsb,
const struct intel_plane_state *plane_state);
+
+ /* Plane Pre/Post CSC */
+ void (*load_plane_luts)(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state);
};
#define CTM_COEFF_SIGN (1ULL << 63)
@@ -4076,11 +4080,23 @@ intel_color_load_plane_csc_matrix(struct intel_dsb *dsb,
display->funcs.color->load_plane_csc_matrix(dsb, plane_state);
}
+static void
+intel_color_load_plane_luts(struct intel_dsb *dsb,
+ const struct intel_plane_state *plane_state)
+{
+ struct intel_display *display = to_intel_display(plane_state);
+
+ if (display->funcs.color->load_plane_luts)
+ display->funcs.color->load_plane_luts(dsb, plane_state);
+}
+
void intel_color_plane_program_pipeline(struct intel_dsb *dsb,
const struct intel_plane_state *plane_state)
{
if (plane_state->hw.ctm)
intel_color_load_plane_csc_matrix(dsb, plane_state);
+ if (plane_state->hw.degamma_lut || plane_state->hw.gamma_lut)
+ intel_color_load_plane_luts(dsb, plane_state);
}
void intel_color_crtc_init(struct intel_crtc *crtc)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d25f90ded71f..d8fe80a55601 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -646,7 +646,7 @@ struct intel_plane_state {
enum drm_color_encoding color_encoding;
enum drm_color_range color_range;
enum drm_scaling_filter scaling_filter;
- struct drm_property_blob *ctm;
+ struct drm_property_blob *ctm, *degamma_lut, *gamma_lut;
} hw;
struct i915_vma *ggtt_vma;
diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
index a5d0f95a6f10..298f8e186fee 100644
--- a/drivers/gpu/drm/i915/display/intel_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_plane.c
@@ -344,6 +344,10 @@ intel_plane_colorop_replace_blob(struct intel_plane_state *plane_state,
{
if (intel_colorop->id == INTEL_PLANE_CB_CSC)
return drm_property_replace_blob(&plane_state->hw.ctm, blob);
+ else if (intel_colorop->id == INTEL_PLANE_CB_PRE_CSC_LUT)
+ return drm_property_replace_blob(&plane_state->hw.degamma_lut, blob);
+ else if (intel_colorop->id == INTEL_PLANE_CB_POST_CSC_LUT)
+ return drm_property_replace_blob(&plane_state->hw.gamma_lut, blob);
return false;
}
--
2.50.1
next prev parent reply other threads:[~2025-11-05 12:23 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-05 12:33 [v6 00/16] Plane Color Pipeline support for Intel platforms Uma Shankar
2025-11-05 12:33 ` [v6 01/16] [NOT FOR REVIEW] drm: AMD series squashed Uma Shankar
2025-11-05 12:33 ` [v6 02/16] drm/i915: Add identifiers for driver specific blocks Uma Shankar
2025-11-11 9:20 ` Kandpal, Suraj
2025-11-05 12:33 ` [v6 03/16] drm/i915: Add intel_color_op Uma Shankar
2025-11-18 6:06 ` Kandpal, Suraj
2025-11-05 12:34 ` [v6 04/16] drm/i915/color: Add helper to create intel colorop Uma Shankar
2025-11-18 6:09 ` Kandpal, Suraj
2025-11-05 12:34 ` [v6 05/16] drm/i915/color: Create a transfer function color pipeline Uma Shankar
2025-11-18 6:23 ` Kandpal, Suraj
2025-11-05 12:34 ` [v6 06/16] drm/i915/color: Add framework to program CSC Uma Shankar
2025-11-18 8:24 ` Kandpal, Suraj
2025-11-18 8:52 ` Borah, Chaitanya Kumar
2025-11-18 8:55 ` Kandpal, Suraj
2025-11-05 12:34 ` [v6 07/16] drm/i915/color: Preserve sign bit when int_bits is Zero Uma Shankar
2025-11-18 6:29 ` Kandpal, Suraj
2025-11-05 12:34 ` [v6 08/16] drm/i915/color: Add plane CTM callback for D12 and beyond Uma Shankar
2025-11-05 12:34 ` [v6 09/16] drm/i915: Add register definitions for Plane Degamma Uma Shankar
2025-11-18 8:56 ` Kandpal, Suraj
2025-11-05 12:34 ` Uma Shankar [this message]
2025-11-18 8:30 ` [v6 10/16] drm/i915/color: Add framework to program PRE/POST CSC LUT Kandpal, Suraj
2025-11-05 12:34 ` [v6 11/16] drm/i915: Add register definitions for Plane Post CSC Uma Shankar
2025-11-05 12:34 ` [v6 12/16] drm/i915/color: Program Pre-CSC registers Uma Shankar
2025-11-18 9:03 ` Kandpal, Suraj
2025-11-19 8:14 ` Borah, Chaitanya Kumar
2025-11-05 12:34 ` [v6 13/16] drm/i915/xelpd: Program Plane Post CSC Registers Uma Shankar
2025-11-06 13:16 ` kernel test robot
2025-11-05 12:34 ` [v6 14/16] drm/i915/display: Add registers for 3D LUT Uma Shankar
2025-11-10 12:08 ` Jani Nikula
2025-11-11 8:39 ` Borah, Chaitanya Kumar
2025-11-18 8:36 ` Kandpal, Suraj
2025-11-05 12:34 ` [v6 15/16] drm/i915/color: Add 3D LUT to color pipeline Uma Shankar
2025-11-10 12:09 ` Jani Nikula
2025-11-11 8:39 ` Borah, Chaitanya Kumar
2025-11-11 9:02 ` Jani Nikula
2025-11-18 8:50 ` Kandpal, Suraj
2025-11-18 8:56 ` Borah, Chaitanya Kumar
2025-11-05 12:34 ` [v6 16/16] drm/i915/color: Enable Plane Color Pipelines Uma Shankar
2025-11-18 8:52 ` Kandpal, Suraj
2025-11-05 13:38 ` ✗ i915.CI.BAT: failure for Plane Color Pipeline support for Intel platforms (rev6) Patchwork
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