From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
Subject: [PATCH 02/16] drm/i915/de: Have intel_de_wait() hand out the final register value
Date: Mon, 10 Nov 2025 19:27:41 +0200 [thread overview]
Message-ID: <20251110172756.2132-3-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20251110172756.2132-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We currently have a bunch of places that want the final register
value after register polling. Currently those places are mostly
using intel_de_wait_custom(). That is not a function that we
want to keep around as it pretty much prevents conversion to
poll_timeout_us().
Have intel_de_wait() also return the final register value so
that some of the current users can be converted over to the
simpler interface.
Done with cocci:
@@
@@
int intel_de_wait(...
+ ,u32 *out_value
)
{
...
__intel_wait_for_register(...,
- NULL
+ out_value
)
...
}
@@
@@
intel_de_wait(...
+ ,NULL
)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_de.h | 8 ++++----
drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 2 +-
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index ea9973dbbffc..a4ad20030c09 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -116,14 +116,14 @@ __intel_de_wait_for_register_atomic_nowl(struct intel_display *display,
static inline int
intel_de_wait(struct intel_display *display, i915_reg_t reg,
- u32 mask, u32 value, unsigned int timeout_ms)
+ u32 mask, u32 value, unsigned int timeout_ms, u32 *out_value)
{
int ret;
intel_dmc_wl_get(display, reg);
ret = __intel_wait_for_register(__to_uncore(display), reg, mask,
- value, 2, timeout_ms, NULL);
+ value, 2, timeout_ms, out_value);
intel_dmc_wl_put(display, reg);
@@ -169,14 +169,14 @@ static inline int
intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg,
u32 mask, unsigned int timeout_ms)
{
- return intel_de_wait(display, reg, mask, mask, timeout_ms);
+ return intel_de_wait(display, reg, mask, mask, timeout_ms, NULL);
}
static inline int
intel_de_wait_for_clear(struct intel_display *display, i915_reg_t reg,
u32 mask, unsigned int timeout_ms)
{
- return intel_de_wait(display, reg, mask, 0, timeout_ms);
+ return intel_de_wait(display, reg, mask, 0, timeout_ms, NULL);
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index eab7019f2252..afa5d8964f0d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1446,7 +1446,7 @@ static void assert_chv_phy_status(struct intel_display *display)
* so the power state can take a while to actually change.
*/
if (intel_de_wait(display, DISPLAY_PHY_STATUS,
- phy_status_mask, phy_status, 10))
+ phy_status_mask, phy_status, 10, NULL))
drm_err(display->drm,
"Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
intel_de_read(display, DISPLAY_PHY_STATUS) & phy_status_mask,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index bd757db85927..27bb2199659f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -784,7 +784,7 @@ intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector,
/* Wait for encryption confirmation */
if (intel_de_wait(display, HDCP_STATUS(display, cpu_transcoder, port),
stream_enc_status, enable ? stream_enc_status : 0,
- HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS, NULL)) {
drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
transcoder_name(cpu_transcoder), str_enabled_disabled(enable));
return -ETIMEDOUT;
@@ -824,7 +824,7 @@ intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
if (intel_de_wait(display, HDCP2_STREAM_STATUS(display, cpu_transcoder, pipe),
STREAM_ENCRYPTION_STATUS,
enable ? STREAM_ENCRYPTION_STATUS : 0,
- HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS, NULL)) {
drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
transcoder_name(cpu_transcoder), str_enabled_disabled(enable));
return -ETIMEDOUT;
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 5df6347a420d..378f0836b5a5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -1193,7 +1193,7 @@ void vlv_wait_port_ready(struct intel_encoder *encoder,
break;
}
- if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000))
+ if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000, NULL))
drm_WARN(display->drm, 1,
"timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
encoder->base.base.id, encoder->base.name,
--
2.49.1
next prev parent reply other threads:[~2025-11-10 17:28 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-10 17:27 [PATCH 00/16] drm/i915/de: Register polling cleanup Ville Syrjala
2025-11-10 17:27 ` [PATCH 01/16] drm/i915/de: Implement register waits one way Ville Syrjala
2025-11-11 4:52 ` Kandpal, Suraj
2025-11-10 17:27 ` Ville Syrjala [this message]
2025-11-11 4:14 ` [PATCH 02/16] drm/i915/de: Have intel_de_wait() hand out the final register value Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 03/16] drm/i915/de: Include units in intel_de_wait*() function names Ville Syrjala
2025-11-11 4:21 ` Kandpal, Suraj
2025-11-11 17:45 ` Ville Syrjälä
2025-11-10 17:27 ` [PATCH 04/16] drm/i915/de: Introduce intel_de_wait_us() Ville Syrjala
2025-11-11 4:24 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 05/16] drm/i915/de: Use intel_de_wait_us() Ville Syrjala
2025-11-11 4:28 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 06/16] drm/i915/de: Use intel_de_wait_ms() for the obvious cases Ville Syrjala
2025-11-11 4:32 ` Kandpal, Suraj
2025-11-11 17:41 ` Ville Syrjälä
2025-11-10 17:27 ` [PATCH 07/16] drm/i915/de: Nuke intel_de_wait_custom() Ville Syrjala
2025-11-11 4:33 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 08/16] drm/i915/de: Introduce intel_de_wait_for_{set, clear}_us() Ville Syrjala
2025-11-11 4:35 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 09/16] drm/i915/de: Use intel_de_wait_for_{set,clear}_us() Ville Syrjala
2025-11-11 4:38 ` [PATCH 09/16] drm/i915/de: Use intel_de_wait_for_{set, clear}_us() Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 10/16] drm/i915/de: Use intel_de_wait_for_{set,clear}_ms() Ville Syrjala
2025-11-11 4:39 ` [PATCH 10/16] drm/i915/de: Use intel_de_wait_for_{set, clear}_ms() Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 11/16] drm/1915/dpio: Stop using intel_de_wait_fw_ms() Ville Syrjala
2025-11-11 4:41 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 12/16] drm/u195/de: Replace __intel_de_rmw_nowl() with intel_de_rmw_fw() Ville Syrjala
2025-11-11 4:44 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 13/16] drm/i915/de: Nuke wakelocks from intel_de_wait_fw_ms() Ville Syrjala
2025-11-11 4:45 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 14/16] drm/i915/de: Replace __intel_de_wait_for_register_nowl() with intel_de_wait_fw_us_atomic() Ville Syrjala
2025-11-11 4:46 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 15/16] drm/i915/power: Use the intel_de_wait_ms() out value Ville Syrjala
2025-11-11 4:48 ` Kandpal, Suraj
2025-11-10 17:27 ` [PATCH 16/16] drm/i915/dpio: " Ville Syrjala
2025-11-11 4:50 ` Kandpal, Suraj
2025-11-10 21:24 ` ✓ i915.CI.BAT: success for drm/i915/de: Register polling cleanup Patchwork
2025-11-11 3:41 ` ✗ i915.CI.Full: failure " Patchwork
2025-11-11 8:01 ` [PATCH 00/16] " Jani Nikula
2025-11-11 16:11 ` Ville Syrjälä
2025-11-11 19:09 ` Ville Syrjälä
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