Re: [PATCH 08/10] drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n ratio > 10

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The `bypass_m_n_ratio_limit` flag is not reset to `false` when recomputing M/N parameters, causing it to leak across atomic modesets and permanently disable DRRS and seamless M/N fastsets, while incorrectly programming hardware for subsequent modes.
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commit 1051e6f37ea4e4c3629ed1e93206c237d8286159
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n ratio > 10

This commit implements the bypass logic for the M/N ratio limit for DP on 
128b/132b links. It calculates the M/N ratio, sets the appropriate flags for 
the workaround, and disables DRRS and seamless M/N fastsets when active.

> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 585762be07bb2..27ffd937c75f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
[ ... ]
> @@ -3385,10 +3389,21 @@ void intel_dp_check_m_n_ratio(struct intel_crtc_state *crtc_state,
>  
>  	m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
>  
> -	if (m_n_ratio > max_m_n_ratio)
> -		drm_WARN(display->drm, 1,
> -			 "Link M/N ratio (%d) exceeds max allowed (%d)\n",
> -			 m_n_ratio, max_m_n_ratio);
> +	if (m_n_ratio <= max_m_n_ratio)
> +		return;

[Severity: High]
When returning early here, should we explicitly reset the
bypass_m_n_ratio_limit flag to false?

Because atomic modesets duplicate the CRTC state, if a user previously
applied a high-bandwidth UHBR mode that set bypass_m_n_ratio_limit to true,
changing to a lower-resolution mode would carry this true flag over into the
new state.

Neither intel_link_compute_m_n() nor the early return or fall-through paths
in intel_dp_check_m_n_ratio() seem to clear this flag. Could this state leak
permanently disable DRRS and seamless M/N updates for that connector, and
potentially lead to incorrectly programming the hardware for non-UHBR modes?

> +
> +	if (intel_dp_is_uhbr(crtc_state) &&
> +	    intel_display_can_bypass_m_n_limit(display, m_n_ratio, crtc->pipe)) {
> +		m_n->bypass_m_n_ratio_limit = true;
> +		drm_dbg_kms(display->drm,
> +			    "Bypassing Link_m/Link_n ratio limit (ratio %d)\n",
> +			    m_n_ratio);
> +		return;
> +	}
> +
> +	drm_WARN(display->drm, 1,
> +		 "Link M/N ratio (%d) exceeds max allowed (%d)\n",
> +		 m_n_ratio, max_m_n_ratio);
>  }
>  
>  static void

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Sashiko AI review · https://sashiko.dev/#/patchset/20260911041449.3699400-1-suraj.kandpal@intel.com?part=8