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* [PATCH] drm/i915/panel: Only consider seamless DRRS modes as the highest mode
@ 2026-09-14  8:55 Fred Gao
  2026-09-14 15:16 ` ✗ i915.CI.BAT: failure for " Patchwork
  0 siblings, 1 reply; 5+ messages in thread
From: Fred Gao @ 2026-09-14  8:55 UTC (permalink / raw)
  To: intel-gfx
  Cc: intel-xe, dri-devel, linux-kernel, jani.nikula, rodrigo.vivi,
	joonas.lahtinen, tursulin, ville.syrjala, Fred Gao, stable,
	Chenchen Wang

intel_dp_mode_clock() uses intel_panel_highest_mode() when seamless M/N
updates are supported, so that the link configuration can accommodate
every refresh rate DRRS may seamlessly switch to.

However, the fixed mode list is populated using is_alt_fixed_mode(),
which only requires a matching active size and non-sync flags. Whether a
mode can actually be reached with a seamless M/N update is decided by
intel_panel_downclock_mode() using is_alt_drrs_mode(), which requires
matching timings and flags. intel_panel_highest_mode() used neither and
simply picked the highest clock in the list. A mode reachable only with a
full modeset could therefore inflate the reserved bandwidth and
needlessly reduce the selected bpp.

On a 5120x2160 eDP panel the DisplayID preferred mode uses 717260 kHz,
while a CTA mode with different blanking uses 742500 kHz. With HBR2 x4,
2160000 kB/s is available. The preferred mode fits at 24 bpp:

  717260 * 24 / 8 = 2151780 kB/s

but the CTA mode does not:

  742500 * 24 / 8 = 2227500 kB/s

Selecting the CTA clock therefore reduces the link configuration to 18
bpp. The firmware state is 24 bpp, so the mismatch forces a full modeset
and an eDP backlight and panel power cycle during driver takeover.

Use is_alt_drrs_mode() so intel_panel_highest_mode() considers the same
set of modes as intel_panel_downclock_mode(). Bandwidth is still reserved
for genuine seamless DRRS alternatives, including when userspace selects
the downclock mode as the active mode, while modes that require a full
modeset no longer affect the result. If no fixed mode is compatible, the
helper continues to return the adjusted mode.

Fixes: e6f29923c048 ("drm/i915: Allow M/N change during fastset on bdw+")
Cc: <stable@vger.kernel.org>
Signed-off-by: Fred Gao <fred.gao@intel.com>
Reviewed-by: Chenchen Wang <chenchen.wang@intel.com>
---
 drivers/gpu/drm/i915/display/intel_panel.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 81e638d0c7b3..343bd8439566 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -192,7 +192,8 @@ intel_panel_highest_mode(struct intel_connector *connector,
 
-	/* pick the fixed_mode that has the highest clock */
+	/* pick the highest clock we can seamlessly switch to */
 	list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head) {
-		if (fixed_mode->clock > best_mode->clock)
+		if (is_alt_drrs_mode(fixed_mode, adjusted_mode) &&
+		    fixed_mode->clock > best_mode->clock)
 			best_mode = fixed_mode;
 	}
 
-- 
2.43.0

^ permalink raw reply related	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2026-09-17  1:49 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2026-09-14  8:55 [PATCH] drm/i915/panel: Only consider seamless DRRS modes as the highest mode Fred Gao
2026-09-14 15:16 ` ✗ i915.CI.BAT: failure for " Patchwork
2026-09-15  5:56   ` Gao, Fred
2026-09-15  8:53     ` Jani Nikula
2026-09-17  1:49       ` Gao, Fred

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