[PATCH] drm/i915/panel: Only consider seamless DRRS modes as the highest mode

[PATCH] drm/i915/panel: Only consider seamless DRRS modes as the highest mode

[Fred Gao]

intel_dp_mode_clock() uses intel_panel_highest_mode() when seamless M/N
updates are supported, so that the link configuration can accommodate
every refresh rate DRRS may seamlessly switch to.

However, the fixed mode list is populated using is_alt_fixed_mode(),
which only requires a matching active size and non-sync flags. Whether a
mode can actually be reached with a seamless M/N update is decided by
intel_panel_downclock_mode() using is_alt_drrs_mode(), which requires
matching timings and flags. intel_panel_highest_mode() used neither and
simply picked the highest clock in the list. A mode reachable only with a
full modeset could therefore inflate the reserved bandwidth and
needlessly reduce the selected bpp.

On a 5120x2160 eDP panel the DisplayID preferred mode uses 717260 kHz,
while a CTA mode with different blanking uses 742500 kHz. With HBR2 x4,
2160000 kB/s is available. The preferred mode fits at 24 bpp:

  717260 * 24 / 8 = 2151780 kB/s

but the CTA mode does not:

  742500 * 24 / 8 = 2227500 kB/s

Selecting the CTA clock therefore reduces the link configuration to 18
bpp. The firmware state is 24 bpp, so the mismatch forces a full modeset
and an eDP backlight and panel power cycle during driver takeover.

Use is_alt_drrs_mode() so intel_panel_highest_mode() considers the same
set of modes as intel_panel_downclock_mode(). Bandwidth is still reserved
for genuine seamless DRRS alternatives, including when userspace selects
the downclock mode as the active mode, while modes that require a full
modeset no longer affect the result. If no fixed mode is compatible, the
helper continues to return the adjusted mode.

Fixes: e6f29923c048 ("drm/i915: Allow M/N change during fastset on bdw+")
Cc: <stable@vger.kernel.org>
Signed-off-by: Fred Gao <fred.gao@intel.com>
Reviewed-by: Chenchen Wang <chenchen.wang@intel.com>
---
 drivers/gpu/drm/i915/display/intel_panel.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 81e638d0c7b3..343bd8439566 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -192,7 +192,8 @@ intel_panel_highest_mode(struct intel_connector *connector,
 
-	/* pick the fixed_mode that has the highest clock */
+	/* pick the highest clock we can seamlessly switch to */
 	list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head) {
-		if (fixed_mode->clock > best_mode->clock)
+		if (is_alt_drrs_mode(fixed_mode, adjusted_mode) &&
+		    fixed_mode->clock > best_mode->clock)
 			best_mode = fixed_mode;
 	}
 
-- 
2.43.0

✗ i915.CI.BAT: failure for drm/i915/panel: Only consider seamless DRRS modes as the highest mode

[Patchwork]

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== Series Details ==

Series: drm/i915/panel: Only consider seamless DRRS modes as the highest mode
URL   : https://patchwork.freedesktop.org/series/174025/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_19141 -> Patchwork_174025v1
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_174025v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_174025v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_174025v1/index.html

Participating hosts (39 -> 37)
------------------------------

  Missing    (2): bat-dg2-13 bat-adls-6 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_174025v1:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@guc_hang:
    - bat-arlh-2:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19141/bat-arlh-2/igt@i915_selftest@live@guc_hang.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_174025v1/bat-arlh-2/igt@i915_selftest@live@guc_hang.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-skl-6600u:       [PASS][3] -> [DMESG-WARN][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19141/fi-skl-6600u/igt@kms_frontbuffer_tracking@basic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_174025v1/fi-skl-6600u/igt@kms_frontbuffer_tracking@basic.html

  
Known issues
------------

  Here are the changes found in Patchwork_174025v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live:
    - bat-arlh-2:         [PASS][5] -> [INCOMPLETE][6] ([i915#16547])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19141/bat-arlh-2/igt@i915_selftest@live.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_174025v1/bat-arlh-2/igt@i915_selftest@live.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@gt_heartbeat:
    - bat-apl-1:          [ABORT][7] -> [PASS][8] +1 other test pass
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19141/bat-apl-1/igt@i915_selftest@live@gt_heartbeat.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_174025v1/bat-apl-1/igt@i915_selftest@live@gt_heartbeat.html

  
  [i915#16547]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16547


Build changes
-------------

  * Linux: CI_DRM_19141 -> Patchwork_174025v1

  CI-20190529: 20190529
  CI_DRM_19141: 4f03eb1cbe37cc93b33d654828cf49b58d9e2bdc @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_9093: 932327f15c92ecb52266ced8c0fbe72931a75880 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_174025v1: 4f03eb1cbe37cc93b33d654828cf49b58d9e2bdc @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_174025v1/index.html

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RE: ✗ i915.CI.BAT: failure for drm/i915/panel: Only consider seamless DRRS modes as the highest mode

[Gao, Fred]

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Hi I915 CI infra team,
   The below 2 issues are not related to my display patch, pls double check

Possible regressions

  *   igt@i915_selftest@live@guc_hang:
     *   bat-arlh-2: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19141/bat-arlh-2/igt@i915_selftest@live@guc_hang.html> -> INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_174025v1/bat-arlh-2/igt@i915_selftest@live@guc_hang.html>
[Fred]
Putting the full picture together now:
Baseline (CI_DRM_19141)
Patched (Patchwork_174025v1)
hangcheck suite (deliberate hang/reset/reload cycles)
runs fine, same pattern
identical pattern, same timestamps
slpc suite → live_slpc_power
starts 470.2s, completes ~3.6s later, suite SUCCESS @477s
starts 468.0s, log dies mid-test @469.4s — no crash message, just stops
guc_hang
starts 487.1s, SUCCESS @493.7s
never reached — machine already unresponsive
eDP/display activity anywhere in the run
link never established (failed to retrieve link info, disabling eDP, pipe A enable: no throughout)
identical — link never established, pipe A enable: no throughout
fixed_modes/panel_highest/is_alt_drrs (the patch's code)
0 occurrences
0 occurrences
So, direct answer: no display-related change is exercised anywhere in this dmesg, in either tree. The eDP connector fails to link on this bench rig in both baseline and patched runs, so intel_panel_highest_mode()/is_alt_drrs_mode() never execute — the patch's code is dead code for this entire test. The actual divergence is a hard hang in intel_slpc_live_selftests/live_slpc_power, a GuC frequency/power-governor selftest with zero relation to display/DRRS. Since the patch touches only display panel-mode selection and that path is never reached, guc_hang's INCOMPLETE status is unrelated to this patch — it's a GuC/SLPC-side hang (likely bat-arlh-2 hardware/firmware flakiness) that happens to occur before the guc_hang subtest is even scheduled to run.


  *   igt@kms_frontbuffer_tracking@basic:
     *   fi-skl-6600u: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19141/fi-skl-6600u/igt@kms_frontbuffer_tracking@basic.html> -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_174025v1/fi-skl-6600u/igt@kms_frontbuffer_tracking@basic.html>


[Fred]  dmesg log<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_174025v1/bat-arlh-2/dmesg0.txt> &  PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19141/bat-arlh-2/igt@i915_selftest@live@guc_hang.html> VS INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_174025v1/bat-arlh-2/igt@i915_selftest@live@guc_hang.html> log shows:

  *   Direct A/B comparison of the two dmesg logs, same machine, same test:
Baseline (CI_DRM_19141)
Patched (Patchwork_174025v1)
pixel clock
373250 kHz
373250 kHz
port_clock / lane count
540000, 4x
540000, 4x
max pipe_bpp / link_bpp
24 (min link_bpp 18.0, max 24.0)
24
subtest result
SUCCESS, ret=0
SUCCESS
"Atomic update failure" occurrences (whole boot)
0
1

  *   The link configuration — pixel clock, bpp, M/N values — is byte-identical between the pre-patch and post-patch runs. That's the direct proof the patch changed nothing on this machine: intel_panel_highest_mode() picked the same 373250 kHz fixed mode either way.
  *   That tracks with the panel's fixed-mode list from the display-info dump:
  *   "3200x1800": 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
  *   "3200x1800": 48 298600 3200 3248 3280 3360 1800 1803 1808 1852 0x40 0xa
Both entries share identical blanking (3200 3248 3280 3360 1800 1803 1808 1852) — this is a genuine high/low-refresh DRRS pair, not the "alternate CTA mode with different blanking" case the patch's is_alt_drrs_mode() filter is designed to exclude. So the filter is a no-op here regardless of its exact matching semantics: the two candidate modes were never in conflict on this panel, and 373250 (the higher clock) wins the max-clock comparison with or without the new condition.



From: Patchwork <patchwork@emeril.freedesktop.org>
Sent: Monday, September 14, 2026 11:17 PM
To: Gao, Fred <fred.gao@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ i915.CI.BAT: failure for drm/i915/panel: Only consider seamless DRRS modes as the highest mode

Patch Details
Series:
drm/i915/panel: Only consider seamless DRRS modes as the highest mode
URL:
https://patchwork.freedesktop.org/series/174025/
State:
failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_174025v1/index.html
CI Bug Log - changes from CI_DRM_19141 -> Patchwork_174025v1
Summary

FAILURE

Serious unknown changes coming with Patchwork_174025v1 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_174025v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org<mailto:I915-ci-infra@lists.freedesktop.org>) to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_174025v1/index.html

Participating hosts (39 -> 37)

Missing (2): bat-dg2-13 bat-adls-6

Possible new issues

Here are the unknown changes that may have been introduced in Patchwork_174025v1:

IGT changes
Possible regressions

  *   igt@i915_selftest@live@guc_hang:

     *   bat-arlh-2: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19141/bat-arlh-2/igt@i915_selftest@live@guc_hang.html> -> INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_174025v1/bat-arlh-2/igt@i915_selftest@live@guc_hang.html>

  *   igt@kms_frontbuffer_tracking@basic:

     *   fi-skl-6600u: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19141/fi-skl-6600u/igt@kms_frontbuffer_tracking@basic.html> -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_174025v1/fi-skl-6600u/igt@kms_frontbuffer_tracking@basic.html>

Known issues

Here are the changes found in Patchwork_174025v1 that come from known issues:

IGT changes
Issues hit

  *   igt@i915_selftest@live:

     *   bat-arlh-2: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19141/bat-arlh-2/igt@i915_selftest@live.html> -> INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_174025v1/bat-arlh-2/igt@i915_selftest@live.html> (i915#16547<https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16547>)

Possible fixes

  *   igt@i915_selftest@live@gt_heartbeat:

     *   bat-apl-1: ABORT<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19141/bat-apl-1/igt@i915_selftest@live@gt_heartbeat.html> -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_174025v1/bat-apl-1/igt@i915_selftest@live@gt_heartbeat.html> +1 other test pass

Build changes

  *   Linux: CI_DRM_19141 -> Patchwork_174025v1

CI-20190529: 20190529
CI_DRM_19141: 4f03eb1cbe37cc93b33d654828cf49b58d9e2bdc @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_9093: 932327f15c92ecb52266ced8c0fbe72931a75880 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_174025v1: 4f03eb1cbe37cc93b33d654828cf49b58d9e2bdc @ git://anongit.freedesktop.org/gfx-ci/linux

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RE: ✗ i915.CI.BAT: failure for drm/i915/panel: Only consider seamless DRRS modes as the highest mode

[Jani Nikula]

On Tue, 15 Sep 2026, "Gao, Fred" <fred.gao@intel.com> wrote:
> Hi I915 CI infra team,
>    The below 2 issues are not related to my display patch, pls double check

Please use plain text and proper quoting when interacting on the public
mailing list.

BR,
Jani.


-- 
Jani Nikula, Intel

RE: ✗ i915.CI.BAT: failure for drm/i915/panel: Only consider seamless DRRS modes as the highest mode

[Gao, Fred]

Thanks Jani for the reminder.

Hi I915 CI infra team,	

The two reported regressions are unrelated to this display patch. Detailed
analysis for each failure is provided below.

> Possible regressions
>
> * igt@i915_selftest@live@guc_hang:
>   * bat-arlh-2: PASS -> INCOMPLETE
>     https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_174025v1/bat-arlh-2/igt@i915_selftest@live@guc_hang.html

Looking at the execution logs between baseline (CI_DRM_19141) and patched
(Patchwork_174025v1):

Test Suite / Event          Baseline (CI_DRM_19141)  Patched (Patchwork_174025v1)
--------------------------        -----------------------         ----------------------------
hangcheck suite           SUCCESS (identical)       SUCCESS (identical)
live_slpc_power           Starts 470.2s, PASS        Starts 468.0s, hard hang @469.4s
guc_hang                Starts 487.1s, PASS        Never reached (rig hung)
eDP link status            Link failed (pipe A off)     Link failed (pipe A off)
is_alt_drrs / panel_highest  0 occurrences            0 occurrences

No display paths were exercised during this execution. The eDP link failed
to train on this test bench in both the baseline and patched runs, meaning
intel_panel_highest_mode() and is_alt_drrs_mode() were never invoked.

The failure was caused by a hard lockup inside intel_slpc_live_selftests
(live_slpc_power) at timestamp 469.4s, which is an unrelated GuC SLPC
frequency/governor selftest. The guc_hang subtest was never scheduled.
Please treat this as an environmental/GuC-side flake.

> * igt@kms_frontbuffer_tracking@basic:
>   * fi-skl-6600u: PASS -> DMESG-WARN
>     https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_174025v1/fi-skl-6600u/igt@kms_frontbuffer_tracking@basic.html

Direct comparison of the dmesg output between baseline and patched runs
shows identical mode programming:

Parameter               Baseline (CI_DRM_19141)   Patched (Patchwork_174025v1)
--------------------------        -----------------------          ----------------------------
Pixel Clock                373250 kHz              373250 kHz
Port Clock / Lanes          540000 kHz, 4x           540000 kHz, 4x
Max Pipe / Link BPP         24 bpp                  24 bpp
Subtest Return Code        SUCCESS (ret=0)          SUCCESS (ret=0)
Atomic update failures       0                      1 (dmesg-warn)

The link parameters and timing registers selected by intel_panel_highest_mode()
are identical across both runs.

The panel exposes the following fixed modes:
  "3200x1800": 60 373250 3200 3248 3280 3360 1800 1803 1808 1852 0x48 0xa
  "3200x1800": 48 298600 3200 3248 3280 3360 1800 1803 1808 1852 0x40 0xa

Both modes share identical blanking timings (3200 3248 3280 3360 1800 1803
1808 1852). This is a standard high/low refresh DRRS pair rather than an
alternate CTA mode with different blanking. Consequently, is_alt_drrs_mode()
is a no-op here, and 373250 kHz is selected in both trees.

The subtest completed with return code 0; the DMESG-WARN was triggered by an
isolated atomic update timing glitch unrelated to panel mode selection.

Thanks,
Fred
> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Tuesday, September 15, 2026 4:54 PM
> To: Gao, Fred <fred.gao@intel.com>; intel-gfx@lists.freedesktop.org;
> I915-ci-infra@lists.freedesktop.org
> Cc: Wang, Chenchen <chenchen.wang@intel.com>
> Subject: RE: ✗ i915.CI.BAT: failure for drm/i915/panel: Only consider seamless
> DRRS modes as the highest mode
> 
> On Tue, 15 Sep 2026, "Gao, Fred" <fred.gao@intel.com> wrote:
> > Hi I915 CI infra team,
> >    The below 2 issues are not related to my display patch, pls double
> > check
> 
> Please use plain text and proper quoting when interacting on the public mailing
> list.
> 
> BR,
> Jani.
> 
> 
> --
> Jani Nikula, Intel