* [Intel-gfx] [PATCH 1/3] drm/i915/guc: Update context registration to new GuC API
2022-04-08 18:03 [Intel-gfx] [PATCH 0/3] Update to GuC v70 John.C.Harrison
@ 2022-04-08 18:03 ` John.C.Harrison
2022-04-12 0:13 ` Ceraolo Spurio, Daniele
2022-04-08 18:03 ` [Intel-gfx] [PATCH 2/3] drm/i915/guc: Update scheduling policies " John.C.Harrison
` (5 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: John.C.Harrison @ 2022-04-08 18:03 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
The latest GuC firmware drops the context descriptor pool in favour of
passing all creation data in the create H2G. It also greatly simplifies
the work queue and removes the process descriptor used for multi-LRC
submission. So, remove all mention of LRC and process descriptors and
update the registration code accordingly.
Unfortunately, the new API also removes the ability to set default
values for the scheduling policies at context registration time.
Instead, a follow up H2G must be sent. This will be addressed in the
next patch.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 5 -
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 52 ++---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 221 ++++++++----------
3 files changed, 116 insertions(+), 162 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 4e431c14b118..3f3373f68123 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -170,11 +170,6 @@ struct intel_guc {
/** @ads_engine_usage_size: size of engine usage in the ADS */
u32 ads_engine_usage_size;
- /** @lrc_desc_pool: object allocated to hold the GuC LRC descriptor pool */
- struct i915_vma *lrc_desc_pool;
- /** @lrc_desc_pool_vaddr: contents of the GuC LRC descriptor pool */
- void *lrc_desc_pool_vaddr;
-
/**
* @context_lookup: used to resolve intel_context from guc_id, if a
* context is present in this structure it is registered with the GuC
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index f21b6de46a99..0e1e8d0079b5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -197,20 +197,28 @@ struct guc_wq_item {
u32 fence_id;
} __packed;
-struct guc_process_desc {
- u32 stage_id;
- u64 db_base_addr;
+struct guc_sched_wq_desc {
u32 head;
u32 tail;
u32 error_offset;
- u64 wq_base_addr;
- u32 wq_size_bytes;
u32 wq_status;
- u32 engine_presence;
- u32 priority;
- u32 reserved[36];
+ u32 reserved[28];
} __packed;
+/* Helper for context registration H2G */
+struct guc_ctxt_registration_info {
+ u32 flags;
+ u32 context_idx;
+ u32 engine_class;
+ u32 engine_submit_mask;
+ u32 wq_desc_lo;
+ u32 wq_desc_hi;
+ u32 wq_base_lo;
+ u32 wq_base_hi;
+ u32 wq_size;
+ u32 hwlrca_lo;
+ u32 hwlrca_hi;
+};
#define CONTEXT_REGISTRATION_FLAG_KMD BIT(0)
#define CONTEXT_POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000
@@ -219,34 +227,6 @@ struct guc_process_desc {
/* Preempt to idle on quantum expiry */
#define CONTEXT_POLICY_FLAG_PREEMPT_TO_IDLE BIT(0)
-/*
- * GuC Context registration descriptor.
- * FIXME: This is only required to exist during context registration.
- * The current 1:1 between guc_lrc_desc and LRCs for the lifetime of the LRC
- * is not required.
- */
-struct guc_lrc_desc {
- u32 hw_context_desc;
- u32 slpm_perf_mode_hint; /* SPLC v1 only */
- u32 slpm_freq_hint;
- u32 engine_submit_mask; /* In logical space */
- u8 engine_class;
- u8 reserved0[3];
- u32 priority;
- u32 process_desc;
- u32 wq_addr;
- u32 wq_size;
- u32 context_flags; /* CONTEXT_REGISTRATION_* */
- /* Time for one workload to execute. (in micro seconds) */
- u32 execution_quantum;
- /* Time to wait for a preemption request to complete before issuing a
- * reset. (in micro seconds).
- */
- u32 preemption_timeout;
- u32 policy_flags; /* CONTEXT_POLICY_* */
- u32 reserved1[19];
-} __packed;
-
#define GUC_POWER_UNSPECIFIED 0
#define GUC_POWER_D0 1
#define GUC_POWER_D1 2
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index e1612c393781..bd0584d7d489 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -396,12 +396,12 @@ struct sync_semaphore {
};
struct parent_scratch {
- struct guc_process_desc pdesc;
+ struct guc_sched_wq_desc wq_desc;
struct sync_semaphore go;
struct sync_semaphore join[MAX_ENGINE_INSTANCE + 1];
- u8 unused[WQ_OFFSET - sizeof(struct guc_process_desc) -
+ u8 unused[WQ_OFFSET - sizeof(struct guc_sched_wq_desc) -
sizeof(struct sync_semaphore) * (MAX_ENGINE_INSTANCE + 2)];
u32 wq[WQ_SIZE / sizeof(u32)];
@@ -438,15 +438,15 @@ __get_parent_scratch(struct intel_context *ce)
LRC_STATE_OFFSET) / sizeof(u32)));
}
-static struct guc_process_desc *
-__get_process_desc(struct intel_context *ce)
+static struct guc_sched_wq_desc *
+__get_wq_desc(struct intel_context *ce)
{
struct parent_scratch *ps = __get_parent_scratch(ce);
- return &ps->pdesc;
+ return &ps->wq_desc;
}
-static u32 *get_wq_pointer(struct guc_process_desc *desc,
+static u32 *get_wq_pointer(struct guc_sched_wq_desc *wq_desc,
struct intel_context *ce,
u32 wqi_size)
{
@@ -458,7 +458,7 @@ static u32 *get_wq_pointer(struct guc_process_desc *desc,
#define AVAILABLE_SPACE \
CIRC_SPACE(ce->parallel.guc.wqi_tail, ce->parallel.guc.wqi_head, WQ_SIZE)
if (wqi_size > AVAILABLE_SPACE) {
- ce->parallel.guc.wqi_head = READ_ONCE(desc->head);
+ ce->parallel.guc.wqi_head = READ_ONCE(wq_desc->head);
if (wqi_size > AVAILABLE_SPACE)
return NULL;
@@ -468,15 +468,6 @@ static u32 *get_wq_pointer(struct guc_process_desc *desc,
return &__get_parent_scratch(ce)->wq[ce->parallel.guc.wqi_tail / sizeof(u32)];
}
-static struct guc_lrc_desc *__get_lrc_desc(struct intel_guc *guc, u32 index)
-{
- struct guc_lrc_desc *base = guc->lrc_desc_pool_vaddr;
-
- GEM_BUG_ON(index >= GUC_MAX_CONTEXT_ID);
-
- return &base[index];
-}
-
static inline struct intel_context *__get_context(struct intel_guc *guc, u32 id)
{
struct intel_context *ce = xa_load(&guc->context_lookup, id);
@@ -486,39 +477,11 @@ static inline struct intel_context *__get_context(struct intel_guc *guc, u32 id)
return ce;
}
-static int guc_lrc_desc_pool_create(struct intel_guc *guc)
-{
- u32 size;
- int ret;
-
- size = PAGE_ALIGN(sizeof(struct guc_lrc_desc) *
- GUC_MAX_CONTEXT_ID);
- ret = intel_guc_allocate_and_map_vma(guc, size, &guc->lrc_desc_pool,
- (void **)&guc->lrc_desc_pool_vaddr);
- if (ret)
- return ret;
-
- return 0;
-}
-
-static void guc_lrc_desc_pool_destroy(struct intel_guc *guc)
-{
- guc->lrc_desc_pool_vaddr = NULL;
- i915_vma_unpin_and_release(&guc->lrc_desc_pool, I915_VMA_RELEASE_MAP);
-}
-
static inline bool guc_submission_initialized(struct intel_guc *guc)
{
return guc->submission_initialized;
}
-static inline void _reset_lrc_desc(struct intel_guc *guc, u32 id)
-{
- struct guc_lrc_desc *desc = __get_lrc_desc(guc, id);
-
- memset(desc, 0, sizeof(*desc));
-}
-
static inline bool ctx_id_mapped(struct intel_guc *guc, u32 id)
{
return __get_context(guc, id);
@@ -545,8 +508,6 @@ static inline void clr_ctx_id_mapping(struct intel_guc *guc, u32 id)
if (unlikely(!guc_submission_initialized(guc)))
return;
- _reset_lrc_desc(guc, id);
-
/*
* xarray API doesn't have xa_erase_irqsave wrapper, so calling
* the lower level functions directly.
@@ -751,7 +712,7 @@ static u32 wq_space_until_wrap(struct intel_context *ce)
return (WQ_SIZE - ce->parallel.guc.wqi_tail);
}
-static void write_wqi(struct guc_process_desc *desc,
+static void write_wqi(struct guc_sched_wq_desc *wq_desc,
struct intel_context *ce,
u32 wqi_size)
{
@@ -764,13 +725,13 @@ static void write_wqi(struct guc_process_desc *desc,
ce->parallel.guc.wqi_tail = (ce->parallel.guc.wqi_tail + wqi_size) &
(WQ_SIZE - 1);
- WRITE_ONCE(desc->tail, ce->parallel.guc.wqi_tail);
+ WRITE_ONCE(wq_desc->tail, ce->parallel.guc.wqi_tail);
}
static int guc_wq_noop_append(struct intel_context *ce)
{
- struct guc_process_desc *desc = __get_process_desc(ce);
- u32 *wqi = get_wq_pointer(desc, ce, wq_space_until_wrap(ce));
+ struct guc_sched_wq_desc *wq_desc = __get_wq_desc(ce);
+ u32 *wqi = get_wq_pointer(wq_desc, ce, wq_space_until_wrap(ce));
u32 len_dw = wq_space_until_wrap(ce) / sizeof(u32) - 1;
if (!wqi)
@@ -789,7 +750,7 @@ static int __guc_wq_item_append(struct i915_request *rq)
{
struct intel_context *ce = request_to_scheduling_context(rq);
struct intel_context *child;
- struct guc_process_desc *desc = __get_process_desc(ce);
+ struct guc_sched_wq_desc *wq_desc = __get_wq_desc(ce);
unsigned int wqi_size = (ce->parallel.number_children + 4) *
sizeof(u32);
u32 *wqi;
@@ -809,7 +770,7 @@ static int __guc_wq_item_append(struct i915_request *rq)
return ret;
}
- wqi = get_wq_pointer(desc, ce, wqi_size);
+ wqi = get_wq_pointer(wq_desc, ce, wqi_size);
if (!wqi)
return -EBUSY;
@@ -824,7 +785,7 @@ static int __guc_wq_item_append(struct i915_request *rq)
for_each_child(ce, child)
*wqi++ = child->ring->tail / sizeof(u64);
- write_wqi(desc, ce, wqi_size);
+ write_wqi(wq_desc, ce, wqi_size);
return 0;
}
@@ -1812,20 +1773,10 @@ static void reset_fail_worker_func(struct work_struct *w);
int intel_guc_submission_init(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
- int ret;
if (guc->submission_initialized)
return 0;
- ret = guc_lrc_desc_pool_create(guc);
- if (ret)
- return ret;
- /*
- * Keep static analysers happy, let them know that we allocated the
- * vma after testing that it didn't exist earlier.
- */
- GEM_BUG_ON(!guc->lrc_desc_pool);
-
guc->submission_state.guc_ids_bitmap =
bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL);
if (!guc->submission_state.guc_ids_bitmap)
@@ -1844,7 +1795,6 @@ void intel_guc_submission_fini(struct intel_guc *guc)
return;
guc_flush_destroyed_contexts(guc);
- guc_lrc_desc_pool_destroy(guc);
i915_sched_engine_put(guc->sched_engine);
bitmap_free(guc->submission_state.guc_ids_bitmap);
guc->submission_initialized = false;
@@ -2104,63 +2054,88 @@ static void unpin_guc_id(struct intel_guc *guc, struct intel_context *ce)
static int __guc_action_register_multi_lrc(struct intel_guc *guc,
struct intel_context *ce,
- u32 guc_id,
- u32 offset,
+ struct guc_ctxt_registration_info *info,
bool loop)
{
struct intel_context *child;
- u32 action[4 + MAX_ENGINE_INSTANCE];
+ u32 action[13 + (MAX_ENGINE_INSTANCE * 2)];
int len = 0;
+ u32 next_id;
GEM_BUG_ON(ce->parallel.number_children > MAX_ENGINE_INSTANCE);
action[len++] = INTEL_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC;
- action[len++] = guc_id;
+ action[len++] = info->flags;
+ action[len++] = info->context_idx;
+ action[len++] = info->engine_class;
+ action[len++] = info->engine_submit_mask;
+ action[len++] = info->wq_desc_lo;
+ action[len++] = info->wq_desc_hi;
+ action[len++] = info->wq_base_lo;
+ action[len++] = info->wq_base_hi;
+ action[len++] = info->wq_size;
action[len++] = ce->parallel.number_children + 1;
- action[len++] = offset;
+ action[len++] = info->hwlrca_lo;
+ action[len++] = info->hwlrca_hi;
+
+ next_id = info->context_idx + 1;
for_each_child(ce, child) {
- offset += sizeof(struct guc_lrc_desc);
- action[len++] = offset;
+ GEM_BUG_ON(next_id++ != child->guc_id.id);
+
+ /*
+ * NB: GuC interface supports 64 bit LRCA even though i915
+ * only supports 32 bit currently.
+ */
+ action[len++] = lower_32_bits(child->lrc.lrca);
+ action[len++] = upper_32_bits(child->lrc.lrca);
}
+ GEM_BUG_ON(len > ARRAY_SIZE(action));
+
return guc_submission_send_busy_loop(guc, action, len, 0, loop);
}
static int __guc_action_register_context(struct intel_guc *guc,
- u32 guc_id,
- u32 offset,
+ struct guc_ctxt_registration_info *info,
bool loop)
{
u32 action[] = {
INTEL_GUC_ACTION_REGISTER_CONTEXT,
- guc_id,
- offset,
+ info->flags,
+ info->context_idx,
+ info->engine_class,
+ info->engine_submit_mask,
+ info->wq_desc_lo,
+ info->wq_desc_hi,
+ info->wq_base_lo,
+ info->wq_base_hi,
+ info->wq_size,
+ info->hwlrca_lo,
+ info->hwlrca_hi,
};
return guc_submission_send_busy_loop(guc, action, ARRAY_SIZE(action),
0, loop);
}
-static void prepare_context_registration_info(struct intel_context *ce);
+static void prepare_context_registration_info(struct intel_context *ce,
+ struct guc_ctxt_registration_info *info);
static int register_context(struct intel_context *ce, bool loop)
{
+ struct guc_ctxt_registration_info info;
struct intel_guc *guc = ce_to_guc(ce);
- u32 offset = intel_guc_ggtt_offset(guc, guc->lrc_desc_pool) +
- ce->guc_id.id * sizeof(struct guc_lrc_desc);
int ret;
GEM_BUG_ON(intel_context_is_child(ce));
trace_intel_context_register(ce);
- prepare_context_registration_info(ce);
+ prepare_context_registration_info(ce, &info);
if (intel_context_is_parent(ce))
- ret = __guc_action_register_multi_lrc(guc, ce, ce->guc_id.id,
- offset, loop);
+ ret = __guc_action_register_multi_lrc(guc, ce, &info, loop);
else
- ret = __guc_action_register_context(guc, ce->guc_id.id, offset,
- loop);
+ ret = __guc_action_register_context(guc, &info, loop);
if (likely(!ret)) {
unsigned long flags;
@@ -2216,6 +2191,8 @@ static inline u32 get_children_join_value(struct intel_context *ce,
return __get_parent_scratch(ce)->join[child_index].semaphore;
}
+#if 0
+/* FIXME: This needs to be updated for new v70 interface... */
static void guc_context_policy_init(struct intel_engine_cs *engine,
struct guc_lrc_desc *desc)
{
@@ -2228,14 +2205,14 @@ static void guc_context_policy_init(struct intel_engine_cs *engine,
desc->execution_quantum = engine->props.timeslice_duration_ms * 1000;
desc->preemption_timeout = engine->props.preempt_timeout_ms * 1000;
}
+#endif
-static void prepare_context_registration_info(struct intel_context *ce)
+static void prepare_context_registration_info(struct intel_context *ce,
+ struct guc_ctxt_registration_info *info)
{
struct intel_engine_cs *engine = ce->engine;
struct intel_guc *guc = &engine->gt->uc.guc;
u32 ctx_id = ce->guc_id.id;
- struct guc_lrc_desc *desc;
- struct intel_context *child;
GEM_BUG_ON(!engine->mask);
@@ -2246,47 +2223,49 @@ static void prepare_context_registration_info(struct intel_context *ce)
GEM_BUG_ON(i915_gem_object_is_lmem(guc->ct.vma->obj) !=
i915_gem_object_is_lmem(ce->ring->vma->obj));
- desc = __get_lrc_desc(guc, ctx_id);
- desc->engine_class = engine_class_to_guc_class(engine->class);
- desc->engine_submit_mask = engine->logical_mask;
- desc->hw_context_desc = ce->lrc.lrca;
- desc->priority = ce->guc_state.prio;
- desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD;
- guc_context_policy_init(engine, desc);
+ memset(info, 0, sizeof(*info));
+ info->context_idx = ctx_id;
+ info->engine_class = engine_class_to_guc_class(engine->class);
+ info->engine_submit_mask = engine->logical_mask;
+ /*
+ * NB: GuC interface supports 64 bit LRCA even though i915
+ * only supports 32 bit currently.
+ */
+ info->hwlrca_lo = lower_32_bits(ce->lrc.lrca);
+ info->hwlrca_hi = upper_32_bits(ce->lrc.lrca);
+ info->flags = CONTEXT_REGISTRATION_FLAG_KMD;
+ /* FIXME: This needs to be updated for new v70 interface... */
+ //desc->priority = ce->guc_state.prio;
+ //guc_context_policy_init(engine, desc);
/*
* If context is a parent, we need to register a process descriptor
* describing a work queue and register all child contexts.
*/
if (intel_context_is_parent(ce)) {
- struct guc_process_desc *pdesc;
+ struct guc_sched_wq_desc *wq_desc;
+ u64 wq_desc_offset, wq_base_offset;
ce->parallel.guc.wqi_tail = 0;
ce->parallel.guc.wqi_head = 0;
- desc->process_desc = i915_ggtt_offset(ce->state) +
- __get_parent_scratch_offset(ce);
- desc->wq_addr = i915_ggtt_offset(ce->state) +
- __get_wq_offset(ce);
- desc->wq_size = WQ_SIZE;
-
- pdesc = __get_process_desc(ce);
- memset(pdesc, 0, sizeof(*(pdesc)));
- pdesc->stage_id = ce->guc_id.id;
- pdesc->wq_base_addr = desc->wq_addr;
- pdesc->wq_size_bytes = desc->wq_size;
- pdesc->wq_status = WQ_STATUS_ACTIVE;
-
- for_each_child(ce, child) {
- desc = __get_lrc_desc(guc, child->guc_id.id);
-
- desc->engine_class =
- engine_class_to_guc_class(engine->class);
- desc->hw_context_desc = child->lrc.lrca;
- desc->priority = ce->guc_state.prio;
- desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD;
- guc_context_policy_init(engine, desc);
- }
+ wq_desc_offset = i915_ggtt_offset(ce->state) +
+ __get_parent_scratch_offset(ce);
+ wq_base_offset = i915_ggtt_offset(ce->state) +
+ __get_wq_offset(ce);
+ info->wq_desc_lo = lower_32_bits(wq_desc_offset);
+ info->wq_desc_hi = upper_32_bits(wq_desc_offset);
+ info->wq_base_lo = lower_32_bits(wq_base_offset);
+ info->wq_base_hi = upper_32_bits(wq_base_offset);
+ info->wq_size = WQ_SIZE;
+
+ wq_desc = __get_wq_desc(ce);
+ memset(wq_desc, 0, sizeof(*wq_desc));
+ wq_desc->wq_status = WQ_STATUS_ACTIVE;
+
+ /* FIXME: This needs to be updated for new v70 interface... */
+ //desc->priority = ce->guc_state.prio;
+ //guc_context_policy_init(engine, desc);
clear_children_join_go_memory(ce);
}
@@ -4360,17 +4339,17 @@ void intel_guc_submission_print_context_info(struct intel_guc *guc,
guc_log_context_priority(p, ce);
if (intel_context_is_parent(ce)) {
- struct guc_process_desc *desc = __get_process_desc(ce);
+ struct guc_sched_wq_desc *wq_desc = __get_wq_desc(ce);
struct intel_context *child;
drm_printf(p, "\t\tNumber children: %u\n",
ce->parallel.number_children);
drm_printf(p, "\t\tWQI Head: %u\n",
- READ_ONCE(desc->head));
+ READ_ONCE(wq_desc->head));
drm_printf(p, "\t\tWQI Tail: %u\n",
- READ_ONCE(desc->tail));
+ READ_ONCE(wq_desc->tail));
drm_printf(p, "\t\tWQI Status: %u\n\n",
- READ_ONCE(desc->wq_status));
+ READ_ONCE(wq_desc->wq_status));
if (ce->engine->emit_bb_start ==
emit_bb_start_parent_no_preempt_mid_batch) {
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [Intel-gfx] [PATCH 1/3] drm/i915/guc: Update context registration to new GuC API
2022-04-08 18:03 ` [Intel-gfx] [PATCH 1/3] drm/i915/guc: Update context registration to new GuC API John.C.Harrison
@ 2022-04-12 0:13 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 11+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-04-12 0:13 UTC (permalink / raw)
To: John.C.Harrison, Intel-GFX; +Cc: DRI-Devel
On 4/8/2022 11:03 AM, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> The latest GuC firmware drops the context descriptor pool in favour of
> passing all creation data in the create H2G. It also greatly simplifies
> the work queue and removes the process descriptor used for multi-LRC
> submission. So, remove all mention of LRC and process descriptors and
> update the registration code accordingly.
>
> Unfortunately, the new API also removes the ability to set default
> values for the scheduling policies at context registration time.
> Instead, a follow up H2G must be sent. This will be addressed in the
> next patch.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 5 -
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 52 ++---
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 221 ++++++++----------
> 3 files changed, 116 insertions(+), 162 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index 4e431c14b118..3f3373f68123 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -170,11 +170,6 @@ struct intel_guc {
> /** @ads_engine_usage_size: size of engine usage in the ADS */
> u32 ads_engine_usage_size;
>
> - /** @lrc_desc_pool: object allocated to hold the GuC LRC descriptor pool */
> - struct i915_vma *lrc_desc_pool;
> - /** @lrc_desc_pool_vaddr: contents of the GuC LRC descriptor pool */
> - void *lrc_desc_pool_vaddr;
> -
> /**
> * @context_lookup: used to resolve intel_context from guc_id, if a
> * context is present in this structure it is registered with the GuC
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> index f21b6de46a99..0e1e8d0079b5 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> @@ -197,20 +197,28 @@ struct guc_wq_item {
> u32 fence_id;
> } __packed;
>
> -struct guc_process_desc {
> - u32 stage_id;
> - u64 db_base_addr;
> +struct guc_sched_wq_desc {
> u32 head;
> u32 tail;
> u32 error_offset;
> - u64 wq_base_addr;
> - u32 wq_size_bytes;
> u32 wq_status;
> - u32 engine_presence;
> - u32 priority;
> - u32 reserved[36];
> + u32 reserved[28];
> } __packed;
>
> +/* Helper for context registration H2G */
> +struct guc_ctxt_registration_info {
> + u32 flags;
> + u32 context_idx;
> + u32 engine_class;
> + u32 engine_submit_mask;
> + u32 wq_desc_lo;
> + u32 wq_desc_hi;
> + u32 wq_base_lo;
> + u32 wq_base_hi;
> + u32 wq_size;
> + u32 hwlrca_lo;
> + u32 hwlrca_hi;
> +};
> #define CONTEXT_REGISTRATION_FLAG_KMD BIT(0)
>
> #define CONTEXT_POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000
> @@ -219,34 +227,6 @@ struct guc_process_desc {
> /* Preempt to idle on quantum expiry */
> #define CONTEXT_POLICY_FLAG_PREEMPT_TO_IDLE BIT(0)
>
> -/*
> - * GuC Context registration descriptor.
> - * FIXME: This is only required to exist during context registration.
> - * The current 1:1 between guc_lrc_desc and LRCs for the lifetime of the LRC
> - * is not required.
> - */
> -struct guc_lrc_desc {
> - u32 hw_context_desc;
> - u32 slpm_perf_mode_hint; /* SPLC v1 only */
> - u32 slpm_freq_hint;
> - u32 engine_submit_mask; /* In logical space */
> - u8 engine_class;
> - u8 reserved0[3];
> - u32 priority;
> - u32 process_desc;
> - u32 wq_addr;
> - u32 wq_size;
> - u32 context_flags; /* CONTEXT_REGISTRATION_* */
> - /* Time for one workload to execute. (in micro seconds) */
> - u32 execution_quantum;
> - /* Time to wait for a preemption request to complete before issuing a
> - * reset. (in micro seconds).
> - */
> - u32 preemption_timeout;
> - u32 policy_flags; /* CONTEXT_POLICY_* */
> - u32 reserved1[19];
> -} __packed;
> -
> #define GUC_POWER_UNSPECIFIED 0
> #define GUC_POWER_D0 1
> #define GUC_POWER_D1 2
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index e1612c393781..bd0584d7d489 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -396,12 +396,12 @@ struct sync_semaphore {
> };
>
> struct parent_scratch {
> - struct guc_process_desc pdesc;
> + struct guc_sched_wq_desc wq_desc;
>
> struct sync_semaphore go;
> struct sync_semaphore join[MAX_ENGINE_INSTANCE + 1];
>
> - u8 unused[WQ_OFFSET - sizeof(struct guc_process_desc) -
> + u8 unused[WQ_OFFSET - sizeof(struct guc_sched_wq_desc) -
> sizeof(struct sync_semaphore) * (MAX_ENGINE_INSTANCE + 2)];
>
> u32 wq[WQ_SIZE / sizeof(u32)];
> @@ -438,15 +438,15 @@ __get_parent_scratch(struct intel_context *ce)
> LRC_STATE_OFFSET) / sizeof(u32)));
> }
>
> -static struct guc_process_desc *
> -__get_process_desc(struct intel_context *ce)
> +static struct guc_sched_wq_desc *
> +__get_wq_desc(struct intel_context *ce)
> {
> struct parent_scratch *ps = __get_parent_scratch(ce);
>
> - return &ps->pdesc;
> + return &ps->wq_desc;
> }
>
> -static u32 *get_wq_pointer(struct guc_process_desc *desc,
> +static u32 *get_wq_pointer(struct guc_sched_wq_desc *wq_desc,
> struct intel_context *ce,
> u32 wqi_size)
> {
> @@ -458,7 +458,7 @@ static u32 *get_wq_pointer(struct guc_process_desc *desc,
> #define AVAILABLE_SPACE \
> CIRC_SPACE(ce->parallel.guc.wqi_tail, ce->parallel.guc.wqi_head, WQ_SIZE)
> if (wqi_size > AVAILABLE_SPACE) {
> - ce->parallel.guc.wqi_head = READ_ONCE(desc->head);
> + ce->parallel.guc.wqi_head = READ_ONCE(wq_desc->head);
>
> if (wqi_size > AVAILABLE_SPACE)
> return NULL;
> @@ -468,15 +468,6 @@ static u32 *get_wq_pointer(struct guc_process_desc *desc,
> return &__get_parent_scratch(ce)->wq[ce->parallel.guc.wqi_tail / sizeof(u32)];
> }
>
> -static struct guc_lrc_desc *__get_lrc_desc(struct intel_guc *guc, u32 index)
> -{
> - struct guc_lrc_desc *base = guc->lrc_desc_pool_vaddr;
> -
> - GEM_BUG_ON(index >= GUC_MAX_CONTEXT_ID);
> -
> - return &base[index];
> -}
> -
> static inline struct intel_context *__get_context(struct intel_guc *guc, u32 id)
> {
> struct intel_context *ce = xa_load(&guc->context_lookup, id);
> @@ -486,39 +477,11 @@ static inline struct intel_context *__get_context(struct intel_guc *guc, u32 id)
> return ce;
> }
>
> -static int guc_lrc_desc_pool_create(struct intel_guc *guc)
> -{
> - u32 size;
> - int ret;
> -
> - size = PAGE_ALIGN(sizeof(struct guc_lrc_desc) *
> - GUC_MAX_CONTEXT_ID);
> - ret = intel_guc_allocate_and_map_vma(guc, size, &guc->lrc_desc_pool,
> - (void **)&guc->lrc_desc_pool_vaddr);
> - if (ret)
> - return ret;
> -
> - return 0;
> -}
> -
> -static void guc_lrc_desc_pool_destroy(struct intel_guc *guc)
> -{
> - guc->lrc_desc_pool_vaddr = NULL;
> - i915_vma_unpin_and_release(&guc->lrc_desc_pool, I915_VMA_RELEASE_MAP);
> -}
> -
> static inline bool guc_submission_initialized(struct intel_guc *guc)
> {
> return guc->submission_initialized;
> }
>
> -static inline void _reset_lrc_desc(struct intel_guc *guc, u32 id)
> -{
> - struct guc_lrc_desc *desc = __get_lrc_desc(guc, id);
> -
> - memset(desc, 0, sizeof(*desc));
> -}
> -
> static inline bool ctx_id_mapped(struct intel_guc *guc, u32 id)
> {
> return __get_context(guc, id);
> @@ -545,8 +508,6 @@ static inline void clr_ctx_id_mapping(struct intel_guc *guc, u32 id)
> if (unlikely(!guc_submission_initialized(guc)))
> return;
>
> - _reset_lrc_desc(guc, id);
> -
> /*
> * xarray API doesn't have xa_erase_irqsave wrapper, so calling
> * the lower level functions directly.
> @@ -751,7 +712,7 @@ static u32 wq_space_until_wrap(struct intel_context *ce)
> return (WQ_SIZE - ce->parallel.guc.wqi_tail);
> }
>
> -static void write_wqi(struct guc_process_desc *desc,
> +static void write_wqi(struct guc_sched_wq_desc *wq_desc,
> struct intel_context *ce,
> u32 wqi_size)
> {
> @@ -764,13 +725,13 @@ static void write_wqi(struct guc_process_desc *desc,
>
> ce->parallel.guc.wqi_tail = (ce->parallel.guc.wqi_tail + wqi_size) &
> (WQ_SIZE - 1);
> - WRITE_ONCE(desc->tail, ce->parallel.guc.wqi_tail);
> + WRITE_ONCE(wq_desc->tail, ce->parallel.guc.wqi_tail);
> }
>
> static int guc_wq_noop_append(struct intel_context *ce)
> {
> - struct guc_process_desc *desc = __get_process_desc(ce);
> - u32 *wqi = get_wq_pointer(desc, ce, wq_space_until_wrap(ce));
> + struct guc_sched_wq_desc *wq_desc = __get_wq_desc(ce);
> + u32 *wqi = get_wq_pointer(wq_desc, ce, wq_space_until_wrap(ce));
> u32 len_dw = wq_space_until_wrap(ce) / sizeof(u32) - 1;
>
> if (!wqi)
> @@ -789,7 +750,7 @@ static int __guc_wq_item_append(struct i915_request *rq)
> {
> struct intel_context *ce = request_to_scheduling_context(rq);
> struct intel_context *child;
> - struct guc_process_desc *desc = __get_process_desc(ce);
> + struct guc_sched_wq_desc *wq_desc = __get_wq_desc(ce);
> unsigned int wqi_size = (ce->parallel.number_children + 4) *
> sizeof(u32);
> u32 *wqi;
> @@ -809,7 +770,7 @@ static int __guc_wq_item_append(struct i915_request *rq)
> return ret;
> }
>
> - wqi = get_wq_pointer(desc, ce, wqi_size);
> + wqi = get_wq_pointer(wq_desc, ce, wqi_size);
> if (!wqi)
> return -EBUSY;
>
> @@ -824,7 +785,7 @@ static int __guc_wq_item_append(struct i915_request *rq)
> for_each_child(ce, child)
> *wqi++ = child->ring->tail / sizeof(u64);
>
> - write_wqi(desc, ce, wqi_size);
> + write_wqi(wq_desc, ce, wqi_size);
>
> return 0;
> }
> @@ -1812,20 +1773,10 @@ static void reset_fail_worker_func(struct work_struct *w);
> int intel_guc_submission_init(struct intel_guc *guc)
> {
> struct intel_gt *gt = guc_to_gt(guc);
> - int ret;
>
> if (guc->submission_initialized)
> return 0;
>
> - ret = guc_lrc_desc_pool_create(guc);
> - if (ret)
> - return ret;
> - /*
> - * Keep static analysers happy, let them know that we allocated the
> - * vma after testing that it didn't exist earlier.
> - */
> - GEM_BUG_ON(!guc->lrc_desc_pool);
> -
> guc->submission_state.guc_ids_bitmap =
> bitmap_zalloc(NUMBER_MULTI_LRC_GUC_ID(guc), GFP_KERNEL);
> if (!guc->submission_state.guc_ids_bitmap)
I was trying to understand why you didn't have to update the error
handling to not delete the desc pool if guc_ids_bitmap fails to allocate
and I realized that that cleanup is actually missing, so this fixes a
potential leak as well.
> @@ -1844,7 +1795,6 @@ void intel_guc_submission_fini(struct intel_guc *guc)
> return;
>
> guc_flush_destroyed_contexts(guc);
> - guc_lrc_desc_pool_destroy(guc);
> i915_sched_engine_put(guc->sched_engine);
> bitmap_free(guc->submission_state.guc_ids_bitmap);
> guc->submission_initialized = false;
> @@ -2104,63 +2054,88 @@ static void unpin_guc_id(struct intel_guc *guc, struct intel_context *ce)
>
> static int __guc_action_register_multi_lrc(struct intel_guc *guc,
> struct intel_context *ce,
> - u32 guc_id,
> - u32 offset,
> + struct guc_ctxt_registration_info *info,
> bool loop)
> {
> struct intel_context *child;
> - u32 action[4 + MAX_ENGINE_INSTANCE];
> + u32 action[13 + (MAX_ENGINE_INSTANCE * 2)];
> int len = 0;
> + u32 next_id;
>
> GEM_BUG_ON(ce->parallel.number_children > MAX_ENGINE_INSTANCE);
>
> action[len++] = INTEL_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC;
> - action[len++] = guc_id;
> + action[len++] = info->flags;
> + action[len++] = info->context_idx;
> + action[len++] = info->engine_class;
> + action[len++] = info->engine_submit_mask;
> + action[len++] = info->wq_desc_lo;
> + action[len++] = info->wq_desc_hi;
> + action[len++] = info->wq_base_lo;
> + action[len++] = info->wq_base_hi;
> + action[len++] = info->wq_size;
> action[len++] = ce->parallel.number_children + 1;
> - action[len++] = offset;
> + action[len++] = info->hwlrca_lo;
> + action[len++] = info->hwlrca_hi;
> +
> + next_id = info->context_idx + 1;
> for_each_child(ce, child) {
> - offset += sizeof(struct guc_lrc_desc);
> - action[len++] = offset;
> + GEM_BUG_ON(next_id++ != child->guc_id.id);
> +
> + /*
> + * NB: GuC interface supports 64 bit LRCA even though i915
> + * only supports 32 bit currently.
> + */
It's not i915 that only supports 32b, it's the HW.
Assuming that, as you said in the cover letter, this is going to be
squashed before merge and so all the ifdef and dead code will go away:
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> + action[len++] = lower_32_bits(child->lrc.lrca);
> + action[len++] = upper_32_bits(child->lrc.lrca);
> }
>
> + GEM_BUG_ON(len > ARRAY_SIZE(action));
> +
> return guc_submission_send_busy_loop(guc, action, len, 0, loop);
> }
>
> static int __guc_action_register_context(struct intel_guc *guc,
> - u32 guc_id,
> - u32 offset,
> + struct guc_ctxt_registration_info *info,
> bool loop)
> {
> u32 action[] = {
> INTEL_GUC_ACTION_REGISTER_CONTEXT,
> - guc_id,
> - offset,
> + info->flags,
> + info->context_idx,
> + info->engine_class,
> + info->engine_submit_mask,
> + info->wq_desc_lo,
> + info->wq_desc_hi,
> + info->wq_base_lo,
> + info->wq_base_hi,
> + info->wq_size,
> + info->hwlrca_lo,
> + info->hwlrca_hi,
> };
>
> return guc_submission_send_busy_loop(guc, action, ARRAY_SIZE(action),
> 0, loop);
> }
>
> -static void prepare_context_registration_info(struct intel_context *ce);
> +static void prepare_context_registration_info(struct intel_context *ce,
> + struct guc_ctxt_registration_info *info);
>
> static int register_context(struct intel_context *ce, bool loop)
> {
> + struct guc_ctxt_registration_info info;
> struct intel_guc *guc = ce_to_guc(ce);
> - u32 offset = intel_guc_ggtt_offset(guc, guc->lrc_desc_pool) +
> - ce->guc_id.id * sizeof(struct guc_lrc_desc);
> int ret;
>
> GEM_BUG_ON(intel_context_is_child(ce));
> trace_intel_context_register(ce);
>
> - prepare_context_registration_info(ce);
> + prepare_context_registration_info(ce, &info);
>
> if (intel_context_is_parent(ce))
> - ret = __guc_action_register_multi_lrc(guc, ce, ce->guc_id.id,
> - offset, loop);
> + ret = __guc_action_register_multi_lrc(guc, ce, &info, loop);
> else
> - ret = __guc_action_register_context(guc, ce->guc_id.id, offset,
> - loop);
> + ret = __guc_action_register_context(guc, &info, loop);
> if (likely(!ret)) {
> unsigned long flags;
>
> @@ -2216,6 +2191,8 @@ static inline u32 get_children_join_value(struct intel_context *ce,
> return __get_parent_scratch(ce)->join[child_index].semaphore;
> }
>
> +#if 0
> +/* FIXME: This needs to be updated for new v70 interface... */
> static void guc_context_policy_init(struct intel_engine_cs *engine,
> struct guc_lrc_desc *desc)
> {
> @@ -2228,14 +2205,14 @@ static void guc_context_policy_init(struct intel_engine_cs *engine,
> desc->execution_quantum = engine->props.timeslice_duration_ms * 1000;
> desc->preemption_timeout = engine->props.preempt_timeout_ms * 1000;
> }
> +#endif
>
> -static void prepare_context_registration_info(struct intel_context *ce)
> +static void prepare_context_registration_info(struct intel_context *ce,
> + struct guc_ctxt_registration_info *info)
> {
> struct intel_engine_cs *engine = ce->engine;
> struct intel_guc *guc = &engine->gt->uc.guc;
> u32 ctx_id = ce->guc_id.id;
> - struct guc_lrc_desc *desc;
> - struct intel_context *child;
>
> GEM_BUG_ON(!engine->mask);
>
> @@ -2246,47 +2223,49 @@ static void prepare_context_registration_info(struct intel_context *ce)
> GEM_BUG_ON(i915_gem_object_is_lmem(guc->ct.vma->obj) !=
> i915_gem_object_is_lmem(ce->ring->vma->obj));
>
> - desc = __get_lrc_desc(guc, ctx_id);
> - desc->engine_class = engine_class_to_guc_class(engine->class);
> - desc->engine_submit_mask = engine->logical_mask;
> - desc->hw_context_desc = ce->lrc.lrca;
> - desc->priority = ce->guc_state.prio;
> - desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD;
> - guc_context_policy_init(engine, desc);
> + memset(info, 0, sizeof(*info));
> + info->context_idx = ctx_id;
> + info->engine_class = engine_class_to_guc_class(engine->class);
> + info->engine_submit_mask = engine->logical_mask;
> + /*
> + * NB: GuC interface supports 64 bit LRCA even though i915
> + * only supports 32 bit currently.
> + */
> + info->hwlrca_lo = lower_32_bits(ce->lrc.lrca);
> + info->hwlrca_hi = upper_32_bits(ce->lrc.lrca);
> + info->flags = CONTEXT_REGISTRATION_FLAG_KMD;
> + /* FIXME: This needs to be updated for new v70 interface... */
> + //desc->priority = ce->guc_state.prio;
> + //guc_context_policy_init(engine, desc);
>
> /*
> * If context is a parent, we need to register a process descriptor
> * describing a work queue and register all child contexts.
> */
> if (intel_context_is_parent(ce)) {
> - struct guc_process_desc *pdesc;
> + struct guc_sched_wq_desc *wq_desc;
> + u64 wq_desc_offset, wq_base_offset;
>
> ce->parallel.guc.wqi_tail = 0;
> ce->parallel.guc.wqi_head = 0;
>
> - desc->process_desc = i915_ggtt_offset(ce->state) +
> - __get_parent_scratch_offset(ce);
> - desc->wq_addr = i915_ggtt_offset(ce->state) +
> - __get_wq_offset(ce);
> - desc->wq_size = WQ_SIZE;
> -
> - pdesc = __get_process_desc(ce);
> - memset(pdesc, 0, sizeof(*(pdesc)));
> - pdesc->stage_id = ce->guc_id.id;
> - pdesc->wq_base_addr = desc->wq_addr;
> - pdesc->wq_size_bytes = desc->wq_size;
> - pdesc->wq_status = WQ_STATUS_ACTIVE;
> -
> - for_each_child(ce, child) {
> - desc = __get_lrc_desc(guc, child->guc_id.id);
> -
> - desc->engine_class =
> - engine_class_to_guc_class(engine->class);
> - desc->hw_context_desc = child->lrc.lrca;
> - desc->priority = ce->guc_state.prio;
> - desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD;
> - guc_context_policy_init(engine, desc);
> - }
> + wq_desc_offset = i915_ggtt_offset(ce->state) +
> + __get_parent_scratch_offset(ce);
> + wq_base_offset = i915_ggtt_offset(ce->state) +
> + __get_wq_offset(ce);
> + info->wq_desc_lo = lower_32_bits(wq_desc_offset);
> + info->wq_desc_hi = upper_32_bits(wq_desc_offset);
> + info->wq_base_lo = lower_32_bits(wq_base_offset);
> + info->wq_base_hi = upper_32_bits(wq_base_offset);
> + info->wq_size = WQ_SIZE;
> +
> + wq_desc = __get_wq_desc(ce);
> + memset(wq_desc, 0, sizeof(*wq_desc));
> + wq_desc->wq_status = WQ_STATUS_ACTIVE;
> +
> + /* FIXME: This needs to be updated for new v70 interface... */
> + //desc->priority = ce->guc_state.prio;
> + //guc_context_policy_init(engine, desc);
>
> clear_children_join_go_memory(ce);
> }
> @@ -4360,17 +4339,17 @@ void intel_guc_submission_print_context_info(struct intel_guc *guc,
> guc_log_context_priority(p, ce);
>
> if (intel_context_is_parent(ce)) {
> - struct guc_process_desc *desc = __get_process_desc(ce);
> + struct guc_sched_wq_desc *wq_desc = __get_wq_desc(ce);
> struct intel_context *child;
>
> drm_printf(p, "\t\tNumber children: %u\n",
> ce->parallel.number_children);
> drm_printf(p, "\t\tWQI Head: %u\n",
> - READ_ONCE(desc->head));
> + READ_ONCE(wq_desc->head));
> drm_printf(p, "\t\tWQI Tail: %u\n",
> - READ_ONCE(desc->tail));
> + READ_ONCE(wq_desc->tail));
> drm_printf(p, "\t\tWQI Status: %u\n\n",
> - READ_ONCE(desc->wq_status));
> + READ_ONCE(wq_desc->wq_status));
>
> if (ce->engine->emit_bb_start ==
> emit_bb_start_parent_no_preempt_mid_batch) {
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/guc: Update scheduling policies to new GuC API
2022-04-08 18:03 [Intel-gfx] [PATCH 0/3] Update to GuC v70 John.C.Harrison
2022-04-08 18:03 ` [Intel-gfx] [PATCH 1/3] drm/i915/guc: Update context registration to new GuC API John.C.Harrison
@ 2022-04-08 18:03 ` John.C.Harrison
2022-04-12 0:35 ` Ceraolo Spurio, Daniele
2022-04-08 18:03 ` [Intel-gfx] [PATCH 3/3] drm/i915/guc: Update to GuC version 70.1.1 John.C.Harrison
` (4 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: John.C.Harrison @ 2022-04-08 18:03 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
The latest GuC firmware drops the individual scheduling policy update
H2G commands in favour of a single KLV based H2G. So, change the
update wrappers accordingly.
Unfortunately, the API changes also mean losing the ability to set any
scheduling policy values during context registration. Instead the same
KLV based H2G must be sent after the registration. Of course, that
second H2G per registration might fail due to being backed up. The
registration code has a complicated state machine to cope with the
actual registration call failing. However, if that works then there is
no support for unwinding if a further call should fail. Unwinding
would require sending a H2G to de-register - but that can't be done
because the CTB is already backed up.
So instead, add a new flag to say whether the context has a pending
policy update. This is set if the policy H2G fails at registration
time. The submission code checks for this flag and retries the policy
update if set. If that call fails, the submission path early exists
with a retry error. This is something that is already supported for
other reasons.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
.../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 4 +-
drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h | 15 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 19 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 176 ++++++++++++++----
4 files changed, 175 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index 9ad6df1b6fbc..be9ac47fa9d0 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -122,11 +122,9 @@ enum intel_guc_action {
INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_DONE = 0x1002,
INTEL_GUC_ACTION_SCHED_ENGINE_MODE_SET = 0x1003,
INTEL_GUC_ACTION_SCHED_ENGINE_MODE_DONE = 0x1004,
- INTEL_GUC_ACTION_SET_CONTEXT_PRIORITY = 0x1005,
- INTEL_GUC_ACTION_SET_CONTEXT_EXECUTION_QUANTUM = 0x1006,
- INTEL_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT = 0x1007,
INTEL_GUC_ACTION_CONTEXT_RESET_NOTIFICATION = 0x1008,
INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009,
+ INTEL_GUC_ACTION_HOST2GUC_UPDATE_CONTEXT_POLICIES = 0x100B,
INTEL_GUC_ACTION_SETUP_PC_GUCRC = 0x3004,
INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
INTEL_GUC_ACTION_GET_HWCONFIG = 0x4100,
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
index f0814a57c191..4a59478c3b5c 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
@@ -6,6 +6,8 @@
#ifndef _ABI_GUC_KLVS_ABI_H
#define _ABI_GUC_KLVS_ABI_H
+#include <linux/types.h>
+
/**
* DOC: GuC KLV
*
@@ -79,4 +81,17 @@
#define GUC_KLV_SELF_CFG_G2H_CTB_SIZE_KEY 0x0907
#define GUC_KLV_SELF_CFG_G2H_CTB_SIZE_LEN 1u
+/*
+ * Per context scheduling policy update keys.
+ */
+enum {
+ GUC_CONTEXT_POLICIES_KLV_ID_EXECUTION_QUANTUM = 0x2001,
+ GUC_CONTEXT_POLICIES_KLV_ID_PREEMPTION_TIMEOUT = 0x2002,
+ GUC_CONTEXT_POLICIES_KLV_ID_SCHEDULING_PRIORITY = 0x2003,
+ GUC_CONTEXT_POLICIES_KLV_ID_PREEMPT_TO_IDLE_ON_QUANTUM_EXPIRY = 0x2004,
+ GUC_CONTEXT_POLICIES_KLV_ID_SLPM_GT_FREQUENCY = 0x2005,
+
+ GUC_CONTEXT_POLICIES_KLV_NUM_IDS = 5,
+};
+
#endif /* _ABI_GUC_KLVS_ABI_H */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 0e1e8d0079b5..c154b5efccde 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -221,11 +221,22 @@ struct guc_ctxt_registration_info {
};
#define CONTEXT_REGISTRATION_FLAG_KMD BIT(0)
-#define CONTEXT_POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000
-#define CONTEXT_POLICY_DEFAULT_PREEMPTION_TIME_US 500000
+/* 32-bit KLV structure as used by policy updates and others */
+struct guc_klv_generic_dw_t {
+ u32 kl;
+ u32 value;
+} __packed;
-/* Preempt to idle on quantum expiry */
-#define CONTEXT_POLICY_FLAG_PREEMPT_TO_IDLE BIT(0)
+/* Format of the UPDATE_CONTEXT_POLICIES H2G data packet */
+struct guc_update_context_policy_header {
+ u32 action;
+ u32 ctx_id;
+} __packed;
+
+struct guc_update_context_policy {
+ struct guc_update_context_policy_header header;
+ struct guc_klv_generic_dw_t klv[GUC_CONTEXT_POLICIES_KLV_NUM_IDS];
+} __packed;
#define GUC_POWER_UNSPECIFIED 0
#define GUC_POWER_D0 1
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index bd0584d7d489..2bd680064942 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -162,7 +162,8 @@ guc_create_parallel(struct intel_engine_cs **engines,
#define SCHED_STATE_ENABLED BIT(4)
#define SCHED_STATE_PENDING_ENABLE BIT(5)
#define SCHED_STATE_REGISTERED BIT(6)
-#define SCHED_STATE_BLOCKED_SHIFT 7
+#define SCHED_STATE_POLICY_REQUIRED BIT(7)
+#define SCHED_STATE_BLOCKED_SHIFT 8
#define SCHED_STATE_BLOCKED BIT(SCHED_STATE_BLOCKED_SHIFT)
#define SCHED_STATE_BLOCKED_MASK (0xfff << SCHED_STATE_BLOCKED_SHIFT)
@@ -301,6 +302,23 @@ static inline void clr_context_registered(struct intel_context *ce)
ce->guc_state.sched_state &= ~SCHED_STATE_REGISTERED;
}
+static inline bool context_policy_required(struct intel_context *ce)
+{
+ return ce->guc_state.sched_state & SCHED_STATE_POLICY_REQUIRED;
+}
+
+static inline void set_context_policy_required(struct intel_context *ce)
+{
+ lockdep_assert_held(&ce->guc_state.lock);
+ ce->guc_state.sched_state |= SCHED_STATE_POLICY_REQUIRED;
+}
+
+static inline void clr_context_policy_required(struct intel_context *ce)
+{
+ lockdep_assert_held(&ce->guc_state.lock);
+ ce->guc_state.sched_state &= ~SCHED_STATE_POLICY_REQUIRED;
+}
+
static inline u32 context_blocked(struct intel_context *ce)
{
return (ce->guc_state.sched_state & SCHED_STATE_BLOCKED_MASK) >>
@@ -593,6 +611,7 @@ int intel_guc_wait_for_idle(struct intel_guc *guc, long timeout)
true, timeout);
}
+static int guc_context_policy_init(struct intel_context *ce, bool loop);
static int try_context_registration(struct intel_context *ce, bool loop);
static int __guc_add_request(struct intel_guc *guc, struct i915_request *rq)
@@ -619,6 +638,12 @@ static int __guc_add_request(struct intel_guc *guc, struct i915_request *rq)
GEM_BUG_ON(!atomic_read(&ce->guc_id.ref));
GEM_BUG_ON(context_guc_id_invalid(ce));
+ if (context_policy_required(ce)) {
+ err = guc_context_policy_init(ce, false);
+ if (err)
+ return err;
+ }
+
spin_lock(&ce->guc_state.lock);
/*
@@ -2142,6 +2167,8 @@ static int register_context(struct intel_context *ce, bool loop)
spin_lock_irqsave(&ce->guc_state.lock, flags);
set_context_registered(ce);
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
+
+ guc_context_policy_init(ce, loop);
}
return ret;
@@ -2191,21 +2218,111 @@ static inline u32 get_children_join_value(struct intel_context *ce,
return __get_parent_scratch(ce)->join[child_index].semaphore;
}
-#if 0
-/* FIXME: This needs to be updated for new v70 interface... */
-static void guc_context_policy_init(struct intel_engine_cs *engine,
- struct guc_lrc_desc *desc)
+struct context_policy {
+ u32 count;
+ struct guc_update_context_policy h2g;
+};
+
+static u32 __guc_context_policy_action_size(struct context_policy *policy)
{
- desc->policy_flags = 0;
+ size_t bytes = sizeof(policy->h2g.header) +
+ (sizeof(policy->h2g.klv[0]) * policy->count);
- if (engine->flags & I915_ENGINE_WANT_FORCED_PREEMPTION)
- desc->policy_flags |= CONTEXT_POLICY_FLAG_PREEMPT_TO_IDLE;
+ return bytes / sizeof(u32);
+}
+
+static void __guc_context_policy_start_klv(struct context_policy *policy, u16 guc_id)
+{
+ policy->h2g.header.action = INTEL_GUC_ACTION_HOST2GUC_UPDATE_CONTEXT_POLICIES;
+ policy->h2g.header.ctx_id = guc_id;
+ policy->count = 0;
+}
+
+#define MAKE_CONTEXT_POLICY_ADD(func, id) \
+static void __guc_context_policy_add_##func(struct context_policy *policy, u32 data) \
+{ \
+ GEM_BUG_ON(policy->count >= GUC_CONTEXT_POLICIES_KLV_NUM_IDS); \
+ policy->h2g.klv[policy->count].kl = \
+ FIELD_PREP(GUC_KLV_0_KEY, GUC_CONTEXT_POLICIES_KLV_ID_##id) | \
+ FIELD_PREP(GUC_KLV_0_LEN, 1); \
+ policy->h2g.klv[policy->count].value = data; \
+ policy->count++; \
+}
+
+MAKE_CONTEXT_POLICY_ADD(execution_quantum, EXECUTION_QUANTUM)
+MAKE_CONTEXT_POLICY_ADD(preemption_timeout, PREEMPTION_TIMEOUT)
+MAKE_CONTEXT_POLICY_ADD(priority, SCHEDULING_PRIORITY)
+MAKE_CONTEXT_POLICY_ADD(preempt_to_idle, PREEMPT_TO_IDLE_ON_QUANTUM_EXPIRY)
+
+#undef MAKE_CONTEXT_POLICY_ADD
+
+static int __guc_context_set_context_policies(struct intel_guc *guc,
+ struct context_policy *policy,
+ bool loop)
+{
+ return guc_submission_send_busy_loop(guc, (u32 *)&policy->h2g,
+ __guc_context_policy_action_size(policy),
+ 0, loop);
+}
+
+static int guc_context_policy_init(struct intel_context *ce, bool loop)
+{
+ struct intel_engine_cs *engine = ce->engine;
+ struct intel_guc *guc = &engine->gt->uc.guc;
+ struct context_policy policy;
+ u32 execution_quantum;
+ u32 preemption_timeout;
+ bool missing = false;
+ unsigned long flags;
+ int ret;
/* NB: For both of these, zero means disabled. */
- desc->execution_quantum = engine->props.timeslice_duration_ms * 1000;
- desc->preemption_timeout = engine->props.preempt_timeout_ms * 1000;
+ execution_quantum = engine->props.timeslice_duration_ms * 1000;
+ preemption_timeout = engine->props.preempt_timeout_ms * 1000;
+
+ __guc_context_policy_start_klv(&policy, ce->guc_id.id);
+
+ __guc_context_policy_add_priority(&policy, ce->guc_state.prio);
+ __guc_context_policy_add_execution_quantum(&policy, execution_quantum);
+ __guc_context_policy_add_preemption_timeout(&policy, preemption_timeout);
+
+ if (engine->flags & I915_ENGINE_WANT_FORCED_PREEMPTION)
+ __guc_context_policy_add_preempt_to_idle(&policy, 1);
+
+ ret = __guc_context_set_context_policies(guc, &policy, loop);
+ missing = ret != 0;
+
+ if (!missing && intel_context_is_parent(ce)) {
+ struct intel_context *child;
+
+ for_each_child(ce, child) {
+ __guc_context_policy_start_klv(&policy, child->guc_id.id);
+
+ if (engine->flags & I915_ENGINE_WANT_FORCED_PREEMPTION)
+ __guc_context_policy_add_preempt_to_idle(&policy, 1);
+
+ child->guc_state.prio = ce->guc_state.prio;
+ __guc_context_policy_add_priority(&policy, ce->guc_state.prio);
+ __guc_context_policy_add_execution_quantum(&policy, execution_quantum);
+ __guc_context_policy_add_preemption_timeout(&policy, preemption_timeout);
+
+ ret = __guc_context_set_context_policies(guc, &policy, loop);
+ if (ret) {
+ missing = true;
+ break;
+ }
+ }
+ }
+
+ spin_lock_irqsave(&ce->guc_state.lock, flags);
+ if (missing)
+ set_context_policy_required(ce);
+ else
+ clr_context_policy_required(ce);
+ spin_unlock_irqrestore(&ce->guc_state.lock, flags);
+
+ return ret;
}
-#endif
static void prepare_context_registration_info(struct intel_context *ce,
struct guc_ctxt_registration_info *info)
@@ -2234,9 +2351,6 @@ static void prepare_context_registration_info(struct intel_context *ce,
info->hwlrca_lo = lower_32_bits(ce->lrc.lrca);
info->hwlrca_hi = upper_32_bits(ce->lrc.lrca);
info->flags = CONTEXT_REGISTRATION_FLAG_KMD;
- /* FIXME: This needs to be updated for new v70 interface... */
- //desc->priority = ce->guc_state.prio;
- //guc_context_policy_init(engine, desc);
/*
* If context is a parent, we need to register a process descriptor
@@ -2263,10 +2377,6 @@ static void prepare_context_registration_info(struct intel_context *ce,
memset(wq_desc, 0, sizeof(*wq_desc));
wq_desc->wq_status = WQ_STATUS_ACTIVE;
- /* FIXME: This needs to be updated for new v70 interface... */
- //desc->priority = ce->guc_state.prio;
- //guc_context_policy_init(engine, desc);
-
clear_children_join_go_memory(ce);
}
}
@@ -2581,13 +2691,11 @@ static void __guc_context_set_preemption_timeout(struct intel_guc *guc,
u16 guc_id,
u32 preemption_timeout)
{
- u32 action[] = {
- INTEL_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT,
- guc_id,
- preemption_timeout
- };
+ struct context_policy policy;
- intel_guc_send_busy_loop(guc, action, ARRAY_SIZE(action), 0, true);
+ __guc_context_policy_start_klv(&policy, guc_id);
+ __guc_context_policy_add_preemption_timeout(&policy, preemption_timeout);
+ __guc_context_set_context_policies(guc, &policy, true);
}
static void guc_context_ban(struct intel_context *ce, struct i915_request *rq)
@@ -2832,16 +2940,20 @@ static int guc_context_alloc(struct intel_context *ce)
return lrc_alloc(ce, ce->engine);
}
+static void __guc_context_set_prio(struct intel_guc *guc,
+ struct intel_context *ce)
+{
+ struct context_policy policy;
+
+ __guc_context_policy_start_klv(&policy, ce->guc_id.id);
+ __guc_context_policy_add_priority(&policy, ce->guc_state.prio);
+ __guc_context_set_context_policies(guc, &policy, true);
+}
+
static void guc_context_set_prio(struct intel_guc *guc,
struct intel_context *ce,
u8 prio)
{
- u32 action[] = {
- INTEL_GUC_ACTION_SET_CONTEXT_PRIORITY,
- ce->guc_id.id,
- prio,
- };
-
GEM_BUG_ON(prio < GUC_CLIENT_PRIORITY_KMD_HIGH ||
prio > GUC_CLIENT_PRIORITY_NORMAL);
lockdep_assert_held(&ce->guc_state.lock);
@@ -2852,9 +2964,9 @@ static void guc_context_set_prio(struct intel_guc *guc,
return;
}
- guc_submission_send_busy_loop(guc, action, ARRAY_SIZE(action), 0, true);
-
ce->guc_state.prio = prio;
+ __guc_context_set_prio(guc, ce);
+
trace_intel_context_set_prio(ce);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [Intel-gfx] [PATCH 2/3] drm/i915/guc: Update scheduling policies to new GuC API
2022-04-08 18:03 ` [Intel-gfx] [PATCH 2/3] drm/i915/guc: Update scheduling policies " John.C.Harrison
@ 2022-04-12 0:35 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 11+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-04-12 0:35 UTC (permalink / raw)
To: John.C.Harrison, Intel-GFX; +Cc: DRI-Devel
On 4/8/2022 11:03 AM, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> The latest GuC firmware drops the individual scheduling policy update
> H2G commands in favour of a single KLV based H2G. So, change the
> update wrappers accordingly.
>
> Unfortunately, the API changes also mean losing the ability to set any
> scheduling policy values during context registration. Instead the same
> KLV based H2G must be sent after the registration. Of course, that
> second H2G per registration might fail due to being backed up. The
> registration code has a complicated state machine to cope with the
> actual registration call failing. However, if that works then there is
> no support for unwinding if a further call should fail. Unwinding
> would require sending a H2G to de-register - but that can't be done
> because the CTB is already backed up.
>
> So instead, add a new flag to say whether the context has a pending
> policy update. This is set if the policy H2G fails at registration
> time. The submission code checks for this flag and retries the policy
> update if set. If that call fails, the submission path early exists
> with a retry error. This is something that is already supported for
> other reasons.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> ---
> .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 4 +-
> drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h | 15 ++
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 19 +-
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 176 ++++++++++++++----
> 4 files changed, 175 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> index 9ad6df1b6fbc..be9ac47fa9d0 100644
> --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
> @@ -122,11 +122,9 @@ enum intel_guc_action {
> INTEL_GUC_ACTION_SCHED_CONTEXT_MODE_DONE = 0x1002,
> INTEL_GUC_ACTION_SCHED_ENGINE_MODE_SET = 0x1003,
> INTEL_GUC_ACTION_SCHED_ENGINE_MODE_DONE = 0x1004,
> - INTEL_GUC_ACTION_SET_CONTEXT_PRIORITY = 0x1005,
> - INTEL_GUC_ACTION_SET_CONTEXT_EXECUTION_QUANTUM = 0x1006,
> - INTEL_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT = 0x1007,
> INTEL_GUC_ACTION_CONTEXT_RESET_NOTIFICATION = 0x1008,
> INTEL_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION = 0x1009,
> + INTEL_GUC_ACTION_HOST2GUC_UPDATE_CONTEXT_POLICIES = 0x100B,
> INTEL_GUC_ACTION_SETUP_PC_GUCRC = 0x3004,
> INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
> INTEL_GUC_ACTION_GET_HWCONFIG = 0x4100,
> diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
> index f0814a57c191..4a59478c3b5c 100644
> --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
> +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
> @@ -6,6 +6,8 @@
> #ifndef _ABI_GUC_KLVS_ABI_H
> #define _ABI_GUC_KLVS_ABI_H
>
> +#include <linux/types.h>
> +
> /**
> * DOC: GuC KLV
> *
> @@ -79,4 +81,17 @@
> #define GUC_KLV_SELF_CFG_G2H_CTB_SIZE_KEY 0x0907
> #define GUC_KLV_SELF_CFG_G2H_CTB_SIZE_LEN 1u
>
> +/*
> + * Per context scheduling policy update keys.
> + */
> +enum {
> + GUC_CONTEXT_POLICIES_KLV_ID_EXECUTION_QUANTUM = 0x2001,
> + GUC_CONTEXT_POLICIES_KLV_ID_PREEMPTION_TIMEOUT = 0x2002,
> + GUC_CONTEXT_POLICIES_KLV_ID_SCHEDULING_PRIORITY = 0x2003,
> + GUC_CONTEXT_POLICIES_KLV_ID_PREEMPT_TO_IDLE_ON_QUANTUM_EXPIRY = 0x2004,
> + GUC_CONTEXT_POLICIES_KLV_ID_SLPM_GT_FREQUENCY = 0x2005,
> +
> + GUC_CONTEXT_POLICIES_KLV_NUM_IDS = 5,
> +};
> +
> #endif /* _ABI_GUC_KLVS_ABI_H */
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> index 0e1e8d0079b5..c154b5efccde 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> @@ -221,11 +221,22 @@ struct guc_ctxt_registration_info {
> };
> #define CONTEXT_REGISTRATION_FLAG_KMD BIT(0)
>
> -#define CONTEXT_POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000
> -#define CONTEXT_POLICY_DEFAULT_PREEMPTION_TIME_US 500000
> +/* 32-bit KLV structure as used by policy updates and others */
> +struct guc_klv_generic_dw_t {
> + u32 kl;
> + u32 value;
> +} __packed;
>
> -/* Preempt to idle on quantum expiry */
> -#define CONTEXT_POLICY_FLAG_PREEMPT_TO_IDLE BIT(0)
> +/* Format of the UPDATE_CONTEXT_POLICIES H2G data packet */
> +struct guc_update_context_policy_header {
> + u32 action;
> + u32 ctx_id;
> +} __packed;
> +
> +struct guc_update_context_policy {
> + struct guc_update_context_policy_header header;
> + struct guc_klv_generic_dw_t klv[GUC_CONTEXT_POLICIES_KLV_NUM_IDS];
> +} __packed;
>
> #define GUC_POWER_UNSPECIFIED 0
> #define GUC_POWER_D0 1
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index bd0584d7d489..2bd680064942 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -162,7 +162,8 @@ guc_create_parallel(struct intel_engine_cs **engines,
> #define SCHED_STATE_ENABLED BIT(4)
> #define SCHED_STATE_PENDING_ENABLE BIT(5)
> #define SCHED_STATE_REGISTERED BIT(6)
> -#define SCHED_STATE_BLOCKED_SHIFT 7
> +#define SCHED_STATE_POLICY_REQUIRED BIT(7)
> +#define SCHED_STATE_BLOCKED_SHIFT 8
> #define SCHED_STATE_BLOCKED BIT(SCHED_STATE_BLOCKED_SHIFT)
> #define SCHED_STATE_BLOCKED_MASK (0xfff << SCHED_STATE_BLOCKED_SHIFT)
>
> @@ -301,6 +302,23 @@ static inline void clr_context_registered(struct intel_context *ce)
> ce->guc_state.sched_state &= ~SCHED_STATE_REGISTERED;
> }
>
> +static inline bool context_policy_required(struct intel_context *ce)
> +{
> + return ce->guc_state.sched_state & SCHED_STATE_POLICY_REQUIRED;
> +}
> +
> +static inline void set_context_policy_required(struct intel_context *ce)
> +{
> + lockdep_assert_held(&ce->guc_state.lock);
> + ce->guc_state.sched_state |= SCHED_STATE_POLICY_REQUIRED;
> +}
> +
> +static inline void clr_context_policy_required(struct intel_context *ce)
> +{
> + lockdep_assert_held(&ce->guc_state.lock);
> + ce->guc_state.sched_state &= ~SCHED_STATE_POLICY_REQUIRED;
> +}
> +
> static inline u32 context_blocked(struct intel_context *ce)
> {
> return (ce->guc_state.sched_state & SCHED_STATE_BLOCKED_MASK) >>
> @@ -593,6 +611,7 @@ int intel_guc_wait_for_idle(struct intel_guc *guc, long timeout)
> true, timeout);
> }
>
> +static int guc_context_policy_init(struct intel_context *ce, bool loop);
> static int try_context_registration(struct intel_context *ce, bool loop);
>
> static int __guc_add_request(struct intel_guc *guc, struct i915_request *rq)
> @@ -619,6 +638,12 @@ static int __guc_add_request(struct intel_guc *guc, struct i915_request *rq)
> GEM_BUG_ON(!atomic_read(&ce->guc_id.ref));
> GEM_BUG_ON(context_guc_id_invalid(ce));
>
> + if (context_policy_required(ce)) {
> + err = guc_context_policy_init(ce, false);
> + if (err)
> + return err;
> + }
> +
> spin_lock(&ce->guc_state.lock);
>
> /*
> @@ -2142,6 +2167,8 @@ static int register_context(struct intel_context *ce, bool loop)
> spin_lock_irqsave(&ce->guc_state.lock, flags);
> set_context_registered(ce);
> spin_unlock_irqrestore(&ce->guc_state.lock, flags);
> +
> + guc_context_policy_init(ce, loop);
> }
>
> return ret;
> @@ -2191,21 +2218,111 @@ static inline u32 get_children_join_value(struct intel_context *ce,
> return __get_parent_scratch(ce)->join[child_index].semaphore;
> }
>
> -#if 0
> -/* FIXME: This needs to be updated for new v70 interface... */
> -static void guc_context_policy_init(struct intel_engine_cs *engine,
> - struct guc_lrc_desc *desc)
> +struct context_policy {
> + u32 count;
> + struct guc_update_context_policy h2g;
> +};
> +
> +static u32 __guc_context_policy_action_size(struct context_policy *policy)
> {
> - desc->policy_flags = 0;
> + size_t bytes = sizeof(policy->h2g.header) +
> + (sizeof(policy->h2g.klv[0]) * policy->count);
>
> - if (engine->flags & I915_ENGINE_WANT_FORCED_PREEMPTION)
> - desc->policy_flags |= CONTEXT_POLICY_FLAG_PREEMPT_TO_IDLE;
> + return bytes / sizeof(u32);
> +}
> +
> +static void __guc_context_policy_start_klv(struct context_policy *policy, u16 guc_id)
> +{
> + policy->h2g.header.action = INTEL_GUC_ACTION_HOST2GUC_UPDATE_CONTEXT_POLICIES;
> + policy->h2g.header.ctx_id = guc_id;
> + policy->count = 0;
> +}
> +
> +#define MAKE_CONTEXT_POLICY_ADD(func, id) \
> +static void __guc_context_policy_add_##func(struct context_policy *policy, u32 data) \
> +{ \
> + GEM_BUG_ON(policy->count >= GUC_CONTEXT_POLICIES_KLV_NUM_IDS); \
> + policy->h2g.klv[policy->count].kl = \
> + FIELD_PREP(GUC_KLV_0_KEY, GUC_CONTEXT_POLICIES_KLV_ID_##id) | \
> + FIELD_PREP(GUC_KLV_0_LEN, 1); \
> + policy->h2g.klv[policy->count].value = data; \
> + policy->count++; \
> +}
> +
> +MAKE_CONTEXT_POLICY_ADD(execution_quantum, EXECUTION_QUANTUM)
> +MAKE_CONTEXT_POLICY_ADD(preemption_timeout, PREEMPTION_TIMEOUT)
> +MAKE_CONTEXT_POLICY_ADD(priority, SCHEDULING_PRIORITY)
> +MAKE_CONTEXT_POLICY_ADD(preempt_to_idle, PREEMPT_TO_IDLE_ON_QUANTUM_EXPIRY)
> +
> +#undef MAKE_CONTEXT_POLICY_ADD
> +
> +static int __guc_context_set_context_policies(struct intel_guc *guc,
> + struct context_policy *policy,
> + bool loop)
> +{
> + return guc_submission_send_busy_loop(guc, (u32 *)&policy->h2g,
> + __guc_context_policy_action_size(policy),
> + 0, loop);
> +}
> +
> +static int guc_context_policy_init(struct intel_context *ce, bool loop)
> +{
> + struct intel_engine_cs *engine = ce->engine;
> + struct intel_guc *guc = &engine->gt->uc.guc;
> + struct context_policy policy;
> + u32 execution_quantum;
> + u32 preemption_timeout;
> + bool missing = false;
> + unsigned long flags;
> + int ret;
>
> /* NB: For both of these, zero means disabled. */
> - desc->execution_quantum = engine->props.timeslice_duration_ms * 1000;
> - desc->preemption_timeout = engine->props.preempt_timeout_ms * 1000;
> + execution_quantum = engine->props.timeslice_duration_ms * 1000;
> + preemption_timeout = engine->props.preempt_timeout_ms * 1000;
> +
> + __guc_context_policy_start_klv(&policy, ce->guc_id.id);
> +
> + __guc_context_policy_add_priority(&policy, ce->guc_state.prio);
> + __guc_context_policy_add_execution_quantum(&policy, execution_quantum);
> + __guc_context_policy_add_preemption_timeout(&policy, preemption_timeout);
> +
> + if (engine->flags & I915_ENGINE_WANT_FORCED_PREEMPTION)
> + __guc_context_policy_add_preempt_to_idle(&policy, 1);
> +
> + ret = __guc_context_set_context_policies(guc, &policy, loop);
> + missing = ret != 0;
> +
> + if (!missing && intel_context_is_parent(ce)) {
> + struct intel_context *child;
> +
> + for_each_child(ce, child) {
> + __guc_context_policy_start_klv(&policy, child->guc_id.id);
> +
> + if (engine->flags & I915_ENGINE_WANT_FORCED_PREEMPTION)
> + __guc_context_policy_add_preempt_to_idle(&policy, 1);
> +
> + child->guc_state.prio = ce->guc_state.prio;
> + __guc_context_policy_add_priority(&policy, ce->guc_state.prio);
> + __guc_context_policy_add_execution_quantum(&policy, execution_quantum);
> + __guc_context_policy_add_preemption_timeout(&policy, preemption_timeout);
> +
> + ret = __guc_context_set_context_policies(guc, &policy, loop);
> + if (ret) {
> + missing = true;
> + break;
> + }
> + }
> + }
> +
> + spin_lock_irqsave(&ce->guc_state.lock, flags);
> + if (missing)
> + set_context_policy_required(ce);
> + else
> + clr_context_policy_required(ce);
> + spin_unlock_irqrestore(&ce->guc_state.lock, flags);
> +
> + return ret;
> }
> -#endif
>
> static void prepare_context_registration_info(struct intel_context *ce,
> struct guc_ctxt_registration_info *info)
> @@ -2234,9 +2351,6 @@ static void prepare_context_registration_info(struct intel_context *ce,
> info->hwlrca_lo = lower_32_bits(ce->lrc.lrca);
> info->hwlrca_hi = upper_32_bits(ce->lrc.lrca);
> info->flags = CONTEXT_REGISTRATION_FLAG_KMD;
> - /* FIXME: This needs to be updated for new v70 interface... */
> - //desc->priority = ce->guc_state.prio;
> - //guc_context_policy_init(engine, desc);
>
> /*
> * If context is a parent, we need to register a process descriptor
> @@ -2263,10 +2377,6 @@ static void prepare_context_registration_info(struct intel_context *ce,
> memset(wq_desc, 0, sizeof(*wq_desc));
> wq_desc->wq_status = WQ_STATUS_ACTIVE;
>
> - /* FIXME: This needs to be updated for new v70 interface... */
> - //desc->priority = ce->guc_state.prio;
> - //guc_context_policy_init(engine, desc);
> -
> clear_children_join_go_memory(ce);
> }
> }
> @@ -2581,13 +2691,11 @@ static void __guc_context_set_preemption_timeout(struct intel_guc *guc,
> u16 guc_id,
> u32 preemption_timeout)
> {
> - u32 action[] = {
> - INTEL_GUC_ACTION_SET_CONTEXT_PREEMPTION_TIMEOUT,
> - guc_id,
> - preemption_timeout
> - };
> + struct context_policy policy;
>
> - intel_guc_send_busy_loop(guc, action, ARRAY_SIZE(action), 0, true);
> + __guc_context_policy_start_klv(&policy, guc_id);
> + __guc_context_policy_add_preemption_timeout(&policy, preemption_timeout);
> + __guc_context_set_context_policies(guc, &policy, true);
> }
>
> static void guc_context_ban(struct intel_context *ce, struct i915_request *rq)
> @@ -2832,16 +2940,20 @@ static int guc_context_alloc(struct intel_context *ce)
> return lrc_alloc(ce, ce->engine);
> }
>
> +static void __guc_context_set_prio(struct intel_guc *guc,
> + struct intel_context *ce)
> +{
> + struct context_policy policy;
> +
> + __guc_context_policy_start_klv(&policy, ce->guc_id.id);
> + __guc_context_policy_add_priority(&policy, ce->guc_state.prio);
> + __guc_context_set_context_policies(guc, &policy, true);
> +}
> +
> static void guc_context_set_prio(struct intel_guc *guc,
> struct intel_context *ce,
> u8 prio)
> {
> - u32 action[] = {
> - INTEL_GUC_ACTION_SET_CONTEXT_PRIORITY,
> - ce->guc_id.id,
> - prio,
> - };
> -
> GEM_BUG_ON(prio < GUC_CLIENT_PRIORITY_KMD_HIGH ||
> prio > GUC_CLIENT_PRIORITY_NORMAL);
> lockdep_assert_held(&ce->guc_state.lock);
> @@ -2852,9 +2964,9 @@ static void guc_context_set_prio(struct intel_guc *guc,
> return;
> }
>
> - guc_submission_send_busy_loop(guc, action, ARRAY_SIZE(action), 0, true);
> -
> ce->guc_state.prio = prio;
> + __guc_context_set_prio(guc, ce);
> +
> trace_intel_context_set_prio(ce);
> }
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915/guc: Update to GuC version 70.1.1
2022-04-08 18:03 [Intel-gfx] [PATCH 0/3] Update to GuC v70 John.C.Harrison
2022-04-08 18:03 ` [Intel-gfx] [PATCH 1/3] drm/i915/guc: Update context registration to new GuC API John.C.Harrison
2022-04-08 18:03 ` [Intel-gfx] [PATCH 2/3] drm/i915/guc: Update scheduling policies " John.C.Harrison
@ 2022-04-08 18:03 ` John.C.Harrison
2022-04-12 0:36 ` Ceraolo Spurio, Daniele
2022-04-08 21:44 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Update to GuC v70 Patchwork
` (3 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: John.C.Harrison @ 2022-04-08 18:03 UTC (permalink / raw)
To: Intel-GFX; +Cc: DRI-Devel
From: John Harrison <John.C.Harrison@Intel.com>
Update to the latest GuC firmware release.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 32 ++++++++++++------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index bb864655c495..cb5dd16421d0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -53,22 +53,22 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
* firmware as TGL.
*/
#define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_def) \
- fw_def(DG2, 0, guc_def(dg2, 69, 0, 3)) \
- fw_def(ALDERLAKE_P, 0, guc_def(adlp, 69, 0, 3)) \
- fw_def(ALDERLAKE_S, 0, guc_def(tgl, 69, 0, 3)) \
- fw_def(DG1, 0, guc_def(dg1, 69, 0, 3)) \
- fw_def(ROCKETLAKE, 0, guc_def(tgl, 69, 0, 3)) \
- fw_def(TIGERLAKE, 0, guc_def(tgl, 69, 0, 3)) \
- fw_def(JASPERLAKE, 0, guc_def(ehl, 69, 0, 3)) \
- fw_def(ELKHARTLAKE, 0, guc_def(ehl, 69, 0, 3)) \
- fw_def(ICELAKE, 0, guc_def(icl, 69, 0, 3)) \
- fw_def(COMETLAKE, 5, guc_def(cml, 69, 0, 3)) \
- fw_def(COMETLAKE, 0, guc_def(kbl, 69, 0, 3)) \
- fw_def(COFFEELAKE, 0, guc_def(kbl, 69, 0, 3)) \
- fw_def(GEMINILAKE, 0, guc_def(glk, 69, 0, 3)) \
- fw_def(KABYLAKE, 0, guc_def(kbl, 69, 0, 3)) \
- fw_def(BROXTON, 0, guc_def(bxt, 69, 0, 3)) \
- fw_def(SKYLAKE, 0, guc_def(skl, 69, 0, 3))
+ fw_def(DG2, 0, guc_def(dg2, 70, 1, 1)) \
+ fw_def(ALDERLAKE_P, 0, guc_def(adlp, 70, 1, 1)) \
+ fw_def(ALDERLAKE_S, 0, guc_def(tgl, 70, 1, 1)) \
+ fw_def(DG1, 0, guc_def(dg1, 70, 1, 1)) \
+ fw_def(ROCKETLAKE, 0, guc_def(tgl, 70, 1, 1)) \
+ fw_def(TIGERLAKE, 0, guc_def(tgl, 70, 1, 1)) \
+ fw_def(JASPERLAKE, 0, guc_def(ehl, 70, 1, 1)) \
+ fw_def(ELKHARTLAKE, 0, guc_def(ehl, 70, 1, 1)) \
+ fw_def(ICELAKE, 0, guc_def(icl, 70, 1, 1)) \
+ fw_def(COMETLAKE, 5, guc_def(cml, 70, 1, 1)) \
+ fw_def(COMETLAKE, 0, guc_def(kbl, 70, 1, 1)) \
+ fw_def(COFFEELAKE, 0, guc_def(kbl, 70, 1, 1)) \
+ fw_def(GEMINILAKE, 0, guc_def(glk, 70, 1, 1)) \
+ fw_def(KABYLAKE, 0, guc_def(kbl, 70, 1, 1)) \
+ fw_def(BROXTON, 0, guc_def(bxt, 70, 1, 1)) \
+ fw_def(SKYLAKE, 0, guc_def(skl, 70, 1, 1))
#define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_def) \
fw_def(ALDERLAKE_P, 0, huc_def(tgl, 7, 9, 3)) \
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [Intel-gfx] [PATCH 3/3] drm/i915/guc: Update to GuC version 70.1.1
2022-04-08 18:03 ` [Intel-gfx] [PATCH 3/3] drm/i915/guc: Update to GuC version 70.1.1 John.C.Harrison
@ 2022-04-12 0:36 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 11+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-04-12 0:36 UTC (permalink / raw)
To: John.C.Harrison, Intel-GFX; +Cc: DRI-Devel
On 4/8/2022 11:03 AM, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Update to the latest GuC firmware release.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> ---
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 32 ++++++++++++------------
> 1 file changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> index bb864655c495..cb5dd16421d0 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> @@ -53,22 +53,22 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
> * firmware as TGL.
> */
> #define INTEL_GUC_FIRMWARE_DEFS(fw_def, guc_def) \
> - fw_def(DG2, 0, guc_def(dg2, 69, 0, 3)) \
> - fw_def(ALDERLAKE_P, 0, guc_def(adlp, 69, 0, 3)) \
> - fw_def(ALDERLAKE_S, 0, guc_def(tgl, 69, 0, 3)) \
> - fw_def(DG1, 0, guc_def(dg1, 69, 0, 3)) \
> - fw_def(ROCKETLAKE, 0, guc_def(tgl, 69, 0, 3)) \
> - fw_def(TIGERLAKE, 0, guc_def(tgl, 69, 0, 3)) \
> - fw_def(JASPERLAKE, 0, guc_def(ehl, 69, 0, 3)) \
> - fw_def(ELKHARTLAKE, 0, guc_def(ehl, 69, 0, 3)) \
> - fw_def(ICELAKE, 0, guc_def(icl, 69, 0, 3)) \
> - fw_def(COMETLAKE, 5, guc_def(cml, 69, 0, 3)) \
> - fw_def(COMETLAKE, 0, guc_def(kbl, 69, 0, 3)) \
> - fw_def(COFFEELAKE, 0, guc_def(kbl, 69, 0, 3)) \
> - fw_def(GEMINILAKE, 0, guc_def(glk, 69, 0, 3)) \
> - fw_def(KABYLAKE, 0, guc_def(kbl, 69, 0, 3)) \
> - fw_def(BROXTON, 0, guc_def(bxt, 69, 0, 3)) \
> - fw_def(SKYLAKE, 0, guc_def(skl, 69, 0, 3))
> + fw_def(DG2, 0, guc_def(dg2, 70, 1, 1)) \
> + fw_def(ALDERLAKE_P, 0, guc_def(adlp, 70, 1, 1)) \
> + fw_def(ALDERLAKE_S, 0, guc_def(tgl, 70, 1, 1)) \
> + fw_def(DG1, 0, guc_def(dg1, 70, 1, 1)) \
> + fw_def(ROCKETLAKE, 0, guc_def(tgl, 70, 1, 1)) \
> + fw_def(TIGERLAKE, 0, guc_def(tgl, 70, 1, 1)) \
> + fw_def(JASPERLAKE, 0, guc_def(ehl, 70, 1, 1)) \
> + fw_def(ELKHARTLAKE, 0, guc_def(ehl, 70, 1, 1)) \
> + fw_def(ICELAKE, 0, guc_def(icl, 70, 1, 1)) \
> + fw_def(COMETLAKE, 5, guc_def(cml, 70, 1, 1)) \
> + fw_def(COMETLAKE, 0, guc_def(kbl, 70, 1, 1)) \
> + fw_def(COFFEELAKE, 0, guc_def(kbl, 70, 1, 1)) \
> + fw_def(GEMINILAKE, 0, guc_def(glk, 70, 1, 1)) \
> + fw_def(KABYLAKE, 0, guc_def(kbl, 70, 1, 1)) \
> + fw_def(BROXTON, 0, guc_def(bxt, 70, 1, 1)) \
> + fw_def(SKYLAKE, 0, guc_def(skl, 70, 1, 1))
>
> #define INTEL_HUC_FIRMWARE_DEFS(fw_def, huc_def) \
> fw_def(ALDERLAKE_P, 0, huc_def(tgl, 7, 9, 3)) \
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Update to GuC v70
2022-04-08 18:03 [Intel-gfx] [PATCH 0/3] Update to GuC v70 John.C.Harrison
` (2 preceding siblings ...)
2022-04-08 18:03 ` [Intel-gfx] [PATCH 3/3] drm/i915/guc: Update to GuC version 70.1.1 John.C.Harrison
@ 2022-04-08 21:44 ` Patchwork
2022-04-08 21:45 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2022-04-08 21:44 UTC (permalink / raw)
To: john.c.harrison; +Cc: intel-gfx
== Series Details ==
Series: Update to GuC v70
URL : https://patchwork.freedesktop.org/series/102430/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ca0a801b1dda drm/i915/guc: Update context registration to new GuC API
-:418: WARNING:IF_0: Consider removing the code enclosed by this #if 0 and its #endif
#418: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:2194:
+#if 0
total: 0 errors, 1 warnings, 0 checks, 492 lines checked
04be6eae2735 drm/i915/guc: Update scheduling policies to new GuC API
634d8272f0e7 drm/i915/guc: Update to GuC version 70.1.1
^ permalink raw reply [flat|nested] 11+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Update to GuC v70
2022-04-08 18:03 [Intel-gfx] [PATCH 0/3] Update to GuC v70 John.C.Harrison
` (3 preceding siblings ...)
2022-04-08 21:44 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Update to GuC v70 Patchwork
@ 2022-04-08 21:45 ` Patchwork
2022-04-08 22:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-04-09 0:15 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2022-04-08 21:45 UTC (permalink / raw)
To: john.c.harrison; +Cc: intel-gfx
== Series Details ==
Series: Update to GuC v70
URL : https://patchwork.freedesktop.org/series/102430/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 11+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for Update to GuC v70
2022-04-08 18:03 [Intel-gfx] [PATCH 0/3] Update to GuC v70 John.C.Harrison
` (4 preceding siblings ...)
2022-04-08 21:45 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-04-08 22:20 ` Patchwork
2022-04-09 0:15 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2022-04-08 22:20 UTC (permalink / raw)
To: john.c.harrison; +Cc: intel-gfx
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== Series Details ==
Series: Update to GuC v70
URL : https://patchwork.freedesktop.org/series/102430/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11479 -> Patchwork_22832
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_22832 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22832, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/index.html
Participating hosts (47 -> 45)
------------------------------
Additional (1): fi-kbl-8809g
Missing (3): fi-bsw-cyan fi-icl-u2 fi-bdw-samus
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22832:
### IGT changes ###
#### Warnings ####
* igt@core_hotunplug@unbind-rebind:
- fi-kbl-7567u: [DMESG-WARN][1] ([i915#5437]) -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/fi-kbl-7567u/igt@core_hotunplug@unbind-rebind.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/fi-kbl-7567u/igt@core_hotunplug@unbind-rebind.html
Known issues
------------
Here are the changes found in Patchwork_22832 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@fbdev@eof:
- fi-kbl-8809g: NOTRUN -> [INCOMPLETE][3] ([i915#5557])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/fi-kbl-8809g/igt@fbdev@eof.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-rkl-11600: [PASS][4] -> [INCOMPLETE][5] ([i915#5127])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/fi-rkl-11600/igt@gem_exec_suspend@basic-s3@smem.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/fi-rkl-11600/igt@gem_exec_suspend@basic-s3@smem.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [PASS][6] -> [DMESG-WARN][7] ([i915#62]) +11 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-cfl-8109u: [PASS][8] -> [DMESG-WARN][9] ([i915#5341] / [i915#62])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
* igt@runner@aborted:
- fi-kbl-8809g: NOTRUN -> [FAIL][10] ([i915#2722])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/fi-kbl-8809g/igt@runner@aborted.html
- fi-bdw-5557u: NOTRUN -> [FAIL][11] ([i915#4312])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/fi-bdw-5557u/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@perf:
- {fi-tgl-dsi}: [DMESG-WARN][12] ([i915#2867]) -> [PASS][13] +17 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/fi-tgl-dsi/igt@i915_selftest@live@perf.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/fi-tgl-dsi/igt@i915_selftest@live@perf.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
[i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
[i915#5437]: https://gitlab.freedesktop.org/drm/intel/issues/5437
[i915#5557]: https://gitlab.freedesktop.org/drm/intel/issues/5557
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
Build changes
-------------
* Linux: CI_DRM_11479 -> Patchwork_22832
CI-20190529: 20190529
CI_DRM_11479: 4dcdb745569d8eef8db09e24e8ff2e5dffc0664c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6415: c3b690bd5f7fb1fb7ed786ab0f3b815930a6a55f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22832: 634d8272f0e73c4e3a803750d6e90b0ab30e4d58 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
634d8272f0e7 drm/i915/guc: Update to GuC version 70.1.1
04be6eae2735 drm/i915/guc: Update scheduling policies to new GuC API
ca0a801b1dda drm/i915/guc: Update context registration to new GuC API
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/index.html
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^ permalink raw reply [flat|nested] 11+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for Update to GuC v70
2022-04-08 18:03 [Intel-gfx] [PATCH 0/3] Update to GuC v70 John.C.Harrison
` (5 preceding siblings ...)
2022-04-08 22:20 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-04-09 0:15 ` Patchwork
6 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2022-04-09 0:15 UTC (permalink / raw)
To: john.c.harrison; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30240 bytes --]
== Series Details ==
Series: Update to GuC v70
URL : https://patchwork.freedesktop.org/series/102430/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11479_full -> Patchwork_22832_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_22832_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-glk: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [FAIL][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) ([i915#4392]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk1/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk1/boot.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk1/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk2/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk2/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk2/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk3/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk3/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk3/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk4/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk4/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk4/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk5/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk5/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk6/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk6/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk6/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk7/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk7/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk7/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk8/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk8/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk8/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk9/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk9/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk1/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk1/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk1/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk2/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk2/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk3/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk3/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk3/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk4/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk4/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk4/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk5/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk5/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk6/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk6/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk6/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk7/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk7/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk7/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk8/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk8/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk8/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk9/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk9/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk9/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@in-flight-contexts-immediate:
- shard-tglb: [PASS][51] -> [TIMEOUT][52] ([i915#3063])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-tglb3/igt@gem_eio@in-flight-contexts-immediate.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-tglb5/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: NOTRUN -> [FAIL][53] ([i915#2842]) +3 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
- shard-glk: [PASS][54] -> [FAIL][55] ([i915#2842]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk6/igt@gem_exec_fair@basic-none@vcs0.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk3/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][56] -> [FAIL][57] ([i915#2842]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-tglb5/igt@gem_exec_fair@basic-pace@bcs0.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-tglb1/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_flush@basic-wb-pro-default:
- shard-snb: [PASS][58] -> [SKIP][59] ([fdo#109271]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-snb7/igt@gem_exec_flush@basic-wb-pro-default.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-snb6/igt@gem_exec_flush@basic-wb-pro-default.html
* igt@gem_exec_whisper@basic-fds-priority-all:
- shard-skl: [PASS][60] -> [INCOMPLETE][61] ([i915#5268])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-skl4/igt@gem_exec_whisper@basic-fds-priority-all.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-skl5/igt@gem_exec_whisper@basic-fds-priority-all.html
* igt@gem_lmem_swapping@heavy-multi:
- shard-apl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#4613])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-apl8/igt@gem_lmem_swapping@heavy-multi.html
* igt@gem_lmem_swapping@random-engines:
- shard-iclb: NOTRUN -> [SKIP][63] ([i915#4613])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-iclb7/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@verify:
- shard-glk: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#4613])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk5/igt@gem_lmem_swapping@verify.html
* igt@gem_lmem_swapping@verify-random:
- shard-kbl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#4613]) +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-kbl4/igt@gem_lmem_swapping@verify-random.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [WARN][66] ([i915#2658])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-apl4/igt@gem_pread@exhaustion.html
* igt@gem_pxp@create-regular-context-1:
- shard-iclb: NOTRUN -> [SKIP][67] ([i915#4270])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-iclb7/igt@gem_pxp@create-regular-context-1.html
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled:
- shard-glk: NOTRUN -> [SKIP][68] ([fdo#109271]) +41 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk5/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled.html
* igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled:
- shard-iclb: NOTRUN -> [SKIP][69] ([i915#768])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-iclb7/igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-apl: NOTRUN -> [SKIP][70] ([fdo#109271]) +84 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-apl4/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
* igt@i915_selftest@live@gt_pm:
- shard-skl: NOTRUN -> [DMESG-FAIL][71] ([i915#1886])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-skl1/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [PASS][72] -> [INCOMPLETE][73] ([i915#3921])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-snb5/igt@i915_selftest@live@hangcheck.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-snb7/igt@i915_selftest@live@hangcheck.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
- shard-iclb: NOTRUN -> [SKIP][74] ([i915#5286])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-iclb7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-skl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#3777])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-skl8/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#3777]) +2 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-kbl1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-glk: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#3777]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk5/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-apl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#3777]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-apl4/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#3886])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk5/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][80] ([fdo#109278] / [i915#3886])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-iclb7/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#3886]) +2 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-kbl1/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#3886]) +3 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-skl8/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#3886]) +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-apl4/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@dp-hpd-storm-disable:
- shard-glk: NOTRUN -> [SKIP][84] ([fdo#109271] / [fdo#111827]) +4 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk5/igt@kms_chamelium@dp-hpd-storm-disable.html
* igt@kms_chamelium@dp-hpd-with-enabled-mode:
- shard-iclb: NOTRUN -> [SKIP][85] ([fdo#109284] / [fdo#111827])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-iclb7/igt@kms_chamelium@dp-hpd-with-enabled-mode.html
* igt@kms_chamelium@hdmi-hpd-storm-disable:
- shard-skl: NOTRUN -> [SKIP][86] ([fdo#109271] / [fdo#111827]) +3 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-skl8/igt@kms_chamelium@hdmi-hpd-storm-disable.html
* igt@kms_chamelium@vga-hpd-for-each-pipe:
- shard-apl: NOTRUN -> [SKIP][87] ([fdo#109271] / [fdo#111827]) +8 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-apl8/igt@kms_chamelium@vga-hpd-for-each-pipe.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-kbl: NOTRUN -> [SKIP][88] ([fdo#109271] / [fdo#111827]) +9 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-kbl1/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_content_protection@atomic:
- shard-apl: NOTRUN -> [TIMEOUT][89] ([i915#1319])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-apl8/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@mei_interface:
- shard-iclb: NOTRUN -> [SKIP][90] ([fdo#109300] / [fdo#111066])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-iclb7/igt@kms_content_protection@mei_interface.html
* igt@kms_cursor_crc@pipe-b-cursor-32x10-offscreen:
- shard-tglb: NOTRUN -> [SKIP][91] ([i915#3359])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-tglb5/igt@kms_cursor_crc@pipe-b-cursor-32x10-offscreen.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: NOTRUN -> [FAIL][92] ([i915#2346])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [PASS][93] -> [FAIL][94] ([i915#2346] / [i915#533])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
- shard-iclb: [PASS][95] -> [FAIL][96] ([i915#2346])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-iclb8/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
* igt@kms_dp_tiled_display@basic-test-pattern:
- shard-iclb: NOTRUN -> [SKIP][97] ([i915#426])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-iclb7/igt@kms_dp_tiled_display@basic-test-pattern.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-iclb: NOTRUN -> [SKIP][98] ([fdo#109274])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-iclb7/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [PASS][99] -> [FAIL][100] ([i915#79]) +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [PASS][101] -> [FAIL][102] ([i915#2122]) +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render:
- shard-tglb: NOTRUN -> [SKIP][103] ([fdo#109280] / [fdo#111825])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-render:
- shard-iclb: NOTRUN -> [SKIP][104] ([fdo#109280]) +5 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc:
- shard-kbl: NOTRUN -> [SKIP][105] ([fdo#109271]) +88 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-kbl1/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#533]) +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-apl4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][107] ([fdo#109271] / [i915#533])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-kbl4/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-apl: [PASS][108] -> [DMESG-WARN][109] ([i915#180]) +4 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][110] ([fdo#108145] / [i915#265]) +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-apl4/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][111] -> [FAIL][112] ([fdo#108145] / [i915#265])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-kbl: NOTRUN -> [FAIL][113] ([fdo#108145] / [i915#265])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-kbl4/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-skl: NOTRUN -> [FAIL][114] ([fdo#108145] / [i915#265])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale:
- shard-iclb: [PASS][115] -> [SKIP][116] ([i915#5235]) +2 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-iclb4/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping:
- shard-iclb: [PASS][117] -> [SKIP][118] ([i915#5176]) +1 similar issue
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-iclb5/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-iclb3/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-b-edp-1-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- shard-kbl: NOTRUN -> [SKIP][119] ([fdo#109271] / [i915#658]) +1 similar issue
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-kbl6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
- shard-glk: NOTRUN -> [SKIP][120] ([fdo#109271] / [i915#658])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk5/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-iclb: NOTRUN -> [SKIP][121] ([fdo#111068] / [i915#658])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-iclb7/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-apl: NOTRUN -> [SKIP][122] ([fdo#109271] / [i915#658]) +1 similar issue
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-apl4/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-iclb: [PASS][123] -> [SKIP][124] ([i915#5519]) +1 similar issue
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-iclb5/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-iclb7/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_scaling_modes@scaling-mode-none@edp-1-pipe-a:
- shard-skl: NOTRUN -> [SKIP][125] ([fdo#109271]) +74 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-skl7/igt@kms_scaling_modes@scaling-mode-none@edp-1-pipe-a.html
* igt@kms_scaling_modes@scaling-mode-none@edp-1-pipe-c:
- shard-iclb: NOTRUN -> [SKIP][126] ([i915#5030]) +2 similar issues
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-iclb7/igt@kms_scaling_modes@scaling-mode-none@edp-1-pipe-c.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-kbl: [PASS][127] -> [DMESG-WARN][128] ([i915#180])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-kbl1/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-kbl7/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@kms_vblank@pipe-d-ts-continuation-idle-hang:
- shard-iclb: NOTRUN -> [SKIP][129] ([fdo#109278]) +8 similar issues
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-iclb7/igt@kms_vblank@pipe-d-ts-continuation-idle-hang.html
* igt@kms_vrr@flip-basic:
- shard-tglb: NOTRUN -> [SKIP][130] ([fdo#109502])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-tglb5/igt@kms_vrr@flip-basic.html
* igt@perf@polling-parameterized:
- shard-glk: [PASS][131] -> [FAIL][132] ([i915#1542])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk6/igt@perf@polling-parameterized.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk1/igt@perf@polling-parameterized.html
- shard-kbl: [PASS][133] -> [FAIL][134] ([i915#1542])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-kbl6/igt@perf@polling-parameterized.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-kbl3/igt@perf@polling-parameterized.html
* igt@prime_nv_test@i915_nv_sharing:
- shard-iclb: NOTRUN -> [SKIP][135] ([fdo#109291]) +1 similar issue
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-iclb7/igt@prime_nv_test@i915_nv_sharing.html
* igt@sysfs_clients@fair-1:
- shard-apl: NOTRUN -> [SKIP][136] ([fdo#109271] / [i915#2994]) +1 similar issue
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-apl4/igt@sysfs_clients@fair-1.html
* igt@sysfs_clients@fair-7:
- shard-kbl: NOTRUN -> [SKIP][137] ([fdo#109271] / [i915#2994]) +1 similar issue
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-kbl6/igt@sysfs_clients@fair-7.html
- shard-glk: NOTRUN -> [SKIP][138] ([fdo#109271] / [i915#2994])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk5/igt@sysfs_clients@fair-7.html
* igt@sysfs_clients@pidname:
- shard-iclb: NOTRUN -> [SKIP][139] ([i915#2994])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-iclb7/igt@sysfs_clients@pidname.html
#### Possible fixes ####
* igt@gem_eio@in-flight-immediate:
- shard-tglb: [TIMEOUT][140] ([i915#3063]) -> [PASS][141]
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-tglb5/igt@gem_eio@in-flight-immediate.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-tglb1/igt@gem_eio@in-flight-immediate.html
* igt@gem_eio@in-flight-suspend:
- shard-kbl: [DMESG-WARN][142] ([i915#180]) -> [PASS][143] +1 similar issue
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-kbl7/igt@gem_eio@in-flight-suspend.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-kbl4/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][144] ([i915#2842]) -> [PASS][145]
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-glk: [FAIL][146] ([i915#2842]) -> [PASS][147]
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk6/igt@gem_exec_fair@basic-none@vecs0.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk3/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][148] ([i915#2849]) -> [PASS][149]
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_flush@basic-wb-rw-before-default:
- shard-snb: [SKIP][150] ([fdo#109271]) -> [PASS][151] +2 similar issues
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-snb6/igt@gem_exec_flush@basic-wb-rw-before-default.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-snb2/igt@gem_exec_flush@basic-wb-rw-before-default.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [SKIP][152] ([i915#4281]) -> [PASS][153]
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-iclb6/igt@i915_pm_dc@dc9-dpms.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-0:
- shard-glk: [DMESG-WARN][154] ([i915#118]) -> [PASS][155]
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk6/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk7/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: [DMESG-WARN][156] ([i915#180]) -> [PASS][157] +1 similar issue
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-apl4/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-apl8/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [FAIL][158] ([i915#2346]) -> [PASS][159]
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_fbcon_fbt@fbc:
- shard-tglb: [FAIL][160] ([i915#4767]) -> [PASS][161]
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11479/shard-tglb6/igt@kms_fbcon_fbt@fbc.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/shard-tglb5/igt@kms_fbcon_fbt@fbc.html
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22832/index.html
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