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From: "Souza, Jose" <jose.souza@intel.com>
To: "Roper, Matthew D" <matthew.d.roper@intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 5/5] drm/i915/vbt: Parse power conservation features block
Date: Tue, 12 Nov 2019 23:56:20 +0000	[thread overview]
Message-ID: <3eb0c3b944fe92f1bdc76808f2176ece5af8538f.camel@intel.com> (raw)
In-Reply-To: <20191112212155.GN21445@mdroper-desk1.amr.corp.intel.com>

On Tue, 2019-11-12 at 13:21 -0800, Matt Roper wrote:
> On Tue, Nov 05, 2019 at 05:45:04PM -0800, José Roberto de Souza
> wrote:
> > Since VBT 228 is from this block that PSR and other power saving
> > features configuration should be read from.
> > 
> > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_bios.c     | 19 +++++++++++-
> >  drivers/gpu/drm/i915/display/intel_vbt_defs.h | 29
> > +++++++++++++++++++
> >  2 files changed, 47 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > b/drivers/gpu/drm/i915/display/intel_bios.c
> > index a03f56b7b4ef..bf79e9858bd8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > @@ -561,7 +561,23 @@ parse_driver_features(struct drm_i915_private
> > *dev_priv,
> >  	 */
> >  	if (!driver->drrs_enabled)
> >  		dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
> > -	dev_priv->vbt.psr.enable = driver->psr_enabled;
> > +	if (bdb->version < 228)
> > +		dev_priv->vbt.psr.enable = driver->psr_enabled;
> > +}
> > +
> > +static void
> > +parse_power_conservation_features(struct drm_i915_private
> > *dev_priv,
> > +				  const struct bdb_header *bdb)
> > +{
> > +	const struct bdb_lfp_power *power;
> > +	u8 panel_type = dev_priv->vbt.panel_type;
> > +
> > +	power = find_section(bdb, BDB_LVDS_POWER);
> > +	if (!power)
> > +		return;
> > +
> > +	if (bdb->version >= 228)
> > +		dev_priv->vbt.psr.enable = power->psr & (1 <<
> > panel_type);
> 
> Should we also be setting dev_priv->vbt.drrs_type =
> DRRS_NOT_SUPPORTED
> if block 44 tells us it isn't valid on this panel?
> 

Yep, it should.
Thanks for catching this.

> 
> Matt
> 
> >  }
> >  
> >  static void
> > @@ -1878,6 +1894,7 @@ void intel_bios_init(struct drm_i915_private
> > *dev_priv)
> >  	parse_lfp_backlight(dev_priv, bdb);
> >  	parse_sdvo_panel_data(dev_priv, bdb);
> >  	parse_driver_features(dev_priv, bdb);
> > +	parse_power_conservation_features(dev_priv, bdb);
> >  	parse_edp(dev_priv, bdb);
> >  	parse_psr(dev_priv, bdb);
> >  	parse_mipi_config(dev_priv, bdb);
> > diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > index 69a7cb1fa121..31f47ce56587 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > @@ -792,6 +792,35 @@ struct bdb_lfp_backlight_data {
> >  	struct lfp_backlight_control_method backlight_control[16];
> >  } __packed;
> >  
> > +/*
> > + * Block 44 - LFP Power Conservation Features Block
> > + */
> > +
> > +struct als_data_entry {
> > +	u16 backlight_adjust;
> > +	u16 lux;
> > +} __packed;
> > +
> > +struct agressiveness_profile_entry {
> > +	u8 dpst_agressiveness : 4;
> > +	u8 lace_agressiveness : 4;
> > +} __packed;
> > +
> > +struct bdb_lfp_power {
> > +	u8 lfp_feature_bits;
> > +	struct als_data_entry als[5];
> > +	u8 lace_aggressiveness_profile;
> > +	u16 dpst;
> > +	u16 psr;
> > +	u16 drrs;
> > +	u16 lace_support;
> > +	u16 adt;
> > +	u16 dmrrs;
> > +	u16 adb;
> > +	u16 lace_enabled_status;
> > +	struct agressiveness_profile_entry aggressivenes[16];
> > +} __packed;
> > +
> >  /*
> >   * Block 52 - MIPI Configuration Block
> >   */
> > -- 
> > 2.24.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: "Souza, Jose" <jose.souza@intel.com>
To: "Roper, Matthew D" <matthew.d.roper@intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 5/5] drm/i915/vbt: Parse power conservation features block
Date: Tue, 12 Nov 2019 23:56:20 +0000	[thread overview]
Message-ID: <3eb0c3b944fe92f1bdc76808f2176ece5af8538f.camel@intel.com> (raw)
Message-ID: <20191112235620.8Hm31JPg-gW7mxoqlA2jp2_2nTc-Wlg3VW6iJQDEOUk@z> (raw)
In-Reply-To: <20191112212155.GN21445@mdroper-desk1.amr.corp.intel.com>

On Tue, 2019-11-12 at 13:21 -0800, Matt Roper wrote:
> On Tue, Nov 05, 2019 at 05:45:04PM -0800, José Roberto de Souza
> wrote:
> > Since VBT 228 is from this block that PSR and other power saving
> > features configuration should be read from.
> > 
> > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_bios.c     | 19 +++++++++++-
> >  drivers/gpu/drm/i915/display/intel_vbt_defs.h | 29
> > +++++++++++++++++++
> >  2 files changed, 47 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > b/drivers/gpu/drm/i915/display/intel_bios.c
> > index a03f56b7b4ef..bf79e9858bd8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > @@ -561,7 +561,23 @@ parse_driver_features(struct drm_i915_private
> > *dev_priv,
> >  	 */
> >  	if (!driver->drrs_enabled)
> >  		dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
> > -	dev_priv->vbt.psr.enable = driver->psr_enabled;
> > +	if (bdb->version < 228)
> > +		dev_priv->vbt.psr.enable = driver->psr_enabled;
> > +}
> > +
> > +static void
> > +parse_power_conservation_features(struct drm_i915_private
> > *dev_priv,
> > +				  const struct bdb_header *bdb)
> > +{
> > +	const struct bdb_lfp_power *power;
> > +	u8 panel_type = dev_priv->vbt.panel_type;
> > +
> > +	power = find_section(bdb, BDB_LVDS_POWER);
> > +	if (!power)
> > +		return;
> > +
> > +	if (bdb->version >= 228)
> > +		dev_priv->vbt.psr.enable = power->psr & (1 <<
> > panel_type);
> 
> Should we also be setting dev_priv->vbt.drrs_type =
> DRRS_NOT_SUPPORTED
> if block 44 tells us it isn't valid on this panel?
> 

Yep, it should.
Thanks for catching this.

> 
> Matt
> 
> >  }
> >  
> >  static void
> > @@ -1878,6 +1894,7 @@ void intel_bios_init(struct drm_i915_private
> > *dev_priv)
> >  	parse_lfp_backlight(dev_priv, bdb);
> >  	parse_sdvo_panel_data(dev_priv, bdb);
> >  	parse_driver_features(dev_priv, bdb);
> > +	parse_power_conservation_features(dev_priv, bdb);
> >  	parse_edp(dev_priv, bdb);
> >  	parse_psr(dev_priv, bdb);
> >  	parse_mipi_config(dev_priv, bdb);
> > diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > index 69a7cb1fa121..31f47ce56587 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > @@ -792,6 +792,35 @@ struct bdb_lfp_backlight_data {
> >  	struct lfp_backlight_control_method backlight_control[16];
> >  } __packed;
> >  
> > +/*
> > + * Block 44 - LFP Power Conservation Features Block
> > + */
> > +
> > +struct als_data_entry {
> > +	u16 backlight_adjust;
> > +	u16 lux;
> > +} __packed;
> > +
> > +struct agressiveness_profile_entry {
> > +	u8 dpst_agressiveness : 4;
> > +	u8 lace_agressiveness : 4;
> > +} __packed;
> > +
> > +struct bdb_lfp_power {
> > +	u8 lfp_feature_bits;
> > +	struct als_data_entry als[5];
> > +	u8 lace_aggressiveness_profile;
> > +	u16 dpst;
> > +	u16 psr;
> > +	u16 drrs;
> > +	u16 lace_support;
> > +	u16 adt;
> > +	u16 dmrrs;
> > +	u16 adb;
> > +	u16 lace_enabled_status;
> > +	struct agressiveness_profile_entry aggressivenes[16];
> > +} __packed;
> > +
> >  /*
> >   * Block 52 - MIPI Configuration Block
> >   */
> > -- 
> > 2.24.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2019-11-12 23:56 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-06  1:45 [PATCH 1/5] drm/i915/psr: Add bits per pixel limitation José Roberto de Souza
2019-11-06  1:45 ` [Intel-gfx] " José Roberto de Souza
2019-11-06  1:45 ` [PATCH 2/5] drm/i915/psr: Refactor psr short pulse handler José Roberto de Souza
2019-11-06  1:45   ` [Intel-gfx] " José Roberto de Souza
2019-11-12 17:31   ` Matt Roper
2019-11-12 17:31     ` [Intel-gfx] " Matt Roper
2019-11-06  1:45 ` [PATCH 3/5] drm/i915/psr: Enable ALPM lock timeout error interruption José Roberto de Souza
2019-11-06  1:45   ` [Intel-gfx] " José Roberto de Souza
2019-11-06  1:45 ` [PATCH 4/5] drm/i915/psr: Check if sink PSR capability changed José Roberto de Souza
2019-11-06  1:45   ` [Intel-gfx] " José Roberto de Souza
2019-11-06  1:45 ` [PATCH 5/5] drm/i915/vbt: Parse power conservation features block José Roberto de Souza
2019-11-06  1:45   ` [Intel-gfx] " José Roberto de Souza
2019-11-12 21:21   ` Matt Roper
2019-11-12 21:21     ` [Intel-gfx] " Matt Roper
2019-11-12 23:56     ` Souza, Jose [this message]
2019-11-12 23:56       ` Souza, Jose
2019-11-26  0:47       ` Souza, Jose
2019-11-26  0:47         ` [Intel-gfx] " Souza, Jose
2019-11-27 18:02         ` Matt Roper
2019-11-27 18:02           ` [Intel-gfx] " Matt Roper
2019-11-27 22:48           ` Souza, Jose
2019-11-27 22:48             ` [Intel-gfx] " Souza, Jose
2019-11-06  2:27 ` ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/psr: Add bits per pixel limitation Patchwork
2019-11-06  2:27   ` [Intel-gfx] " Patchwork
2019-11-06 23:24 ` ✓ Fi.CI.IGT: " Patchwork
2019-11-06 23:24   ` [Intel-gfx] " Patchwork
2019-11-12 17:16 ` [PATCH 1/5] " Matt Roper
2019-11-12 17:16   ` [Intel-gfx] " Matt Roper
2019-11-12 18:30   ` Souza, Jose
2019-11-12 18:30     ` [Intel-gfx] " Souza, Jose
2019-11-13 19:15   ` Lucas De Marchi
2019-11-13 19:15     ` [Intel-gfx] " Lucas De Marchi
2019-11-13 19:12 ` Lucas De Marchi
2019-11-13 19:12   ` [Intel-gfx] " Lucas De Marchi

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