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From: "Shankar, Uma" <uma.shankar@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 07/20] drm/i915: Relocate CHV CGM gamma masks
Date: Thu, 17 Sep 2020 19:46:30 +0000	[thread overview]
Message-ID: <3fd51d2bbba34400811ed4594d0df94e@intel.com> (raw)
In-Reply-To: <20200717211345.26851-8-ville.syrjala@linux.intel.com>



> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Saturday, July 18, 2020 2:44 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 07/20] drm/i915: Relocate CHV CGM gamma masks
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> CGM_PIPE_GAMMA_RED_MASK & co. are misplaced. Move then below the
> relevant register. And while at it add the degamma counterparts.

Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b9607ac3620d..428ef06b8084 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10999,14 +10999,17 @@ enum skl_power_gate {
>  #define _CGM_PIPE_A_CSC_COEFF67	(VLV_DISPLAY_BASE + 0x6790C)
>  #define _CGM_PIPE_A_CSC_COEFF8	(VLV_DISPLAY_BASE + 0x67910)
>  #define _CGM_PIPE_A_DEGAMMA	(VLV_DISPLAY_BASE + 0x66000)
> +#define   CGM_PIPE_DEGAMMA_RED_MASK	REG_GENMASK(13, 0)
> +#define   CGM_PIPE_DEGAMMA_GREEN_MASK	REG_GENMASK(29, 16)
> +#define   CGM_PIPE_DEGAMMA_BLUE_MASK	REG_GENMASK(13, 0)
>  #define _CGM_PIPE_A_GAMMA	(VLV_DISPLAY_BASE + 0x67000)
> +#define   CGM_PIPE_GAMMA_RED_MASK	REG_GENMASK(9, 0)
> +#define   CGM_PIPE_GAMMA_GREEN_MASK	REG_GENMASK(25, 16)
> +#define   CGM_PIPE_GAMMA_BLUE_MASK	REG_GENMASK(9, 0)
>  #define _CGM_PIPE_A_MODE	(VLV_DISPLAY_BASE + 0x67A00)
>  #define   CGM_PIPE_MODE_GAMMA	(1 << 2)
>  #define   CGM_PIPE_MODE_CSC	(1 << 1)
>  #define   CGM_PIPE_MODE_DEGAMMA	(1 << 0)
> -#define   CGM_PIPE_GAMMA_RED_MASK   REG_GENMASK(9, 0)
> -#define   CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16)
> -#define   CGM_PIPE_GAMMA_BLUE_MASK  REG_GENMASK(9, 0)
> 
>  #define _CGM_PIPE_B_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x69900)
>  #define _CGM_PIPE_B_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x69904)
> --
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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  parent reply	other threads:[~2020-09-17 19:46 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20200717211345.26851-1-ville.syrjala@linux.intel.com>
     [not found] ` <20200717211345.26851-2-ville.syrjala@linux.intel.com>
2020-09-17 19:20   ` [Intel-gfx] [PATCH 01/20] drm/i915: Fix state checker hw.active/hw.enable readout Shankar, Uma
     [not found] ` <20200717211345.26851-3-ville.syrjala@linux.intel.com>
2020-09-17 19:24   ` [Intel-gfx] [PATCH 02/20] drm/i915: Move MST master transcoder dump earlier Shankar, Uma
     [not found] ` <20200717211345.26851-4-ville.syrjala@linux.intel.com>
2020-09-17 19:27   ` [Intel-gfx] [PATCH 03/20] drm/i915: Include the LUT sizes in the state dump Shankar, Uma
     [not found] ` <20200717211345.26851-5-ville.syrjala@linux.intel.com>
2020-09-17 19:29   ` [Intel-gfx] [PATCH 04/20] drm/i915: s/glk_read_lut_10/bdw_read_lut_10/ Shankar, Uma
     [not found] ` <20200717211345.26851-6-ville.syrjala@linux.intel.com>
2020-09-17 19:39   ` [Intel-gfx] [PATCH 05/20] drm/i915: Reset glk degamma index after programming/readout Shankar, Uma
     [not found] ` <20200717211345.26851-7-ville.syrjala@linux.intel.com>
2020-09-17 19:42   ` [Intel-gfx] [PATCH 06/20] drm/i915: Shuffle chv_cgm_gamma_pack() around a bit Shankar, Uma
     [not found] ` <20200717211345.26851-8-ville.syrjala@linux.intel.com>
2020-09-17 19:46   ` Shankar, Uma [this message]
     [not found] ` <20200717211345.26851-9-ville.syrjala@linux.intel.com>
2020-09-17 19:58   ` [Intel-gfx] [PATCH 08/20] drm/i915: Add glk+ degamma readout Shankar, Uma
     [not found] ` <20200717211345.26851-10-ville.syrjala@linux.intel.com>
2020-09-17 20:06   ` [Intel-gfx] [PATCH 09/20] drm/i915: Read out CHV CGM degamma Shankar, Uma
     [not found] ` <20200717211345.26851-11-ville.syrjala@linux.intel.com>
2020-09-17 20:15   ` [Intel-gfx] [PATCH 10/20] drm/i915: Add gamma/degamma readout for bdw+ Shankar, Uma
     [not found] ` <20200717211345.26851-12-ville.syrjala@linux.intel.com>
2020-09-17 20:40   ` [Intel-gfx] [PATCH 11/20] drm/i915: Do degamma+gamma readout in bdw+ split gamma mode Shankar, Uma
     [not found] ` <20200717211345.26851-13-ville.syrjala@linux.intel.com>
2020-09-17 20:43   ` [Intel-gfx] [PATCH 12/20] drm/i915: Polish bdw_read_lut_10() a bit Shankar, Uma
     [not found] ` <20200717211345.26851-14-ville.syrjala@linux.intel.com>
2020-09-17 20:46   ` [Intel-gfx] [PATCH 13/20] drm/i915: Add gamma/degamm readout for ivb/hsw Shankar, Uma
     [not found] ` <20200717211345.26851-15-ville.syrjala@linux.intel.com>
2020-09-17 20:52   ` [Intel-gfx] [PATCH 14/20] drm/i915: Replace some gamma_mode ifs with switches Shankar, Uma
     [not found] ` <20200717211345.26851-16-ville.syrjala@linux.intel.com>
2020-09-17 20:56   ` [Intel-gfx] [PATCH 15/20] drm/i915: Make ilk_load_luts() deal with degamma Shankar, Uma
     [not found] ` <20200717211345.26851-17-ville.syrjala@linux.intel.com>
2020-09-17 20:58   ` [Intel-gfx] [PATCH 16/20] drm/i915: Make ilk_read_luts() capable of degamma readout Shankar, Uma
     [not found] ` <20200717211345.26851-18-ville.syrjala@linux.intel.com>
2020-09-17 21:00   ` [Intel-gfx] [PATCH 17/20] drm/i915: Make .read_luts() mandatory Shankar, Uma
     [not found] ` <20200717211345.26851-19-ville.syrjala@linux.intel.com>
2020-09-17 21:03   ` [Intel-gfx] [PATCH 18/20] drm/i915: Extract ilk_crtc_has_gamma() & co Shankar, Uma
     [not found] ` <20200717211345.26851-20-ville.syrjala@linux.intel.com>
2020-09-17 21:52   ` [Intel-gfx] [PATCH 19/20] drm/i915: Complete the gamma/degamma state checking Shankar, Uma
     [not found] ` <20200717211345.26851-21-ville.syrjala@linux.intel.com>
2020-09-21 19:40   ` [Intel-gfx] [PATCH 20/20] drm/i915: Add 10bit gamma mode for gen2/3 Shankar, Uma

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