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From: "Hogander, Jouni" <jouni.hogander@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"jani.nikula@linux.intel.com" <jani.nikula@linux.intel.com>
Subject: Re: [PATCH 04/13] drm/i915: Simplify PIPESRC_ERLY_TPT definition
Date: Mon, 20 May 2024 09:56:57 +0000	[thread overview]
Message-ID: <43b054c388feab4890acf70f3bacce0f0ad65aaf.camel@intel.com> (raw)
In-Reply-To: <87zfsku8m1.fsf@intel.com>

On Mon, 2024-05-20 at 12:37 +0300, Jani Nikula wrote:
> On Mon, 20 May 2024, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> > On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com>
> > wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x70000
> > > range.
> > > so using _MMIO_TRANS2() for it is not really correct. Also since
> > > this
> > > is a pipe register, and not present on CHV, the registers will be
> > > equally spaced out, so we can use the simpler _MMIO_PIPE()
> > > instead
> > > of _MMIO_PIPE2().
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> Side note, while reviewing this I found this monstrosity:
> 
> static bool intel_psr2_sel_fetch_config_valid(struct intel_dp
> *intel_dp,
>                                               struct intel_crtc_state
> *crtc_state)
> {
>         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> 
>         if (!dev_priv->display.params.enable_psr2_sel_fetch &&
>             intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
>                 drm_dbg_kms(&dev_priv->drm,
>                             "PSR2 sel fetch not enabled, disabled by
> parameter\n");
>                 return false;
>         }
> 
>         if (crtc_state->uapi.async_flip) {
>                 drm_dbg_kms(&dev_priv->drm,
>                             "PSR2 sel fetch not enabled, async flip
> enabled\n");
>                 return false;
>         }
> 
>         return crtc_state->enable_psr2_sel_fetch = true;
>         ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> }
> 
> Judging by name, a predicate function to check if config is valid,
> actually modifies the config in what looks like a typoed return
> statement. Ugh.

Yes, I have inhaled this already enough that it begun to look like
normal.

BR,

Jouni Högander


> 
> BR,
> Jani.
> 
> 


  reply	other threads:[~2024-05-20  9:57 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
2024-05-16 13:56 ` [PATCH 01/13] drm/i915: Add skl+ plane name aliases to enum plane_id Ville Syrjala
2024-05-17 15:33   ` Jani Nikula
2024-05-17 15:55     ` Ville Syrjälä
2024-05-17 17:12   ` [PATCH v2 " Ville Syrjala
2024-05-20  8:56     ` Jani Nikula
2024-05-16 13:56 ` [PATCH 02/13] drm/i915: Clean up the cursor register defines Ville Syrjala
2024-05-20  9:10   ` Jani Nikula
2024-05-20 16:23     ` Ville Syrjälä
2024-05-20 16:34       ` Jani Nikula
2024-05-16 13:56 ` [PATCH 03/13] drm/i915: Add separate define for SEL_FETCH_CUR_CTL() Ville Syrjala
2024-05-20  9:27   ` Jani Nikula
2024-05-20 17:08     ` Ville Syrjälä
2024-05-20 17:14   ` [PATCH v2 " Ville Syrjala
2024-05-16 13:56 ` [PATCH 04/13] drm/i915: Simplify PIPESRC_ERLY_TPT definition Ville Syrjala
2024-05-20  9:35   ` Jani Nikula
2024-05-20  9:37     ` Jani Nikula
2024-05-20  9:56       ` Hogander, Jouni [this message]
2024-05-16 13:56 ` [PATCH 05/13] drm/i915: Rename selective fetch plane registers Ville Syrjala
2024-05-20  9:39   ` Jani Nikula
2024-05-16 13:56 ` [PATCH 06/13] drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES() Ville Syrjala
2024-05-23  9:15   ` Jani Nikula
2024-05-23 12:06     ` Ville Syrjälä
2024-05-16 13:56 ` [PATCH 07/13] drm/i915: Add separate defines for cursor WM/DDB register bits Ville Syrjala
2024-05-20 13:24   ` Jani Nikula
2024-05-16 13:56 ` [PATCH 08/13] drm/i915: Move PIPEGCMAX to intel_color_regs.h Ville Syrjala
2024-05-20 13:07   ` Jani Nikula
2024-05-16 13:56 ` [PATCH 09/13] drm/i915: Extract i9xx_plane_regs.h Ville Syrjala
2024-05-20 13:09   ` Jani Nikula
2024-05-16 13:56 ` [PATCH 10/13] drm/i915: Polish pre-skl primary plane registers Ville Syrjala
2024-05-20 13:12   ` Jani Nikula
2024-05-16 13:56 ` [PATCH 11/13] drm/i915: Document a few pre-skl primary plane platform dependencies Ville Syrjala
2024-05-20 13:16   ` Jani Nikula
2024-05-16 13:56 ` [PATCH 12/13] drm/i915: Polish sprite plane register definitions Ville Syrjala
2024-05-20 13:17   ` Jani Nikula
2024-05-20 13:18     ` Jani Nikula
2024-05-16 13:56 ` [PATCH 13/13] drm/i915: Document which platforms use which sprite registers Ville Syrjala
2024-05-20 13:18   ` Jani Nikula
2024-05-16 14:36 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanups Patchwork
2024-05-16 14:36 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-05-16 18:21 ` ✗ Fi.CI.BAT: failure " Patchwork
2024-05-17 18:07 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanups (rev2) Patchwork
2024-05-17 18:08 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-05-17 18:26 ` ✓ Fi.CI.BAT: success " Patchwork
2024-05-18  5:46 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-05-20 18:08 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanups (rev3) Patchwork
2024-05-20 18:08 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-05-20 18:20 ` ✓ Fi.CI.BAT: success " Patchwork
2024-05-21  5:29 ` ✗ Fi.CI.IGT: failure " Patchwork

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