Re: [PATCH 03/13] drm/i915: Add separate define for SEL_FETCH_CUR_CTL()

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Mon, May 20, 2024 at 12:27:20PM +0300, Jani Nikula wrote:
> On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Split the cursor stuff from the rest of the selective fetch
> > plane registers so that we can collect all cursor registers
> > in intel_cursor_regs.h. Also take the opportunity to rename
> > the registers to match the spec.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cursor.c      | 6 +++---
> >  drivers/gpu/drm/i915/display/intel_cursor_regs.h | 5 +++++
> >  2 files changed, 8 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> > index c780ce146131..b44809899502 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> > @@ -508,7 +508,7 @@ static void i9xx_cursor_disable_sel_fetch_arm(struct intel_plane *plane,
> >  	if (!crtc_state->enable_psr2_sel_fetch)
> >  		return;
> >  
> > -	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
> > +	intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), 0);
> >  }
> >  
> >  static void wa_16021440873(struct intel_plane *plane,
> > @@ -523,7 +523,7 @@ static void wa_16021440873(struct intel_plane *plane,
> >  	ctl &= ~MCURSOR_MODE_MASK;
> >  	ctl |= MCURSOR_MODE_64_2B;
> >  
> > -	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), ctl);
> > +	intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl);
> >  
> >  	intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe),
> >  		       PIPESRC_HEIGHT(et_y_position));
> > @@ -548,7 +548,7 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane,
> >  					  val);
> >  		}
> >  
> > -		intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
> > +		intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe),
> >  				  plane_state->ctl);
> >  	} else {
> >  		/* Wa_16021440873 */
> > diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> > index 270c26c2e6df..ab02d497fba6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> > @@ -95,4 +95,9 @@
> >  #define _CUR_BUF_CFG_B		0x7117c
> >  #define CUR_BUF_CFG(pipe)	_MMIO_PIPE((pipe), _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
> >  
> > +#define _SEL_FETCH_CUR_CTL_A	0x70880 /* mtl+ */
> > +#define _SEL_FETCH_CUR_CTL_B	0x71880
> > +#define SEL_FETCH_CUR_CTL(pipe)	_MMIO_PIPE((pipe), _SEL_FETCH_CUR_CTL_A, _SEL_FETCH_CUR_CTL_A)
> 
> _SEL_FETCH_CUR_CTL_A is doubled, the latter should be _B.

Derp. I also don't know where I got that mtl+ note. I must have been
thinking about early transport or something, but selective fetch
in general should be a thing for tgl+.

> 
> With that,
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> I must admit I was trying to follow how PLANE_SEL_FETCH_CTL(pipe,
> CURSOR_A) ends up being identical to this new SEL_FETCH_CUR_CTL(pipe),
> but holy crap it trips my brain completely. How did we come up with so
> many levels of abstractions for this stuff, in such complicated ways?!
> :o
> 
> 
> > +#define   SEL_FETCH_CUR_CTL_ENABLE	REG_BIT(31)
> > +
> >  #endif /* __INTEL_CURSOR_REGS_H__ */
> 
> -- 
> Jani Nikula, Intel

-- 
Ville Syrjälä
Intel