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From: Kenneth Graunke <kenneth@whitecape.org>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/3] i915: Rename PIPE_CONTROL bit defines to be less terse.
Date: Tue, 04 Oct 2011 22:13:47 -0700	[thread overview]
Message-ID: <4E8BE78B.5060005@whitecape.org> (raw)
In-Reply-To: <20111004083027.GA2870@phenom.ffwll.local>

On 10/04/2011 01:30 AM, Daniel Vetter wrote:
> On Mon, Oct 03, 2011 at 11:02:39PM -0700, Kenneth Graunke wrote:
>> "STALL_AT_SCOREBOARD" is much clearer than "STALL_EN" now that there are
>> several different kinds of stalls.  Also, "INSTRUCTION_CACHE_FLUSH" is a
>> lot easier to understand at a glance than the terse "IS_FLUSH."
>>
>> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h         |   16 ++++++++--------
>>  drivers/gpu/drm/i915/intel_ringbuffer.c |    6 ++++--
>>  2 files changed, 12 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index d691781..bfe8488 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -243,15 +243,15 @@
>>  #define   DISPLAY_PLANE_A           (0<<20)
>>  #define   DISPLAY_PLANE_B           (1<<20)
>>  #define GFX_OP_PIPE_CONTROL	((0x3<<29)|(0x3<<27)|(0x2<<24))
>> -#define   PIPE_CONTROL_QW_WRITE	(1<<14)
>> -#define   PIPE_CONTROL_DEPTH_STALL (1<<13)
>> -#define   PIPE_CONTROL_WC_FLUSH	(1<<12)
>> -#define   PIPE_CONTROL_IS_FLUSH	(1<<11) /* MBZ on Ironlake */
>> -#define   PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
>> -#define   PIPE_CONTROL_ISP_DIS	(1<<9)
>> -#define   PIPE_CONTROL_NOTIFY	(1<<8)
>> +#define   PIPE_CONTROL_QW_WRITE			(1<<14)
>> +#define   PIPE_CONTROL_DEPTH_STALL		(1<<13)
>> +#define   PIPE_CONTROL_WRITE_FLUSH		(1<<12)
>> +#define   PIPE_CONTROL_INSTRUCTION_CACHE_FLUSH	(1<<11) /* MBZ on Ironlake */
>> +#define   PIPE_CONTROL_TEXTURE_CACHE_FLUSH	(1<<10) /* GM45+ only */
> 
> Minor bikeshed: You retain the _FLUSH for the read-only
> instruction/texture caches, but use _INVALIDATE for the new bits for
> read-only caches. I think we want _INVALIDATE for all of them.
> 
> Otherwise, these three patches are:
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Yeah.  The docs for pre-SNB use "Flush" in all the field names, while
the docs for SNB+ switch to "Invalidate".  So I just used it for the new
ones.  If we'd rather go with "invalidate" for the old bits too, I can
do that.

  reply	other threads:[~2011-10-05  5:12 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-10-04  6:02 [PATCH 1/3] i915: Remove implied length of 2 from GFX_OP_PIPE_CONTROL #define Kenneth Graunke
2011-10-04  6:02 ` [PATCH 2/3] i915: Rename PIPE_CONTROL bit defines to be less terse Kenneth Graunke
2011-10-04  8:30   ` Daniel Vetter
2011-10-05  5:13     ` Kenneth Graunke [this message]
2011-10-05 10:05       ` Daniel Vetter
2011-10-05 22:29   ` Ben Widawsky
2011-10-04  6:02 ` [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing on gen6+ Kenneth Graunke
2011-10-05 22:57   ` Ben Widawsky
2011-10-05 23:36     ` Chris Wilson
2011-10-05 23:54       ` Daniel Vetter
2011-10-06  0:59     ` Eric Anholt
2011-10-06  5:15       ` Ben Widawsky
2011-10-06 18:00         ` Eric Anholt
2011-10-06 19:01           ` Ben Widawsky
2011-10-05 23:39   ` Ben Widawsky
2011-10-05 20:35 ` [PATCH 1/3] i915: Remove implied length of 2 from GFX_OP_PIPE_CONTROL #define Ben Widawsky
2011-10-11 11:09 ` Daniel Vetter
2011-10-11 17:20   ` Jesse Barnes
2011-10-11 18:39     ` Ben Widawsky
2011-10-11 18:53       ` Jesse Barnes
2011-10-11 22:17         ` Keith Packard

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