From: Eric Anholt <eric@anholt.net>
To: Ben Widawsky <ben@bwidawsk.net>, Kenneth Graunke <kenneth@whitecape.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing on gen6+.
Date: Wed, 05 Oct 2011 17:59:31 -0700 [thread overview]
Message-ID: <87zkhf2avg.fsf@eliezer.anholt.net> (raw)
In-Reply-To: <20111005155713.6e2f0c6c@bwidawsk.net>
[-- Attachment #1.1: Type: text/plain, Size: 911 bytes --]
On Wed, 5 Oct 2011 15:57:13 -0700, Ben Widawsky <ben@bwidawsk.net> wrote:
> I think we also want a TLB invalidate here, bit 18. This requires another
> workaround before issuing this flush: We need 2 Store Data Commands (such as
> MI_STORE_DATA_IMM or MI_STORE_DATA_INDEX) before sending PIPE_CONTROL w/ stall
> (20) and TLB inv bit (18) set
From the docs for GFX_MODE:
"This field controls the invalidation if the TLB cache inside the
hardware. When enabled this bit limits the invalidation of the TLB
only to batch buffer boundaries or to pipe_control commands which
have the TLB invalidation bit set. If disabled, the TLB caches are
flushed for every full flush of the pipeline"
We're already getting TLB invalidate at batchbuffer boundaries
(actually, even more: every pipeline stall, since that bit is 0 on my
hardware). What would we need this new flush for?
[-- Attachment #1.2: Type: application/pgp-signature, Size: 197 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2011-10-06 0:59 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-10-04 6:02 [PATCH 1/3] i915: Remove implied length of 2 from GFX_OP_PIPE_CONTROL #define Kenneth Graunke
2011-10-04 6:02 ` [PATCH 2/3] i915: Rename PIPE_CONTROL bit defines to be less terse Kenneth Graunke
2011-10-04 8:30 ` Daniel Vetter
2011-10-05 5:13 ` Kenneth Graunke
2011-10-05 10:05 ` Daniel Vetter
2011-10-05 22:29 ` Ben Widawsky
2011-10-04 6:02 ` [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing on gen6+ Kenneth Graunke
2011-10-05 22:57 ` Ben Widawsky
2011-10-05 23:36 ` Chris Wilson
2011-10-05 23:54 ` Daniel Vetter
2011-10-06 0:59 ` Eric Anholt [this message]
2011-10-06 5:15 ` Ben Widawsky
2011-10-06 18:00 ` Eric Anholt
2011-10-06 19:01 ` Ben Widawsky
2011-10-05 23:39 ` Ben Widawsky
2011-10-05 20:35 ` [PATCH 1/3] i915: Remove implied length of 2 from GFX_OP_PIPE_CONTROL #define Ben Widawsky
2011-10-11 11:09 ` Daniel Vetter
2011-10-11 17:20 ` Jesse Barnes
2011-10-11 18:39 ` Ben Widawsky
2011-10-11 18:53 ` Jesse Barnes
2011-10-11 22:17 ` Keith Packard
-- strict thread matches above, loose matches on Subject: below --
2011-10-11 21:41 [PATCH 1/3] drm/i915: " Daniel Vetter
2011-10-11 21:41 ` [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing on gen6+ Daniel Vetter
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87zkhf2avg.fsf@eliezer.anholt.net \
--to=eric@anholt.net \
--cc=ben@bwidawsk.net \
--cc=intel-gfx@lists.freedesktop.org \
--cc=kenneth@whitecape.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox