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From: Lyude Paul <lyude@redhat.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 07/18] drm/dp: Pimp drm_dp_downstream_max_bpc()
Date: Thu, 10 Sep 2020 15:40:22 -0400	[thread overview]
Message-ID: <4a86567044381fad26fe6e16ac5a2685b3c9cd84.camel@redhat.com> (raw)
In-Reply-To: <20200910144623.GA6112@intel.com>

On Thu, 2020-09-10 at 17:46 +0300, Ville Syrjälä wrote:
> On Tue, Sep 08, 2020 at 01:51:56PM -0400, Lyude Paul wrote:
> > On Fri, 2020-09-04 at 14:53 +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Deal with more cases in drm_dp_downstream_max_bpc():
> > > - DPCD 1.0 -> assume 8bpc for non-DP
> > > - DPCD 1.1+ DP (or DP++ with DP sink) -> allow anything
> > > - DPCD 1.1+ TMDS -> check the caps, assume 8bpc if the value is crap
> > > - anything else -> assume 8bpc
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/drm_dp_helper.c               | 69 +++++++++++--------
> > >  .../drm/i915/display/intel_display_debugfs.c  |  3 +-
> > >  drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
> > >  include/drm/drm_dp_helper.h                   | 10 ++-
> > >  4 files changed, 51 insertions(+), 33 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/drm_dp_helper.c
> > > b/drivers/gpu/drm/drm_dp_helper.c
> > > index 0fcb94f7dbe5..ab87209c25d8 100644
> > > --- a/drivers/gpu/drm/drm_dp_helper.c
> > > +++ b/drivers/gpu/drm/drm_dp_helper.c
> > > @@ -653,36 +653,44 @@ int drm_dp_downstream_max_clock(const u8
> > > dpcd[DP_RECEIVER_CAP_SIZE],
> > >  EXPORT_SYMBOL(drm_dp_downstream_max_clock);
> > >  
> > >  /**
> > > - * drm_dp_downstream_max_bpc() - extract branch device max
> > > - *                               bits per component
> > > - * @dpcd: DisplayPort configuration data
> > > - * @port_cap: port capabilities
> > > - *
> > > - * See also:
> > > - * drm_dp_read_downstream_info()
> > > - * drm_dp_downstream_max_clock()
> > > - *
> > > - * Returns: Max bpc on success or 0 if max bpc not defined
> > > - */
> > > +  * drm_dp_downstream_max_bpc() - extract downstream facing port max
> > > +  *                               bits per component
> > > +  * @dpcd: DisplayPort configuration data
> > > +  * @port_cap: downstream facing port capabilities
> > > +  * @edid: EDID
> > > +  *
> > > +  * Returns max bpc on success or 0 if max bpc not defined
> > > +  */
> > >  int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> > > -			      const u8 port_cap[4])
> > > +			      const u8 port_cap[4],
> > > +			      const struct edid *edid)
> > >  {
> > > -	int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
> > > -	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
> > > -		DP_DETAILED_CAP_INFO_AVAILABLE;
> > > -	int bpc;
> > > -
> > > -	if (!detailed_cap_info)
> > 
> > I don't think we can drop this check. There's a somewhat surprising blurb
> > about downstream port caps in the DP 2.0 spec (section 5.3.3.1):
> > 
> >    In addition, the adapter shall set the Detailed Capabilities Info
> > registers
> >    (DPCD Addresses 00080h through 0008Fh) to show all the downstream types,
> >    including DFP 0. Either one or four bytes are used, per DFP type
> >    indication. Therefore, up to 16 (with 1-byte descriptor) or four (with 4-
> >    byte descriptor) DFP capabilities can be stored.
> > 
> > I've never once actually seen a sink do this, but this does mean it's
> > technically possible tthat if we don't check the detailed caps bit then we
> > might end up reading another port's DFP type instead of max_bpc info. Note
> > though that we can make the assumption the four byte version of the field is
> > used for DP 1.4+
> 
> The check is now ...
> 
> 
> > > +	if (!drm_dp_is_branch(dpcd))
> > >  		return 0;
> > >  
> > > -	switch (type) {
> > > -	case DP_DS_PORT_TYPE_VGA:
> > > -	case DP_DS_PORT_TYPE_DVI:
> > > -	case DP_DS_PORT_TYPE_HDMI:
> > > +	if (dpcd[DP_DPCD_REV] < 0x11) {
> > > +		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] &
> > > DP_DWN_STRM_PORT_TYPE_MASK) {
> > > +		case DP_DWN_STRM_PORT_TYPE_DP:
> > > +			return 0;
> > > +		default:
> > > +			return 8;
> > > +		}
> > > +	}
> > > +
> > > +	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
> > > +	case DP_DS_PORT_TYPE_DP:
> > > +		return 0;
> > >  	case DP_DS_PORT_TYPE_DP_DUALMODE:
> > > -		bpc = port_cap[2] & DP_DS_MAX_BPC_MASK;
> > > +		if (is_edid_digital_input_dp(edid))
> > > +			return 0;
> > > +		fallthrough;
> > > +	case DP_DS_PORT_TYPE_HDMI:
> > > +	case DP_DS_PORT_TYPE_DVI:
> > > +	case DP_DS_PORT_TYPE_VGA:
> > > +		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] &
> > > DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
> > > +			return 8;
> 
> ... here

Ah-missed that! R-b'd by me then :)
> 
> 
> > >  
> > > -		switch (bpc) {
> > > +		switch (port_cap[2] & DP_DS_MAX_BPC_MASK) {
> > >  		case DP_DS_8BPC:
> > >  			return 8;
> > >  		case DP_DS_10BPC:
> > > @@ -691,10 +699,12 @@ int drm_dp_downstream_max_bpc(const u8
> > > dpcd[DP_RECEIVER_CAP_SIZE],
> > >  			return 12;
> > >  		case DP_DS_16BPC:
> > >  			return 16;
> > > +		default:
> > > +			return 8;
> > >  		}
> > > -		fallthrough;
> > > +		break;
> > >  	default:
> > > -		return 0;
> > > +		return 8;
> > >  	}
> > >  }
> > >  EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
> > > @@ -717,12 +727,15 @@ EXPORT_SYMBOL(drm_dp_downstream_id);
> > >   * @m: pointer for debugfs file
> > >   * @dpcd: DisplayPort configuration data
> > >   * @port_cap: port capabilities
> > > + * @edid: EDID
> > >   * @aux: DisplayPort AUX channel
> > >   *
> > >   */
> > >  void drm_dp_downstream_debug(struct seq_file *m,
> > >  			     const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> > > -			     const u8 port_cap[4], struct drm_dp_aux *aux)
> > > +			     const u8 port_cap[4],
> > > +			     const struct edid *edid,
> > > +			     struct drm_dp_aux *aux)
> > >  {
> > >  	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
> > >  				 DP_DETAILED_CAP_INFO_AVAILABLE;
> > > @@ -789,7 +802,7 @@ void drm_dp_downstream_debug(struct seq_file *m,
> > >  				seq_printf(m, "\t\tMax TMDS clock: %d kHz\n",
> > > clk);
> > >  		}
> > >  
> > > -		bpc = drm_dp_downstream_max_bpc(dpcd, port_cap);
> > > +		bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid);
> > >  
> > >  		if (bpc > 0)
> > >  			seq_printf(m, "\t\tMax bpc: %d\n", bpc);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > index 53a0a3d9a22d..0bf31f9a8af5 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > @@ -626,6 +626,7 @@ static void intel_dp_info(struct seq_file *m,
> > >  {
> > >  	struct intel_encoder *intel_encoder =
> > > intel_attached_encoder(intel_connector);
> > >  	struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
> > > +	const struct drm_property_blob *edid = intel_connector-
> > > > base.edid_blob_ptr;
> > >  
> > >  	seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
> > >  	seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
> > > @@ -633,7 +634,7 @@ static void intel_dp_info(struct seq_file *m,
> > >  		intel_panel_info(m, &intel_connector->panel);
> > >  
> > >  	drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
> > > -				&intel_dp->aux);
> > > +				edid ? edid->data : NULL, &intel_dp->aux);
> > >  }
> > >  
> > >  static void intel_dp_mst_info(struct seq_file *m,
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 2c8e82d97a34..c73b3efd84e0 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -6071,7 +6071,7 @@ intel_dp_set_edid(struct intel_dp *intel_dp)
> > >  
> > >  	intel_dp->dfp.max_bpc =
> > >  		drm_dp_downstream_max_bpc(intel_dp->dpcd,
> > > -					  intel_dp->downstream_ports);
> > > +					  intel_dp->downstream_ports, edid);
> > >  
> > >  	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] DFP max bpc %d\n",
> > >  		    connector->base.base.id, connector->base.name,
> > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > > index 4f946826dfce..6218de1294c1 100644
> > > --- a/include/drm/drm_dp_helper.h
> > > +++ b/include/drm/drm_dp_helper.h
> > > @@ -1646,10 +1646,14 @@ bool drm_dp_downstream_is_tmds(const u8
> > > dpcd[DP_RECEIVER_CAP_SIZE],
> > >  int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> > >  				const u8 port_cap[4]);
> > >  int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> > > -			      const u8 port_cap[4]);
> > > +			      const u8 port_cap[4],
> > > +			      const struct edid *edid);
> > >  int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
> > > -void drm_dp_downstream_debug(struct seq_file *m, const u8
> > > dpcd[DP_RECEIVER_CAP_SIZE],
> > > -			     const u8 port_cap[4], struct drm_dp_aux *aux);
> > > +void drm_dp_downstream_debug(struct seq_file *m,
> > > +			     const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> > > +			     const u8 port_cap[4],
> > > +			     const struct edid *edid,
> > > +			     struct drm_dp_aux *aux);
> > >  enum drm_mode_subconnector
> > >  drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> > >  			 const u8 port_cap[4]);
> > -- 
> > Cheers,
> > 	Lyude Paul (she/her)
> > 	Software Engineer at Red Hat
-- 
Sincerely,
      Lyude Paul (she/her)
      Software Engineer at Red Hat

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  reply	other threads:[~2020-09-10 19:40 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-04 11:53 [Intel-gfx] [PATCH v2 00/18] drm/i915: Pimp DP DFP handling Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 01/18] drm/dp: Dump downstream facing port caps Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 02/18] drm/i915/lspcon: Do not send infoframes to non-HDMI sinks Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 03/18] drm/dp: Define protocol converter DPCD registers Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 04/18] drm/dp: Define more downstream facing port caps Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 05/18] drm/i915: Reworkd DFP max bpc handling Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 06/18] drm/dp: Add helpers to identify downstream facing port types Ville Syrjala
2020-09-08 17:30   ` Lyude Paul
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 07/18] drm/dp: Pimp drm_dp_downstream_max_bpc() Ville Syrjala
2020-09-08 17:32   ` Lyude Paul
2020-09-08 17:51   ` Lyude Paul
2020-09-10 14:46     ` Ville Syrjälä
2020-09-10 19:40       ` Lyude Paul [this message]
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 08/18] drm/dp: Redo drm_dp_downstream_max_clock() as drm_dp_downstream_max_dotclock() Ville Syrjala
2020-09-08 17:56   ` Lyude Paul
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 09/18] drm/i915: Reworkd DP DFP clock handling Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Ville Syrjala
2020-09-08 18:04   ` Lyude Paul
2020-09-17 12:46     ` Ville Syrjälä
2020-09-08 18:08   ` Lyude Paul
2020-09-10 13:55     ` Ville Syrjälä
2020-09-10 19:40       ` Lyude Paul
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 11/18] drm/i915: Deal with TMDS DFP clock limits Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 12/18] drm/i915: Configure DP 1.3+ protocol converted HDMI mode Ville Syrjala
2020-09-08 18:11   ` Lyude Paul
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 13/18] drm/dp: Add drm_dp_downstream_mode() Ville Syrjala
2020-09-08 18:13   ` Lyude Paul
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 14/18] drm/i915: Handle downstream facing ports w/o EDID Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 15/18] drm/i915: Extract intel_hdmi_has_audio() Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 16/18] drm/i915: DP->HDMI TMDS clock limits vs. deep color Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 17/18] drm/dp: Add helpers for DFP YCbCr 4:2:0 handling Ville Syrjala
2020-09-08 18:15   ` Lyude Paul
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 18/18] drm/i915: Do YCbCr 444->420 conversion via DP protocol converters Ville Syrjala
2020-09-04 13:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Pimp DP DFP handling (rev2) Patchwork
2020-09-04 13:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-09-04 20:09 ` [Intel-gfx] [PATCH v2 00/18] drm/i915: Pimp DP DFP handling Lyude Paul
2020-09-04 21:32 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Pimp DP DFP handling (rev2) Patchwork
2020-09-08 18:34 ` [Intel-gfx] [PATCH v2 00/18] drm/i915: Pimp DP DFP handling Lyude Paul
2020-09-17 16:11   ` Ville Syrjälä

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