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From: Lyude Paul <lyude@redhat.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	 dri-devel@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 13/18] drm/dp: Add drm_dp_downstream_mode()
Date: Tue, 08 Sep 2020 14:13:18 -0400	[thread overview]
Message-ID: <d2654d714808cdead0b713c52601ffe897bbb640.camel@redhat.com> (raw)
In-Reply-To: <20200904115354.25336-14-ville.syrjala@linux.intel.com>

On Fri, 2020-09-04 at 14:53 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The downstream facing port caps in the DPCD can give us a hint
> as to what kind of display mode the sink can use if it doesn't
> have an EDID. Use that information to pick a suitable mode.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/drm_dp_helper.c | 54 +++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/drm_edid.c      | 19 ++++++++++++
>  include/drm/drm_dp_helper.h     | 12 ++++++++
>  include/drm/drm_edid.h          |  4 +++
>  4 files changed, 89 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c
> b/drivers/gpu/drm/drm_dp_helper.c
> index f567428f2aef..0d5e9bcf11d0 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -808,6 +808,60 @@ int drm_dp_downstream_max_bpc(const u8
> dpcd[DP_RECEIVER_CAP_SIZE],
>  }
>  EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
>  
> +/**
> + * drm_dp_downstream_mode() - return a mode for downstream facing port
> + * @dpcd: DisplayPort configuration data
> + * @port_cap: port capabilities
> + *
> + * Provides a suitable mode for downstream facing ports without EDID.
> + *
> + * Returns a new drm_display_mode on success or NULL on failure
> + */
> +struct drm_display_mode *
> +drm_dp_downstream_mode(struct drm_device *dev,
> +		       const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> +		       const u8 port_cap[4])
> +
> +{
> +	u8 vic;
> +
> +	if (!drm_dp_is_branch(dpcd))
> +		return NULL;
> +
> +	if (dpcd[DP_DPCD_REV] < 0x11)
> +		return NULL;
> +
> +	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
> +	case DP_DS_PORT_TYPE_NON_EDID:
> +		switch (port_cap[0] & DP_DS_NON_EDID_MASK) {
> +		case DP_DS_NON_EDID_720x480i_60:
> +			vic = 6;
> +			break;
> +		case DP_DS_NON_EDID_720x480i_50:
> +			vic = 21;
> +			break;
> +		case DP_DS_NON_EDID_1920x1080i_60:
> +			vic = 5;
> +			break;
> +		case DP_DS_NON_EDID_1920x1080i_50:
> +			vic = 20;
> +			break;
> +		case DP_DS_NON_EDID_1280x720_60:
> +			vic = 4;
> +			break;
> +		case DP_DS_NON_EDID_1280x720_50:
> +			vic = 19;
> +			break;
> +		default:
> +			return NULL;
> +		}
> +		return drm_display_mode_from_cea_vic(dev, vic);
> +	default:
> +		return NULL;
> +	}
> +}
> +EXPORT_SYMBOL(drm_dp_downstream_mode);
> +
>  /**
>   * drm_dp_downstream_id() - identify branch device
>   * @aux: DisplayPort AUX channel
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 6840f0530a38..b9419fed6c28 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -3738,6 +3738,25 @@ drm_add_cmdb_modes(struct drm_connector *connector,
> u8 svd)
>  	bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
>  }
>  
> +struct drm_display_mode *
> +drm_display_mode_from_cea_vic(struct drm_device *dev,
> +			      u8 video_code)
> +{
> +	const struct drm_display_mode *cea_mode;
> +	struct drm_display_mode *newmode;
> +
> +	cea_mode = cea_mode_for_vic(video_code);
> +	if (!cea_mode)
> +		return NULL;
> +
> +	newmode = drm_mode_duplicate(dev, cea_mode);
> +	if (!newmode)
> +		return NULL;
> +
> +	return newmode;
> +}
> +EXPORT_SYMBOL(drm_display_mode_from_cea_vic);

Forgot the kdocs

> +
>  static int
>  do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
>  {
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 6812a3e0de8d..fbba4a0f7366 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -28,6 +28,8 @@
>  #include <linux/types.h>
>  #include <drm/drm_connector.h>
>  
> +struct drm_device;
> +
>  /*
>   * Unless otherwise noted, all values are from the DP 1.1a spec.  Note that
>   * DP and DPCD versions are independent.  Differences from 1.0 are not
> noted,
> @@ -385,6 +387,13 @@
>  # define DP_DS_PORT_TYPE_DP_DUALMODE        5
>  # define DP_DS_PORT_TYPE_WIRELESS           6
>  # define DP_DS_PORT_HPD			    (1 << 3)
> +# define DP_DS_NON_EDID_MASK		    (0xf << 4)
> +# define DP_DS_NON_EDID_720x480i_60	    (1 << 4)
> +# define DP_DS_NON_EDID_720x480i_50	    (2 << 4)
> +# define DP_DS_NON_EDID_1920x1080i_60	    (3 << 4)
> +# define DP_DS_NON_EDID_1920x1080i_50	    (4 << 4)
> +# define DP_DS_NON_EDID_1280x720_60	    (5 << 4)
> +# define DP_DS_NON_EDID_1280x720_50	    (7 << 4)
>  /* offset 1 for VGA is maximum megapixels per second / 8 */
>  /* offset 1 for DVI/HDMI is maximum TMDS clock in Mbps / 2.5 */
>  /* offset 2 for VGA/DVI/HDMI */
> @@ -1654,6 +1663,9 @@ int drm_dp_downstream_min_tmds_clock(const u8
> dpcd[DP_RECEIVER_CAP_SIZE],
>  int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
>  			      const u8 port_cap[4],
>  			      const struct edid *edid);
> +struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
> +						const u8
> dpcd[DP_RECEIVER_CAP_SIZE],
> +						const u8 port_cap[4]);
>  int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
>  void drm_dp_downstream_debug(struct seq_file *m,
>  			     const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
> index cfa4f5af49af..b27a0e2169c8 100644
> --- a/include/drm/drm_edid.h
> +++ b/include/drm/drm_edid.h
> @@ -517,4 +517,8 @@ void drm_edid_get_monitor_name(struct edid *edid, char
> *name,
>  struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
>  					   int hsize, int vsize, int fresh,
>  					   bool rb);
> +struct drm_display_mode *
> +drm_display_mode_from_cea_vic(struct drm_device *dev,
> +			      u8 video_code);
> +
>  #endif /* __DRM_EDID_H__ */
-- 
Cheers,
	Lyude Paul (she/her)
	Software Engineer at Red Hat

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  reply	other threads:[~2020-09-08 18:13 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-04 11:53 [Intel-gfx] [PATCH v2 00/18] drm/i915: Pimp DP DFP handling Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 01/18] drm/dp: Dump downstream facing port caps Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 02/18] drm/i915/lspcon: Do not send infoframes to non-HDMI sinks Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 03/18] drm/dp: Define protocol converter DPCD registers Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 04/18] drm/dp: Define more downstream facing port caps Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 05/18] drm/i915: Reworkd DFP max bpc handling Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 06/18] drm/dp: Add helpers to identify downstream facing port types Ville Syrjala
2020-09-08 17:30   ` Lyude Paul
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 07/18] drm/dp: Pimp drm_dp_downstream_max_bpc() Ville Syrjala
2020-09-08 17:32   ` Lyude Paul
2020-09-08 17:51   ` Lyude Paul
2020-09-10 14:46     ` Ville Syrjälä
2020-09-10 19:40       ` Lyude Paul
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 08/18] drm/dp: Redo drm_dp_downstream_max_clock() as drm_dp_downstream_max_dotclock() Ville Syrjala
2020-09-08 17:56   ` Lyude Paul
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 09/18] drm/i915: Reworkd DP DFP clock handling Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Ville Syrjala
2020-09-08 18:04   ` Lyude Paul
2020-09-17 12:46     ` Ville Syrjälä
2020-09-08 18:08   ` Lyude Paul
2020-09-10 13:55     ` Ville Syrjälä
2020-09-10 19:40       ` Lyude Paul
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 11/18] drm/i915: Deal with TMDS DFP clock limits Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 12/18] drm/i915: Configure DP 1.3+ protocol converted HDMI mode Ville Syrjala
2020-09-08 18:11   ` Lyude Paul
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 13/18] drm/dp: Add drm_dp_downstream_mode() Ville Syrjala
2020-09-08 18:13   ` Lyude Paul [this message]
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 14/18] drm/i915: Handle downstream facing ports w/o EDID Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 15/18] drm/i915: Extract intel_hdmi_has_audio() Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 16/18] drm/i915: DP->HDMI TMDS clock limits vs. deep color Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 17/18] drm/dp: Add helpers for DFP YCbCr 4:2:0 handling Ville Syrjala
2020-09-08 18:15   ` Lyude Paul
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 18/18] drm/i915: Do YCbCr 444->420 conversion via DP protocol converters Ville Syrjala
2020-09-04 13:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Pimp DP DFP handling (rev2) Patchwork
2020-09-04 13:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-09-04 20:09 ` [Intel-gfx] [PATCH v2 00/18] drm/i915: Pimp DP DFP handling Lyude Paul
2020-09-04 21:32 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Pimp DP DFP handling (rev2) Patchwork
2020-09-08 18:34 ` [Intel-gfx] [PATCH v2 00/18] drm/i915: Pimp DP DFP handling Lyude Paul
2020-09-17 16:11   ` Ville Syrjälä

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