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From: Lyude Paul <lyude@redhat.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	 dri-devel@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 06/18] drm/dp: Add helpers to identify downstream facing port types
Date: Tue, 08 Sep 2020 13:30:15 -0400	[thread overview]
Message-ID: <badcf7f2b6dbfff6638db3d140f8ffc764249576.camel@redhat.com> (raw)
In-Reply-To: <20200904115354.25336-7-ville.syrjala@linux.intel.com>

On Fri, 2020-09-04 at 14:53 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add a few helpers to let us better identify which kind of DFP
> we're dealing with.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/drm_dp_helper.c | 60 +++++++++++++++++++++++++++++++++
>  include/drm/drm_dp_helper.h     |  5 +++
>  2 files changed, 65 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c
> b/drivers/gpu/drm/drm_dp_helper.c
> index c21bbfc3d714..0fcb94f7dbe5 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -363,6 +363,66 @@ int drm_dp_dpcd_read_link_status(struct drm_dp_aux
> *aux,
>  }
>  EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
>  
> +static bool is_edid_digital_input_dp(const struct edid *edid)
> +{
> +	return edid && edid->revision >= 4 &&
> +		edid->input & DRM_EDID_INPUT_DIGITAL &&
> +		(edid->input & DRM_EDID_DIGITAL_TYPE_MASK) ==
> DRM_EDID_DIGITAL_TYPE_DP;
> +}
> +
> +/**
> + * drm_dp_downstream_is_type() - is the downstream facing port of certain
> type?
> + * @dpcd: DisplayPort configuration data
> + * @port_cap: port capabilities
> + *
> + * Caveat: Only works with DPCD 1.1+ port caps.
> + *
> + * Returns whether the downstream facing port matches the type.

Nitpick: s/Returns/Returns:/ for kdoc purposes

> + */
> +bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> +			       const u8 port_cap[4], u8 type)
> +{
> +	return drm_dp_is_branch(dpcd) &&
> +		dpcd[DP_DPCD_REV] >= 0x11 &&
> +		(port_cap[0] & DP_DS_PORT_TYPE_MASK) == type;
> +}
> +EXPORT_SYMBOL(drm_dp_downstream_is_type);
> +
> +/**
> + * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS?
> + * @dpcd: DisplayPort configuration data
> + * @port_cap: port capabilities
> + * @edid: EDID
> + *
> + * Returns whether the downstream facing port is TMDS (HDMI/DVI).

Same nitpick here

> + */
> +bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> +			       const u8 port_cap[4],
> +			       const struct edid *edid)
> +{
> +	if (dpcd[DP_DPCD_REV] < 0x11) {
> +		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] &
> DP_DWN_STRM_PORT_TYPE_MASK) {
> +		case DP_DWN_STRM_PORT_TYPE_TMDS:
> +			return true;
> +		default:
> +			return false;
> +		}
> +	}
> +
> +	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
> +	case DP_DS_PORT_TYPE_DP_DUALMODE:
> +		if (is_edid_digital_input_dp(edid))
> +			return false;
> +		fallthrough;
> +	case DP_DS_PORT_TYPE_DVI:
> +	case DP_DS_PORT_TYPE_HDMI:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +EXPORT_SYMBOL(drm_dp_downstream_is_tmds);
> +
>  /**
>   * drm_dp_send_real_edid_checksum() - send back real edid checksum value
>   * @aux: DisplayPort AUX channel
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 86461a40066b..4f946826dfce 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1638,6 +1638,11 @@ bool drm_dp_send_real_edid_checksum(struct drm_dp_aux
> *aux,
>  int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
>  				const u8 dpcd[DP_RECEIVER_CAP_SIZE],
>  				u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]);
> +bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> +			       const u8 port_cap[4], u8 type);
> +bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> +			       const u8 port_cap[4],
> +			       const struct edid *edid);
>  int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
>  				const u8 port_cap[4]);
>  int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
-- 
Cheers,
	Lyude Paul (she/her)
	Software Engineer at Red Hat

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  reply	other threads:[~2020-09-08 17:30 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-04 11:53 [Intel-gfx] [PATCH v2 00/18] drm/i915: Pimp DP DFP handling Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 01/18] drm/dp: Dump downstream facing port caps Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 02/18] drm/i915/lspcon: Do not send infoframes to non-HDMI sinks Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 03/18] drm/dp: Define protocol converter DPCD registers Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 04/18] drm/dp: Define more downstream facing port caps Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 05/18] drm/i915: Reworkd DFP max bpc handling Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 06/18] drm/dp: Add helpers to identify downstream facing port types Ville Syrjala
2020-09-08 17:30   ` Lyude Paul [this message]
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 07/18] drm/dp: Pimp drm_dp_downstream_max_bpc() Ville Syrjala
2020-09-08 17:32   ` Lyude Paul
2020-09-08 17:51   ` Lyude Paul
2020-09-10 14:46     ` Ville Syrjälä
2020-09-10 19:40       ` Lyude Paul
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 08/18] drm/dp: Redo drm_dp_downstream_max_clock() as drm_dp_downstream_max_dotclock() Ville Syrjala
2020-09-08 17:56   ` Lyude Paul
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 09/18] drm/i915: Reworkd DP DFP clock handling Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 10/18] drm/dp: Add drm_dp_downstream_{min, max}_tmds_clock() Ville Syrjala
2020-09-08 18:04   ` Lyude Paul
2020-09-17 12:46     ` Ville Syrjälä
2020-09-08 18:08   ` Lyude Paul
2020-09-10 13:55     ` Ville Syrjälä
2020-09-10 19:40       ` Lyude Paul
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 11/18] drm/i915: Deal with TMDS DFP clock limits Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 12/18] drm/i915: Configure DP 1.3+ protocol converted HDMI mode Ville Syrjala
2020-09-08 18:11   ` Lyude Paul
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 13/18] drm/dp: Add drm_dp_downstream_mode() Ville Syrjala
2020-09-08 18:13   ` Lyude Paul
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 14/18] drm/i915: Handle downstream facing ports w/o EDID Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 15/18] drm/i915: Extract intel_hdmi_has_audio() Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 16/18] drm/i915: DP->HDMI TMDS clock limits vs. deep color Ville Syrjala
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 17/18] drm/dp: Add helpers for DFP YCbCr 4:2:0 handling Ville Syrjala
2020-09-08 18:15   ` Lyude Paul
2020-09-04 11:53 ` [Intel-gfx] [PATCH v2 18/18] drm/i915: Do YCbCr 444->420 conversion via DP protocol converters Ville Syrjala
2020-09-04 13:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Pimp DP DFP handling (rev2) Patchwork
2020-09-04 13:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-09-04 20:09 ` [Intel-gfx] [PATCH v2 00/18] drm/i915: Pimp DP DFP handling Lyude Paul
2020-09-04 21:32 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Pimp DP DFP handling (rev2) Patchwork
2020-09-08 18:34 ` [Intel-gfx] [PATCH v2 00/18] drm/i915: Pimp DP DFP handling Lyude Paul
2020-09-17 16:11   ` Ville Syrjälä

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