[PATCH 1/6] drm/i915/gen9: Add WaDisableSamplerPowerBypassForSOPingPong

[PATCH 1/6] drm/i915/gen9: Add WaDisableSamplerPowerBypassForSOPingPong

[Arun Siluvery]

Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d2e0b3b..0e1ed0b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -983,6 +983,13 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 		tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
 	WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 
+	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
+	if (IS_SKYLAKE(dev) ||
+	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
+		WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
+				  GEN8_SAMPLER_POWER_BYPASS_DIS);
+	}
+
 	return 0;
 }
 
-- 
1.9.1

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[PATCH 2/6] drm/i915/bxt: Add WaSetClckGatingDisableMedia

[Arun Siluvery]

Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 +
 drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 84ed9ab..2c719b0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6894,6 +6894,7 @@ enum skl_disp_power_wells {
 #define   GEN7_DOP_CLOCK_GATE_ENABLE		(1<<0)
 #define   GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE	(1<<2)
 #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE	(1<<4)
+#define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE     (1<<6)
 
 #define GEN8_GARBCNTL                   0xB004
 #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 64bc77e..920872a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -134,6 +134,12 @@ static void bxt_init_clock_gating(struct drm_device *dev)
 		 */
 		I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
 	}
+
+	/* WaSetClckGatingDisableMedia:bxt */
+	if (INTEL_REVID(dev) == BXT_REVID_A0) {
+		I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
+					    ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
+	}
 }
 
 static void i915_pineview_get_mem_freq(struct drm_device *dev)
-- 
1.9.1

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[PATCH 3/6] drm/i915/gen9: Update WaDisableSDEUnitClockGating

[Arun Siluvery]

Apply in common gen9_init_clock_gating() fn and add revid check for bxt.

Cc: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 920872a..0f6588c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -63,6 +63,13 @@ static void gen9_init_clock_gating(struct drm_device *dev)
 	/* WaDisableKillLogic:bxt,skl */
 	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 		   ECOCHK_DIS_TLB);
+
+	 /* WaDisableSDEUnitClockGating:skl,bxt */
+	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
+	    (IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) {
+		I915_WRITE(GEN8_UCGCTL6, (I915_READ(GEN8_UCGCTL6) |
+					  GEN8_SDEUNIT_CLOCK_GATE_DISABLE));
+	}
 }
 
 static void skl_init_clock_gating(struct drm_device *dev)
@@ -72,13 +79,9 @@ static void skl_init_clock_gating(struct drm_device *dev)
 	gen9_init_clock_gating(dev);
 
 	if (INTEL_REVID(dev) <= SKL_REVID_B0) {
-		/*
-		 * WaDisableSDEUnitClockGating:skl
-		 * WaSetGAPSunitClckGateDisable:skl
-		 */
-		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
-			   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
-			   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+		/* WaSetGAPSunitClckGateDisable:skl */
+		I915_WRITE(GEN8_UCGCTL6, (I915_READ(GEN8_UCGCTL6) |
+					  GEN8_GAPSUNIT_CLOCK_GATE_DISABLE));
 
 		/* WaDisableVFUnitClockGating:skl */
 		I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
@@ -116,10 +119,6 @@ static void bxt_init_clock_gating(struct drm_device *dev)
 
 	gen9_init_clock_gating(dev);
 
-	/* WaDisableSDEUnitClockGating:bxt */
-	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
-		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
-
 	/*
 	 * FIXME:
 	 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
-- 
1.9.1

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[PATCH 4/6] drm/i915/bxt: Update WaSetHDCunitClckGatingDisable

[Arun Siluvery]

As per spec this is applicable to 3x6 SKUs only, add condition to
check the same.

Cc: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0f6588c..bfce904 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -119,12 +119,12 @@ static void bxt_init_clock_gating(struct drm_device *dev)
 
 	gen9_init_clock_gating(dev);
 
-	/*
-	 * FIXME:
-	 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
-	 */
-	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
-		   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
+	/* WaSetHDCunitClckGatingDisable:bxt */
+	/* as per spec this is applicable to 3x6 GT SKUs only */
+	if (INTEL_INFO(dev)->subslice_total == 3) {
+		I915_WRITE(GEN8_UCGCTL6, (I915_READ(GEN8_UCGCTL6) |
+					  GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ));
+	}
 
 	if (INTEL_REVID(dev) == BXT_REVID_A0) {
 		/*
-- 
1.9.1

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[PATCH 5/6] drm/i915/gen9: WA ST Unit Power Optimization Disable

[Arun Siluvery]

From: Robert Beckett <robert.beckett@intel.com>

WaDisableSTUnitPowerOptimization:skl,bxt

Signed-off-by: Robert Beckett <robert.beckett@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 3 +++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2c719b0..9b47dd4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6940,6 +6940,9 @@ enum skl_disp_power_wells {
 #define HSW_ROW_CHICKEN3		0xe49c
 #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
 
+#define HALF_SLICE_CHICKEN2		0xe180
+#define   GEN8_ST_PO_DISABLE		(1<<13)
+
 #define HALF_SLICE_CHICKEN3		0xe184
 #define   HSW_SAMPLE_C_PERFORMANCE	(1<<9)
 #define   GEN8_CENTROID_PIXEL_OPT_DIS	(1<<8)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 0e1ed0b..028c099 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -990,6 +990,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 				  GEN8_SAMPLER_POWER_BYPASS_DIS);
 	}
 
+	/* WaDisableSTUnitPowerOptimization:skl,bxt */
+	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
+
 	return 0;
 }
 
-- 
1.9.1

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[PATCH 6/6] drm/i915/gen9: Add WaDisableMinuteIaClockGating

[Arun Siluvery]

From: Nick Hoath <nicholas.hoath@intel.com>

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 5eafd31..e0601cc 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -330,6 +330,13 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 	/* Enable MIA caching. GuC clock gating is disabled. */
 	I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
 
+	/* WaDisableMinuteIaClockGating:skl,bxt */
+	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
+	    (IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) {
+		I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
+					      ~GUC_ENABLE_MIA_CLOCK_GATING));
+	}
+
 	/* WaC6DisallowByGfxPause*/
 	I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
 
-- 
1.9.1

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Re: [PATCH 6/6] drm/i915/gen9: Add WaDisableMinuteIaClockGating

[Kamble, Sagar A]

This is applicable to SKL GT3 and GT4.
Can you add that check as well?

-----Original Message-----
From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Arun Siluvery
Sent: Tuesday, September 8, 2015 3:02 PM
To: intel-gfx@lists.freedesktop.org
Cc: Kuoppala, Mika <mika.kuoppala@intel.com>
Subject: [Intel-gfx] [PATCH 6/6] drm/i915/gen9: Add WaDisableMinuteIaClockGating

From: Nick Hoath <nicholas.hoath@intel.com>

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 5eafd31..e0601cc 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -330,6 +330,13 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 	/* Enable MIA caching. GuC clock gating is disabled. */
 	I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
 
+	/* WaDisableMinuteIaClockGating:skl,bxt */
+	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
+	    (IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) {
+		I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
+					      ~GUC_ENABLE_MIA_CLOCK_GATING));
+	}
+
 	/* WaC6DisallowByGfxPause*/
 	I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
 
-- 
1.9.1

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Re: [PATCH 6/6] drm/i915/gen9: Add WaDisableMinuteIaClockGating

[Kamble, Sagar A]

Ignore the comment. I thought about CPG.
Sorry.

-----Original Message-----
From: Kamble, Sagar A 
Sent: Tuesday, September 8, 2015 3:44 PM
To: 'Arun Siluvery' <arun.siluvery@linux.intel.com>; intel-gfx@lists.freedesktop.org
Cc: Kuoppala, Mika <mika.kuoppala@intel.com>
Subject: RE: [Intel-gfx] [PATCH 6/6] drm/i915/gen9: Add WaDisableMinuteIaClockGating

This is applicable to SKL GT3 and GT4.
Can you add that check as well?

-----Original Message-----
From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Arun Siluvery
Sent: Tuesday, September 8, 2015 3:02 PM
To: intel-gfx@lists.freedesktop.org
Cc: Kuoppala, Mika <mika.kuoppala@intel.com>
Subject: [Intel-gfx] [PATCH 6/6] drm/i915/gen9: Add WaDisableMinuteIaClockGating

From: Nick Hoath <nicholas.hoath@intel.com>

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 5eafd31..e0601cc 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -330,6 +330,13 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 	/* Enable MIA caching. GuC clock gating is disabled. */
 	I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
 
+	/* WaDisableMinuteIaClockGating:skl,bxt */
+	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
+	    (IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) {
+		I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
+					      ~GUC_ENABLE_MIA_CLOCK_GATING));
+	}
+
 	/* WaC6DisallowByGfxPause*/
 	I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
 
-- 
1.9.1

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Re: [PATCH 1/6] drm/i915/gen9: Add WaDisableSamplerPowerBypassForSOPingPong

[Kamble, Sagar A]

Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>

On 9/8/2015 3:01 PM, Arun Siluvery wrote:
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++++
>   1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index d2e0b3b..0e1ed0b 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -983,6 +983,13 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
>   		tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
>   	WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
>   
> +	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
> +	if (IS_SKYLAKE(dev) ||
> +	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
> +		WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> +				  GEN8_SAMPLER_POWER_BYPASS_DIS);
> +	}
> +
>   	return 0;
>   }
>   

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Re: [PATCH 2/6] drm/i915/bxt: Add WaSetClckGatingDisableMedia

[Kamble, Sagar A]

Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>

On 9/8/2015 3:01 PM, Arun Siluvery wrote:
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h | 1 +
>   drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
>   2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 84ed9ab..2c719b0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6894,6 +6894,7 @@ enum skl_disp_power_wells {
>   #define   GEN7_DOP_CLOCK_GATE_ENABLE		(1<<0)
>   #define   GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE	(1<<2)
>   #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE	(1<<4)
> +#define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE     (1<<6)
>   
>   #define GEN8_GARBCNTL                   0xB004
>   #define   GEN9_GAPS_TSV_CREDIT_DISABLE  (1<<7)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 64bc77e..920872a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -134,6 +134,12 @@ static void bxt_init_clock_gating(struct drm_device *dev)
>   		 */
>   		I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
>   	}
> +
> +	/* WaSetClckGatingDisableMedia:bxt */
> +	if (INTEL_REVID(dev) == BXT_REVID_A0) {
> +		I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
> +					    ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
> +	}
>   }
>   
>   static void i915_pineview_get_mem_freq(struct drm_device *dev)

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Re: [PATCH 5/6] drm/i915/gen9: WA ST Unit Power Optimization Disable

[Kamble, Sagar A]

On 9/8/2015 3:01 PM, Arun Siluvery wrote:
> From: Robert Beckett <robert.beckett@intel.com>
>
> WaDisableSTUnitPowerOptimization:skl,bxt
>
> Signed-off-by: Robert Beckett <robert.beckett@intel.com>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h         | 3 +++
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
>   2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2c719b0..9b47dd4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6940,6 +6940,9 @@ enum skl_disp_power_wells {
>   #define HSW_ROW_CHICKEN3		0xe49c
>   #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
>   
> +#define HALF_SLICE_CHICKEN2		0xe180
> +#define   GEN8_ST_PO_DISABLE		(1<<13)
Can we name this as GEN9_STUNIT_PO_DISABLE, since this does not apply on 
GEN8?
With that: Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> +
>   #define HALF_SLICE_CHICKEN3		0xe184
>   #define   HSW_SAMPLE_C_PERFORMANCE	(1<<9)
>   #define   GEN8_CENTROID_PIXEL_OPT_DIS	(1<<8)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 0e1ed0b..028c099 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -990,6 +990,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
>   				  GEN8_SAMPLER_POWER_BYPASS_DIS);
>   	}
>   
> +	/* WaDisableSTUnitPowerOptimization:skl,bxt */
> +	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
> +
>   	return 0;
>   }
>   

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Re: [PATCH 6/6] drm/i915/gen9: Add WaDisableMinuteIaClockGating

[Kamble, Sagar A]

Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>

On 9/8/2015 3:01 PM, Arun Siluvery wrote:
> From: Nick Hoath <nicholas.hoath@intel.com>
>
> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++++++
>   1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 5eafd31..e0601cc 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -330,6 +330,13 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
>   	/* Enable MIA caching. GuC clock gating is disabled. */
>   	I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
>   
> +	/* WaDisableMinuteIaClockGating:skl,bxt */
> +	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
> +	    (IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) {
> +		I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
> +					      ~GUC_ENABLE_MIA_CLOCK_GATING));
> +	}
> +
>   	/* WaC6DisallowByGfxPause*/
>   	I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
>   

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Re: [PATCH 6/6] drm/i915/gen9: Add WaDisableMinuteIaClockGating

[Daniel Vetter]

On Sat, Sep 12, 2015 at 11:26:38PM +0530, Kamble, Sagar A wrote:
> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> 
> On 9/8/2015 3:01 PM, Arun Siluvery wrote:
> >From: Nick Hoath <nicholas.hoath@intel.com>
> >
> >Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
> >Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>

Applied 3 patches from this series with Sagar's review-by.

Thanks, Daniel

> >---
> >  drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++++++
> >  1 file changed, 7 insertions(+)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> >index 5eafd31..e0601cc 100644
> >--- a/drivers/gpu/drm/i915/intel_guc_loader.c
> >+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> >@@ -330,6 +330,13 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
> >  	/* Enable MIA caching. GuC clock gating is disabled. */
> >  	I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
> >+	/* WaDisableMinuteIaClockGating:skl,bxt */
> >+	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
> >+	    (IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) {
> >+		I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
> >+					      ~GUC_ENABLE_MIA_CLOCK_GATING));
> >+	}
> >+
> >  	/* WaC6DisallowByGfxPause*/
> >  	I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
> 
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 5/6] drm/i915/gen9: WA ST Unit Power Optimization Disable

[Arun Siluvery]

On 12/09/2015 17:52, Kamble, Sagar A wrote:
>
>
> On 9/8/2015 3:01 PM, Arun Siluvery wrote:
>> From: Robert Beckett <robert.beckett@intel.com>
>>
>> WaDisableSTUnitPowerOptimization:skl,bxt
>>
>> Signed-off-by: Robert Beckett <robert.beckett@intel.com>
>> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_reg.h         | 3 +++
>>   drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
>>   2 files changed, 6 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 2c719b0..9b47dd4 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6940,6 +6940,9 @@ enum skl_disp_power_wells {
>>   #define HSW_ROW_CHICKEN3        0xe49c
>>   #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
>> +#define HALF_SLICE_CHICKEN2        0xe180
>> +#define   GEN8_ST_PO_DISABLE        (1<<13)
> Can we name this as GEN9_STUNIT_PO_DISABLE, since this does not apply on
> GEN8?

According to the spec this bit is applicable for BDW also so Gen8 should 
be ok.

regards
Arun

> With that: Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> +
>>   #define HALF_SLICE_CHICKEN3        0xe184
>>   #define   HSW_SAMPLE_C_PERFORMANCE    (1<<9)
>>   #define   GEN8_CENTROID_PIXEL_OPT_DIS    (1<<8)
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index 0e1ed0b..028c099 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -990,6 +990,9 @@ static int gen9_init_workarounds(struct
>> intel_engine_cs *ring)
>>                     GEN8_SAMPLER_POWER_BYPASS_DIS);
>>       }
>> +    /* WaDisableSTUnitPowerOptimization:skl,bxt */
>> +    WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
>> +
>>       return 0;
>>   }
>
>

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Re: [PATCH 5/6] drm/i915/gen9: WA ST Unit Power Optimization Disable

[Kamble, Sagar A]

Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>

On 9/14/2015 2:55 PM, Arun Siluvery wrote:
> On 12/09/2015 17:52, Kamble, Sagar A wrote:
>>
>>
>> On 9/8/2015 3:01 PM, Arun Siluvery wrote:
>>> From: Robert Beckett <robert.beckett@intel.com>
>>>
>>> WaDisableSTUnitPowerOptimization:skl,bxt
>>>
>>> Signed-off-by: Robert Beckett <robert.beckett@intel.com>
>>> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/i915_reg.h         | 3 +++
>>>   drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
>>>   2 files changed, 6 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>>> b/drivers/gpu/drm/i915/i915_reg.h
>>> index 2c719b0..9b47dd4 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -6940,6 +6940,9 @@ enum skl_disp_power_wells {
>>>   #define HSW_ROW_CHICKEN3        0xe49c
>>>   #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
>>> +#define HALF_SLICE_CHICKEN2        0xe180
>>> +#define   GEN8_ST_PO_DISABLE        (1<<13)
>> Can we name this as GEN9_STUNIT_PO_DISABLE, since this does not apply on
>> GEN8?
>
> According to the spec this bit is applicable for BDW also so Gen8 
> should be ok.
>
> regards
> Arun
>
>> With that: Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>>> +
>>>   #define HALF_SLICE_CHICKEN3        0xe184
>>>   #define   HSW_SAMPLE_C_PERFORMANCE    (1<<9)
>>>   #define   GEN8_CENTROID_PIXEL_OPT_DIS    (1<<8)
>>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> b/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> index 0e1ed0b..028c099 100644
>>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> @@ -990,6 +990,9 @@ static int gen9_init_workarounds(struct
>>> intel_engine_cs *ring)
>>>                     GEN8_SAMPLER_POWER_BYPASS_DIS);
>>>       }
>>> +    /* WaDisableSTUnitPowerOptimization:skl,bxt */
>>> +    WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
>>> +
>>>       return 0;
>>>   }
>>
>>
>

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Re: [PATCH 5/6] drm/i915/gen9: WA ST Unit Power Optimization Disable

[Daniel Vetter]

On Mon, Sep 14, 2015 at 08:21:20PM +0530, Kamble, Sagar A wrote:
> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>

Queued for -next, thanks for the patch.
-Daniel

> 
> On 9/14/2015 2:55 PM, Arun Siluvery wrote:
> >On 12/09/2015 17:52, Kamble, Sagar A wrote:
> >>
> >>
> >>On 9/8/2015 3:01 PM, Arun Siluvery wrote:
> >>>From: Robert Beckett <robert.beckett@intel.com>
> >>>
> >>>WaDisableSTUnitPowerOptimization:skl,bxt
> >>>
> >>>Signed-off-by: Robert Beckett <robert.beckett@intel.com>
> >>>Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> >>>---
> >>>  drivers/gpu/drm/i915/i915_reg.h         | 3 +++
> >>>  drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
> >>>  2 files changed, 6 insertions(+)
> >>>
> >>>diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >>>b/drivers/gpu/drm/i915/i915_reg.h
> >>>index 2c719b0..9b47dd4 100644
> >>>--- a/drivers/gpu/drm/i915/i915_reg.h
> >>>+++ b/drivers/gpu/drm/i915/i915_reg.h
> >>>@@ -6940,6 +6940,9 @@ enum skl_disp_power_wells {
> >>>  #define HSW_ROW_CHICKEN3        0xe49c
> >>>  #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
> >>>+#define HALF_SLICE_CHICKEN2        0xe180
> >>>+#define   GEN8_ST_PO_DISABLE        (1<<13)
> >>Can we name this as GEN9_STUNIT_PO_DISABLE, since this does not apply on
> >>GEN8?
> >
> >According to the spec this bit is applicable for BDW also so Gen8 should
> >be ok.
> >
> >regards
> >Arun
> >
> >>With that: Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> >>>+
> >>>  #define HALF_SLICE_CHICKEN3        0xe184
> >>>  #define   HSW_SAMPLE_C_PERFORMANCE    (1<<9)
> >>>  #define   GEN8_CENTROID_PIXEL_OPT_DIS    (1<<8)
> >>>diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> >>>b/drivers/gpu/drm/i915/intel_ringbuffer.c
> >>>index 0e1ed0b..028c099 100644
> >>>--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> >>>+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> >>>@@ -990,6 +990,9 @@ static int gen9_init_workarounds(struct
> >>>intel_engine_cs *ring)
> >>>                    GEN8_SAMPLER_POWER_BYPASS_DIS);
> >>>      }
> >>>+    /* WaDisableSTUnitPowerOptimization:skl,bxt */
> >>>+    WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
> >>>+
> >>>      return 0;
> >>>  }
> >>
> >>
> >
> 
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-- 
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