* [PATCH 0/2] BXT Pooled EU kernel support @ 2016-05-12 9:37 Arun Siluvery 2016-05-12 9:37 ` [PATCH 1/2] drm/i915:bxt: Enable Pooled EU support Arun Siluvery 2016-05-12 9:37 ` [PATCH 2/2] drm/i915/bxt: Add WaEnablePooledEuFor2x6 Arun Siluvery 0 siblings, 2 replies; 8+ messages in thread From: Arun Siluvery @ 2016-05-12 9:37 UTC (permalink / raw) To: intel-gfx Pooled EU is a BXT only feature, prep patches are merged a while ago. Patch that enables the feature is also reviewed but not merged because of lack of opensource user. https://lists.freedesktop.org/archives/intel-gfx/2015-July/072051.html Kernel simply enables the support, userspace enquires certain parameters from kernel and dispatches threads to use this feature. One of the patch is a WA related to this feature, this only affects 2x6 devices, please check the patch for more details. Beignet recently expressed interest in using feature and asked to complete kernel support, they are currently adding userspace and libdrm support, meanwhile we can get some testing done on these patches. Arun Siluvery (2): drm/i915:bxt: Enable Pooled EU support drm/i915/bxt: Add WaEnablePooledEuFor2x6 drivers/gpu/drm/i915/i915_debugfs.c | 5 ++++ drivers/gpu/drm/i915/i915_dma.c | 36 ++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 6 ++++- drivers/gpu/drm/i915/i915_gem_render_state.c | 24 +++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 2 ++ include/uapi/drm/i915_drm.h | 2 ++ 7 files changed, 75 insertions(+), 1 deletion(-) -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] drm/i915:bxt: Enable Pooled EU support 2016-05-12 9:37 [PATCH 0/2] BXT Pooled EU kernel support Arun Siluvery @ 2016-05-12 9:37 ` Arun Siluvery 2016-05-17 10:04 ` Daniel Vetter 2016-05-12 9:37 ` [PATCH 2/2] drm/i915/bxt: Add WaEnablePooledEuFor2x6 Arun Siluvery 1 sibling, 1 reply; 8+ messages in thread From: Arun Siluvery @ 2016-05-12 9:37 UTC (permalink / raw) To: intel-gfx; +Cc: Armin Reese, Mika Kuoppala This mode allows to assign EUs to pools which can process work collectively. The command to enable this mode should be issued as part of context initialization. The pooled mode is global, once enabled it has to stay the same across all contexts until HW reset hence this is sent in auxiliary golden context batch. Thanks to Mika for the preliminary review and comments. v2: explain why this is enabled in golden context, use feature flag while enabling the support (Chris) v3: Pooled EU support announced in userspace before enabling in kernel, to simplify include all changes in the same patch. User space clients need to know when the pooled EU feature is present and enabled on the hardware so that they can adapt work submissions. Create a new device info flag for this purpose, and create a new GETPARAM entry to allow user space to query its setting. Set has_pooled_eu to true in the Broxton static device info - Broxton supports the feature in hardware and the driver will enable it by default. Opensource users for this feature are mesa, libva and beignet. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Winiarski, Michal <michal.winiarski@intel.com> Cc: Zou, Nanhai <nanhai.zou@intel.com> Cc: Yang, Rong R <rong.r.yang@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Armin Reese <armin.c.reese@intel.com> Cc: Tim Gore <tim.gore@intel.com> Signed-off-by: Jeff McGee <jeff.mcgee@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> --- drivers/gpu/drm/i915/i915_dma.c | 3 +++ drivers/gpu/drm/i915/i915_drv.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 5 ++++- drivers/gpu/drm/i915/i915_gem_render_state.c | 13 +++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 2 ++ include/uapi/drm/i915_drm.h | 1 + 6 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 0eadeb6..5cd2ad4 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -222,6 +222,9 @@ static int i915_getparam(struct drm_device *dev, void *data, if (!value) return -ENODEV; break; + case I915_PARAM_HAS_POOLED_EU: + value = HAS_POOLED_EU(dev); + break; case I915_PARAM_HAS_GPU_RESET: value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv); break; diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 5ae7960..33e0fd0 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -357,6 +357,7 @@ static const struct intel_device_info intel_broxton_info = { .has_ddi = 1, .has_fpga_dbg = 1, .has_fbc = 1, + .has_pooled_eu = 1, GEN_DEFAULT_PIPEOFFSETS, IVB_CURSOR_OFFSETS, BDW_COLORS, diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7a0b513..5b2a7a3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -750,7 +750,8 @@ struct intel_csr { func(has_llc) sep \ func(has_snoop) sep \ func(has_ddi) sep \ - func(has_fpga_dbg) + func(has_fpga_dbg) sep \ + func(has_pooled_eu) #define DEFINE_FLAG(name) u8 name:1 #define SEP_SEMICOLON ; @@ -2736,6 +2737,8 @@ struct drm_i915_cmd_table { !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \ !IS_BROXTON(dev)) +#define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu) + #define INTEL_PCH_DEVICE_ID_MASK 0xff00 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c index 7c93327..1284f99 100644 --- a/drivers/gpu/drm/i915/i915_gem_render_state.c +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c @@ -94,6 +94,7 @@ free_gem: static int render_state_setup(struct render_state *so) { + struct drm_device *dev = so->obj->base.dev; const struct intel_renderstate_rodata *rodata = so->rodata; unsigned int i = 0, reloc_index = 0; struct page *page; @@ -135,6 +136,18 @@ static int render_state_setup(struct render_state *so) so->aux_batch_offset = i * sizeof(u32); + if (HAS_POOLED_EU(dev)) { + u32 pool_config = (INTEL_INFO(dev)->subslice_total == 3 ? + 0x00777000 : 0); + + OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE); + OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE); + OUT_BATCH(d, i, pool_config); + OUT_BATCH(d, i, 0); + OUT_BATCH(d, i, 0); + OUT_BATCH(d, i, 0); + } + OUT_BATCH(d, i, MI_BATCH_BUFFER_END); so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 54ce0b1..dc67e0e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -442,6 +442,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) */ #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) +#define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4) +#define GEN9_MEDIA_POOL_ENABLE (1 << 31) #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) #define SC_UPDATE_SCISSOR (0x1<<1) diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index a5524cc..0b0acad 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -357,6 +357,7 @@ typedef struct drm_i915_irq_wait { #define I915_PARAM_HAS_GPU_RESET 35 #define I915_PARAM_HAS_RESOURCE_STREAMER 36 #define I915_PARAM_HAS_EXEC_SOFTPIN 37 +#define I915_PARAM_HAS_POOLED_EU 38 typedef struct drm_i915_getparam { __s32 param; -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] drm/i915:bxt: Enable Pooled EU support 2016-05-12 9:37 ` [PATCH 1/2] drm/i915:bxt: Enable Pooled EU support Arun Siluvery @ 2016-05-17 10:04 ` Daniel Vetter 2016-05-17 11:02 ` Arun Siluvery 0 siblings, 1 reply; 8+ messages in thread From: Daniel Vetter @ 2016-05-17 10:04 UTC (permalink / raw) To: Arun Siluvery; +Cc: intel-gfx, Armin Reese, Mika Kuoppala On Thu, May 12, 2016 at 10:37:14AM +0100, Arun Siluvery wrote: > This mode allows to assign EUs to pools which can process work collectively. > The command to enable this mode should be issued as part of context initialization. > > The pooled mode is global, once enabled it has to stay the same across all > contexts until HW reset hence this is sent in auxiliary golden context batch. > Thanks to Mika for the preliminary review and comments. > > v2: explain why this is enabled in golden context, use feature flag while > enabling the support (Chris) > > v3: Pooled EU support announced in userspace before enabling in kernel, > to simplify include all changes in the same patch. > > User space clients need to know when the pooled EU feature is present > and enabled on the hardware so that they can adapt work submissions. > Create a new device info flag for this purpose, and create a new GETPARAM > entry to allow user space to query its setting. > > Set has_pooled_eu to true in the Broxton static device info - Broxton > supports the feature in hardware and the driver will enable it by > default. > > Opensource users for this feature are mesa, libva and beignet. Link to those patches would be great. At least I haven't seen anything fly by for mesa or libva, might have missed it though. Note that the patches must be fully reviewed an ready for merging by respective userspace upstream, before we can land the kernel side. -Daniel > > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Winiarski, Michal <michal.winiarski@intel.com> > Cc: Zou, Nanhai <nanhai.zou@intel.com> > Cc: Yang, Rong R <rong.r.yang@intel.com> > Cc: Mika Kuoppala <mika.kuoppala@intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Armin Reese <armin.c.reese@intel.com> > Cc: Tim Gore <tim.gore@intel.com> > Signed-off-by: Jeff McGee <jeff.mcgee@intel.com> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_dma.c | 3 +++ > drivers/gpu/drm/i915/i915_drv.c | 1 + > drivers/gpu/drm/i915/i915_drv.h | 5 ++++- > drivers/gpu/drm/i915/i915_gem_render_state.c | 13 +++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > include/uapi/drm/i915_drm.h | 1 + > 6 files changed, 24 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c > index 0eadeb6..5cd2ad4 100644 > --- a/drivers/gpu/drm/i915/i915_dma.c > +++ b/drivers/gpu/drm/i915/i915_dma.c > @@ -222,6 +222,9 @@ static int i915_getparam(struct drm_device *dev, void *data, > if (!value) > return -ENODEV; > break; > + case I915_PARAM_HAS_POOLED_EU: > + value = HAS_POOLED_EU(dev); > + break; > case I915_PARAM_HAS_GPU_RESET: > value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv); > break; > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 5ae7960..33e0fd0 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -357,6 +357,7 @@ static const struct intel_device_info intel_broxton_info = { > .has_ddi = 1, > .has_fpga_dbg = 1, > .has_fbc = 1, > + .has_pooled_eu = 1, > GEN_DEFAULT_PIPEOFFSETS, > IVB_CURSOR_OFFSETS, > BDW_COLORS, > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 7a0b513..5b2a7a3 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -750,7 +750,8 @@ struct intel_csr { > func(has_llc) sep \ > func(has_snoop) sep \ > func(has_ddi) sep \ > - func(has_fpga_dbg) > + func(has_fpga_dbg) sep \ > + func(has_pooled_eu) > > #define DEFINE_FLAG(name) u8 name:1 > #define SEP_SEMICOLON ; > @@ -2736,6 +2737,8 @@ struct drm_i915_cmd_table { > !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \ > !IS_BROXTON(dev)) > > +#define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu) > + > #define INTEL_PCH_DEVICE_ID_MASK 0xff00 > #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 > #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 > diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c > index 7c93327..1284f99 100644 > --- a/drivers/gpu/drm/i915/i915_gem_render_state.c > +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c > @@ -94,6 +94,7 @@ free_gem: > > static int render_state_setup(struct render_state *so) > { > + struct drm_device *dev = so->obj->base.dev; > const struct intel_renderstate_rodata *rodata = so->rodata; > unsigned int i = 0, reloc_index = 0; > struct page *page; > @@ -135,6 +136,18 @@ static int render_state_setup(struct render_state *so) > > so->aux_batch_offset = i * sizeof(u32); > > + if (HAS_POOLED_EU(dev)) { > + u32 pool_config = (INTEL_INFO(dev)->subslice_total == 3 ? > + 0x00777000 : 0); > + > + OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE); > + OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE); > + OUT_BATCH(d, i, pool_config); > + OUT_BATCH(d, i, 0); > + OUT_BATCH(d, i, 0); > + OUT_BATCH(d, i, 0); > + } > + > OUT_BATCH(d, i, MI_BATCH_BUFFER_END); > so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset; > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 54ce0b1..dc67e0e 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -442,6 +442,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > */ > #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) > > +#define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4) > +#define GEN9_MEDIA_POOL_ENABLE (1 << 31) > #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) > #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) > #define SC_UPDATE_SCISSOR (0x1<<1) > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > index a5524cc..0b0acad 100644 > --- a/include/uapi/drm/i915_drm.h > +++ b/include/uapi/drm/i915_drm.h > @@ -357,6 +357,7 @@ typedef struct drm_i915_irq_wait { > #define I915_PARAM_HAS_GPU_RESET 35 > #define I915_PARAM_HAS_RESOURCE_STREAMER 36 > #define I915_PARAM_HAS_EXEC_SOFTPIN 37 > +#define I915_PARAM_HAS_POOLED_EU 38 > > typedef struct drm_i915_getparam { > __s32 param; > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] drm/i915:bxt: Enable Pooled EU support 2016-05-17 10:04 ` Daniel Vetter @ 2016-05-17 11:02 ` Arun Siluvery 2016-05-17 11:13 ` Daniel Vetter 0 siblings, 1 reply; 8+ messages in thread From: Arun Siluvery @ 2016-05-17 11:02 UTC (permalink / raw) To: Daniel Vetter; +Cc: intel-gfx, Mika Kuoppala On 17/05/2016 15:34, Daniel Vetter wrote: > On Thu, May 12, 2016 at 10:37:14AM +0100, Arun Siluvery wrote: >> This mode allows to assign EUs to pools which can process work collectively. >> The command to enable this mode should be issued as part of context initialization. >> >> The pooled mode is global, once enabled it has to stay the same across all >> contexts until HW reset hence this is sent in auxiliary golden context batch. >> Thanks to Mika for the preliminary review and comments. >> >> v2: explain why this is enabled in golden context, use feature flag while >> enabling the support (Chris) >> >> v3: Pooled EU support announced in userspace before enabling in kernel, >> to simplify include all changes in the same patch. >> >> User space clients need to know when the pooled EU feature is present >> and enabled on the hardware so that they can adapt work submissions. >> Create a new device info flag for this purpose, and create a new GETPARAM >> entry to allow user space to query its setting. >> >> Set has_pooled_eu to true in the Broxton static device info - Broxton >> supports the feature in hardware and the driver will enable it by >> default. >> >> Opensource users for this feature are mesa, libva and beignet. > > Link to those patches would be great. At least I haven't seen anything fly > by for mesa or libva, might have missed it though. Note that the patches > must be fully reviewed an ready for merging by respective userspace > upstream, before we can land the kernel side. Initially beignet is trying to use it and they are adding support to it. I will share links once they send them to the list, reviewed and ready to be merged. regards Arun > -Daniel > >> >> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> >> Cc: Winiarski, Michal <michal.winiarski@intel.com> >> Cc: Zou, Nanhai <nanhai.zou@intel.com> >> Cc: Yang, Rong R <rong.r.yang@intel.com> >> Cc: Mika Kuoppala <mika.kuoppala@intel.com> >> Cc: Chris Wilson <chris@chris-wilson.co.uk> >> Cc: Armin Reese <armin.c.reese@intel.com> >> Cc: Tim Gore <tim.gore@intel.com> >> Signed-off-by: Jeff McGee <jeff.mcgee@intel.com> >> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> >> --- >> drivers/gpu/drm/i915/i915_dma.c | 3 +++ >> drivers/gpu/drm/i915/i915_drv.c | 1 + >> drivers/gpu/drm/i915/i915_drv.h | 5 ++++- >> drivers/gpu/drm/i915/i915_gem_render_state.c | 13 +++++++++++++ >> drivers/gpu/drm/i915/i915_reg.h | 2 ++ >> include/uapi/drm/i915_drm.h | 1 + >> 6 files changed, 24 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c >> index 0eadeb6..5cd2ad4 100644 >> --- a/drivers/gpu/drm/i915/i915_dma.c >> +++ b/drivers/gpu/drm/i915/i915_dma.c >> @@ -222,6 +222,9 @@ static int i915_getparam(struct drm_device *dev, void *data, >> if (!value) >> return -ENODEV; >> break; >> + case I915_PARAM_HAS_POOLED_EU: >> + value = HAS_POOLED_EU(dev); >> + break; >> case I915_PARAM_HAS_GPU_RESET: >> value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv); >> break; >> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c >> index 5ae7960..33e0fd0 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.c >> +++ b/drivers/gpu/drm/i915/i915_drv.c >> @@ -357,6 +357,7 @@ static const struct intel_device_info intel_broxton_info = { >> .has_ddi = 1, >> .has_fpga_dbg = 1, >> .has_fbc = 1, >> + .has_pooled_eu = 1, >> GEN_DEFAULT_PIPEOFFSETS, >> IVB_CURSOR_OFFSETS, >> BDW_COLORS, >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h >> index 7a0b513..5b2a7a3 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.h >> +++ b/drivers/gpu/drm/i915/i915_drv.h >> @@ -750,7 +750,8 @@ struct intel_csr { >> func(has_llc) sep \ >> func(has_snoop) sep \ >> func(has_ddi) sep \ >> - func(has_fpga_dbg) >> + func(has_fpga_dbg) sep \ >> + func(has_pooled_eu) >> >> #define DEFINE_FLAG(name) u8 name:1 >> #define SEP_SEMICOLON ; >> @@ -2736,6 +2737,8 @@ struct drm_i915_cmd_table { >> !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \ >> !IS_BROXTON(dev)) >> >> +#define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu) >> + >> #define INTEL_PCH_DEVICE_ID_MASK 0xff00 >> #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 >> #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 >> diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c >> index 7c93327..1284f99 100644 >> --- a/drivers/gpu/drm/i915/i915_gem_render_state.c >> +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c >> @@ -94,6 +94,7 @@ free_gem: >> >> static int render_state_setup(struct render_state *so) >> { >> + struct drm_device *dev = so->obj->base.dev; >> const struct intel_renderstate_rodata *rodata = so->rodata; >> unsigned int i = 0, reloc_index = 0; >> struct page *page; >> @@ -135,6 +136,18 @@ static int render_state_setup(struct render_state *so) >> >> so->aux_batch_offset = i * sizeof(u32); >> >> + if (HAS_POOLED_EU(dev)) { >> + u32 pool_config = (INTEL_INFO(dev)->subslice_total == 3 ? >> + 0x00777000 : 0); >> + >> + OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE); >> + OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE); >> + OUT_BATCH(d, i, pool_config); >> + OUT_BATCH(d, i, 0); >> + OUT_BATCH(d, i, 0); >> + OUT_BATCH(d, i, 0); >> + } >> + >> OUT_BATCH(d, i, MI_BATCH_BUFFER_END); >> so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset; >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> index 54ce0b1..dc67e0e 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -442,6 +442,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) >> */ >> #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) >> >> +#define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4) >> +#define GEN9_MEDIA_POOL_ENABLE (1 << 31) >> #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) >> #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) >> #define SC_UPDATE_SCISSOR (0x1<<1) >> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h >> index a5524cc..0b0acad 100644 >> --- a/include/uapi/drm/i915_drm.h >> +++ b/include/uapi/drm/i915_drm.h >> @@ -357,6 +357,7 @@ typedef struct drm_i915_irq_wait { >> #define I915_PARAM_HAS_GPU_RESET 35 >> #define I915_PARAM_HAS_RESOURCE_STREAMER 36 >> #define I915_PARAM_HAS_EXEC_SOFTPIN 37 >> +#define I915_PARAM_HAS_POOLED_EU 38 >> >> typedef struct drm_i915_getparam { >> __s32 param; >> -- >> 1.9.1 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] drm/i915:bxt: Enable Pooled EU support 2016-05-17 11:02 ` Arun Siluvery @ 2016-05-17 11:13 ` Daniel Vetter 2016-05-17 11:31 ` Arun Siluvery 0 siblings, 1 reply; 8+ messages in thread From: Daniel Vetter @ 2016-05-17 11:13 UTC (permalink / raw) To: Arun Siluvery; +Cc: intel-gfx, Mika Kuoppala On Tue, May 17, 2016 at 04:32:49PM +0530, Arun Siluvery wrote: > On 17/05/2016 15:34, Daniel Vetter wrote: > >On Thu, May 12, 2016 at 10:37:14AM +0100, Arun Siluvery wrote: > >>This mode allows to assign EUs to pools which can process work collectively. > >>The command to enable this mode should be issued as part of context initialization. > >> > >>The pooled mode is global, once enabled it has to stay the same across all > >>contexts until HW reset hence this is sent in auxiliary golden context batch. > >>Thanks to Mika for the preliminary review and comments. > >> > >>v2: explain why this is enabled in golden context, use feature flag while > >>enabling the support (Chris) > >> > >>v3: Pooled EU support announced in userspace before enabling in kernel, > >>to simplify include all changes in the same patch. > >> > >>User space clients need to know when the pooled EU feature is present > >>and enabled on the hardware so that they can adapt work submissions. > >>Create a new device info flag for this purpose, and create a new GETPARAM > >>entry to allow user space to query its setting. > >> > >>Set has_pooled_eu to true in the Broxton static device info - Broxton > >>supports the feature in hardware and the driver will enable it by > >>default. > >> > >>Opensource users for this feature are mesa, libva and beignet. > > > >Link to those patches would be great. At least I haven't seen anything fly > >by for mesa or libva, might have missed it though. Note that the patches > >must be fully reviewed an ready for merging by respective userspace > >upstream, before we can land the kernel side. > > Initially beignet is trying to use it and they are adding support to it. I > will share links once they send them to the list, reviewed and ready to be > merged. Then please don't say you have the userspace when it doesn't exist yet. The other question: Will existing userspace fall over if we enable this in the kernel, or is it purely opt-in? Would be good to clarify in the commit message. -Daniel > > regards > Arun > > >-Daniel > > > >> > >>Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> > >>Cc: Winiarski, Michal <michal.winiarski@intel.com> > >>Cc: Zou, Nanhai <nanhai.zou@intel.com> > >>Cc: Yang, Rong R <rong.r.yang@intel.com> > >>Cc: Mika Kuoppala <mika.kuoppala@intel.com> > >>Cc: Chris Wilson <chris@chris-wilson.co.uk> > >>Cc: Armin Reese <armin.c.reese@intel.com> > >>Cc: Tim Gore <tim.gore@intel.com> > >>Signed-off-by: Jeff McGee <jeff.mcgee@intel.com> > >>Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> > >>--- > >> drivers/gpu/drm/i915/i915_dma.c | 3 +++ > >> drivers/gpu/drm/i915/i915_drv.c | 1 + > >> drivers/gpu/drm/i915/i915_drv.h | 5 ++++- > >> drivers/gpu/drm/i915/i915_gem_render_state.c | 13 +++++++++++++ > >> drivers/gpu/drm/i915/i915_reg.h | 2 ++ > >> include/uapi/drm/i915_drm.h | 1 + > >> 6 files changed, 24 insertions(+), 1 deletion(-) > >> > >>diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c > >>index 0eadeb6..5cd2ad4 100644 > >>--- a/drivers/gpu/drm/i915/i915_dma.c > >>+++ b/drivers/gpu/drm/i915/i915_dma.c > >>@@ -222,6 +222,9 @@ static int i915_getparam(struct drm_device *dev, void *data, > >> if (!value) > >> return -ENODEV; > >> break; > >>+ case I915_PARAM_HAS_POOLED_EU: > >>+ value = HAS_POOLED_EU(dev); > >>+ break; > >> case I915_PARAM_HAS_GPU_RESET: > >> value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv); > >> break; > >>diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > >>index 5ae7960..33e0fd0 100644 > >>--- a/drivers/gpu/drm/i915/i915_drv.c > >>+++ b/drivers/gpu/drm/i915/i915_drv.c > >>@@ -357,6 +357,7 @@ static const struct intel_device_info intel_broxton_info = { > >> .has_ddi = 1, > >> .has_fpga_dbg = 1, > >> .has_fbc = 1, > >>+ .has_pooled_eu = 1, > >> GEN_DEFAULT_PIPEOFFSETS, > >> IVB_CURSOR_OFFSETS, > >> BDW_COLORS, > >>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > >>index 7a0b513..5b2a7a3 100644 > >>--- a/drivers/gpu/drm/i915/i915_drv.h > >>+++ b/drivers/gpu/drm/i915/i915_drv.h > >>@@ -750,7 +750,8 @@ struct intel_csr { > >> func(has_llc) sep \ > >> func(has_snoop) sep \ > >> func(has_ddi) sep \ > >>- func(has_fpga_dbg) > >>+ func(has_fpga_dbg) sep \ > >>+ func(has_pooled_eu) > >> > >> #define DEFINE_FLAG(name) u8 name:1 > >> #define SEP_SEMICOLON ; > >>@@ -2736,6 +2737,8 @@ struct drm_i915_cmd_table { > >> !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \ > >> !IS_BROXTON(dev)) > >> > >>+#define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu) > >>+ > >> #define INTEL_PCH_DEVICE_ID_MASK 0xff00 > >> #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 > >> #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 > >>diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c > >>index 7c93327..1284f99 100644 > >>--- a/drivers/gpu/drm/i915/i915_gem_render_state.c > >>+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c > >>@@ -94,6 +94,7 @@ free_gem: > >> > >> static int render_state_setup(struct render_state *so) > >> { > >>+ struct drm_device *dev = so->obj->base.dev; > >> const struct intel_renderstate_rodata *rodata = so->rodata; > >> unsigned int i = 0, reloc_index = 0; > >> struct page *page; > >>@@ -135,6 +136,18 @@ static int render_state_setup(struct render_state *so) > >> > >> so->aux_batch_offset = i * sizeof(u32); > >> > >>+ if (HAS_POOLED_EU(dev)) { > >>+ u32 pool_config = (INTEL_INFO(dev)->subslice_total == 3 ? > >>+ 0x00777000 : 0); > >>+ > >>+ OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE); > >>+ OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE); > >>+ OUT_BATCH(d, i, pool_config); > >>+ OUT_BATCH(d, i, 0); > >>+ OUT_BATCH(d, i, 0); > >>+ OUT_BATCH(d, i, 0); > >>+ } > >>+ > >> OUT_BATCH(d, i, MI_BATCH_BUFFER_END); > >> so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset; > >> > >>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > >>index 54ce0b1..dc67e0e 100644 > >>--- a/drivers/gpu/drm/i915/i915_reg.h > >>+++ b/drivers/gpu/drm/i915/i915_reg.h > >>@@ -442,6 +442,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > >> */ > >> #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) > >> > >>+#define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4) > >>+#define GEN9_MEDIA_POOL_ENABLE (1 << 31) > >> #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) > >> #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) > >> #define SC_UPDATE_SCISSOR (0x1<<1) > >>diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > >>index a5524cc..0b0acad 100644 > >>--- a/include/uapi/drm/i915_drm.h > >>+++ b/include/uapi/drm/i915_drm.h > >>@@ -357,6 +357,7 @@ typedef struct drm_i915_irq_wait { > >> #define I915_PARAM_HAS_GPU_RESET 35 > >> #define I915_PARAM_HAS_RESOURCE_STREAMER 36 > >> #define I915_PARAM_HAS_EXEC_SOFTPIN 37 > >>+#define I915_PARAM_HAS_POOLED_EU 38 > >> > >> typedef struct drm_i915_getparam { > >> __s32 param; > >>-- > >>1.9.1 > >> > >>_______________________________________________ > >>Intel-gfx mailing list > >>Intel-gfx@lists.freedesktop.org > >>https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] drm/i915:bxt: Enable Pooled EU support 2016-05-17 11:13 ` Daniel Vetter @ 2016-05-17 11:31 ` Arun Siluvery 2016-05-17 11:58 ` Daniel Vetter 0 siblings, 1 reply; 8+ messages in thread From: Arun Siluvery @ 2016-05-17 11:31 UTC (permalink / raw) To: Daniel Vetter; +Cc: intel-gfx, Mika Kuoppala On 17/05/2016 16:43, Daniel Vetter wrote: > On Tue, May 17, 2016 at 04:32:49PM +0530, Arun Siluvery wrote: >> On 17/05/2016 15:34, Daniel Vetter wrote: >>> On Thu, May 12, 2016 at 10:37:14AM +0100, Arun Siluvery wrote: >>>> This mode allows to assign EUs to pools which can process work collectively. >>>> The command to enable this mode should be issued as part of context initialization. >>>> >>>> The pooled mode is global, once enabled it has to stay the same across all >>>> contexts until HW reset hence this is sent in auxiliary golden context batch. >>>> Thanks to Mika for the preliminary review and comments. >>>> >>>> v2: explain why this is enabled in golden context, use feature flag while >>>> enabling the support (Chris) >>>> >>>> v3: Pooled EU support announced in userspace before enabling in kernel, >>>> to simplify include all changes in the same patch. >>>> >>>> User space clients need to know when the pooled EU feature is present >>>> and enabled on the hardware so that they can adapt work submissions. >>>> Create a new device info flag for this purpose, and create a new GETPARAM >>>> entry to allow user space to query its setting. >>>> >>>> Set has_pooled_eu to true in the Broxton static device info - Broxton >>>> supports the feature in hardware and the driver will enable it by >>>> default. >>>> >>>> Opensource users for this feature are mesa, libva and beignet. >>> >>> Link to those patches would be great. At least I haven't seen anything fly >>> by for mesa or libva, might have missed it though. Note that the patches >>> must be fully reviewed an ready for merging by respective userspace >>> upstream, before we can land the kernel side. >> >> Initially beignet is trying to use it and they are adding support to it. I >> will share links once they send them to the list, reviewed and ready to be >> merged. > > Then please don't say you have the userspace when it doesn't exist yet. Hi Daniel, I never claimed userspace exists for this feature, only mentioned who are the users and clearly stated in cover letter that Beignet team is currently adding userspace and libdrm support, sorry if I gave that impression. > > The other question: Will existing userspace fall over if we enable this in > the kernel, or is it purely opt-in? Would be good to clarify in the commit > message. Yes it is an opt-in, userspace queries its availability and configures itself. We do have one WA affecting few revisions where it needs to be enabled (explained in cover letter). I will add a note to the commit msg as well. regards Arun > -Daniel >> >> regards >> Arun >> >>> -Daniel >>> >>>> >>>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> >>>> Cc: Winiarski, Michal <michal.winiarski@intel.com> >>>> Cc: Zou, Nanhai <nanhai.zou@intel.com> >>>> Cc: Yang, Rong R <rong.r.yang@intel.com> >>>> Cc: Mika Kuoppala <mika.kuoppala@intel.com> >>>> Cc: Chris Wilson <chris@chris-wilson.co.uk> >>>> Cc: Armin Reese <armin.c.reese@intel.com> >>>> Cc: Tim Gore <tim.gore@intel.com> >>>> Signed-off-by: Jeff McGee <jeff.mcgee@intel.com> >>>> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> >>>> --- >>>> drivers/gpu/drm/i915/i915_dma.c | 3 +++ >>>> drivers/gpu/drm/i915/i915_drv.c | 1 + >>>> drivers/gpu/drm/i915/i915_drv.h | 5 ++++- >>>> drivers/gpu/drm/i915/i915_gem_render_state.c | 13 +++++++++++++ >>>> drivers/gpu/drm/i915/i915_reg.h | 2 ++ >>>> include/uapi/drm/i915_drm.h | 1 + >>>> 6 files changed, 24 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c >>>> index 0eadeb6..5cd2ad4 100644 >>>> --- a/drivers/gpu/drm/i915/i915_dma.c >>>> +++ b/drivers/gpu/drm/i915/i915_dma.c >>>> @@ -222,6 +222,9 @@ static int i915_getparam(struct drm_device *dev, void *data, >>>> if (!value) >>>> return -ENODEV; >>>> break; >>>> + case I915_PARAM_HAS_POOLED_EU: >>>> + value = HAS_POOLED_EU(dev); >>>> + break; >>>> case I915_PARAM_HAS_GPU_RESET: >>>> value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv); >>>> break; >>>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c >>>> index 5ae7960..33e0fd0 100644 >>>> --- a/drivers/gpu/drm/i915/i915_drv.c >>>> +++ b/drivers/gpu/drm/i915/i915_drv.c >>>> @@ -357,6 +357,7 @@ static const struct intel_device_info intel_broxton_info = { >>>> .has_ddi = 1, >>>> .has_fpga_dbg = 1, >>>> .has_fbc = 1, >>>> + .has_pooled_eu = 1, >>>> GEN_DEFAULT_PIPEOFFSETS, >>>> IVB_CURSOR_OFFSETS, >>>> BDW_COLORS, >>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h >>>> index 7a0b513..5b2a7a3 100644 >>>> --- a/drivers/gpu/drm/i915/i915_drv.h >>>> +++ b/drivers/gpu/drm/i915/i915_drv.h >>>> @@ -750,7 +750,8 @@ struct intel_csr { >>>> func(has_llc) sep \ >>>> func(has_snoop) sep \ >>>> func(has_ddi) sep \ >>>> - func(has_fpga_dbg) >>>> + func(has_fpga_dbg) sep \ >>>> + func(has_pooled_eu) >>>> >>>> #define DEFINE_FLAG(name) u8 name:1 >>>> #define SEP_SEMICOLON ; >>>> @@ -2736,6 +2737,8 @@ struct drm_i915_cmd_table { >>>> !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \ >>>> !IS_BROXTON(dev)) >>>> >>>> +#define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu) >>>> + >>>> #define INTEL_PCH_DEVICE_ID_MASK 0xff00 >>>> #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 >>>> #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 >>>> diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c >>>> index 7c93327..1284f99 100644 >>>> --- a/drivers/gpu/drm/i915/i915_gem_render_state.c >>>> +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c >>>> @@ -94,6 +94,7 @@ free_gem: >>>> >>>> static int render_state_setup(struct render_state *so) >>>> { >>>> + struct drm_device *dev = so->obj->base.dev; >>>> const struct intel_renderstate_rodata *rodata = so->rodata; >>>> unsigned int i = 0, reloc_index = 0; >>>> struct page *page; >>>> @@ -135,6 +136,18 @@ static int render_state_setup(struct render_state *so) >>>> >>>> so->aux_batch_offset = i * sizeof(u32); >>>> >>>> + if (HAS_POOLED_EU(dev)) { >>>> + u32 pool_config = (INTEL_INFO(dev)->subslice_total == 3 ? >>>> + 0x00777000 : 0); >>>> + >>>> + OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE); >>>> + OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE); >>>> + OUT_BATCH(d, i, pool_config); >>>> + OUT_BATCH(d, i, 0); >>>> + OUT_BATCH(d, i, 0); >>>> + OUT_BATCH(d, i, 0); >>>> + } >>>> + >>>> OUT_BATCH(d, i, MI_BATCH_BUFFER_END); >>>> so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset; >>>> >>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >>>> index 54ce0b1..dc67e0e 100644 >>>> --- a/drivers/gpu/drm/i915/i915_reg.h >>>> +++ b/drivers/gpu/drm/i915/i915_reg.h >>>> @@ -442,6 +442,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) >>>> */ >>>> #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) >>>> >>>> +#define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4) >>>> +#define GEN9_MEDIA_POOL_ENABLE (1 << 31) >>>> #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) >>>> #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) >>>> #define SC_UPDATE_SCISSOR (0x1<<1) >>>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h >>>> index a5524cc..0b0acad 100644 >>>> --- a/include/uapi/drm/i915_drm.h >>>> +++ b/include/uapi/drm/i915_drm.h >>>> @@ -357,6 +357,7 @@ typedef struct drm_i915_irq_wait { >>>> #define I915_PARAM_HAS_GPU_RESET 35 >>>> #define I915_PARAM_HAS_RESOURCE_STREAMER 36 >>>> #define I915_PARAM_HAS_EXEC_SOFTPIN 37 >>>> +#define I915_PARAM_HAS_POOLED_EU 38 >>>> >>>> typedef struct drm_i915_getparam { >>>> __s32 param; >>>> -- >>>> 1.9.1 >>>> >>>> _______________________________________________ >>>> Intel-gfx mailing list >>>> Intel-gfx@lists.freedesktop.org >>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx >>> >> > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] drm/i915:bxt: Enable Pooled EU support 2016-05-17 11:31 ` Arun Siluvery @ 2016-05-17 11:58 ` Daniel Vetter 0 siblings, 0 replies; 8+ messages in thread From: Daniel Vetter @ 2016-05-17 11:58 UTC (permalink / raw) To: Arun Siluvery; +Cc: intel-gfx, Mika Kuoppala On Tue, May 17, 2016 at 05:01:56PM +0530, Arun Siluvery wrote: > On 17/05/2016 16:43, Daniel Vetter wrote: > >On Tue, May 17, 2016 at 04:32:49PM +0530, Arun Siluvery wrote: > >>On 17/05/2016 15:34, Daniel Vetter wrote: > >>>On Thu, May 12, 2016 at 10:37:14AM +0100, Arun Siluvery wrote: > >>>>This mode allows to assign EUs to pools which can process work collectively. > >>>>The command to enable this mode should be issued as part of context initialization. > >>>> > >>>>The pooled mode is global, once enabled it has to stay the same across all > >>>>contexts until HW reset hence this is sent in auxiliary golden context batch. > >>>>Thanks to Mika for the preliminary review and comments. > >>>> > >>>>v2: explain why this is enabled in golden context, use feature flag while > >>>>enabling the support (Chris) > >>>> > >>>>v3: Pooled EU support announced in userspace before enabling in kernel, > >>>>to simplify include all changes in the same patch. > >>>> > >>>>User space clients need to know when the pooled EU feature is present > >>>>and enabled on the hardware so that they can adapt work submissions. > >>>>Create a new device info flag for this purpose, and create a new GETPARAM > >>>>entry to allow user space to query its setting. > >>>> > >>>>Set has_pooled_eu to true in the Broxton static device info - Broxton > >>>>supports the feature in hardware and the driver will enable it by > >>>>default. > >>>> > >>>>Opensource users for this feature are mesa, libva and beignet. > >>> > >>>Link to those patches would be great. At least I haven't seen anything fly > >>>by for mesa or libva, might have missed it though. Note that the patches > >>>must be fully reviewed an ready for merging by respective userspace > >>>upstream, before we can land the kernel side. > >> > >>Initially beignet is trying to use it and they are adding support to it. I > >>will share links once they send them to the list, reviewed and ready to be > >>merged. > > > >Then please don't say you have the userspace when it doesn't exist yet. > > Hi Daniel, > > I never claimed userspace exists for this feature, only mentioned who are > the users and clearly stated in cover letter that Beignet team is currently > adding userspace and libdrm support, sorry if I gave that impression. Sorry for missing that, I just spotted the one line in the patch here and assumed it's all there already. > >The other question: Will existing userspace fall over if we enable this in > >the kernel, or is it purely opt-in? Would be good to clarify in the commit > >message. > Yes it is an opt-in, userspace queries its availability and configures > itself. We do have one WA affecting few revisions where it needs to be > enabled (explained in cover letter). I will add a note to the commit msg as > well. For the places where we must enable it, might be good to just merge that without the userspace flag. That way we don't block the wa on the userspace/ABI question. Then just add the patch with the getparam later on when we have the userspace reviewed. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/2] drm/i915/bxt: Add WaEnablePooledEuFor2x6 2016-05-12 9:37 [PATCH 0/2] BXT Pooled EU kernel support Arun Siluvery 2016-05-12 9:37 ` [PATCH 1/2] drm/i915:bxt: Enable Pooled EU support Arun Siluvery @ 2016-05-12 9:37 ` Arun Siluvery 1 sibling, 0 replies; 8+ messages in thread From: Arun Siluvery @ 2016-05-12 9:37 UTC (permalink / raw) To: intel-gfx Pooled EU is enabled by default for BXT but for fused down 2x6 parts it is advised to turn it off. But there is another HW issue in these parts (fused down 2x6 parts) before C0 that requires Pooled EU to be enabled as a workaround. In this case the pool configuration changes depending upon which subslice is disabled. This doesn't affect if the device has all 3 subslices enabled. Userspace need to know min no. of eus in a pool as it varies based on which subslice is disabled, this is exported using a new private getparam ioctl as there is no opensource user available for this feature yet. Cc: Winiarski, Michal <michal.winiarski@intel.com> Cc: Zou, Nanhai <nanhai.zou@intel.com> Cc: Yang, Rong R <rong.r.yang@intel.com> Cc: Tim Gore <tim.gore@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 5 +++++ drivers/gpu/drm/i915/i915_dma.c | 33 ++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_render_state.c | 17 +++++++++++--- include/uapi/drm/i915_drm.h | 1 + 6 files changed, 55 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 5e5b5cc..a61a4f9 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -5274,6 +5274,11 @@ static int i915_sseu_status(struct seq_file *m, void *unused) INTEL_INFO(dev)->eu_total); seq_printf(m, " Available EU Per Subslice: %u\n", INTEL_INFO(dev)->eu_per_subslice); + seq_printf(m, " Has Pooled EU: %s\n", + yesno(HAS_POOLED_EU(dev))); + if (HAS_POOLED_EU(dev)) + seq_printf(m, " Min EU in pool: %u\n", + INTEL_INFO(dev)->min_eu_in_pool); seq_printf(m, " Has Slice Power Gating: %s\n", yesno(INTEL_INFO(dev)->has_slice_pg)); seq_printf(m, " Has Subslice Power Gating: %s\n", diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 5cd2ad4..eab53fd 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -225,6 +225,9 @@ static int i915_getparam(struct drm_device *dev, void *data, case I915_PARAM_HAS_POOLED_EU: value = HAS_POOLED_EU(dev); break; + case I915_PARAM_MIN_EU_IN_POOL: + value = INTEL_INFO(dev)->min_eu_in_pool; + break; case I915_PARAM_HAS_GPU_RESET: value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv); break; @@ -770,6 +773,32 @@ static void gen9_sseu_info_init(struct drm_device *dev) (info->slice_total > 1)); info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1)); info->has_eu_pg = (info->eu_per_subslice > 2); + + if (IS_BROXTON(dev)) { +#define IS_SS_DISABLED(_ss_disable, ss) (_ss_disable & (0x1 << ss)) + /* + * There is a HW issue in 2x6 fused down parts that requires + * Pooled EU to be enabled as a WA. The pool configuration + * changes depending upon which subslice is fused down. This + * doesn't affect if the device has all 3 subslices enabled. + */ + /* WaEnablePooledEuFor2x6:bxt */ + info->has_pooled_eu = ((info->subslice_total == 3) || + (info->subslice_total == 2 && + INTEL_REVID(dev) < BXT_REVID_C0)); + + info->min_eu_in_pool = 0; + if (info->has_pooled_eu) { + if (IS_SS_DISABLED(ss_disable, 0) || + IS_SS_DISABLED(ss_disable, 2)) + info->min_eu_in_pool = 3; + else if (IS_SS_DISABLED(ss_disable, 1)) + info->min_eu_in_pool = 6; + else + info->min_eu_in_pool = 9; + } +#undef IS_SS_DISABLED + } } static void broadwell_sseu_info_init(struct drm_device *dev) @@ -966,6 +995,10 @@ static void intel_device_info_runtime_init(struct drm_device *dev) DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice); DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total); DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice); + DRM_DEBUG_DRIVER("Has Pooled EU: %s\n", + HAS_POOLED_EU(dev) ? "y" : "n"); + if (HAS_POOLED_EU(dev)) + DRM_DEBUG_DRIVER("Min EU in pool: %u\n", info->min_eu_in_pool); DRM_DEBUG_DRIVER("has slice power gating: %s\n", info->has_slice_pg ? "y" : "n"); DRM_DEBUG_DRIVER("has subslice power gating: %s\n", diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 33e0fd0..4d6052d 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -357,7 +357,7 @@ static const struct intel_device_info intel_broxton_info = { .has_ddi = 1, .has_fpga_dbg = 1, .has_fbc = 1, - .has_pooled_eu = 1, + .has_pooled_eu = 0, GEN_DEFAULT_PIPEOFFSETS, IVB_CURSOR_OFFSETS, BDW_COLORS, diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5b2a7a3..d87f43c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -777,6 +777,7 @@ struct intel_device_info { u8 subslice_per_slice; u8 eu_total; u8 eu_per_subslice; + u8 min_eu_in_pool; /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ u8 subslice_7eu[3]; u8 has_slice_pg:1; diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c index 1284f99..33bd8ce 100644 --- a/drivers/gpu/drm/i915/i915_gem_render_state.c +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c @@ -137,12 +137,23 @@ static int render_state_setup(struct render_state *so) so->aux_batch_offset = i * sizeof(u32); if (HAS_POOLED_EU(dev)) { - u32 pool_config = (INTEL_INFO(dev)->subslice_total == 3 ? - 0x00777000 : 0); + /* + * We always program 3x6 pool config but depending upon which + * subslice is disabled HW drops down to appropriate config + * shown below. + * + * SNo subslices config eu pool configuration + * ----------------------------------------------------------- + * 1 3 subslices enabled (3x6) - 0x00777000 (9+9) + * 2 ss0 disabled (2x6) - 0x00777000 (3+9) + * 3 ss1 disabled (2x6) - 0x00770000 (6+6) + * 4 ss2 disabled (2x6) - 0x00007000 (9+3) + */ + u32 eu_pool_config = 0x00777000; OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE); OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE); - OUT_BATCH(d, i, pool_config); + OUT_BATCH(d, i, eu_pool_config); OUT_BATCH(d, i, 0); OUT_BATCH(d, i, 0); OUT_BATCH(d, i, 0); diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 0b0acad..7efba36 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -358,6 +358,7 @@ typedef struct drm_i915_irq_wait { #define I915_PARAM_HAS_RESOURCE_STREAMER 36 #define I915_PARAM_HAS_EXEC_SOFTPIN 37 #define I915_PARAM_HAS_POOLED_EU 38 +#define I915_PARAM_MIN_EU_IN_POOL 39 typedef struct drm_i915_getparam { __s32 param; -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2016-05-17 11:58 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-05-12 9:37 [PATCH 0/2] BXT Pooled EU kernel support Arun Siluvery 2016-05-12 9:37 ` [PATCH 1/2] drm/i915:bxt: Enable Pooled EU support Arun Siluvery 2016-05-17 10:04 ` Daniel Vetter 2016-05-17 11:02 ` Arun Siluvery 2016-05-17 11:13 ` Daniel Vetter 2016-05-17 11:31 ` Arun Siluvery 2016-05-17 11:58 ` Daniel Vetter 2016-05-12 9:37 ` [PATCH 2/2] drm/i915/bxt: Add WaEnablePooledEuFor2x6 Arun Siluvery
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