From: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>
To: <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 04/12] drm/i915: Start using struct intel_csc_matrix for chv cgm csc
Date: Thu, 6 Apr 2023 14:35:56 +0530 [thread overview]
Message-ID: <64678098-8db1-b6c3-eaed-afcb94e13d01@intel.com> (raw)
In-Reply-To: <20230329135002.3096-5-ville.syrjala@linux.intel.com>
On 3/29/2023 7:19 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Convert chv_cgm_csc_convert_ctm() over to using the nee
nitpick: typo: new.
Otherwise LGTM.
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> intel_csc_matrix structure. No pre/post offsets on this
> hardware so only the coefficients get filled out.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 24 +++++++++++-----------
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 47af24e64a7e..a76cea4ab1ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -399,7 +399,7 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
> }
> }
>
> -static void chv_cgm_csc_convert_ctm(u16 coeffs[9],
> +static void chv_cgm_csc_convert_ctm(struct intel_csc_matrix *csc,
> const struct drm_property_blob *blob)
> {
> const struct drm_color_ctm *ctm = blob->data;
> @@ -413,14 +413,14 @@ static void chv_cgm_csc_convert_ctm(u16 coeffs[9],
> /* Clamp to hardware limits. */
> abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
>
> - coeffs[i] = 0;
> + csc->coeff[i] = 0;
>
> /* Write coefficients in S3.12 format. */
> if (ctm->matrix[i] & (1ULL << 63))
> - coeffs[i] |= 1 << 15;
> + csc->coeff[i] |= 1 << 15;
>
> - coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
> - coeffs[i] |= (abs_coeff >> 20) & 0xfff;
> + csc->coeff[i] |= ((abs_coeff >> 32) & 7) << 12;
> + csc->coeff[i] |= (abs_coeff >> 20) & 0xfff;
> }
> }
>
> @@ -429,20 +429,20 @@ static void chv_load_cgm_csc(struct intel_crtc *crtc,
> {
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> - u16 coeffs[9];
> + struct intel_csc_matrix tmp;
>
> - chv_cgm_csc_convert_ctm(coeffs, blob);
> + chv_cgm_csc_convert_ctm(&tmp, blob);
>
> intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF01(pipe),
> - coeffs[1] << 16 | coeffs[0]);
> + tmp.coeff[1] << 16 | tmp.coeff[0]);
> intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF23(pipe),
> - coeffs[3] << 16 | coeffs[2]);
> + tmp.coeff[3] << 16 | tmp.coeff[2]);
> intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF45(pipe),
> - coeffs[5] << 16 | coeffs[4]);
> + tmp.coeff[5] << 16 | tmp.coeff[4]);
> intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF67(pipe),
> - coeffs[7] << 16 | coeffs[6]);
> + tmp.coeff[7] << 16 | tmp.coeff[6]);
> intel_de_write_fw(i915, CGM_PIPE_CSC_COEFF8(pipe),
> - coeffs[8]);
> + tmp.coeff[8]);
> }
>
> /* convert hw value with given bit_precision to lut property val */
next prev parent reply other threads:[~2023-04-06 9:06 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-29 13:49 [Intel-gfx] [PATCH 00/12] drm/i915: Add CSC state readout/check Ville Syrjala
2023-03-29 13:49 ` [Intel-gfx] [PATCH 01/12] drm/i915: Fix limited range csc matrix Ville Syrjala
2023-04-06 10:56 ` Nautiyal, Ankit K
2023-04-06 11:10 ` Ville Syrjälä
2023-04-06 11:54 ` Nautiyal, Ankit K
2023-03-29 13:49 ` [Intel-gfx] [PATCH 02/12] drm/i915: Introduce intel_csc_matrix struct Ville Syrjala
2023-04-06 9:00 ` Nautiyal, Ankit K
2023-04-11 5:07 ` Ville Syrjälä
2023-04-11 5:35 ` Nautiyal, Ankit K
2023-03-29 13:49 ` [Intel-gfx] [PATCH 03/12] drm/i915: Split chv_load_cgm_csc() into pieces Ville Syrjala
2023-04-06 9:03 ` Nautiyal, Ankit K
2023-04-06 9:17 ` Nautiyal, Ankit K
2023-04-06 10:45 ` Ville Syrjälä
2023-03-29 13:49 ` [Intel-gfx] [PATCH 04/12] drm/i915: Start using struct intel_csc_matrix for chv cgm csc Ville Syrjala
2023-04-06 9:05 ` Nautiyal, Ankit K [this message]
2023-03-29 13:49 ` [Intel-gfx] [PATCH 05/12] drm/i915: Store ilk+ csc matrices in the crtc state Ville Syrjala
2023-04-06 9:12 ` Nautiyal, Ankit K
2023-03-29 13:49 ` [Intel-gfx] [PATCH 06/12] drm/i915: Utilize crtc_state->csc on chv Ville Syrjala
2023-04-06 9:21 ` Nautiyal, Ankit K
2023-03-29 13:49 ` [Intel-gfx] [PATCH 07/12] drm/i915: Sprinke a few sanity check WARNS during csc assignment Ville Syrjala
2023-04-06 9:24 ` Nautiyal, Ankit K
2023-03-29 13:49 ` [Intel-gfx] [PATCH 08/12] drm/i915: Add hardware csc readout for ilk+ Ville Syrjala
2023-04-06 9:30 ` Nautiyal, Ankit K
2023-03-29 13:49 ` [Intel-gfx] [PATCH 09/12] drm/i915: Implement chv cgm csc readout Ville Syrjala
2023-04-06 9:31 ` Nautiyal, Ankit K
2023-03-29 13:50 ` [Intel-gfx] [PATCH 10/12] drm/i915: Include the csc matrices in the crtc state dump Ville Syrjala
2023-04-06 9:49 ` Nautiyal, Ankit K
2023-03-29 13:50 ` [Intel-gfx] [PATCH 11/12] drm/i915: Hook up csc into state checker Ville Syrjala
2023-04-06 9:53 ` Nautiyal, Ankit K
2023-03-29 13:50 ` [Intel-gfx] [PATCH 12/12] drm/i915: Do state check for color management changes Ville Syrjala
2023-03-29 18:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add CSC state readout/check Patchwork
2023-03-29 18:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-03-29 18:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-30 11:06 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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