From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 02/12] drm/i915: Introduce intel_csc_matrix struct
Date: Tue, 11 Apr 2023 08:07:30 +0300 [thread overview]
Message-ID: <ZDTrEg/fQR6PKUUn@intel.com> (raw)
In-Reply-To: <1e25f41e-9c6c-e6b5-e56f-fc49a441176e@intel.com>
> > @@ -294,13 +293,20 @@ static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
> > }
> >
> > static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
> > - u16 coeffs[9], bool limited_color_range)
> > + struct intel_csc_matrix *csc,
> > + bool limited_color_range)
> > {
> > const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
> > const u64 *input;
> > u64 temp[9];
> > int i;
> >
> > + /* for preoff/postoff */
> > + if (limited_color_range)
> > + *csc = ilk_csc_matrix_limited_range;
> > + else
> > + *csc = ilk_csc_matrix_identity;
>
>
> Lets merge this if block with the below if block, as we are again
> checking limited_color_range.
I considered that, but didn't really like it. Seemed clearner to
first setup the pre/post offsets, and only then deal with the
input matrix.
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2023-04-11 5:07 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-29 13:49 [Intel-gfx] [PATCH 00/12] drm/i915: Add CSC state readout/check Ville Syrjala
2023-03-29 13:49 ` [Intel-gfx] [PATCH 01/12] drm/i915: Fix limited range csc matrix Ville Syrjala
2023-04-06 10:56 ` Nautiyal, Ankit K
2023-04-06 11:10 ` Ville Syrjälä
2023-04-06 11:54 ` Nautiyal, Ankit K
2023-03-29 13:49 ` [Intel-gfx] [PATCH 02/12] drm/i915: Introduce intel_csc_matrix struct Ville Syrjala
2023-04-06 9:00 ` Nautiyal, Ankit K
2023-04-11 5:07 ` Ville Syrjälä [this message]
2023-04-11 5:35 ` Nautiyal, Ankit K
2023-03-29 13:49 ` [Intel-gfx] [PATCH 03/12] drm/i915: Split chv_load_cgm_csc() into pieces Ville Syrjala
2023-04-06 9:03 ` Nautiyal, Ankit K
2023-04-06 9:17 ` Nautiyal, Ankit K
2023-04-06 10:45 ` Ville Syrjälä
2023-03-29 13:49 ` [Intel-gfx] [PATCH 04/12] drm/i915: Start using struct intel_csc_matrix for chv cgm csc Ville Syrjala
2023-04-06 9:05 ` Nautiyal, Ankit K
2023-03-29 13:49 ` [Intel-gfx] [PATCH 05/12] drm/i915: Store ilk+ csc matrices in the crtc state Ville Syrjala
2023-04-06 9:12 ` Nautiyal, Ankit K
2023-03-29 13:49 ` [Intel-gfx] [PATCH 06/12] drm/i915: Utilize crtc_state->csc on chv Ville Syrjala
2023-04-06 9:21 ` Nautiyal, Ankit K
2023-03-29 13:49 ` [Intel-gfx] [PATCH 07/12] drm/i915: Sprinke a few sanity check WARNS during csc assignment Ville Syrjala
2023-04-06 9:24 ` Nautiyal, Ankit K
2023-03-29 13:49 ` [Intel-gfx] [PATCH 08/12] drm/i915: Add hardware csc readout for ilk+ Ville Syrjala
2023-04-06 9:30 ` Nautiyal, Ankit K
2023-03-29 13:49 ` [Intel-gfx] [PATCH 09/12] drm/i915: Implement chv cgm csc readout Ville Syrjala
2023-04-06 9:31 ` Nautiyal, Ankit K
2023-03-29 13:50 ` [Intel-gfx] [PATCH 10/12] drm/i915: Include the csc matrices in the crtc state dump Ville Syrjala
2023-04-06 9:49 ` Nautiyal, Ankit K
2023-03-29 13:50 ` [Intel-gfx] [PATCH 11/12] drm/i915: Hook up csc into state checker Ville Syrjala
2023-04-06 9:53 ` Nautiyal, Ankit K
2023-03-29 13:50 ` [Intel-gfx] [PATCH 12/12] drm/i915: Do state check for color management changes Ville Syrjala
2023-03-29 18:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add CSC state readout/check Patchwork
2023-03-29 18:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-03-29 18:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-30 11:06 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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