[PATCH v2 00/10] Enable DP2.1 alpm

[PATCH v2 00/10] Enable DP2.1 alpm

[Animesh Manna]

ALPM support added on DP2.1 and xe3p will support DP2.1 alpm.
This patch series extending alpm supoort for DP2.1.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>

Animesh Manna (10):
  drm/i915/alpm: Add dpcd definition for DP2.1 alpm capability
  drm/i915/alpm: alpm_init() for DP2.1
  drm/i915/alpm: Enable debugfs for DP2.1
  drm/i915/alpm: Refactor Auxless wake time calculation
  drm/i915/alpm: Auxless wake time calculation for Xe3p
  drm/i915/alpm: Half LFPS cycle calculation
  drm/i915/alpm: Program lttpr count for DP 2.1 alpm
  drm/i915/alpm: Enable MAC Transmitting LFPS for LT phy
  drm/i915/alpm: Replace is_edp() with alpm_is_possible()
  drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf

 drivers/gpu/drm/i915/display/intel_alpm.c     | 148 ++++++++++++++----
 drivers/gpu/drm/i915/display/intel_alpm.h     |   1 +
 drivers/gpu/drm/i915/display/intel_ddi.c      |   5 +-
 .../drm/i915/display/intel_display_types.h    |   2 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  11 +-
 .../drm/i915/display/intel_dp_link_training.c |  12 ++
 drivers/gpu/drm/i915/display/intel_lt_phy.c   |  35 +++++
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |   2 +
 .../gpu/drm/i915/display/intel_lt_phy_regs.h  |   3 +
 drivers/gpu/drm/i915/display/intel_psr.c      |  23 ++-
 drivers/gpu/drm/i915/display/intel_psr.h      |   1 -
 include/drm/display/drm_dp.h                  |   4 +-
 12 files changed, 197 insertions(+), 50 deletions(-)

-- 
2.29.0

[PATCH v2 01/10] drm/i915/alpm: Add dpcd definition for DP2.1 alpm capability

[Animesh Manna]

Add required dpcd address which will be needed to enable DP2.1 alpm.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 include/drm/display/drm_dp.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index e4eebabab975..b4bacbcf130e 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1512,6 +1512,8 @@
 /* See DP_128B132B_SUPPORTED_LINK_RATES for values */
 #define DP_PHY_REPEATER_128B132B_RATES			    0xf0007 /* 2.0 */
 #define DP_PHY_REPEATER_EQ_DONE                             0xf0008 /* 2.0 E11 */
+#define DP_LTTPR_ALPM_CAPABILITIES                          0xf0009 /* 2.1 */
+#define DP_TOTAL_LTTPR_CNT                                  0xf000a /* 2.1 */
 
 enum drm_dp_phy {
 	DP_PHY_DPRX,
@@ -1691,7 +1693,7 @@ enum drm_dp_phy {
 #define DP_DSC_BRANCH_CAP_SIZE		3
 #define EDP_PSR_RECEIVER_CAP_SIZE	2
 #define EDP_DISPLAY_CTL_CAP_SIZE	5
-#define DP_LTTPR_COMMON_CAP_SIZE	8
+#define DP_LTTPR_COMMON_CAP_SIZE	10
 #define DP_LTTPR_PHY_CAP_SIZE		3
 
 #define DP_SDP_AUDIO_TIMESTAMP		0x01
-- 
2.29.0

[PATCH v2 02/10] drm/i915/alpm: alpm_init() for DP2.1

[Animesh Manna]

Initialize alpm for DP2.1 and separate out alpm mutex-init
from alpm-init.

v1: Initial version.
v2: Separate out mutex-init. [Jani]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c |  1 -
 drivers/gpu/drm/i915/display/intel_dp.c   | 11 ++++++++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 6372f533f65b..639941e332f3 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -49,7 +49,6 @@ void intel_alpm_init(struct intel_dp *intel_dp)
 		return;
 
 	intel_dp->alpm_dpcd = dpcd;
-	mutex_init(&intel_dp->alpm.lock);
 }
 
 static int get_silence_period_symbols(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0ec82fcbcf48..f995a98df2c3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6074,8 +6074,12 @@ intel_dp_detect(struct drm_connector *_connector,
 	if (ret == 1)
 		connector->base.epoch_counter++;
 
-	if (!intel_dp_is_edp(intel_dp))
+	if (!intel_dp_is_edp(intel_dp)) {
+		if (DISPLAY_VER(display) >= 35)
+			intel_alpm_init(intel_dp);
+
 		intel_psr_init_dpcd(intel_dp);
+	}
 
 	intel_dp_detect_dsc_caps(intel_dp, connector);
 
@@ -6717,6 +6721,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 	intel_hpd_enable_detection(encoder);
 
 	intel_alpm_init(intel_dp);
+	if (intel_dp->alpm_dpcd)
+		mutex_init(&intel_dp->alpm.lock);
 
 	/* Cache DPCD and EDID for edp. */
 	has_dpcd = intel_edp_init_dpcd(intel_dp, connector);
@@ -6932,6 +6938,9 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
 
 	intel_psr_init(intel_dp);
 
+	if (DISPLAY_VER(display) >= 35)
+		mutex_init(&intel_dp->alpm.lock);
+
 	return true;
 
 fail:
-- 
2.29.0

[PATCH v2 03/10] drm/i915/alpm: Enable debugfs for DP2.1

[Animesh Manna]

Enable AlPM debug info through lobf debug info.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 639941e332f3..779718d0c8dd 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -541,9 +541,15 @@ void intel_alpm_lobf_debugfs_add(struct intel_connector *connector)
 	struct intel_display *display = to_intel_display(connector);
 	struct dentry *root = connector->base.debugfs_entry;
 
-	if (DISPLAY_VER(display) < 20 ||
-	    connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
+	if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
+		if (DISPLAY_VER(display) < 35)
+			return;
+	} else if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
+		if (DISPLAY_VER(display) < 20)
+			return;
+	} else {
 		return;
+	}
 
 	debugfs_create_file("i915_edp_lobf_debug", 0644, root,
 			    connector, &i915_edp_lobf_debug_fops);
-- 
2.29.0

[PATCH v2 04/10] drm/i915/alpm: Refactor Auxless wake time calculation

[Animesh Manna]

Divide the auxless wake time calculation in parts which will
help later to add Xe3p related modification.

v1: Initial version.
v2: Refactor first existing calculation. [Jani]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 37 ++++++++++++++++-------
 1 file changed, 26 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 779718d0c8dd..8d07455a62c2 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -85,6 +85,26 @@ static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
 		1000 / (2 * LFPS_CYCLE_COUNT);
 }
 
+static int get_tphy2_p2_to_p0(struct intel_dp *intel_dp)
+{
+	return 12 * 1000;
+}
+
+static int get_establishment_period(struct intel_dp *intel_dp,
+				    const struct intel_crtc_state *crtc_state)
+{
+	int port_clock = crtc_state->port_clock;
+	int t1 = 50 * 1000;
+	int tps4 = (252 * 10);
+	long tml_phy_lock = 1000 * 1000 * tps4 / port_clock / 10;
+	int tcds, establishment_period;
+
+	tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * tml_phy_lock;
+	establishment_period = (SILENCE_PERIOD_TIME + t1 + tcds);
+
+	return establishment_period;
+}
+
 /*
  * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+
  * tSilence, Max+ tPHY Establishment + tCDS) / tline)
@@ -104,19 +124,14 @@ static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
  * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )
  * TPS4 Length = 252 Symbols
  */
-static int _lnl_compute_aux_less_wake_time(const struct intel_crtc_state *crtc_state)
+static int _lnl_compute_aux_less_wake_time(struct intel_dp *intel_dp,
+					   const struct intel_crtc_state *crtc_state)
 {
-	int tphy2_p2_to_p0 = 12 * 1000;
-	int t1 = 50 * 1000;
-	int tps4 = 252;
-	/* port_clock is link rate in 10kbit/s units */
-	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock;
-	int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
-	int t2 = num_ml_phy_lock * tml_phy_lock;
-	int tcds = 1 * t2;
+	int tphy2_p2_to_p0 = get_tphy2_p2_to_p0(intel_dp);
+	int establishment_period = get_establishment_period(intel_dp, crtc_state);
 
 	return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(crtc_state) +
-			    SILENCE_PERIOD_TIME + t1 + tcds, 1000);
+			    establishment_period, 1000);
 }
 
 static int
@@ -128,7 +143,7 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
 		lfps_half_cycle;
 
 	aux_less_wake_time =
-		_lnl_compute_aux_less_wake_time(crtc_state);
+		_lnl_compute_aux_less_wake_time(intel_dp, crtc_state);
 	aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
 						       aux_less_wake_time);
 	silence_period = get_silence_period_symbols(crtc_state);
-- 
2.29.0

[PATCH v2 05/10] drm/i915/alpm: Auxless wake time calculation for Xe3p

[Animesh Manna]

Add support for auxless waketime calculation for DP2.1 ALPM
as dependent parameter got changed.

v1: Initial version.
v2: Use intel_dp_is_uhbr(). [Jani]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 51 ++++++++++++++++++++---
 1 file changed, 46 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 8d07455a62c2..5686064def8d 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -87,7 +87,9 @@ static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
 
 static int get_tphy2_p2_to_p0(struct intel_dp *intel_dp)
 {
-	return 12 * 1000;
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	return DISPLAY_VER(display) >= 35 ? (40 * 1000) : (12 * 1000);
 }
 
 static int get_establishment_period(struct intel_dp *intel_dp,
@@ -95,16 +97,54 @@ static int get_establishment_period(struct intel_dp *intel_dp,
 {
 	int port_clock = crtc_state->port_clock;
 	int t1 = 50 * 1000;
-	int tps4 = (252 * 10);
+	int tps4 = intel_dp_is_uhbr(crtc_state) ? (396 * 32) : (252 * 10);
 	long tml_phy_lock = 1000 * 1000 * tps4 / port_clock / 10;
+	int lttpr_count = 0;
 	int tcds, establishment_period;
 
-	tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * tml_phy_lock;
-	establishment_period = (SILENCE_PERIOD_TIME + t1 + tcds);
+	if (intel_dp_is_edp(intel_dp)) {
+		tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * tml_phy_lock;
+	} else {
+		tcds = 7 * tml_phy_lock;
+		lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
+	}
+
+	if (lttpr_count) {
+		int tlw = 13000;
+		int tcs = 10000;
+		int tlfps_period = get_lfps_cycle_time(crtc_state);
+		int tdcs = (SILENCE_PERIOD_TIME + t1 + tcs +
+			    (lttpr_count - 1) * (tlw + tlfps_period));
+		int tacds = 70000;
+		int tds = (lttpr_count - 1) * 7 * tml_phy_lock;
+
+		/* tdrl is same as tcds*/
+		establishment_period = tlw + tlfps_period + tdcs + tacds + tds + tcds;
+	} else {
+		/* TODO: Add a check for data realign by DPCD 0x116[3] */
+
+		establishment_period = (SILENCE_PERIOD_TIME + t1 + tcds);
+	}
 
 	return establishment_period;
 }
 
+static int get_switch_to_active(const struct intel_crtc_state *crtc_state)
+{
+	int port_clock = crtc_state->port_clock;
+	int switch_to_active;
+
+	if (intel_dp_is_uhbr(crtc_state)) {
+		int symbol_clock = port_clock / intel_dp_link_symbol_size(port_clock);
+
+		switch_to_active = 32 * DIV_ROUND_UP((396 + 3 + 64), symbol_clock);
+	} else {
+		switch_to_active = 0;
+	}
+
+	return switch_to_active;
+}
+
 /*
  * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+
  * tSilence, Max+ tPHY Establishment + tCDS) / tline)
@@ -129,9 +169,10 @@ static int _lnl_compute_aux_less_wake_time(struct intel_dp *intel_dp,
 {
 	int tphy2_p2_to_p0 = get_tphy2_p2_to_p0(intel_dp);
 	int establishment_period = get_establishment_period(intel_dp, crtc_state);
+	int switch_to_active = get_switch_to_active(crtc_state);
 
 	return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(crtc_state) +
-			    establishment_period, 1000);
+			    establishment_period + switch_to_active, 1000);
 }
 
 static int
-- 
2.29.0

[PATCH v2 06/10] drm/i915/alpm: Half LFPS cycle calculation

[Animesh Manna]

Add support for half LFPS cycle calculation for DP2.1 ALPM as dependent
parameters got changed.

v1: Initial version.
v2: Avoid returning early. [Jani]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 38 +++++++++++++++--------
 1 file changed, 25 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 5686064def8d..97813ce2d4d0 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -57,31 +57,43 @@ static int get_silence_period_symbols(const struct intel_crtc_state *crtc_state)
 		1000 / 1000;
 }
 
-static void get_lfps_cycle_min_max_time(const struct intel_crtc_state *crtc_state,
+static void get_lfps_cycle_min_max_time(struct intel_dp *intel_dp,
+					const struct intel_crtc_state *crtc_state,
 					int *min, int *max)
 {
-	if (crtc_state->port_clock < 540000) {
-		*min = 65 * LFPS_CYCLE_COUNT;
-		*max = 75 * LFPS_CYCLE_COUNT;
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	if (intel_dp_is_edp(intel_dp)) {
+		if (crtc_state->port_clock < 540000) {
+			*min = DISPLAY_VER(display) < 35 ? 65 * LFPS_CYCLE_COUNT : 140;
+			*max = DISPLAY_VER(display) < 35 ? 75 * LFPS_CYCLE_COUNT : 800;
+		} else {
+			*min = 140;
+			*max = 800;
+		}
 	} else {
-		*min = 140;
-		*max = 800;
+		*min = 320;
+		*max = 1600;
+		return;
 	}
 }
 
-static int get_lfps_cycle_time(const struct intel_crtc_state *crtc_state)
+static int get_lfps_cycle_time(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state)
 {
 	int tlfps_cycle_min, tlfps_cycle_max;
 
-	get_lfps_cycle_min_max_time(crtc_state, &tlfps_cycle_min,
+	get_lfps_cycle_min_max_time(intel_dp, crtc_state, &tlfps_cycle_min,
 				    &tlfps_cycle_max);
 
 	return tlfps_cycle_min +  (tlfps_cycle_max - tlfps_cycle_min) / 2;
 }
 
-static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
+static int get_lfps_half_cycle_clocks(struct intel_dp *intel_dp,
+				      const struct intel_crtc_state *crtc_state)
 {
-	return get_lfps_cycle_time(crtc_state) * crtc_state->port_clock / 1000 /
+	return get_lfps_cycle_time(intel_dp, crtc_state) *
+		crtc_state->port_clock / 1000 /
 		1000 / (2 * LFPS_CYCLE_COUNT);
 }
 
@@ -112,7 +124,7 @@ static int get_establishment_period(struct intel_dp *intel_dp,
 	if (lttpr_count) {
 		int tlw = 13000;
 		int tcs = 10000;
-		int tlfps_period = get_lfps_cycle_time(crtc_state);
+		int tlfps_period = get_lfps_cycle_time(intel_dp, crtc_state);
 		int tdcs = (SILENCE_PERIOD_TIME + t1 + tcs +
 			    (lttpr_count - 1) * (tlw + tlfps_period));
 		int tacds = 70000;
@@ -171,7 +183,7 @@ static int _lnl_compute_aux_less_wake_time(struct intel_dp *intel_dp,
 	int establishment_period = get_establishment_period(intel_dp, crtc_state);
 	int switch_to_active = get_switch_to_active(crtc_state);
 
-	return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(crtc_state) +
+	return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(intel_dp, crtc_state) +
 			    establishment_period + switch_to_active, 1000);
 }
 
@@ -189,7 +201,7 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
 						       aux_less_wake_time);
 	silence_period = get_silence_period_symbols(crtc_state);
 
-	lfps_half_cycle = get_lfps_half_cycle_clocks(crtc_state);
+	lfps_half_cycle = get_lfps_half_cycle_clocks(intel_dp, crtc_state);
 
 	if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK ||
 	    silence_period > PORT_ALPM_CTL_SILENCE_PERIOD_MASK ||
-- 
2.29.0

[PATCH v2 07/10] drm/i915/alpm: Program lttpr count for DP 2.1 alpm

[Animesh Manna]

Issue a aux write transaction to dpcd 0xf000a with total number of lttpr
before link traning.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 .../gpu/drm/i915/display/intel_dp_link_training.c    | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index aad5fe14962f..cf25fd51f452 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1624,6 +1624,16 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
 	return passed;
 }
 
+static void intel_dp_update_lttpr_count(struct intel_dp *intel_dp,
+					int lttpr_count)
+{
+	if (!intel_dp_is_edp(intel_dp) ||
+	    intel_dp->lttpr_common_caps[0] <= 0x20)
+		return;
+
+	drm_dp_dpcd_writeb(&intel_dp->aux, DP_TOTAL_LTTPR_CNT, lttpr_count);
+}
+
 /**
  * intel_dp_start_link_train - start link training
  * @state: Atomic state
@@ -1660,6 +1670,8 @@ void intel_dp_start_link_train(struct intel_atomic_state *state,
 
 	intel_dp_prepare_link_train(intel_dp, crtc_state);
 
+	intel_dp_update_lttpr_count(intel_dp, lttpr_count);
+
 	if (intel_dp_is_uhbr(crtc_state))
 		passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count);
 	else
-- 
2.29.0

[PATCH v2 08/10] drm/i915/alpm: Enable MAC Transmitting LFPS for LT phy

[Animesh Manna]

Enable LT phy for transmitting LFPS during aux-less alpm.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      |  5 ++-
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 35 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |  2 ++
 .../gpu/drm/i915/display/intel_lt_phy_regs.h  |  3 ++
 4 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 733ef4559131..f6450ebea2a8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3781,7 +3781,10 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
 	 *     ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" PIPE
 	 *         register
 	 */
-	intel_lnl_mac_transmit_lfps(encoder, crtc_state);
+	if (HAS_LT_PHY(display))
+		intel_xe3plpd_mac_transmit_lfps(encoder, crtc_state);
+	else
+		intel_lnl_mac_transmit_lfps(encoder, crtc_state);
 }
 
 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index af48d6cde226..87659a9d9847 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -7,6 +7,7 @@
 
 #include "i915_reg.h"
 #include "i915_utils.h"
+#include "intel_alpm.h"
 #include "intel_cx0_phy.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_ddi.h"
@@ -1998,3 +1999,37 @@ void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
 		intel_lt_phy_pll_disable(encoder);
 
 }
+
+/*
+ * According to HAS we need to enable MAC Transmitting LFPS in the "PHY Common
+ * Control 0" PIPE register in case of AUX Less ALPM is going to be used. This
+ * function is doing that and is called by link retrain sequence.
+ */
+void intel_xe3plpd_mac_transmit_lfps(struct intel_encoder *encoder,
+				     const struct intel_crtc_state *crtc_state)
+{
+	intel_wakeref_t wakeref;
+	int i;
+	u8 owned_lane_mask;
+
+	if (!intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder), crtc_state))
+		return;
+
+	owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
+
+	wakeref = intel_lt_phy_transaction_begin(encoder);
+
+	for (i = 0; i < 4; i++) {
+		int tx = i % 2 + 1;
+		u8 lane_mask = i < 2 ? INTEL_LT_PHY_LANE0 : INTEL_LT_PHY_LANE1;
+
+		if (!(owned_lane_mask & lane_mask))
+			continue;
+
+		intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_CMN_CTL(tx, 0),
+				 LT_PHY_CMN_LFPS_ENABLE,
+				 LT_PHY_CMN_LFPS_ENABLE, MB_WRITE_COMMITTED);
+	}
+
+	intel_lt_phy_transaction_end(encoder, wakeref);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index a538d4c69210..7391dd7252d7 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -38,6 +38,8 @@ void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state,
 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *crtc_state);
 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
+void intel_xe3plpd_mac_transmit_lfps(struct intel_encoder *encoder,
+				     const struct intel_crtc_state *crtc_state);
 
 #define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35)
 
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
index 9223487d764e..8a19b7cb59dc 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
@@ -36,6 +36,9 @@
 #define LT_PHY_TXY_CTL10_MAC(idx)	_MMIO(LT_PHY_TXY_CTL10(idx))
 #define  LT_PHY_TX_LANE_ENABLE		REG_BIT8(0)
 
+#define LT_PHY_CMN_CTL(idx, control)	(0x800 + (0x200 * ((idx) - 1)) + (control))
+#define  LT_PHY_CMN_LFPS_ENABLE		REG_BIT8(1)
+
 /* LT Phy Vendor Register */
 #define LT_PHY_VDR_0_CONFIG	0xC02
 #define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)
-- 
2.29.0

[PATCH v2 09/10] drm/i915/alpm: Replace is_edp() with alpm_is_possible()

[Animesh Manna]

Add a separate alpm_is_possible() which will check for both edp and dp.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 16 +++++++++++++---
 drivers/gpu/drm/i915/display/intel_alpm.h |  1 +
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 97813ce2d4d0..16fe66a75f05 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -41,6 +41,16 @@ bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
 		(crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));
 }
 
+bool intel_alpm_is_possible(struct intel_dp *intel_dp)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	return (DISPLAY_VER(display) >= 12 && intel_dp->alpm_dpcd) ||
+	       (DISPLAY_VER(display) >= 35 &&
+		intel_dp->lttpr_common_caps[DP_LTTPR_ALPM_CAPABILITIES -
+					    DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]);
+}
+
 void intel_alpm_init(struct intel_dp *intel_dp)
 {
 	u8 dpcd;
@@ -332,7 +342,7 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
 	if (intel_dp->alpm.sink_alpm_error)
 		return;
 
-	if (!intel_dp_is_edp(intel_dp))
+	if (!intel_alpm_is_possible(intel_dp))
 		return;
 
 	if (DISPLAY_VER(display) < 20)
@@ -483,7 +493,7 @@ void intel_alpm_pre_plane_update(struct intel_atomic_state *state,
 
 		intel_dp = enc_to_intel_dp(encoder);
 
-		if (!intel_dp_is_edp(intel_dp))
+		if (!intel_alpm_is_possible(intel_dp))
 			continue;
 
 		if (old_crtc_state->has_lobf) {
@@ -535,7 +545,7 @@ void intel_alpm_post_plane_update(struct intel_atomic_state *state,
 
 		intel_dp = enc_to_intel_dp(encoder);
 
-		if (intel_dp_is_edp(intel_dp)) {
+		if (intel_alpm_is_possible(intel_dp)) {
 			intel_alpm_enable_sink(intel_dp, crtc_state);
 			intel_alpm_configure(intel_dp, crtc_state);
 		}
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index 53599b464dea..0c9972faa2e0 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -15,6 +15,7 @@ struct intel_connector;
 struct intel_atomic_state;
 struct intel_crtc;
 
+bool intel_alpm_is_possible(struct intel_dp *intel_dp);
 void intel_alpm_init(struct intel_dp *intel_dp);
 bool intel_alpm_compute_params(struct intel_dp *intel_dp,
 			       struct intel_crtc_state *crtc_state);
-- 
2.29.0

[PATCH v2 10/10] drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf

[Animesh Manna]

For DP2.1, ALPM is optional and there can be scenario where panel replay
will be supported without ALPM. So decouple ALPM feaure by has_alpm flag
from related display features.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     |  7 +++---
 .../drm/i915/display/intel_display_types.h    |  2 ++
 drivers/gpu/drm/i915/display/intel_psr.c      | 23 ++++++++-----------
 drivers/gpu/drm/i915/display/intel_psr.h      |  1 -
 4 files changed, 15 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 16fe66a75f05..e1988f43cbb9 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -376,6 +376,8 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
 
 	crtc_state->has_lobf = (context_latency + guardband) >
 		(first_sdp_position + waketime_in_lines);
+
+	crtc_state->has_alpm = crtc_state->has_lobf;
 }
 
 static void lnl_alpm_configure(struct intel_dp *intel_dp,
@@ -385,8 +387,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	u32 alpm_ctl;
 
-	if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
-					  !crtc_state->has_lobf))
+	if (!crtc_state->has_alpm)
 		return;
 
 	mutex_lock(&intel_dp->alpm.lock);
@@ -510,7 +511,7 @@ void intel_alpm_enable_sink(struct intel_dp *intel_dp,
 {
 	u8 val;
 
-	if (!intel_psr_needs_alpm(intel_dp, crtc_state) && !crtc_state->has_lobf)
+	if (!crtc_state->has_alpm)
 		return;
 
 	val = DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 00600134bda0..0b60ada4b972 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1392,6 +1392,8 @@ struct intel_crtc_state {
 		u8 silence_period_sym_clocks;
 		u8 lfps_half_cycle_num_of_syms;
 	} alpm_state;
+
+	bool has_alpm;
 };
 
 enum intel_pipe_crc_source {
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 05014ffe3ce1..eeb4255b5e5e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1681,6 +1681,8 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
 	crtc_state->enable_psr2_su_region_et =
 		psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay);
 
+	crtc_state->has_alpm = intel_alpm_is_possible(intel_dp);
+
 	return true;
 
 unsupported:
@@ -1750,11 +1752,17 @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
 		return false;
 	}
 
+	if (intel_alpm_is_possible(intel_dp))
+		crtc_state->has_alpm = alpm_config_valid(intel_dp, crtc_state, true, true, false);
+
 	if (!intel_dp_is_edp(intel_dp))
 		return true;
 
 	/* Remaining checks are for eDP only */
 
+	if (!crtc_state->has_alpm)
+		return false;
+
 	if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A &&
 	    to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B)
 		return false;
@@ -1777,9 +1785,6 @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	if (!alpm_config_valid(intel_dp, crtc_state, true, true, false))
-		return false;
-
 	return true;
 }
 
@@ -4445,16 +4450,6 @@ void intel_psr_connector_debugfs_add(struct intel_connector *connector)
 				    connector, &i915_psr_status_fops);
 }
 
-bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state)
-{
-	/*
-	 * eDP Panel Replay uses always ALPM
-	 * PSR2 uses ALPM but PSR1 doesn't
-	 */
-	return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update ||
-					     crtc_state->has_panel_replay);
-}
-
 bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
 				   const struct intel_crtc_state *crtc_state)
 {
@@ -4470,7 +4465,7 @@ void intel_psr_compute_config_late(struct intel_dp *intel_dp,
 
 	if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state))
 		wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
-	else if (intel_psr_needs_alpm(intel_dp, crtc_state))
+	else if (crtc_state->has_alpm)
 		wake_lines = DISPLAY_VER(display) < 20 ?
 			     psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,
 						    crtc_state->alpm_state.fast_wake_lines) :
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 620b35928832..3cb4fa20e427 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -80,7 +80,6 @@ void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
 int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state);
 void intel_psr_connector_debugfs_add(struct intel_connector *connector);
 void intel_psr_debugfs_register(struct intel_display *display);
-bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state);
 bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
 				   const struct intel_crtc_state *crtc_state);
 void intel_psr_compute_config_late(struct intel_dp *intel_dp,
-- 
2.29.0

✗ i915.CI.BAT: failure for Enable DP2.1 alpm (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5852 bytes --]

== Series Details ==

Series: Enable DP2.1 alpm (rev2)
URL   : https://patchwork.freedesktop.org/series/156417/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_17480 -> Patchwork_156417v2
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_156417v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_156417v2, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v2/index.html

Participating hosts (45 -> 44)
------------------------------

  Additional (1): bat-arlh-3 
  Missing    (2): fi-snb-2520m bat-adls-6 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_156417v2:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_module_load@load:
    - bat-arlh-3:         NOTRUN -> [ABORT][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v2/bat-arlh-3/igt@i915_module_load@load.html
    - bat-twl-1:          [PASS][2] -> [ABORT][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17480/bat-twl-1/igt@i915_module_load@load.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v2/bat-twl-1/igt@i915_module_load@load.html
    - bat-adlp-6:         [PASS][4] -> [ABORT][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17480/bat-adlp-6/igt@i915_module_load@load.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v2/bat-adlp-6/igt@i915_module_load@load.html
    - bat-twl-2:          [PASS][6] -> [ABORT][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17480/bat-twl-2/igt@i915_module_load@load.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v2/bat-twl-2/igt@i915_module_load@load.html
    - bat-mtlp-9:         [PASS][8] -> [ABORT][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17480/bat-mtlp-9/igt@i915_module_load@load.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v2/bat-mtlp-9/igt@i915_module_load@load.html
    - bat-mtlp-8:         [PASS][10] -> [ABORT][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17480/bat-mtlp-8/igt@i915_module_load@load.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v2/bat-mtlp-8/igt@i915_module_load@load.html

  * igt@i915_selftest@live@dmabuf:
    - bat-mtlp-6:         [PASS][12] -> [INCOMPLETE][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17480/bat-mtlp-6/igt@i915_selftest@live@dmabuf.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v2/bat-mtlp-6/igt@i915_selftest@live@dmabuf.html

  
Known issues
------------

  Here are the changes found in Patchwork_156417v2 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@dmabuf@all-tests@dma_fence_chain:
    - fi-bsw-n3050:       [PASS][14] -> [ABORT][15] ([i915#12904]) +1 other test abort
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17480/fi-bsw-n3050/igt@dmabuf@all-tests@dma_fence_chain.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v2/fi-bsw-n3050/igt@dmabuf@all-tests@dma_fence_chain.html

  * igt@i915_selftest@live:
    - bat-mtlp-6:         [PASS][16] -> [INCOMPLETE][17] ([i915#15176])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17480/bat-mtlp-6/igt@i915_selftest@live.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v2/bat-mtlp-6/igt@i915_selftest@live.html

  * igt@i915_selftest@live@guc:
    - bat-adlp-11:        [PASS][18] -> [ABORT][19] ([i915#14365]) +1 other test abort
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17480/bat-adlp-11/igt@i915_selftest@live@guc.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v2/bat-adlp-11/igt@i915_selftest@live@guc.html

  
#### Possible fixes ####

  * igt@i915_selftest@live:
    - fi-glk-j4005:       [ABORT][20] -> [PASS][21] +1 other test pass
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17480/fi-glk-j4005/igt@i915_selftest@live.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v2/fi-glk-j4005/igt@i915_selftest@live.html

  * igt@i915_selftest@live@workarounds:
    - bat-dg2-14:         [DMESG-FAIL][22] ([i915#12061]) -> [PASS][23] +1 other test pass
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17480/bat-dg2-14/igt@i915_selftest@live@workarounds.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v2/bat-dg2-14/igt@i915_selftest@live@workarounds.html
    - bat-arls-6:         [DMESG-FAIL][24] ([i915#12061]) -> [PASS][25] +1 other test pass
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17480/bat-arls-6/igt@i915_selftest@live@workarounds.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v2/bat-arls-6/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904
  [i915#14365]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14365
  [i915#15176]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15176


Build changes
-------------

  * Linux: CI_DRM_17480 -> Patchwork_156417v2

  CI-20190529: 20190529
  CI_DRM_17480: 3d82a6cdc5241dbae65a59cf1197ff3bfd90ec2c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8605: 8605
  Patchwork_156417v2: 3d82a6cdc5241dbae65a59cf1197ff3bfd90ec2c @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v2/index.html

[-- Attachment #2: Type: text/html, Size: 6745 bytes --]

RE: [PATCH v2 01/10] drm/i915/alpm: Add dpcd definition for DP2.1 alpm capability

[Kandpal, Suraj]

> Subject: [PATCH v2 01/10] drm/i915/alpm: Add dpcd definition for DP2.1 alpm
> capability

*DPCD
*ALPM

Try to keep abbreviation in uppercase

> 
> Add required dpcd address which will be needed to enable DP2.1 alpm.

Diito 

Otherwise LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  include/drm/display/drm_dp.h | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index e4eebabab975..b4bacbcf130e 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -1512,6 +1512,8 @@
>  /* See DP_128B132B_SUPPORTED_LINK_RATES for values */
>  #define DP_PHY_REPEATER_128B132B_RATES			    0xf0007 /*
> 2.0 */
>  #define DP_PHY_REPEATER_EQ_DONE                             0xf0008 /* 2.0 E11 */
> +#define DP_LTTPR_ALPM_CAPABILITIES                          0xf0009 /* 2.1 */
> +#define DP_TOTAL_LTTPR_CNT                                  0xf000a /* 2.1 */
> 
>  enum drm_dp_phy {
>  	DP_PHY_DPRX,
> @@ -1691,7 +1693,7 @@ enum drm_dp_phy {
>  #define DP_DSC_BRANCH_CAP_SIZE		3
>  #define EDP_PSR_RECEIVER_CAP_SIZE	2
>  #define EDP_DISPLAY_CTL_CAP_SIZE	5
> -#define DP_LTTPR_COMMON_CAP_SIZE	8
> +#define DP_LTTPR_COMMON_CAP_SIZE	10
>  #define DP_LTTPR_PHY_CAP_SIZE		3
> 
>  #define DP_SDP_AUDIO_TIMESTAMP		0x01
> --
> 2.29.0

RE: [PATCH v2 03/10] drm/i915/alpm: Enable debugfs for DP2.1

[Kandpal, Suraj]

> Subject: [PATCH v2 03/10] drm/i915/alpm: Enable debugfs for DP2.1
> 
> Enable AlPM debug info through lobf debug info.
> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 639941e332f3..779718d0c8dd 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -541,9 +541,15 @@ void intel_alpm_lobf_debugfs_add(struct
> intel_connector *connector)
>  	struct intel_display *display = to_intel_display(connector);
>  	struct dentry *root = connector->base.debugfs_entry;
> 
> -	if (DISPLAY_VER(display) < 20 ||
> -	    connector->base.connector_type !=
> DRM_MODE_CONNECTOR_eDP)
> +	if (connector->base.connector_type ==
> DRM_MODE_CONNECTOR_DisplayPort) {
> +		if (DISPLAY_VER(display) < 35)
> +			return;
> +	} else if (connector->base.connector_type ==
> DRM_MODE_CONNECTOR_eDP) {
> +		if (DISPLAY_VER(display) < 20)
> +			return;
> +	} else {
>  		return;
> +	}

How about 
if (!((connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort && DISPLAY_VER(display) >= 35) ||
      (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP && DISPLAY_VER(display) >= 20)))
	return;
Regards,
Suraj Kandpal

> 
>  	debugfs_create_file("i915_edp_lobf_debug", 0644, root,
>  			    connector, &i915_edp_lobf_debug_fops);
> --
> 2.29.0

RE: [PATCH v2 08/10] drm/i915/alpm: Enable MAC Transmitting LFPS for LT phy

[Kandpal, Suraj]

> Subject: [PATCH v2 08/10] drm/i915/alpm: Enable MAC Transmitting LFPS for
> LT phy
> 
> Enable LT phy for transmitting LFPS during aux-less alpm.

Not really !
You are actually enabling MAC to transmit LFPS via LT PHY

> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  5 ++-
>  drivers/gpu/drm/i915/display/intel_lt_phy.c   | 35 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_lt_phy.h   |  2 ++
>  .../gpu/drm/i915/display/intel_lt_phy_regs.h  |  3 ++
>  4 files changed, 44 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 733ef4559131..f6450ebea2a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3781,7 +3781,10 @@ static void mtl_ddi_prepare_link_retrain(struct
> intel_dp *intel_dp,
>  	 *     ii. Enable MAC Transmits LFPS in the "PHY Common Control 0"
> PIPE
>  	 *         register
>  	 */
> -	intel_lnl_mac_transmit_lfps(encoder, crtc_state);
> +	if (HAS_LT_PHY(display))
> +		intel_xe3plpd_mac_transmit_lfps(encoder, crtc_state);
> +	else
> +		intel_lnl_mac_transmit_lfps(encoder, crtc_state);
>  }
> 
>  static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, diff --git
> a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index af48d6cde226..87659a9d9847 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -7,6 +7,7 @@
> 
>  #include "i915_reg.h"
>  #include "i915_utils.h"
> +#include "intel_alpm.h"
>  #include "intel_cx0_phy.h"
>  #include "intel_cx0_phy_regs.h"
>  #include "intel_ddi.h"
> @@ -1998,3 +1999,37 @@ void intel_xe3plpd_pll_disable(struct
> intel_encoder *encoder)
>  		intel_lt_phy_pll_disable(encoder);
> 
>  }
> +
> +/*
> + * According to HAS we need to enable MAC Transmitting LFPS in the "PHY
> +Common
> + * Control 0" PIPE register in case of AUX Less ALPM is going to be
> +used. This
> + * function is doing that and is called by link retrain sequence.
> + */
> +void intel_xe3plpd_mac_transmit_lfps(struct intel_encoder *encoder,
> +				     const struct intel_crtc_state *crtc_state) {
> +	intel_wakeref_t wakeref;
> +	int i;
> +	u8 owned_lane_mask;
> +
> +	if (!intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
> crtc_state))
> +		return;
> +
> +	owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
> +
> +	wakeref = intel_lt_phy_transaction_begin(encoder);
> +
> +	for (i = 0; i < 4; i++) {
> +		int tx = i % 2 + 1;
> +		u8 lane_mask = i < 2 ? INTEL_LT_PHY_LANE0 :
> INTEL_LT_PHY_LANE1;
> +
> +		if (!(owned_lane_mask & lane_mask))
> +			continue;
> +
> +		intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_CMN_CTL(tx,
> 0),
> +				 LT_PHY_CMN_LFPS_ENABLE,
> +				 LT_PHY_CMN_LFPS_ENABLE,
> MB_WRITE_COMMITTED);

All this loop not needed you have no dependency on the transmitter
LT_PHY_CMN_CTL0 is only one of its kind at address 0x800.
A simple lt_phy_rmw to enable LT_PHY_CMN_LFPS_ENABLE should work

> +	}
> +
> +	intel_lt_phy_transaction_end(encoder, wakeref); }
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index a538d4c69210..7391dd7252d7 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -38,6 +38,8 @@ void intel_lt_phy_pll_state_verify(struct
> intel_atomic_state *state,  void intel_xe3plpd_pll_enable(struct intel_encoder
> *encoder,
>  			      const struct intel_crtc_state *crtc_state);  void
> intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
> +void intel_xe3plpd_mac_transmit_lfps(struct intel_encoder *encoder,
> +				     const struct intel_crtc_state *crtc_state);
> 
>  #define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> index 9223487d764e..8a19b7cb59dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> @@ -36,6 +36,9 @@
>  #define LT_PHY_TXY_CTL10_MAC(idx)	_MMIO(LT_PHY_TXY_CTL10(idx))
>  #define  LT_PHY_TX_LANE_ENABLE		REG_BIT8(0)
> 
> +#define LT_PHY_CMN_CTL(idx, control)	(0x800 + (0x200 * ((idx) - 1)) +
> (control))

No need should only be 0x800
And name should be LT_PHY_CMN_CTL_0

Regards,
Suraj Kandpal

> +#define  LT_PHY_CMN_LFPS_ENABLE		REG_BIT8(1)
> +
>  /* LT Phy Vendor Register */
>  #define LT_PHY_VDR_0_CONFIG	0xC02
>  #define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)
> --
> 2.29.0

RE: [PATCH v2 10/10] drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf

[Kandpal, Suraj]

> Subject: [PATCH v2 10/10] drm/i915/alpm: Introduce has_alpm to decouple
> from pr/psr2/lobf
> 
> For DP2.1, ALPM is optional and there can be scenario where panel replay will
> be supported without ALPM. So decouple ALPM feaure by has_alpm flag from

Typo *feature

> related display features.
> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c     |  7 +++---
>  .../drm/i915/display/intel_display_types.h    |  2 ++
>  drivers/gpu/drm/i915/display/intel_psr.c      | 23 ++++++++-----------
>  drivers/gpu/drm/i915/display/intel_psr.h      |  1 -
>  4 files changed, 15 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 16fe66a75f05..e1988f43cbb9 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -376,6 +376,8 @@ void intel_alpm_lobf_compute_config(struct intel_dp
> *intel_dp,
> 
>  	crtc_state->has_lobf = (context_latency + guardband) >
>  		(first_sdp_position + waketime_in_lines);
> +
> +	crtc_state->has_alpm = crtc_state->has_lobf;
>  }
> 
>  static void lnl_alpm_configure(struct intel_dp *intel_dp, @@ -385,8 +387,7
> @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	u32 alpm_ctl;
> 
> -	if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp,
> crtc_state) &&
> -					  !crtc_state->has_lobf))
> +	if (!crtc_state->has_alpm)
>  		return;
> 
>  	mutex_lock(&intel_dp->alpm.lock);
> @@ -510,7 +511,7 @@ void intel_alpm_enable_sink(struct intel_dp
> *intel_dp,  {
>  	u8 val;
> 
> -	if (!intel_psr_needs_alpm(intel_dp, crtc_state) && !crtc_state-
> >has_lobf)
> +	if (!crtc_state->has_alpm)
>  		return;
> 
>  	val = DP_ALPM_ENABLE |
> DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 00600134bda0..0b60ada4b972 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1392,6 +1392,8 @@ struct intel_crtc_state {
>  		u8 silence_period_sym_clocks;
>  		u8 lfps_half_cycle_num_of_syms;
>  	} alpm_state;
> +
> +	bool has_alpm;
>  };
> 
>  enum intel_pipe_crc_source {
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 05014ffe3ce1..eeb4255b5e5e 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1681,6 +1681,8 @@ static bool intel_sel_update_config_valid(struct
> intel_dp *intel_dp,
>  	crtc_state->enable_psr2_su_region_et =
>  		psr2_su_region_et_valid(intel_dp, crtc_state-
> >has_panel_replay);
> 
> +	crtc_state->has_alpm = intel_alpm_is_possible(intel_dp);
> +
>  	return true;
> 
>  unsupported:
> @@ -1750,11 +1752,17 @@ _panel_replay_compute_config(struct intel_dp
> *intel_dp,
>  		return false;
>  	}
> 
> +	if (intel_alpm_is_possible(intel_dp))
> +		crtc_state->has_alpm = alpm_config_valid(intel_dp,
> crtc_state, true,
> +true, false);
> +
>  	if (!intel_dp_is_edp(intel_dp))
>  		return true;
> 
>  	/* Remaining checks are for eDP only */
> 
> +	if (!crtc_state->has_alpm)
> +		return false;

Why return false here didn't you state that ALPM is optional and PR can
Be supported without it.

Regards,
Suraj Kandpal

> +
>  	if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A &&
>  	    to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B)
>  		return false;
> @@ -1777,9 +1785,6 @@ _panel_replay_compute_config(struct intel_dp
> *intel_dp,
>  		return false;
>  	}
> 
> -	if (!alpm_config_valid(intel_dp, crtc_state, true, true, false))
> -		return false;
> -
>  	return true;
>  }
> 
> @@ -4445,16 +4450,6 @@ void intel_psr_connector_debugfs_add(struct
> intel_connector *connector)
>  				    connector, &i915_psr_status_fops);  }
> 
> -bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct
> intel_crtc_state *crtc_state) -{
> -	/*
> -	 * eDP Panel Replay uses always ALPM
> -	 * PSR2 uses ALPM but PSR1 doesn't
> -	 */
> -	return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update ||
> -					     crtc_state->has_panel_replay);
> -}
> -
>  bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
>  				   const struct intel_crtc_state *crtc_state)  {
> @@ -4470,7 +4465,7 @@ void intel_psr_compute_config_late(struct
> intel_dp *intel_dp,
> 
>  	if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state))
>  		wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
> -	else if (intel_psr_needs_alpm(intel_dp, crtc_state))
> +	else if (crtc_state->has_alpm)
>  		wake_lines = DISPLAY_VER(display) < 20 ?
>  			     psr2_block_count_lines(crtc_state-
> >alpm_state.io_wake_lines,
>  						    crtc_state-
> >alpm_state.fast_wake_lines) :
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index 620b35928832..3cb4fa20e427 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -80,7 +80,6 @@ void intel_psr_trigger_frame_change_event(struct
> intel_dsb *dsb,  int intel_psr_min_set_context_latency(const struct
> intel_crtc_state *crtc_state);  void intel_psr_connector_debugfs_add(struct
> intel_connector *connector);  void intel_psr_debugfs_register(struct
> intel_display *display); -bool intel_psr_needs_alpm(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state);  bool
> intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
>  				   const struct intel_crtc_state *crtc_state);
> void intel_psr_compute_config_late(struct intel_dp *intel_dp,
> --
> 2.29.0

RE: [PATCH v2 04/10] drm/i915/alpm: Refactor Auxless wake time calculation

[Kandpal, Suraj]

> Subject: [PATCH v2 04/10] drm/i915/alpm: Refactor Auxless wake time
> calculation
> 
> Divide the auxless wake time calculation in parts which will help later to add
> Xe3p related modification.
> 
> v1: Initial version.

No need for this you can start off with v2 directly
Same for all patches where this has occured

> v2: Refactor first existing calculation. [Jani]
> 

Add Bspec link

> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 37 ++++++++++++++++-------
>  1 file changed, 26 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 779718d0c8dd..8d07455a62c2 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -85,6 +85,26 @@ static int get_lfps_half_cycle_clocks(const struct
> intel_crtc_state *crtc_state)
>  		1000 / (2 * LFPS_CYCLE_COUNT);
>  }
> 
> +static int get_tphy2_p2_to_p0(struct intel_dp *intel_dp) {
> +	return 12 * 1000;
> +}
> +
> +static int get_establishment_period(struct intel_dp *intel_dp,
> +				    const struct intel_crtc_state *crtc_state) {
> +	int port_clock = crtc_state->port_clock;
> +	int t1 = 50 * 1000;
> +	int tps4 = (252 * 10);

Where did this * 10 come from?

> +	long tml_phy_lock = 1000 * 1000 * tps4 / port_clock / 10;

Why the extra /10 required here also if you had not multiplied tps4 with 10 then this wouldn't be required
You also removed the comment telling us portclock need to be in 10Kb/s

> +	int tcds, establishment_period;
> +
> +	tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * tml_phy_lock;
> +	establishment_period = (SILENCE_PERIOD_TIME + t1 + tcds);
> +
> +	return establishment_period;
> +}
> +
>  /*
>   * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+
>   * tSilence, Max+ tPHY Establishment + tCDS) / tline) @@ -104,19 +124,14
> @@ static int get_lfps_half_cycle_clocks(const struct intel_crtc_state
> *crtc_state)
>   * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )
>   * TPS4 Length = 252 Symbols
>   */
> -static int _lnl_compute_aux_less_wake_time(const struct intel_crtc_state
> *crtc_state)
> +static int _lnl_compute_aux_less_wake_time(struct intel_dp *intel_dp,
> +					   const struct intel_crtc_state

I don’t see any justified reason to send intel_dp here

Regards,
Suraj Kandpal

> *crtc_state)
>  {
> -	int tphy2_p2_to_p0 = 12 * 1000;
> -	int t1 = 50 * 1000;
> -	int tps4 = 252;
> -	/* port_clock is link rate in 10kbit/s units */
> -	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock;
> -	int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
> -	int t2 = num_ml_phy_lock * tml_phy_lock;
> -	int tcds = 1 * t2;
> +	int tphy2_p2_to_p0 = get_tphy2_p2_to_p0(intel_dp);
> +	int establishment_period = get_establishment_period(intel_dp,
> +crtc_state);
> 
>  	return DIV_ROUND_UP(tphy2_p2_to_p0 +
> get_lfps_cycle_time(crtc_state) +
> -			    SILENCE_PERIOD_TIME + t1 + tcds, 1000);
> +			    establishment_period, 1000);
>  }
> 
>  static int
> @@ -128,7 +143,7 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp
> *intel_dp,
>  		lfps_half_cycle;
> 
>  	aux_less_wake_time =
> -		_lnl_compute_aux_less_wake_time(crtc_state);
> +		_lnl_compute_aux_less_wake_time(intel_dp, crtc_state);
>  	aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state-
> >hw.adjusted_mode,
>  						       aux_less_wake_time);
>  	silence_period = get_silence_period_symbols(crtc_state);
> --
> 2.29.0

RE: [PATCH v2 04/10] drm/i915/alpm: Refactor Auxless wake time calculation

[Manna, Animesh]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Friday, November 7, 2025 9:31 AM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org; dri-
> devel@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>; Hogander, Jouni
> <jouni.hogander@intel.com>
> Subject: RE: [PATCH v2 04/10] drm/i915/alpm: Refactor Auxless wake time
> calculation
> 
> > Subject: [PATCH v2 04/10] drm/i915/alpm: Refactor Auxless wake time
> > calculation
> >
> > Divide the auxless wake time calculation in parts which will help
> > later to add Xe3p related modification.
> >
> > v1: Initial version.
> 
> No need for this you can start off with v2 directly Same for all patches where
> this has occured
> 
> > v2: Refactor first existing calculation. [Jani]
> >
> 
> Add Bspec link
> 
> > Cc: Jouni Högander <jouni.hogander@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_alpm.c | 37
> > ++++++++++++++++-------
> >  1 file changed, 26 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index 779718d0c8dd..8d07455a62c2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -85,6 +85,26 @@ static int get_lfps_half_cycle_clocks(const struct
> > intel_crtc_state *crtc_state)
> >  		1000 / (2 * LFPS_CYCLE_COUNT);
> >  }
> >
> > +static int get_tphy2_p2_to_p0(struct intel_dp *intel_dp) {
> > +	return 12 * 1000;
> > +}
> > +
> > +static int get_establishment_period(struct intel_dp *intel_dp,
> > +				    const struct intel_crtc_state *crtc_state) {
> > +	int port_clock = crtc_state->port_clock;
> > +	int t1 = 50 * 1000;
> > +	int tps4 = (252 * 10);
> 
> Where did this * 10 come from?

The Link Rate Divider (Rate Div) is 10 for 8b/10b and 32 128b/132b. Also please check the next patch for more clarity.

> 
> > +	long tml_phy_lock = 1000 * 1000 * tps4 / port_clock / 10;
> 
> Why the extra /10 required here also if you had not multiplied tps4 with 10
> then this wouldn't be required You also removed the comment telling us
> portclock need to be in 10Kb/s

Divide by 10 always needed due to unit size of 10kb/sec, earlier both negated but for 128b/132b mode rate_div is 32. It will be more clear with next patch where added the changes for 128b/132b.

> 
> > +	int tcds, establishment_period;
> > +
> > +	tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * tml_phy_lock;
> > +	establishment_period = (SILENCE_PERIOD_TIME + t1 + tcds);
> > +
> > +	return establishment_period;
> > +}
> > +
> >  /*
> >   * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+
> >   * tSilence, Max+ tPHY Establishment + tCDS) / tline) @@ -104,19
> > +124,14 @@ static int get_lfps_half_cycle_clocks(const struct
> > intel_crtc_state
> > *crtc_state)
> >   * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )
> >   * TPS4 Length = 252 Symbols
> >   */
> > -static int _lnl_compute_aux_less_wake_time(const struct
> > intel_crtc_state
> > *crtc_state)
> > +static int _lnl_compute_aux_less_wake_time(struct intel_dp *intel_dp,
> > +					   const struct intel_crtc_state
> 
> I don’t see any justified reason to send intel_dp here

Its needed in next patch, fix the function prototype here.

Regards,
Animesh

> 
> Regards,
> Suraj Kandpal
> 
> > *crtc_state)
> >  {
> > -	int tphy2_p2_to_p0 = 12 * 1000;
> > -	int t1 = 50 * 1000;
> > -	int tps4 = 252;
> > -	/* port_clock is link rate in 10kbit/s units */
> > -	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock;
> > -	int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
> > -	int t2 = num_ml_phy_lock * tml_phy_lock;
> > -	int tcds = 1 * t2;
> > +	int tphy2_p2_to_p0 = get_tphy2_p2_to_p0(intel_dp);
> > +	int establishment_period = get_establishment_period(intel_dp,
> > +crtc_state);
> >
> >  	return DIV_ROUND_UP(tphy2_p2_to_p0 +
> > get_lfps_cycle_time(crtc_state) +
> > -			    SILENCE_PERIOD_TIME + t1 + tcds, 1000);
> > +			    establishment_period, 1000);
> >  }
> >
> >  static int
> > @@ -128,7 +143,7 @@ _lnl_compute_aux_less_alpm_params(struct
> intel_dp
> > *intel_dp,
> >  		lfps_half_cycle;
> >
> >  	aux_less_wake_time =
> > -		_lnl_compute_aux_less_wake_time(crtc_state);
> > +		_lnl_compute_aux_less_wake_time(intel_dp, crtc_state);
> >  	aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state-
> > >hw.adjusted_mode,
> >  						       aux_less_wake_time);
> >  	silence_period = get_silence_period_symbols(crtc_state);
> > --
> > 2.29.0

RE: [PATCH v2 10/10] drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf

[Manna, Animesh]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Friday, November 7, 2025 9:19 AM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org; dri-
> devel@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>; Hogander, Jouni
> <jouni.hogander@intel.com>
> Subject: RE: [PATCH v2 10/10] drm/i915/alpm: Introduce has_alpm to
> decouple from pr/psr2/lobf
> 
> > Subject: [PATCH v2 10/10] drm/i915/alpm: Introduce has_alpm to
> > decouple from pr/psr2/lobf
> >
> > For DP2.1, ALPM is optional and there can be scenario where panel
> > replay will be supported without ALPM. So decouple ALPM feaure by
> > has_alpm flag from
> 
> Typo *feature
> 
> > related display features.
> >
> > Cc: Jouni Högander <jouni.hogander@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_alpm.c     |  7 +++---
> >  .../drm/i915/display/intel_display_types.h    |  2 ++
> >  drivers/gpu/drm/i915/display/intel_psr.c      | 23 ++++++++-----------
> >  drivers/gpu/drm/i915/display/intel_psr.h      |  1 -
> >  4 files changed, 15 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index 16fe66a75f05..e1988f43cbb9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -376,6 +376,8 @@ void intel_alpm_lobf_compute_config(struct
> > intel_dp *intel_dp,
> >
> >  	crtc_state->has_lobf = (context_latency + guardband) >
> >  		(first_sdp_position + waketime_in_lines);
> > +
> > +	crtc_state->has_alpm = crtc_state->has_lobf;
> >  }
> >
> >  static void lnl_alpm_configure(struct intel_dp *intel_dp, @@ -385,8
> > +387,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
> >  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >  	u32 alpm_ctl;
> >
> > -	if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp,
> > crtc_state) &&
> > -					  !crtc_state->has_lobf))
> > +	if (!crtc_state->has_alpm)
> >  		return;
> >
> >  	mutex_lock(&intel_dp->alpm.lock);
> > @@ -510,7 +511,7 @@ void intel_alpm_enable_sink(struct intel_dp
> > *intel_dp,  {
> >  	u8 val;
> >
> > -	if (!intel_psr_needs_alpm(intel_dp, crtc_state) && !crtc_state-
> > >has_lobf)
> > +	if (!crtc_state->has_alpm)
> >  		return;
> >
> >  	val = DP_ALPM_ENABLE |
> > DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 00600134bda0..0b60ada4b972 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1392,6 +1392,8 @@ struct intel_crtc_state {
> >  		u8 silence_period_sym_clocks;
> >  		u8 lfps_half_cycle_num_of_syms;
> >  	} alpm_state;
> > +
> > +	bool has_alpm;
> >  };
> >
> >  enum intel_pipe_crc_source {
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 05014ffe3ce1..eeb4255b5e5e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1681,6 +1681,8 @@ static bool intel_sel_update_config_valid(struct
> > intel_dp *intel_dp,
> >  	crtc_state->enable_psr2_su_region_et =
> >  		psr2_su_region_et_valid(intel_dp, crtc_state-
> > >has_panel_replay);
> >
> > +	crtc_state->has_alpm = intel_alpm_is_possible(intel_dp);
> > +
> >  	return true;
> >
> >  unsupported:
> > @@ -1750,11 +1752,17 @@ _panel_replay_compute_config(struct intel_dp
> > *intel_dp,
> >  		return false;
> >  	}
> >
> > +	if (intel_alpm_is_possible(intel_dp))
> > +		crtc_state->has_alpm = alpm_config_valid(intel_dp,
> > crtc_state, true,
> > +true, false);
> > +
> >  	if (!intel_dp_is_edp(intel_dp))
> >  		return true;
> >
> >  	/* Remaining checks are for eDP only */
> >
> > +	if (!crtc_state->has_alpm)
> > +		return false;
> 
> Why return false here didn't you state that ALPM is optional and PR can Be
> supported without it.

This check is for EDP and ALPM is mandatory for EDP-PR.

Regards,
Animesh

> 
> Regards,
> Suraj Kandpal
> 
> > +
> >  	if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A &&
> >  	    to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B)
> >  		return false;
> > @@ -1777,9 +1785,6 @@ _panel_replay_compute_config(struct intel_dp
> > *intel_dp,
> >  		return false;
> >  	}
> >
> > -	if (!alpm_config_valid(intel_dp, crtc_state, true, true, false))
> > -		return false;
> > -
> >  	return true;
> >  }
> >
> > @@ -4445,16 +4450,6 @@ void intel_psr_connector_debugfs_add(struct
> > intel_connector *connector)
> >  				    connector, &i915_psr_status_fops);  }
> >
> > -bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct
> > intel_crtc_state *crtc_state) -{
> > -	/*
> > -	 * eDP Panel Replay uses always ALPM
> > -	 * PSR2 uses ALPM but PSR1 doesn't
> > -	 */
> > -	return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update ||
> > -					     crtc_state->has_panel_replay);
> > -}
> > -
> >  bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
> >  				   const struct intel_crtc_state *crtc_state)  {
> @@ -4470,7
> > +4465,7 @@ void intel_psr_compute_config_late(struct
> > intel_dp *intel_dp,
> >
> >  	if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state))
> >  		wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
> > -	else if (intel_psr_needs_alpm(intel_dp, crtc_state))
> > +	else if (crtc_state->has_alpm)
> >  		wake_lines = DISPLAY_VER(display) < 20 ?
> >  			     psr2_block_count_lines(crtc_state-
> > >alpm_state.io_wake_lines,
> >  						    crtc_state-
> > >alpm_state.fast_wake_lines) :
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > b/drivers/gpu/drm/i915/display/intel_psr.h
> > index 620b35928832..3cb4fa20e427 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > @@ -80,7 +80,6 @@ void intel_psr_trigger_frame_change_event(struct
> > intel_dsb *dsb,  int intel_psr_min_set_context_latency(const struct
> > intel_crtc_state *crtc_state);  void
> > intel_psr_connector_debugfs_add(struct
> > intel_connector *connector);  void intel_psr_debugfs_register(struct
> > intel_display *display); -bool intel_psr_needs_alpm(struct intel_dp
> > *intel_dp, const struct intel_crtc_state *crtc_state);  bool
> > intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
> >  				   const struct intel_crtc_state *crtc_state);
> void
> > intel_psr_compute_config_late(struct intel_dp *intel_dp,
> > --
> > 2.29.0

Re: [PATCH v2 02/10] drm/i915/alpm: alpm_init() for DP2.1

[Jani Nikula]

On Tue, 04 Nov 2025, Animesh Manna <animesh.manna@intel.com> wrote:
> Initialize alpm for DP2.1 and separate out alpm mutex-init
> from alpm-init.
>
> v1: Initial version.
> v2: Separate out mutex-init. [Jani]

Under no circumstances should you have two places and code paths to
initialize a mutex.

I think you need two or three functions, one for initializing the mutex
(and potentially other similar stuff), one for dynamic initialization
for eDP and one for DP. Don't sprinkle the display version checks all
over the place.

BR,
Jani.

>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c |  1 -
>  drivers/gpu/drm/i915/display/intel_dp.c   | 11 ++++++++++-
>  2 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 6372f533f65b..639941e332f3 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -49,7 +49,6 @@ void intel_alpm_init(struct intel_dp *intel_dp)
>  		return;
>  
>  	intel_dp->alpm_dpcd = dpcd;
> -	mutex_init(&intel_dp->alpm.lock);
>  }
>  
>  static int get_silence_period_symbols(const struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0ec82fcbcf48..f995a98df2c3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6074,8 +6074,12 @@ intel_dp_detect(struct drm_connector *_connector,
>  	if (ret == 1)
>  		connector->base.epoch_counter++;
>  
> -	if (!intel_dp_is_edp(intel_dp))
> +	if (!intel_dp_is_edp(intel_dp)) {
> +		if (DISPLAY_VER(display) >= 35)
> +			intel_alpm_init(intel_dp);
> +
>  		intel_psr_init_dpcd(intel_dp);
> +	}
>  
>  	intel_dp_detect_dsc_caps(intel_dp, connector);
>  
> @@ -6717,6 +6721,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
>  	intel_hpd_enable_detection(encoder);
>  
>  	intel_alpm_init(intel_dp);
> +	if (intel_dp->alpm_dpcd)
> +		mutex_init(&intel_dp->alpm.lock);
>  
>  	/* Cache DPCD and EDID for edp. */
>  	has_dpcd = intel_edp_init_dpcd(intel_dp, connector);
> @@ -6932,6 +6938,9 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
>  
>  	intel_psr_init(intel_dp);
>  
> +	if (DISPLAY_VER(display) >= 35)
> +		mutex_init(&intel_dp->alpm.lock);
> +
>  	return true;
>  
>  fail:

-- 
Jani Nikula, Intel

Re: [PATCH v2 03/10] drm/i915/alpm: Enable debugfs for DP2.1

[Jani Nikula]

On Tue, 04 Nov 2025, Animesh Manna <animesh.manna@intel.com> wrote:
> Enable AlPM debug info through lobf debug info.
>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 639941e332f3..779718d0c8dd 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -541,9 +541,15 @@ void intel_alpm_lobf_debugfs_add(struct intel_connector *connector)
>  	struct intel_display *display = to_intel_display(connector);
>  	struct dentry *root = connector->base.debugfs_entry;
>  
> -	if (DISPLAY_VER(display) < 20 ||
> -	    connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
> +	if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
> +		if (DISPLAY_VER(display) < 35)
> +			return;
> +	} else if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
> +		if (DISPLAY_VER(display) < 20)
> +			return;
> +	} else {
>  		return;
> +	}

These are the same conditions that you're sprinkling all over the place
in the previous patch, and basically boil down to "does the connector
support alpm?"

BR,
Jani.


>  
>  	debugfs_create_file("i915_edp_lobf_debug", 0644, root,
>  			    connector, &i915_edp_lobf_debug_fops);

-- 
Jani Nikula, Intel

RE: [PATCH v2 04/10] drm/i915/alpm: Refactor Auxless wake time calculation

[Jani Nikula]

On Fri, 07 Nov 2025, "Manna, Animesh" <animesh.manna@intel.com> wrote:
>> -----Original Message-----
>> From: Kandpal, Suraj <suraj.kandpal@intel.com>
>> Sent: Friday, November 7, 2025 9:31 AM
>> To: Manna, Animesh <animesh.manna@intel.com>; intel-
>> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org; dri-
>> devel@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>; Manna, Animesh
>> <animesh.manna@intel.com>; Hogander, Jouni
>> <jouni.hogander@intel.com>
>> Subject: RE: [PATCH v2 04/10] drm/i915/alpm: Refactor Auxless wake time
>> calculation
>> 
>> > Subject: [PATCH v2 04/10] drm/i915/alpm: Refactor Auxless wake time
>> > calculation
>> >
>> > Divide the auxless wake time calculation in parts which will help
>> > later to add Xe3p related modification.
>> >
>> > v1: Initial version.
>> 
>> No need for this you can start off with v2 directly Same for all patches where
>> this has occured
>> 
>> > v2: Refactor first existing calculation. [Jani]
>> >
>> 
>> Add Bspec link
>> 
>> > Cc: Jouni Högander <jouni.hogander@intel.com>
>> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_alpm.c | 37
>> > ++++++++++++++++-------
>> >  1 file changed, 26 insertions(+), 11 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
>> > b/drivers/gpu/drm/i915/display/intel_alpm.c
>> > index 779718d0c8dd..8d07455a62c2 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
>> > @@ -85,6 +85,26 @@ static int get_lfps_half_cycle_clocks(const struct
>> > intel_crtc_state *crtc_state)
>> >  		1000 / (2 * LFPS_CYCLE_COUNT);
>> >  }
>> >
>> > +static int get_tphy2_p2_to_p0(struct intel_dp *intel_dp) {
>> > +	return 12 * 1000;
>> > +}
>> > +
>> > +static int get_establishment_period(struct intel_dp *intel_dp,
>> > +				    const struct intel_crtc_state *crtc_state) {
>> > +	int port_clock = crtc_state->port_clock;
>> > +	int t1 = 50 * 1000;
>> > +	int tps4 = (252 * 10);
>> 
>> Where did this * 10 come from?
>
> The Link Rate Divider (Rate Div) is 10 for 8b/10b and 32
> 128b/132b. Also please check the next patch for more clarity.

Please separate pure code movement and changes like this.

git show --color-moved on the commit should give you a nice idea what
code movement looks like. It's a breeze to review when very few things
change during code movement.

BR,
Jani.



>
>> 
>> > +	long tml_phy_lock = 1000 * 1000 * tps4 / port_clock / 10;
>> 
>> Why the extra /10 required here also if you had not multiplied tps4 with 10
>> then this wouldn't be required You also removed the comment telling us
>> portclock need to be in 10Kb/s
>
> Divide by 10 always needed due to unit size of 10kb/sec, earlier both negated but for 128b/132b mode rate_div is 32. It will be more clear with next patch where added the changes for 128b/132b.
>
>> 
>> > +	int tcds, establishment_period;
>> > +
>> > +	tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * tml_phy_lock;
>> > +	establishment_period = (SILENCE_PERIOD_TIME + t1 + tcds);
>> > +
>> > +	return establishment_period;
>> > +}
>> > +
>> >  /*
>> >   * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+
>> >   * tSilence, Max+ tPHY Establishment + tCDS) / tline) @@ -104,19
>> > +124,14 @@ static int get_lfps_half_cycle_clocks(const struct
>> > intel_crtc_state
>> > *crtc_state)
>> >   * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )
>> >   * TPS4 Length = 252 Symbols
>> >   */
>> > -static int _lnl_compute_aux_less_wake_time(const struct
>> > intel_crtc_state
>> > *crtc_state)
>> > +static int _lnl_compute_aux_less_wake_time(struct intel_dp *intel_dp,
>> > +					   const struct intel_crtc_state
>> 
>> I don’t see any justified reason to send intel_dp here
>
> Its needed in next patch, fix the function prototype here.
>
> Regards,
> Animesh
>
>> 
>> Regards,
>> Suraj Kandpal
>> 
>> > *crtc_state)
>> >  {
>> > -	int tphy2_p2_to_p0 = 12 * 1000;
>> > -	int t1 = 50 * 1000;
>> > -	int tps4 = 252;
>> > -	/* port_clock is link rate in 10kbit/s units */
>> > -	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock;
>> > -	int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
>> > -	int t2 = num_ml_phy_lock * tml_phy_lock;
>> > -	int tcds = 1 * t2;
>> > +	int tphy2_p2_to_p0 = get_tphy2_p2_to_p0(intel_dp);
>> > +	int establishment_period = get_establishment_period(intel_dp,
>> > +crtc_state);
>> >
>> >  	return DIV_ROUND_UP(tphy2_p2_to_p0 +
>> > get_lfps_cycle_time(crtc_state) +
>> > -			    SILENCE_PERIOD_TIME + t1 + tcds, 1000);
>> > +			    establishment_period, 1000);
>> >  }
>> >
>> >  static int
>> > @@ -128,7 +143,7 @@ _lnl_compute_aux_less_alpm_params(struct
>> intel_dp
>> > *intel_dp,
>> >  		lfps_half_cycle;
>> >
>> >  	aux_less_wake_time =
>> > -		_lnl_compute_aux_less_wake_time(crtc_state);
>> > +		_lnl_compute_aux_less_wake_time(intel_dp, crtc_state);
>> >  	aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state-
>> > >hw.adjusted_mode,
>> >  						       aux_less_wake_time);
>> >  	silence_period = get_silence_period_symbols(crtc_state);
>> > --
>> > 2.29.0
>

-- 
Jani Nikula, Intel