From: Keith Packard <keithp@keithp.com>
To: Chris Wilson <chris@chris-wilson.co.uk>,
Jesse Barnes <jbarnes@virtuousgeek.org>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: prefer wide & slow to fast & narrow in DP configs
Date: Fri, 22 Jun 2012 10:40:22 -0700 [thread overview]
Message-ID: <86a9zvqm7t.fsf@sumi.keithp.com> (raw)
In-Reply-To: <1340355948_38587@CP5-2952>
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Chris Wilson <chris@chris-wilson.co.uk> writes:
> On Thu, 21 Jun 2012 18:13:19 -0700, Keith Packard <keithp@keithp.com> wrote:
> It was structured to minimise lane count because certain chipsets did
> not wire up all the lanes, right? Is that still relevant as we are using
> the advertised max_lane_count from the DPCD now?
We've always used the max_lane_count from dpcd; has there been some
recent change that fixed usage of that? What I recall is one acer laptop
that advertised 4 lanes but had only wired up two of them.
--
keith.packard@intel.com
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next prev parent reply other threads:[~2012-06-22 17:40 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-21 22:13 [PATCH] drm/i915: prefer wide & slow to fast & narrow in DP configs Jesse Barnes
2012-06-22 1:13 ` Keith Packard
2012-06-22 9:05 ` Chris Wilson
2012-06-22 14:21 ` Adam Jackson
2012-06-22 16:29 ` Jesse Barnes
2012-06-22 17:42 ` Keith Packard
2012-06-22 17:40 ` Keith Packard [this message]
2012-06-22 17:53 ` Chris Wilson
2012-07-04 7:42 ` Daniel Vetter
2012-08-06 0:12 ` [3.2.y, 3.4.y, 3.5.y] " Jonathan Nieder
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