[PATCH v2 00/13] Enable/Disable DC balance along with VRR DSB

[PATCH v2 00/13] Enable/Disable DC balance along with VRR DSB

[Mitul Golani]

Control DC Balance Adjustment bit to accomodate changes along
with VRR DSB implementation.

Mitul Golani (7):
  drm/i915/display: Add source param for dc balance
  drm/i915/vrr: Add enable/disable calls for DC Balance
  drm/i915/vrr: Add compute config for DC balance params
  drm/i915/vrr: Add state dump for dc balance params
  drm/i915/vrr: Add state checker for dc balance params
  drm/i915/display: Prepare state checker for dc balance enable
  drm/i915/vrr: enable dc balance bit

Ville Syrjälä (6):
  drm/i915/vrr: Refactor vmin/vmax stuff
  drm/i915/vrr: Add functions to read out vmin/vmax stuff
  drm/i915: Extract vrr_vblank_start()
  drm/i915/vrr: Implement vblank evasion with DC balancing
  drm/i915/dsb: Add pipedmc dc balance enable/disable
  drm/i915/vrr: Pause DC balancing for DSB commits

 .../drm/i915/display/intel_crtc_state_dump.c  |   9 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  21 ++
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_types.h    |   7 +
 drivers/gpu/drm/i915/display/intel_dmc.c      |  24 ++
 drivers/gpu/drm/i915/display/intel_dmc.h      |   5 +
 drivers/gpu/drm/i915/display/intel_dmc_regs.h |  80 +++++++
 drivers/gpu/drm/i915/display/intel_dsb.c      |  31 ++-
 drivers/gpu/drm/i915/display/intel_vblank.c   |  33 ++-
 drivers/gpu/drm/i915/display/intel_vrr.c      | 210 +++++++++++++++---
 drivers/gpu/drm/i915/display/intel_vrr.h      |   5 +
 drivers/gpu/drm/i915/display/intel_vrr_regs.h |  66 ++++++
 12 files changed, 452 insertions(+), 40 deletions(-)

-- 
2.48.1

[PATCH v2 01/13] drm/i915/vrr: Refactor vmin/vmax stuff

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Refactor vmin/vmax functions for better computation.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 41 +++++++++++-------------
 1 file changed, 19 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index c6565baf815a..adfd231eb578 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -146,37 +146,41 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat
 		return crtc_state->vrr.pipeline_full + crtc_state->framestart_delay + 1;
 }
 
-int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
+static int intel_vrr_vtotal(const struct intel_crtc_state *crtc_state, int vmin_vmax)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 
-	/* Min vblank actually determined by flipline */
 	if (DISPLAY_VER(display) >= 13)
-		return intel_vrr_vmin_flipline(crtc_state);
+		return vmin_vmax;
 	else
-		return intel_vrr_vmin_flipline(crtc_state) +
-			intel_vrr_real_vblank_delay(crtc_state);
+		return vmin_vmax + intel_vrr_real_vblank_delay(crtc_state);
 }
 
-int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
+static int intel_vrr_vblank_start(const struct intel_crtc_state *crtc_state,
+				  int vmin_vmax)
 {
-	struct intel_display *display = to_intel_display(crtc_state);
+	return intel_vrr_vtotal(crtc_state, vmin_vmax) -
+			intel_vrr_vblank_exit_length(crtc_state);
+}
 
-	if (DISPLAY_VER(display) >= 13)
-		return crtc_state->vrr.vmax;
-	else
-		return crtc_state->vrr.vmax +
-			intel_vrr_real_vblank_delay(crtc_state);
+int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
+{
+	return intel_vrr_vtotal(crtc_state, intel_vrr_vmin_flipline(crtc_state));
+}
+
+int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
+{
+	return intel_vrr_vtotal(crtc_state, crtc_state->vrr.vmax);
 }
 
 int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
 {
-	return intel_vrr_vmin_vtotal(crtc_state) - intel_vrr_vblank_exit_length(crtc_state);
+	return intel_vrr_vblank_start(crtc_state, intel_vrr_vmin_flipline(crtc_state));
 }
 
 int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
 {
-	return intel_vrr_vmax_vtotal(crtc_state) - intel_vrr_vblank_exit_length(crtc_state);
+	return intel_vrr_vblank_start(crtc_state, crtc_state->vrr.vmax);
 }
 
 static bool
@@ -257,14 +261,7 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
 static
 int intel_vrr_fixed_rr_vtotal(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_display *display = to_intel_display(crtc_state);
-	int crtc_vtotal = crtc_state->hw.adjusted_mode.crtc_vtotal;
-
-	if (DISPLAY_VER(display) >= 13)
-		return crtc_vtotal;
-	else
-		return crtc_vtotal -
-			intel_vrr_real_vblank_delay(crtc_state);
+	return intel_vrr_vtotal(crtc_state, crtc_state->hw.adjusted_mode.crtc_vtotal);
 }
 
 static
-- 
2.48.1

[PATCH v2 02/13] drm/i915/vrr: Add functions to read out vmin/vmax stuff

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Calculate delayed vblank start position with the help of added
vmin/vmax stuff for next frame and final computation.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c      | 57 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h      |  5 ++
 drivers/gpu/drm/i915/display/intel_vrr_regs.h | 44 ++++++++++++++
 3 files changed, 106 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index adfd231eb578..1c0eaa08927b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -746,3 +746,60 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 	if (crtc_state->vrr.enable)
 		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 }
+
+int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp;
+
+	tmp = intel_de_read(display,
+			    TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(display, cpu_transcoder));
+
+	if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0)
+		return -1;
+
+	return intel_vrr_vblank_start(crtc_state,
+				      REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_MASK, tmp) + 1);
+}
+
+int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp;
+
+	tmp = intel_de_read(display,
+			    TRANS_VRR_DCB_ADJ_VMAX_CFG(display, cpu_transcoder));
+
+	if (REG_FIELD_GET(VRR_DCB_ADJ_VMAX_CNT_MASK, tmp) == 0)
+		return -1;
+
+	return intel_vrr_vblank_start(crtc_state,
+				      REG_FIELD_GET(VRR_DCB_ADJ_VMAX_MASK, tmp) + 1);
+}
+
+int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp;
+
+	tmp = intel_de_read(display,
+			    TRANS_VRR_FLIPLINE_DCB(display, cpu_transcoder));
+
+	return intel_vrr_vblank_start(crtc_state,
+				      REG_FIELD_GET(VRR_FLIPLINE_DCB_MASK, tmp) + 1);
+}
+
+int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 tmp;
+
+	tmp = intel_de_read(display, TRANS_VRR_VMAX_DCB(display, cpu_transcoder));
+
+	return intel_vrr_vblank_start(crtc_state,
+				      REG_FIELD_GET(VRR_VMAX_DCB_MASK, tmp) + 1);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 38bf9996b883..e62b8b50aec6 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -42,4 +42,9 @@ void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
 void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
 bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
 
+int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
+int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
+
 #endif /* __INTEL_VRR_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index 6ed0e0dc97e7..2214c10d4084 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -9,6 +9,50 @@
 #include "intel_display_reg_defs.h"
 
 /* VRR registers */
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A		0x604D4
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B		0x614D4
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_C		0x624D4
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_D		0x634D4
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_E		0x6B4D4
+#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(dev_priv, trans)	\
+					_MMIO_TRANS2(dev_priv, \
+						     trans, \
+						     _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A)
+
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A			0x604D8
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B			0x614D8
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_C			0x624D8
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_D			0x634D8
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_E			0x6B4D8
+#define TRANS_VRR_DCB_ADJ_VMAX_CFG(dev_priv, trans)	_MMIO_TRANS2(dev_priv, \
+								     trans, \
+								     _TRANS_VRR_DCB_ADJ_VMAX_CFG_A)
+
+#define _TRANS_VRR_FLIPLINE_DCB_A		0x60418
+#define _TRANS_VRR_FLIPLINE_DCB_B		0x61418
+#define _TRANS_VRR_FLIPLINE_DCB_C		0x62418
+#define _TRANS_VRR_FLIPLINE_DCB_D		0x63418
+#define _TRANS_VRR_FLIPLINE_DCB_E		0x6B418
+#define TRANS_VRR_FLIPLINE_DCB(dev_priv, trans) _MMIO_TRANS2(dev_priv, \
+							     trans, \
+							     _TRANS_VRR_FLIPLINE_DCB_A)
+
+#define _TRANS_VRR_VMAX_DCB_A			0x60414
+#define _TRANS_VRR_VMAX_DCB_B			0x61414
+#define _TRANS_VRR_VMAX_DCB_C			0x62414
+#define _TRANS_VRR_VMAX_DCB_D			0x63414
+#define _TRANS_VRR_VMAX_DCB_E			0x6B414
+#define TRANS_VRR_VMAX_DCB(dev_priv, trans)	_MMIO_TRANS2(dev_priv, \
+							     trans, \
+							     _TRANS_VRR_VMAX_DCB_A)
+
+#define VRR_DCB_ADJ_FLIPLINE_CNT_MASK		REG_GENMASK(31, 24)
+#define VRR_DCB_ADJ_FLIPLINE_MASK		REG_GENMASK(19, 0)
+#define VRR_DCB_ADJ_VMAX_CNT_MASK		REG_GENMASK(31, 24)
+#define VRR_DCB_ADJ_VMAX_MASK			REG_GENMASK(19, 0)
+#define VRR_FLIPLINE_DCB_MASK			REG_GENMASK(19, 0)
+#define VRR_VMAX_DCB_MASK			REG_GENMASK(19, 0)
+
 #define _TRANS_VRR_CTL_A			0x60420
 #define _TRANS_VRR_CTL_B			0x61420
 #define _TRANS_VRR_CTL_C			0x62420
-- 
2.48.1

[PATCH v2 03/13] drm/i915/display: Add source param for dc balance

[Mitul Golani]

Add source param for dc balance enablement further.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 87c666792c0d..653483fa99ea 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -144,6 +144,7 @@ struct intel_display_platforms {
 #define HAS_4TILE(__display)		((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
 #define HAS_ASYNC_FLIPS(__display)	(DISPLAY_VER(__display) >= 5)
 #define HAS_AS_SDP(__display)		(DISPLAY_VER(__display) >= 13)
+#define HAS_DC_BALANCE(__display)		(DISPLAY_VER(__display) >= 30)
 #define HAS_BIGJOINER(__display)	(DISPLAY_VER(__display) >= 11 && HAS_DSC(__display))
 #define HAS_CDCLK_CRAWL(__display)	(DISPLAY_INFO(__display)->has_cdclk_crawl)
 #define HAS_CDCLK_SQUASH(__display)	(DISPLAY_INFO(__display)->has_cdclk_squash)
-- 
2.48.1

[PATCH v2 04/13] drm/i915/vrr: Add enable/disable calls for DC Balance

[Mitul Golani]

Add enable/disable calls along with required hw registers
for DC balance enablement.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  7 ++
 drivers/gpu/drm/i915/display/intel_dmc_regs.h | 71 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.c      | 29 ++++++++
 drivers/gpu/drm/i915/display/intel_vrr_regs.h | 10 +++
 4 files changed, 117 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 94468a9d2e0d..126d54e6a393 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1307,6 +1307,13 @@ struct intel_crtc_state {
 		u8 pipeline_full;
 		u16 flipline, vmin, vmax, guardband;
 		u32 vsync_end, vsync_start;
+		struct {
+			bool enable;
+			u16 vmin, vmax;
+			u16 guardband, slope;
+			u16 max_increase, max_decrease;
+			u16 vblank_target;
+		} dc_balance;
 	} vrr;
 
 	/* Content Match Refresh Rate state */
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index 1bf446f96a10..39e4f70005ab 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -103,4 +103,75 @@
 #define  DMC_WAKELOCK_CTL_REQ	 REG_BIT(31)
 #define  DMC_WAKELOCK_CTL_ACK	 REG_BIT(15)
 
+#define _PIPEDMC_DCB_CTL_A			0x5F1A0
+#define _PIPEDMC_DCB_CTL_B			0x5F5A0
+#define _PIPEDMC_DCB_CTL_C			0x5F9A0
+#define _PIPEDMC_DCB_CTL_D			0x5FDA0
+#define _PIPEDMC_DCB_CTL_E			0x551A0
+#define _PIPEDMC_DCB_CTL_F			0x555A0
+#define PIPEDMC_DCB_CTL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_CTL_A)
+#define PIPEDMC_ADAPTIVE_DCB_ENABLE		REG_BIT(31)
+
+#define _PIPEDMC_DCB_VBLANK_A			0x5F1BC
+#define _PIPEDMC_DCB_VBLANK_B			0x5F5BC
+#define _PIPEDMC_DCB_VBLANK_C			0x5F9BC
+#define _PIPEDMC_DCB_VBLANK_D			0x5FDBC
+#define _PIPEDMC_DCB_VBLANK_E			0x551BC
+#define _PIPEDMC_DCB_VBLANK_F			0x555BC
+#define PIPEDMC_DCB_VBLANK(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_VBLANK_A)
+
+#define _PIPEDMC_DCB_SLOPE_A			0x5F1B8
+#define _PIPEDMC_DCB_SLOPE_B			0x5F5B8
+#define _PIPEDMC_DCB_SLOPE_C			0x5F9B8
+#define _PIPEDMC_DCB_SLOPE_D			0x5FDB8
+#define _PIPEDMC_DCB_SLOPE_E			0x551B8
+#define _PIPEDMC_DCB_SLOPE_F			0x555B8
+#define PIPEDMC_DCB_SLOPE(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_SLOPE_A)
+
+#define _PIPEDMC_DCB_GUARDBAND_A		0x5F1B4
+#define _PIPEDMC_DCB_GUARDBAND_B		0x5F5B4
+#define _PIPEDMC_DCB_GUARDBAND_C		0x5F9B4
+#define _PIPEDMC_DCB_GUARDBAND_D		0x5FDB4
+#define _PIPEDMC_DCB_GUARDBAND_E		0x551B4
+#define _PIPEDMC_DCB_GUARDBAND_F		0x555B4
+#define PIPEDMC_DCB_GUARDBAND(dev_priv, trans)	_MMIO_TRANS2(dev_priv, \
+							     trans, \
+							     _PIPEDMC_DCB_GUARDBAND_A)
+
+#define _PIPEDMC_DCB_MAX_INCREASE_A			0x5F1AC
+#define _PIPEDMC_DCB_MAX_INCREASE_B			0x5F5AC
+#define _PIPEDMC_DCB_MAX_INCREASE_C			0x5F9AC
+#define _PIPEDMC_DCB_MAX_INCREASE_D			0x5FDAC
+#define _PIPEDMC_DCB_MAX_INCREASE_E			0x551AC
+#define _PIPEDMC_DCB_MAX_INCREASE_F			0x555AC
+#define PIPEDMC_DCB_MAX_INCREASE(dev_priv, trans)	_MMIO_TRANS2(dev_priv, \
+								     trans, \
+								     _PIPEDMC_DCB_MAX_INCREASE_A)
+
+#define _PIPEDMC_DCB_MAX_DECREASE_A			0x5F1B0
+#define _PIPEDMC_DCB_MAX_DECREASE_B			0x5F5B0
+#define _PIPEDMC_DCB_MAX_DECREASE_C			0x5F9B0
+#define _PIPEDMC_DCB_MAX_DECREASE_D			0x5FDB0
+#define _PIPEDMC_DCB_MAX_DECREASE_E			0x551B0
+#define _PIPEDMC_DCB_MAX_DECREASE_F			0x555B0
+#define PIPEDMC_DCB_MAX_DECREASE(dev_priv, trans)	_MMIO_TRANS2(dev_priv, \
+								     trans, \
+								     _PIPEDMC_DCB_MAX_DECREASE_A)
+
+#define _PIPEDMC_DCB_VMIN_A			0x5F1A4
+#define _PIPEDMC_DCB_VMIN_B			0x5F5A4
+#define _PIPEDMC_DCB_VMIN_C			0x5F9A4
+#define _PIPEDMC_DCB_VMIN_D			0x5FDA4
+#define _PIPEDMC_DCB_VMIN_E			0x551A4
+#define _PIPEDMC_DCB_VMIN_F			0x555A4
+#define PIPEDMC_DCB_VMIN(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_VMIN_A)
+
+#define _PIPEDMC_DCB_VMAX_A			0x5F1A8
+#define _PIPEDMC_DCB_VMAX_B			0x5F5A8
+#define _PIPEDMC_DCB_VMAX_C			0x5F9A8
+#define _PIPEDMC_DCB_VMAX_D			0x5FDA8
+#define _PIPEDMC_DCB_VMAX_E			0x551A8
+#define _PIPEDMC_DCB_VMAX_F			0x555A8
+#define PIPEDMC_DCB_VMAX(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_VMAX_A)
+
 #endif /* __INTEL_DMC_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 1c0eaa08927b..c4fb78d86ab0 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -10,6 +10,7 @@
 #include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_dp.h"
+#include "intel_dmc_regs.h"
 #include "intel_vrr.h"
 #include "intel_vrr_regs.h"
 
@@ -601,6 +602,23 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 				       VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
 		}
 	}
+
+	if (crtc_state->vrr.dc_balance.enable && HAS_DC_BALANCE(display)) {
+		intel_de_write(display, PIPEDMC_DCB_VMIN(display, cpu_transcoder),
+			       crtc_state->vrr.dc_balance.vmin - 1);
+		intel_de_write(display, PIPEDMC_DCB_VMAX(display, cpu_transcoder),
+			       crtc_state->vrr.dc_balance.vmax - 1);
+		intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(display, cpu_transcoder),
+			       crtc_state->vrr.dc_balance.max_increase);
+		intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(display, cpu_transcoder),
+			       crtc_state->vrr.dc_balance.max_decrease);
+		intel_de_write(display, PIPEDMC_DCB_GUARDBAND(display, cpu_transcoder),
+			       crtc_state->vrr.dc_balance.guardband);
+		intel_de_write(display, PIPEDMC_DCB_SLOPE(display, cpu_transcoder),
+			       crtc_state->vrr.dc_balance.slope);
+		intel_de_write(display, PIPEDMC_DCB_VBLANK(display, cpu_transcoder),
+			       crtc_state->vrr.dc_balance.vblank_target);
+	}
 }
 
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
@@ -611,6 +629,17 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 	if (!old_crtc_state->vrr.enable)
 		return;
 
+	if (old_crtc_state->vrr.dc_balance.enable && HAS_DC_BALANCE(display)) {
+		intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(display, cpu_transcoder), 0);
+		intel_de_write(display, PIPEDMC_DCB_VMIN(display, cpu_transcoder), 0);
+		intel_de_write(display, PIPEDMC_DCB_VMAX(display, cpu_transcoder), 0);
+		intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(display, cpu_transcoder), 0);
+		intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(display, cpu_transcoder), 0);
+		intel_de_write(display, PIPEDMC_DCB_GUARDBAND(display, cpu_transcoder), 0);
+		intel_de_write(display, PIPEDMC_DCB_SLOPE(display, cpu_transcoder), 0);
+		intel_de_write(display, PIPEDMC_DCB_VBLANK(display, cpu_transcoder), 0);
+	}
+
 	if (!intel_vrr_always_use_vrr_tg(display)) {
 		intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
 			       trans_vrr_ctl(old_crtc_state));
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index 2214c10d4084..2db477325c83 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -53,6 +53,16 @@
 #define VRR_FLIPLINE_DCB_MASK			REG_GENMASK(19, 0)
 #define VRR_VMAX_DCB_MASK			REG_GENMASK(19, 0)
 
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A			0x604C0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B			0x614C0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_C			0x624C0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_D			0x634C0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_E			0x6B4C0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_F			0x6C4C0
+#define TRANS_ADAPTIVE_SYNC_DCB_CTL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, \
+								     trans, \
+								     _TRANS_ADAPTIVE_SYNC_DCB_CTL_A)
+
 #define _TRANS_VRR_CTL_A			0x60420
 #define _TRANS_VRR_CTL_B			0x61420
 #define _TRANS_VRR_CTL_C			0x62420
-- 
2.48.1

[PATCH v2 05/13] drm/i915/vrr: Add compute config for DC balance params

[Mitul Golani]

Add compute config for DC balance params. This will be required
to calculate correct balance requirement for DMC firmware.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index c4fb78d86ab0..383024dc2784 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -16,6 +16,9 @@
 
 #define FIXED_POINT_PRECISION		100
 #define CMRR_PRECISION_TOLERANCE	10
+#define DCB_CORRECTION_SENSITIVITY	30
+#define DCB_CORRECTION_AGGRESSIVENESS	1000
+#define DCB_BLANK_TARGET		50
 
 bool intel_vrr_is_capable(struct intel_connector *connector)
 {
@@ -409,6 +412,24 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 			(crtc_state->hw.adjusted_mode.crtc_vtotal -
 			 crtc_state->hw.adjusted_mode.vsync_end);
 	}
+
+	if (crtc_state->vrr.dc_balance.enable && HAS_DC_BALANCE(display)) {
+		crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax;
+		crtc_state->vrr.dc_balance.vmin = crtc_state->vrr.vmin;
+		crtc_state->vrr.dc_balance.max_increase =
+			crtc_state->vrr.vmax - crtc_state->vrr.vmin;
+		crtc_state->vrr.dc_balance.max_decrease =
+			crtc_state->vrr.vmax - crtc_state->vrr.vmin;
+		crtc_state->vrr.dc_balance.guardband =
+		DIV_ROUND_UP(crtc_state->vrr.dc_balance.vmax * DCB_CORRECTION_SENSITIVITY,
+			     100);
+		crtc_state->vrr.dc_balance.slope =
+			DIV_ROUND_UP(DCB_CORRECTION_AGGRESSIVENESS * 10,
+				     crtc_state->vrr.dc_balance.guardband);
+		crtc_state->vrr.dc_balance.vblank_target =
+		DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) * DCB_BLANK_TARGET,
+			     100);
+	}
 }
 
 void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
-- 
2.48.1

[PATCH v2 06/13] drm/i915/vrr: Add state dump for dc balance params

[Mitul Golani]

Add state dump for dc balance params to track dc balance
crtc state config.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 0c7f91046996..9baafc63d9ea 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -304,7 +304,14 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 	drm_printf(&p, "vrr: vmin vblank: %d, vmax vblank: %d, vmin vtotal: %d, vmax vtotal: %d\n",
 		   intel_vrr_vmin_vblank_start(pipe_config), intel_vrr_vmax_vblank_start(pipe_config),
 		   intel_vrr_vmin_vtotal(pipe_config), intel_vrr_vmax_vtotal(pipe_config));
-
+	drm_printf(&p, "vrr: dc balance: %s, vmin: %d vmax: %d guardband: %d, slope: %d max increase: %d max decrease: %d Vblank target: %d\n",
+		   str_yes_no(pipe_config->vrr.dc_balance.enable),
+		   pipe_config->vrr.dc_balance.vmin, pipe_config->vrr.dc_balance.vmax,
+		   pipe_config->vrr.dc_balance.guardband,
+		   pipe_config->vrr.dc_balance.slope,
+		   pipe_config->vrr.dc_balance.max_increase,
+		   pipe_config->vrr.dc_balance.max_decrease,
+		   pipe_config->vrr.dc_balance.vblank_target);
 	drm_printf(&p, "requested mode: " DRM_MODE_FMT "\n",
 		   DRM_MODE_ARG(&pipe_config->hw.mode));
 	drm_printf(&p, "adjusted mode: " DRM_MODE_FMT "\n",
-- 
2.48.1

[PATCH v2 07/13] drm/i915: Extract vrr_vblank_start()

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Initialise delayed vblank position for evasion logic.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vblank.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 139fa5deba80..680013f00fc0 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -642,6 +642,14 @@ intel_pre_commit_crtc_state(struct intel_atomic_state *state,
 	return pre_commit_crtc_state(old_crtc_state, new_crtc_state);
 }
 
+static int vrr_vblank_start(const struct intel_crtc_state *crtc_state)
+{
+	if (intel_vrr_is_push_sent(crtc_state))
+		return intel_vrr_vmin_vblank_start(crtc_state);
+	else
+		return intel_vrr_vmax_vblank_start(crtc_state);
+}
+
 void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
 			     const struct intel_crtc_state *new_crtc_state,
 			     struct intel_vblank_evade_ctx *evade)
@@ -668,10 +676,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
 		drm_WARN_ON(crtc->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
 			    new_crtc_state->update_m_n || new_crtc_state->update_lrr);
 
-		if (intel_vrr_is_push_sent(crtc_state))
-			evade->vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
-		else
-			evade->vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
+		evade->vblank_start = vrr_vblank_start(crtc_state);
 
 		vblank_delay = intel_vrr_vblank_delay(crtc_state);
 	} else {
-- 
2.48.1

[PATCH v2 08/13] drm/i915/vrr: Implement vblank evasion with DC balancing

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add vblank evasion logic when vrr is already enabled along with
dc balance is computed.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c    | 31 ++++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vblank.c | 26 +++++++++++++++--
 2 files changed, 53 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 72fe390c5af2..ffd10ee96e29 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -577,7 +577,36 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
 	if (crtc_state->has_psr)
 		intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0);
 
-	if (pre_commit_is_vrr_active(state, crtc)) {
+	if (pre_commit_is_vrr_active(state, crtc) && crtc_state->vrr.dc_balance.enable) {
+		int vblank_delay = intel_vrr_vblank_delay(crtc_state);
+		int vmin_vblank_start, vmax_vblank_start;
+
+		vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
+
+		if (vmin_vblank_start >= 0) {
+			end = vmin_vblank_start;
+			start = end - vblank_delay - latency;
+			intel_dsb_wait_scanline_out(state, dsb, start, end);
+		}
+
+		vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state);
+
+		if (vmax_vblank_start >= 0) {
+			end = vmax_vblank_start;
+			start = end - vblank_delay - latency;
+			intel_dsb_wait_scanline_out(state, dsb, start, end);
+		}
+
+		vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state);
+		end = vmin_vblank_start;
+		start = end - vblank_delay - latency;
+		intel_dsb_wait_scanline_out(state, dsb, start, end);
+
+		vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state);
+		end = vmax_vblank_start;
+		start = end - vblank_delay - latency;
+		intel_dsb_wait_scanline_out(state, dsb, start, end);
+	} else if (pre_commit_is_vrr_active(state, crtc)) {
 		int vblank_delay = intel_vrr_vblank_delay(crtc_state);
 
 		end = intel_vrr_vmin_vblank_start(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 680013f00fc0..eb74d08d6690 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -644,10 +644,30 @@ intel_pre_commit_crtc_state(struct intel_atomic_state *state,
 
 static int vrr_vblank_start(const struct intel_crtc_state *crtc_state)
 {
-	if (intel_vrr_is_push_sent(crtc_state))
-		return intel_vrr_vmin_vblank_start(crtc_state);
+	bool is_push_sent = intel_vrr_is_push_sent(crtc_state);
+	int vblank_start;
+
+	if (!crtc_state->vrr.dc_balance.enable) {
+		if (is_push_sent)
+			return intel_vrr_vmin_vblank_start(crtc_state);
+		else
+			return intel_vrr_vmax_vblank_start(crtc_state);
+	}
+
+	if (is_push_sent)
+		vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
 	else
-		return intel_vrr_vmax_vblank_start(crtc_state);
+		vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state);
+
+	if (vblank_start >= 0)
+		return vblank_start;
+
+	if (is_push_sent)
+		vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state);
+	else
+		vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state);
+
+	return vblank_start;
 }
 
 void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
-- 
2.48.1

[PATCH v2 09/13] drm/i915/dsb: Add pipedmc dc balance enable/disable

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add function to control DC balance enable/disable bit via DSB.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c      | 24 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dmc.h      |  5 ++++
 drivers/gpu/drm/i915/display/intel_dmc_regs.h |  9 +++++++
 3 files changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index ff2b97a752b1..e32599a4f68f 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -30,6 +30,7 @@
 #include "intel_de.h"
 #include "intel_display_rpm.h"
 #include "intel_display_power_well.h"
+#include "intel_display_types.h"
 #include "intel_dmc.h"
 #include "intel_dmc_regs.h"
 #include "intel_step.h"
@@ -1355,3 +1356,26 @@ void intel_dmc_debugfs_register(struct intel_display *display)
 	debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root,
 			    display, &intel_dmc_debugfs_status_fops);
 }
+
+void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	struct intel_crtc_state *crtc_state =
+		to_intel_crtc_state(crtc->base.state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	intel_de_write_dsb(display, dsb,
+			   PIPEDMC_DCB_CTL(display, cpu_transcoder),
+			   PIPEDMC_ADAPTIVE_DCB_ENABLE);
+}
+
+void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	struct intel_crtc_state *crtc_state =
+		to_intel_crtc_state(crtc->base.state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	intel_de_write_dsb(display, dsb,
+			   PIPEDMC_DCB_CTL(display, cpu_transcoder), 0);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index c78426eb4cd5..74dcd142f5b1 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -10,8 +10,10 @@
 
 enum pipe;
 struct drm_printer;
+struct intel_crtc;
 struct intel_display;
 struct intel_dmc_snapshot;
+struct intel_dsb;
 
 void intel_dmc_init(struct intel_display *display);
 void intel_dmc_load_program(struct intel_display *display);
@@ -30,4 +32,7 @@ void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool star
 
 void assert_dmc_loaded(struct intel_display *display);
 
+void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc);
+void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc);
+
 #endif /* __INTEL_DMC_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index 39e4f70005ab..6788afb816ea 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -174,4 +174,13 @@
 #define _PIPEDMC_DCB_VMAX_F			0x555A8
 #define PIPEDMC_DCB_VMAX(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_VMAX_A)
 
+#define _PIPEDMC_DCB_CTL_A			0x5F1A0
+#define _PIPEDMC_DCB_CTL_B			0x5F5A0
+#define _PIPEDMC_DCB_CTL_C			0x5F9A0
+#define _PIPEDMC_DCB_CTL_D			0x5FDA0
+#define _PIPEDMC_DCB_CTL_E			0x551A0
+#define _PIPEDMC_DCB_CTL_F			0x555A0
+#define PIPEDMC_DCB_CTL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_CTL_A)
+#define PIPEDMC_ADAPTIVE_DCB_ENABLE		REG_BIT(31)
+
 #endif /* __INTEL_DMC_REGS_H__ */
-- 
2.48.1

[PATCH v2 10/13] drm/i915/vrr: Pause DC balancing for DSB commits

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pause the DMC DC balancing for the remainder of the
commit so that vmin/vmax won't change after we've baked
them into the DSB vblank evasion commands.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 13 +++++++
 drivers/gpu/drm/i915/display/intel_vrr.c      | 38 +++++++++++++------
 drivers/gpu/drm/i915/display/intel_vrr_regs.h | 12 ++++++
 3 files changed, 51 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 33c09999c42e..274d01552ccf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7194,6 +7194,17 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 	}
 
 	if (new_crtc_state->use_dsb) {
+		/*
+		 * Pause the DMC DC balancing for the remainder of the
+		 * commit so that vmin/vmax won't change after we've baked
+		 * them into the DSB vblank evasion commands.
+		 *
+		 * FIXME maybe need a small delay here to make sure DMC has
+		 * finished updating the values? Or we need a better DMC<->driver
+		 * protocol that gives is real guarantees about that...
+		 */
+		intel_pipedmc_dcb_disable(NULL, crtc);
+
 		if (intel_crtc_needs_color_update(new_crtc_state))
 			intel_color_commit_noarm(new_crtc_state->dsb_commit,
 						 new_crtc_state);
@@ -7230,6 +7241,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
 			intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
 			intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit);
 			intel_vrr_check_push_sent(new_crtc_state->dsb_commit, new_crtc_state);
+			if (new_crtc_state->vrr.dc_balance.enable)
+				intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit, crtc);
 			intel_dsb_interrupt(new_crtc_state->dsb_commit);
 		}
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 383024dc2784..fb96d03bbf03 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -9,6 +9,7 @@
 #include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
+#include "intel_dmc.h"
 #include "intel_dp.h"
 #include "intel_dmc_regs.h"
 #include "intel_vrr.h"
@@ -598,7 +599,9 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display)
 void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 ctl;
 
 	if (!crtc_state->vrr.enable)
 		return;
@@ -609,20 +612,19 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 		       crtc_state->vrr.vmax - 1);
 	intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
 		       crtc_state->vrr.flipline - 1);
+	if (!intel_vrr_always_use_vrr_tg(display))
+		intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN);
 
 	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
 		       TRANS_PUSH_EN);
 
-	if (!intel_vrr_always_use_vrr_tg(display)) {
-		if (crtc_state->cmrr.enable) {
-			intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
-				       VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
-				       trans_vrr_ctl(crtc_state));
-		} else {
-			intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
-				       VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
-		}
-	}
+	ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
+	if (crtc_state->cmrr.enable)
+		ctl |= VRR_CTL_CMRR_ENABLE;
+	if (crtc_state->vrr.dc_balance.enable)
+		ctl |= VRR_CTL_DCB_ADJ_ENABLE;
+
+	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl);
 
 	if (crtc_state->vrr.dc_balance.enable && HAS_DC_BALANCE(display)) {
 		intel_de_write(display, PIPEDMC_DCB_VMIN(display, cpu_transcoder),
@@ -639,18 +641,26 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 			       crtc_state->vrr.dc_balance.slope);
 		intel_de_write(display, PIPEDMC_DCB_VBLANK(display, cpu_transcoder),
 			       crtc_state->vrr.dc_balance.vblank_target);
+		/* FIXME reset counters? */
+		intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(display, cpu_transcoder),
+			       ADAPTIVE_SYNC_COUNTER_EN);
+		/* FIMXE configure pipedmc DC balance parameters somewhere */
+		intel_pipedmc_dcb_enable(NULL, crtc);
 	}
 }
 
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 {
 	struct intel_display *display = to_intel_display(old_crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
+	u32 ctl;
 
 	if (!old_crtc_state->vrr.enable)
 		return;
 
 	if (old_crtc_state->vrr.dc_balance.enable && HAS_DC_BALANCE(display)) {
+		intel_pipedmc_dcb_disable(NULL, crtc);
 		intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(display, cpu_transcoder), 0);
 		intel_de_write(display, PIPEDMC_DCB_VMIN(display, cpu_transcoder), 0);
 		intel_de_write(display, PIPEDMC_DCB_VMAX(display, cpu_transcoder), 0);
@@ -661,9 +671,13 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
 		intel_de_write(display, PIPEDMC_DCB_VBLANK(display, cpu_transcoder), 0);
 	}
 
+	ctl = trans_vrr_ctl(old_crtc_state);
+	if (intel_vrr_always_use_vrr_tg(display))
+		ctl |= VRR_CTL_VRR_ENABLE;
+
+	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl);
+
 	if (!intel_vrr_always_use_vrr_tg(display)) {
-		intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
-			       trans_vrr_ctl(old_crtc_state));
 		intel_de_wait_for_clear(display,
 					TRANS_VRR_STATUS(display, cpu_transcoder),
 					VRR_STATUS_VRR_EN_LIVE, 1000);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index 2db477325c83..a88fcd69111f 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -63,6 +63,17 @@
 								     trans, \
 								     _TRANS_ADAPTIVE_SYNC_DCB_CTL_A)
 
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A			0x604C0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B			0x614C0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_C			0x624C0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_D			0x634C0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_E			0x6B4C0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_F			0x6C4C0
+#define TRANS_ADAPTIVE_SYNC_DCB_CTL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, \
+								     trans, \
+								     _TRANS_ADAPTIVE_SYNC_DCB_CTL_A)
+#define  ADAPTIVE_SYNC_COUNTER_EN			REG_BIT(31)
+
 #define _TRANS_VRR_CTL_A			0x60420
 #define _TRANS_VRR_CTL_B			0x61420
 #define _TRANS_VRR_CTL_C			0x62420
@@ -71,6 +82,7 @@
 #define  VRR_CTL_VRR_ENABLE			REG_BIT(31)
 #define  VRR_CTL_IGN_MAX_SHIFT			REG_BIT(30)
 #define  VRR_CTL_FLIP_LINE_EN			REG_BIT(29)
+#define  VRR_CTL_DCB_ADJ_ENABLE			REG_BIT(28)
 #define  VRR_CTL_PIPELINE_FULL_MASK		REG_GENMASK(10, 3)
 #define  VRR_CTL_PIPELINE_FULL(x)		REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
 #define  VRR_CTL_PIPELINE_FULL_OVERRIDE		REG_BIT(0)
-- 
2.48.1

[PATCH v2 11/13] drm/i915/vrr: Add state checker for dc balance params

[Mitul Golani]

Add state checker for dc balance params. Also add macro to
check source support.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  7 +++++++
 drivers/gpu/drm/i915/display/intel_vrr.c     | 20 +++++++++++++++++++-
 2 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 274d01552ccf..4a21acb88aa7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5402,6 +5402,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
 		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
 		PIPE_CONF_CHECK_BOOL(cmrr.enable);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.slope);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease);
+		PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target);
 	}
 
 	if (!fastset || intel_vrr_always_use_vrr_tg(display)) {
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index fb96d03bbf03..e8802348e5fa 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -740,7 +740,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-	u32 trans_vrr_ctl, trans_vrr_vsync;
+	u32 trans_vrr_ctl, trans_vrr_vsync, dcb_ctl;
 	bool vrr_enable;
 
 	trans_vrr_ctl = intel_de_read(display,
@@ -802,6 +802,24 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 	else
 		crtc_state->vrr.enable = vrr_enable;
 
+	if (HAS_DC_BALANCE(display)) {
+		dcb_ctl = intel_de_read(display, PIPEDMC_DCB_CTL(display, cpu_transcoder));
+		crtc_state->vrr.dc_balance.vmin =
+			intel_de_read(display, PIPEDMC_DCB_VMIN(display, cpu_transcoder)) + 1;
+		crtc_state->vrr.dc_balance.vmax =
+			intel_de_read(display, PIPEDMC_DCB_VMAX(display, cpu_transcoder)) + 1;
+		crtc_state->vrr.dc_balance.guardband =
+			intel_de_read(display, PIPEDMC_DCB_GUARDBAND(display, cpu_transcoder));
+		crtc_state->vrr.dc_balance.max_increase =
+			intel_de_read(display, PIPEDMC_DCB_MAX_INCREASE(display, cpu_transcoder));
+		crtc_state->vrr.dc_balance.max_decrease =
+			intel_de_read(display, PIPEDMC_DCB_MAX_DECREASE(display, cpu_transcoder));
+		crtc_state->vrr.dc_balance.slope =
+			intel_de_read(display, PIPEDMC_DCB_SLOPE(display, cpu_transcoder));
+		crtc_state->vrr.dc_balance.vblank_target =
+			intel_de_read(display, PIPEDMC_DCB_VBLANK(display, cpu_transcoder));
+	}
+
 	/*
 	 * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags.
 	 * Since CMRR is currently disabled, set this flag for VRR for now.
-- 
2.48.1

[PATCH v2 12/13] drm/i915/display: Prepare state checker for dc balance enable

[Mitul Golani]

Prepare state check param for enabling dc balance enable bit.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 1 +
 drivers/gpu/drm/i915/display/intel_vrr.c     | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4a21acb88aa7..0bb39134f52d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5402,6 +5402,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
 		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
 		PIPE_CONF_CHECK_BOOL(cmrr.enable);
+		PIPE_CONF_CHECK_BOOL(vrr.dc_balance.enable);
 		PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
 		PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
 		PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index e8802348e5fa..7c09f384a684 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -804,6 +804,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 
 	if (HAS_DC_BALANCE(display)) {
 		dcb_ctl = intel_de_read(display, PIPEDMC_DCB_CTL(display, cpu_transcoder));
+		crtc_state->vrr.dc_balance.enable = dcb_ctl & PIPEDMC_ADAPTIVE_DCB_ENABLE;
 		crtc_state->vrr.dc_balance.vmin =
 			intel_de_read(display, PIPEDMC_DCB_VMIN(display, cpu_transcoder)) + 1;
 		crtc_state->vrr.dc_balance.vmax =
-- 
2.48.1

[PATCH v2 13/13] drm/i915/vrr: enable dc balance bit

[Mitul Golani]

enable dc balance from vrr compute config when vrr is
enabled in adaptive vtotal mode

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 7c09f384a684..a21dbbce9ac7 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -255,7 +255,12 @@ void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
 static
 void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	crtc_state->vrr.enable = true;
+
+	if (HAS_DC_BALANCE(display))
+		crtc_state->vrr.dc_balance.enable = true;
+
 	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 }
 
-- 
2.48.1

✗ Fi.CI.SPARSE: warning for Enable/Disable DC balance along with VRR DSB (rev2)

[Patchwork]

== Series Details ==

Series: Enable/Disable DC balance along with VRR DSB (rev2)
URL   : https://patchwork.freedesktop.org/series/147799/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✗ i915.CI.BAT: failure for Enable/Disable DC balance along with VRR DSB (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 11741 bytes --]

== Series Details ==

Series: Enable/Disable DC balance along with VRR DSB (rev2)
URL   : https://patchwork.freedesktop.org/series/147799/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_16442 -> Patchwork_147799v2
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_147799v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_147799v2, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/index.html

Participating hosts (44 -> 44)
------------------------------

  Additional (1): bat-adlp-11 
  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_147799v2:

### IGT changes ###

#### Possible regressions ####

  * igt@fbdev@write:
    - bat-adls-6:         [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16442/bat-adls-6/igt@fbdev@write.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-adls-6/igt@fbdev@write.html

  * igt@gem_huc_copy@huc-copy:
    - bat-dg2-14:         [PASS][3] -> [ABORT][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16442/bat-dg2-14/igt@gem_huc_copy@huc-copy.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-dg2-14/igt@gem_huc_copy@huc-copy.html

  * igt@gem_tiled_blits@basic:
    - bat-rpls-4:         [PASS][5] -> [ABORT][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16442/bat-rpls-4/igt@gem_tiled_blits@basic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-rpls-4/igt@gem_tiled_blits@basic.html

  * igt@kms_addfb_basic@addfb25-modifier-no-flag:
    - bat-mtlp-9:         [PASS][7] -> [ABORT][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16442/bat-mtlp-9/igt@kms_addfb_basic@addfb25-modifier-no-flag.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-mtlp-9/igt@kms_addfb_basic@addfb25-modifier-no-flag.html

  * igt@kms_busy@basic@modeset:
    - bat-dg2-9:          [PASS][9] -> [ABORT][10] +1 other test abort
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16442/bat-dg2-9/igt@kms_busy@basic@modeset.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-dg2-9/igt@kms_busy@basic@modeset.html

  * igt@kms_chamelium_edid@dp-edid-read:
    - bat-dg2-13:         [PASS][11] -> [ABORT][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16442/bat-dg2-13/igt@kms_chamelium_edid@dp-edid-read.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-dg2-13/igt@kms_chamelium_edid@dp-edid-read.html

  * igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-hdmi-a-2:
    - bat-dg2-11:         [PASS][13] -> [ABORT][14] +1 other test abort
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16442/bat-dg2-11/igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-hdmi-a-2.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-dg2-11/igt@kms_pipe_crc_basic@hang-read-crc@pipe-a-hdmi-a-2.html

  * igt@kms_pipe_crc_basic@read-crc@pipe-d-dp-1:
    - bat-dg2-8:          [PASS][15] -> [ABORT][16] +1 other test abort
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16442/bat-dg2-8/igt@kms_pipe_crc_basic@read-crc@pipe-d-dp-1.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-dg2-8/igt@kms_pipe_crc_basic@read-crc@pipe-d-dp-1.html

  
Known issues
------------

  Here are the changes found in Patchwork_147799v2 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@fbdev@eof:
    - bat-adlp-11:        NOTRUN -> [SKIP][17] ([i915#2582]) +3 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-adlp-11/igt@fbdev@eof.html

  * igt@fbdev@info:
    - bat-adlp-11:        NOTRUN -> [SKIP][18] ([i915#1849] / [i915#2582])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-adlp-11/igt@fbdev@info.html

  * igt@gem_lmem_swapping@verify-random:
    - bat-adlp-11:        NOTRUN -> [SKIP][19] ([i915#4613]) +3 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-adlp-11/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_tiled_pread_basic:
    - bat-adlp-11:        NOTRUN -> [SKIP][20] ([i915#3282])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-adlp-11/igt@gem_tiled_pread_basic.html

  * igt@i915_module_load@load:
    - bat-mtlp-9:         [PASS][21] -> [DMESG-WARN][22] ([i915#13494])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16442/bat-mtlp-9/igt@i915_module_load@load.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-mtlp-9/igt@i915_module_load@load.html

  * igt@i915_pm_rps@basic-api:
    - bat-adlp-11:        NOTRUN -> [SKIP][23] ([i915#6621])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-adlp-11/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live:
    - bat-mtlp-8:         [PASS][24] -> [DMESG-FAIL][25] ([i915#12061]) +1 other test dmesg-fail
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16442/bat-mtlp-8/igt@i915_selftest@live.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-mtlp-8/igt@i915_selftest@live.html

  * igt@intel_hwmon@hwmon-read:
    - bat-adlp-11:        NOTRUN -> [SKIP][26] ([i915#7707]) +1 other test skip
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-adlp-11/igt@intel_hwmon@hwmon-read.html

  * igt@kms_flip@basic-flip-vs-dpms:
    - bat-adlp-11:        NOTRUN -> [SKIP][27] ([i915#3637]) +3 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-adlp-11/igt@kms_flip@basic-flip-vs-dpms.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - bat-adlp-11:        NOTRUN -> [SKIP][28] ([i915#4093]) +3 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-adlp-11/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_frontbuffer_tracking@basic:
    - bat-adlp-11:        NOTRUN -> [SKIP][29] ([i915#4342] / [i915#5354])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-adlp-11/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_hdmi_inject@inject-audio:
    - bat-adlp-11:        NOTRUN -> [SKIP][30] ([i915#4369])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-adlp-11/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_pipe_crc_basic@read-crc:
    - bat-adlp-11:        NOTRUN -> [SKIP][31] ([i915#10470]) +16 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-adlp-11/igt@kms_pipe_crc_basic@read-crc.html

  * igt@kms_pm_backlight@basic-brightness:
    - bat-adlp-11:        NOTRUN -> [SKIP][32] ([i915#9812])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-adlp-11/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_psr@psr-primary-page-flip:
    - bat-adlp-11:        NOTRUN -> [SKIP][33] ([i915#1072] / [i915#9732]) +3 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-adlp-11/igt@kms_psr@psr-primary-page-flip.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-adlp-11:        NOTRUN -> [SKIP][34] ([i915#3555])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-adlp-11/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-adlp-11:        NOTRUN -> [SKIP][35] ([i915#10470] / [i915#3708])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-adlp-11/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-write:
    - bat-adlp-11:        NOTRUN -> [SKIP][36] ([i915#3291] / [i915#3708]) +2 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-adlp-11/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@dmabuf@all-tests@dma_fence_chain:
    - fi-bsw-n3050:       [INCOMPLETE][37] ([i915#12904]) -> [PASS][38] +1 other test pass
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16442/fi-bsw-n3050/igt@dmabuf@all-tests@dma_fence_chain.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/fi-bsw-n3050/igt@dmabuf@all-tests@dma_fence_chain.html

  * igt@i915_selftest@live:
    - bat-arlh-2:         [INCOMPLETE][39] ([i915#14046]) -> [PASS][40] +1 other test pass
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16442/bat-arlh-2/igt@i915_selftest@live.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-arlh-2/igt@i915_selftest@live.html

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-3:         [DMESG-FAIL][41] ([i915#12061]) -> [PASS][42] +1 other test pass
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16442/bat-arlh-3/igt@i915_selftest@live@workarounds.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-arlh-3/igt@i915_selftest@live@workarounds.html
    - bat-mtlp-6:         [DMESG-FAIL][43] ([i915#12061]) -> [PASS][44] +1 other test pass
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16442/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/bat-mtlp-6/igt@i915_selftest@live@workarounds.html

  
  [i915#10470]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10470
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904
  [i915#13494]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13494
  [i915#14046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14046
  [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
  [i915#2582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2582
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#4093]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4093
  [i915#4342]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4342
  [i915#4369]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4369
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812


Build changes
-------------

  * Linux: CI_DRM_16442 -> Patchwork_147799v2

  CI-20190529: 20190529
  CI_DRM_16442: 7453e9c769c0591f7be7a1bb254905dd2c8be125 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8329: 8329
  Patchwork_147799v2: 7453e9c769c0591f7be7a1bb254905dd2c8be125 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_147799v2/index.html

[-- Attachment #2: Type: text/html, Size: 13484 bytes --]

Re: [PATCH v2 01/13] drm/i915/vrr: Refactor vmin/vmax stuff

[Nautiyal, Ankit K]

On 4/21/2025 9:18 PM, Mitul Golani wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Refactor vmin/vmax functions for better computation.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 41 +++++++++++-------------
>   1 file changed, 19 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index c6565baf815a..adfd231eb578 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -146,37 +146,41 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat
>   		return crtc_state->vrr.pipeline_full + crtc_state->framestart_delay + 1;
>   }
>   
> -int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
> +static int intel_vrr_vtotal(const struct intel_crtc_state *crtc_state, int vmin_vmax)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
>   
> -	/* Min vblank actually determined by flipline */
>   	if (DISPLAY_VER(display) >= 13)
> -		return intel_vrr_vmin_flipline(crtc_state);
> +		return vmin_vmax;
>   	else
> -		return intel_vrr_vmin_flipline(crtc_state) +
> -			intel_vrr_real_vblank_delay(crtc_state);
> +		return vmin_vmax + intel_vrr_real_vblank_delay(crtc_state);
>   }
>   
> -int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
> +static int intel_vrr_vblank_start(const struct intel_crtc_state *crtc_state,
> +				  int vmin_vmax)
>   {
> -	struct intel_display *display = to_intel_display(crtc_state);
> +	return intel_vrr_vtotal(crtc_state, vmin_vmax) -
> +			intel_vrr_vblank_exit_length(crtc_state);
> +}
>   
> -	if (DISPLAY_VER(display) >= 13)
> -		return crtc_state->vrr.vmax;
> -	else
> -		return crtc_state->vrr.vmax +
> -			intel_vrr_real_vblank_delay(crtc_state);
> +int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
> +{
> +	return intel_vrr_vtotal(crtc_state, intel_vrr_vmin_flipline(crtc_state));
> +}
> +
> +int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
> +{
> +	return intel_vrr_vtotal(crtc_state, crtc_state->vrr.vmax);
>   }
>   
>   int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
>   {
> -	return intel_vrr_vmin_vtotal(crtc_state) - intel_vrr_vblank_exit_length(crtc_state);
> +	return intel_vrr_vblank_start(crtc_state, intel_vrr_vmin_flipline(crtc_state));
>   }
>   
>   int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
>   {
> -	return intel_vrr_vmax_vtotal(crtc_state) - intel_vrr_vblank_exit_length(crtc_state);
> +	return intel_vrr_vblank_start(crtc_state, crtc_state->vrr.vmax);
>   }
>   
>   static bool
> @@ -257,14 +261,7 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
>   static
>   int intel_vrr_fixed_rr_vtotal(const struct intel_crtc_state *crtc_state)
>   {
> -	struct intel_display *display = to_intel_display(crtc_state);
> -	int crtc_vtotal = crtc_state->hw.adjusted_mode.crtc_vtotal;
> -
> -	if (DISPLAY_VER(display) >= 13)
> -		return crtc_vtotal;
> -	else
> -		return crtc_vtotal -
> -			intel_vrr_real_vblank_delay(crtc_state);
> +	return intel_vrr_vtotal(crtc_state, crtc_state->hw.adjusted_mode.crtc_vtotal);

This seems to be off for Display < 13.

If I see it correctly, instead of subtracting we are now adding 
intel_vrr_real_vblank_delay(crtc_state);


Can this be rechecked? or I am missing something?

Rest of the changes seem fine.


Regards,

Ankit



>   }
>   
>   static

Re: [PATCH v2 02/13] drm/i915/vrr: Add functions to read out vmin/vmax stuff

[Nautiyal, Ankit K]

On 4/21/2025 9:18 PM, Mitul Golani wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Calculate delayed vblank start position with the help of added
> vmin/vmax stuff for next frame and final computation.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c      | 57 +++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_vrr.h      |  5 ++
>   drivers/gpu/drm/i915/display/intel_vrr_regs.h | 44 ++++++++++++++
>   3 files changed, 106 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index adfd231eb578..1c0eaa08927b 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -746,3 +746,60 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>   	if (crtc_state->vrr.enable)
>   		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>   }
> +
> +int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 tmp;
> +
> +	tmp = intel_de_read(display,
> +			    TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(display, cpu_transcoder));
> +
> +	if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0)
> +		return -1;
> +
> +	return intel_vrr_vblank_start(crtc_state,
> +				      REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_MASK, tmp) + 1);
> +}
> +
> +int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 tmp;
> +
> +	tmp = intel_de_read(display,
> +			    TRANS_VRR_DCB_ADJ_VMAX_CFG(display, cpu_transcoder));
> +
> +	if (REG_FIELD_GET(VRR_DCB_ADJ_VMAX_CNT_MASK, tmp) == 0)
> +		return -1;
> +
> +	return intel_vrr_vblank_start(crtc_state,
> +				      REG_FIELD_GET(VRR_DCB_ADJ_VMAX_MASK, tmp) + 1);
> +}
> +
> +int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 tmp;
> +
> +	tmp = intel_de_read(display,
> +			    TRANS_VRR_FLIPLINE_DCB(display, cpu_transcoder));
> +
> +	return intel_vrr_vblank_start(crtc_state,
> +				      REG_FIELD_GET(VRR_FLIPLINE_DCB_MASK, tmp) + 1);
> +}
> +
> +int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 tmp;
> +
> +	tmp = intel_de_read(display, TRANS_VRR_VMAX_DCB(display, cpu_transcoder));
> +
> +	return intel_vrr_vblank_start(crtc_state,
> +				      REG_FIELD_GET(VRR_VMAX_DCB_MASK, tmp) + 1);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index 38bf9996b883..e62b8b50aec6 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -42,4 +42,9 @@ void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
>   void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
>   bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
>   
> +int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state);
> +int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state);
> +int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
> +int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
> +
>   #endif /* __INTEL_VRR_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> index 6ed0e0dc97e7..2214c10d4084 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> @@ -9,6 +9,50 @@
>   #include "intel_display_reg_defs.h"
>   
>   /* VRR registers */
> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A		0x604D4
> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B		0x614D4
> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_C		0x624D4
> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_D		0x634D4
> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_E		0x6B4D4
For regs for E/F we need to add TRANSCODER_E/F and use _MMIO_TRANS2_ 
with offset of Transocder E.

However, adding these should be fine I guess. Perhaps add offset for F also?


Patch looks good to me though.
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> +#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(dev_priv, trans)	\
> +					_MMIO_TRANS2(dev_priv, \
> +						     trans, \
> +						     _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A)
> +
> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A			0x604D8
> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B			0x614D8
> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_C			0x624D8
> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_D			0x634D8
> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_E			0x6B4D8
> +#define TRANS_VRR_DCB_ADJ_VMAX_CFG(dev_priv, trans)	_MMIO_TRANS2(dev_priv, \
> +								     trans, \
> +								     _TRANS_VRR_DCB_ADJ_VMAX_CFG_A)
> +
> +#define _TRANS_VRR_FLIPLINE_DCB_A		0x60418
> +#define _TRANS_VRR_FLIPLINE_DCB_B		0x61418
> +#define _TRANS_VRR_FLIPLINE_DCB_C		0x62418
> +#define _TRANS_VRR_FLIPLINE_DCB_D		0x63418
> +#define _TRANS_VRR_FLIPLINE_DCB_E		0x6B418
> +#define TRANS_VRR_FLIPLINE_DCB(dev_priv, trans) _MMIO_TRANS2(dev_priv, \
> +							     trans, \
> +							     _TRANS_VRR_FLIPLINE_DCB_A)
> +
> +#define _TRANS_VRR_VMAX_DCB_A			0x60414
> +#define _TRANS_VRR_VMAX_DCB_B			0x61414
> +#define _TRANS_VRR_VMAX_DCB_C			0x62414
> +#define _TRANS_VRR_VMAX_DCB_D			0x63414
> +#define _TRANS_VRR_VMAX_DCB_E			0x6B414
> +#define TRANS_VRR_VMAX_DCB(dev_priv, trans)	_MMIO_TRANS2(dev_priv, \
> +							     trans, \
> +							     _TRANS_VRR_VMAX_DCB_A)
> +
> +#define VRR_DCB_ADJ_FLIPLINE_CNT_MASK		REG_GENMASK(31, 24)
> +#define VRR_DCB_ADJ_FLIPLINE_MASK		REG_GENMASK(19, 0)
> +#define VRR_DCB_ADJ_VMAX_CNT_MASK		REG_GENMASK(31, 24)
> +#define VRR_DCB_ADJ_VMAX_MASK			REG_GENMASK(19, 0)
> +#define VRR_FLIPLINE_DCB_MASK			REG_GENMASK(19, 0)
> +#define VRR_VMAX_DCB_MASK			REG_GENMASK(19, 0)
> +
>   #define _TRANS_VRR_CTL_A			0x60420
>   #define _TRANS_VRR_CTL_B			0x61420
>   #define _TRANS_VRR_CTL_C			0x62420

Re: [PATCH v2 03/13] drm/i915/display: Add source param for dc balance

[Nautiyal, Ankit K]

On 4/21/2025 9:18 PM, Mitul Golani wrote:
> Add source param for dc balance enablement further.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 87c666792c0d..653483fa99ea 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -144,6 +144,7 @@ struct intel_display_platforms {
>   #define HAS_4TILE(__display)		((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
>   #define HAS_ASYNC_FLIPS(__display)	(DISPLAY_VER(__display) >= 5)
>   #define HAS_AS_SDP(__display)		(DISPLAY_VER(__display) >= 13)
> +#define HAS_DC_BALANCE(__display)		(DISPLAY_VER(__display) >= 30)

Add in asciibetical order.

Also HAS VRR_DC_BALANCE or HAS_AS_DC_BALANCE would be better?


Regards,

Ankit

>   #define HAS_BIGJOINER(__display)	(DISPLAY_VER(__display) >= 11 && HAS_DSC(__display))
>   #define HAS_CDCLK_CRAWL(__display)	(DISPLAY_INFO(__display)->has_cdclk_crawl)
>   #define HAS_CDCLK_SQUASH(__display)	(DISPLAY_INFO(__display)->has_cdclk_squash)

Re: [PATCH v2 04/13] drm/i915/vrr: Add enable/disable calls for DC Balance

[Nautiyal, Ankit K]

On 4/21/2025 9:18 PM, Mitul Golani wrote:
> Add enable/disable calls along with required hw registers
> for DC balance enablement.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   .../drm/i915/display/intel_display_types.h    |  7 ++
>   drivers/gpu/drm/i915/display/intel_dmc_regs.h | 71 +++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_vrr.c      | 29 ++++++++
>   drivers/gpu/drm/i915/display/intel_vrr_regs.h | 10 +++
>   4 files changed, 117 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 94468a9d2e0d..126d54e6a393 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1307,6 +1307,13 @@ struct intel_crtc_state {
>   		u8 pipeline_full;
>   		u16 flipline, vmin, vmax, guardband;
>   		u32 vsync_end, vsync_start;
> +		struct {
> +			bool enable;
> +			u16 vmin, vmax;
> +			u16 guardband, slope;
> +			u16 max_increase, max_decrease;
> +			u16 vblank_target;
> +		} dc_balance;
>   	} vrr;
>   
>   	/* Content Match Refresh Rate state */
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> index 1bf446f96a10..39e4f70005ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> @@ -103,4 +103,75 @@
>   #define  DMC_WAKELOCK_CTL_REQ	 REG_BIT(31)
>   #define  DMC_WAKELOCK_CTL_ACK	 REG_BIT(15)
>   
> +#define _PIPEDMC_DCB_CTL_A			0x5F1A0
These are again added in Patch #9
> +#define _PIPEDMC_DCB_CTL_B			0x5F5A0
> +#define _PIPEDMC_DCB_CTL_C			0x5F9A0
> +#define _PIPEDMC_DCB_CTL_D			0x5FDA0
> +#define _PIPEDMC_DCB_CTL_E			0x551A0
> +#define _PIPEDMC_DCB_CTL_F			0x555A0
> +#define PIPEDMC_DCB_CTL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_CTL_A)
> +#define PIPEDMC_ADAPTIVE_DCB_ENABLE		REG_BIT(31)
> +
> +#define _PIPEDMC_DCB_VBLANK_A			0x5F1BC
> +#define _PIPEDMC_DCB_VBLANK_B			0x5F5BC
> +#define _PIPEDMC_DCB_VBLANK_C			0x5F9BC
> +#define _PIPEDMC_DCB_VBLANK_D			0x5FDBC
> +#define _PIPEDMC_DCB_VBLANK_E			0x551BC
> +#define _PIPEDMC_DCB_VBLANK_F			0x555BC
> +#define PIPEDMC_DCB_VBLANK(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_VBLANK_A)
> +
> +#define _PIPEDMC_DCB_SLOPE_A			0x5F1B8
> +#define _PIPEDMC_DCB_SLOPE_B			0x5F5B8
> +#define _PIPEDMC_DCB_SLOPE_C			0x5F9B8
> +#define _PIPEDMC_DCB_SLOPE_D			0x5FDB8
> +#define _PIPEDMC_DCB_SLOPE_E			0x551B8
> +#define _PIPEDMC_DCB_SLOPE_F			0x555B8
> +#define PIPEDMC_DCB_SLOPE(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_SLOPE_A)
> +
> +#define _PIPEDMC_DCB_GUARDBAND_A		0x5F1B4
> +#define _PIPEDMC_DCB_GUARDBAND_B		0x5F5B4
> +#define _PIPEDMC_DCB_GUARDBAND_C		0x5F9B4
> +#define _PIPEDMC_DCB_GUARDBAND_D		0x5FDB4
> +#define _PIPEDMC_DCB_GUARDBAND_E		0x551B4
> +#define _PIPEDMC_DCB_GUARDBAND_F		0x555B4
> +#define PIPEDMC_DCB_GUARDBAND(dev_priv, trans)	_MMIO_TRANS2(dev_priv, \
> +							     trans, \
> +							     _PIPEDMC_DCB_GUARDBAND_A)
> +
> +#define _PIPEDMC_DCB_MAX_INCREASE_A			0x5F1AC
> +#define _PIPEDMC_DCB_MAX_INCREASE_B			0x5F5AC
> +#define _PIPEDMC_DCB_MAX_INCREASE_C			0x5F9AC
> +#define _PIPEDMC_DCB_MAX_INCREASE_D			0x5FDAC
> +#define _PIPEDMC_DCB_MAX_INCREASE_E			0x551AC
> +#define _PIPEDMC_DCB_MAX_INCREASE_F			0x555AC
> +#define PIPEDMC_DCB_MAX_INCREASE(dev_priv, trans)	_MMIO_TRANS2(dev_priv, \
> +								     trans, \
> +								     _PIPEDMC_DCB_MAX_INCREASE_A)
> +
> +#define _PIPEDMC_DCB_MAX_DECREASE_A			0x5F1B0
> +#define _PIPEDMC_DCB_MAX_DECREASE_B			0x5F5B0
> +#define _PIPEDMC_DCB_MAX_DECREASE_C			0x5F9B0
> +#define _PIPEDMC_DCB_MAX_DECREASE_D			0x5FDB0
> +#define _PIPEDMC_DCB_MAX_DECREASE_E			0x551B0
> +#define _PIPEDMC_DCB_MAX_DECREASE_F			0x555B0
> +#define PIPEDMC_DCB_MAX_DECREASE(dev_priv, trans)	_MMIO_TRANS2(dev_priv, \
> +								     trans, \
> +								     _PIPEDMC_DCB_MAX_DECREASE_A)
> +
> +#define _PIPEDMC_DCB_VMIN_A			0x5F1A4
> +#define _PIPEDMC_DCB_VMIN_B			0x5F5A4
> +#define _PIPEDMC_DCB_VMIN_C			0x5F9A4
> +#define _PIPEDMC_DCB_VMIN_D			0x5FDA4
> +#define _PIPEDMC_DCB_VMIN_E			0x551A4
> +#define _PIPEDMC_DCB_VMIN_F			0x555A4
> +#define PIPEDMC_DCB_VMIN(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_VMIN_A)
> +
> +#define _PIPEDMC_DCB_VMAX_A			0x5F1A8
> +#define _PIPEDMC_DCB_VMAX_B			0x5F5A8
> +#define _PIPEDMC_DCB_VMAX_C			0x5F9A8
> +#define _PIPEDMC_DCB_VMAX_D			0x5FDA8
> +#define _PIPEDMC_DCB_VMAX_E			0x551A8
> +#define _PIPEDMC_DCB_VMAX_F			0x555A8
> +#define PIPEDMC_DCB_VMAX(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_VMAX_A)
> +
>   #endif /* __INTEL_DMC_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 1c0eaa08927b..c4fb78d86ab0 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -10,6 +10,7 @@
>   #include "intel_de.h"
>   #include "intel_display_types.h"
>   #include "intel_dp.h"
> +#include "intel_dmc_regs.h"
>   #include "intel_vrr.h"
>   #include "intel_vrr_regs.h"
>   
> @@ -601,6 +602,23 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>   				       VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
>   		}
>   	}
> +
> +	if (crtc_state->vrr.dc_balance.enable && HAS_DC_BALANCE(display)) {
> +		intel_de_write(display, PIPEDMC_DCB_VMIN(display, cpu_transcoder),
> +			       crtc_state->vrr.dc_balance.vmin - 1);
> +		intel_de_write(display, PIPEDMC_DCB_VMAX(display, cpu_transcoder),
> +			       crtc_state->vrr.dc_balance.vmax - 1);
> +		intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(display, cpu_transcoder),
> +			       crtc_state->vrr.dc_balance.max_increase);
> +		intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(display, cpu_transcoder),
> +			       crtc_state->vrr.dc_balance.max_decrease);
> +		intel_de_write(display, PIPEDMC_DCB_GUARDBAND(display, cpu_transcoder),
> +			       crtc_state->vrr.dc_balance.guardband);
> +		intel_de_write(display, PIPEDMC_DCB_SLOPE(display, cpu_transcoder),
> +			       crtc_state->vrr.dc_balance.slope);
> +		intel_de_write(display, PIPEDMC_DCB_VBLANK(display, cpu_transcoder),
> +			       crtc_state->vrr.dc_balance.vblank_target);
> +	}
>   }
>   
>   void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
> @@ -611,6 +629,17 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
>   	if (!old_crtc_state->vrr.enable)
>   		return;
>   
> +	if (old_crtc_state->vrr.dc_balance.enable && HAS_DC_BALANCE(display)) {
> +		intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(display, cpu_transcoder), 0);
> +		intel_de_write(display, PIPEDMC_DCB_VMIN(display, cpu_transcoder), 0);
> +		intel_de_write(display, PIPEDMC_DCB_VMAX(display, cpu_transcoder), 0);
> +		intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(display, cpu_transcoder), 0);
> +		intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(display, cpu_transcoder), 0);
> +		intel_de_write(display, PIPEDMC_DCB_GUARDBAND(display, cpu_transcoder), 0);
> +		intel_de_write(display, PIPEDMC_DCB_SLOPE(display, cpu_transcoder), 0);
> +		intel_de_write(display, PIPEDMC_DCB_VBLANK(display, cpu_transcoder), 0);
> +	}
> +
>   	if (!intel_vrr_always_use_vrr_tg(display)) {
>   		intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
>   			       trans_vrr_ctl(old_crtc_state));
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> index 2214c10d4084..2db477325c83 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> @@ -53,6 +53,16 @@
>   #define VRR_FLIPLINE_DCB_MASK			REG_GENMASK(19, 0)
>   #define VRR_VMAX_DCB_MASK			REG_GENMASK(19, 0)
>   
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A			0x604C0

These are again added in Patch#10.

I think lets have a separate patch where new members are introduced.

Regards,

Ankit

> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B			0x614C0
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_C			0x624C0
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_D			0x634C0
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_E			0x6B4C0
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_F			0x6C4C0
> +#define TRANS_ADAPTIVE_SYNC_DCB_CTL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, \
> +								     trans, \
> +								     _TRANS_ADAPTIVE_SYNC_DCB_CTL_A)
> +
>   #define _TRANS_VRR_CTL_A			0x60420
>   #define _TRANS_VRR_CTL_B			0x61420
>   #define _TRANS_VRR_CTL_C			0x62420

Re: [PATCH v2 05/13] drm/i915/vrr: Add compute config for DC balance params

[Nautiyal, Ankit K]

On 4/21/2025 9:18 PM, Mitul Golani wrote:
> Add compute config for DC balance params. This will be required
> to calculate correct balance requirement for DMC firmware.
Subject can simply be Compute DC balance parameters.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 21 +++++++++++++++++++++
>   1 file changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index c4fb78d86ab0..383024dc2784 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -16,6 +16,9 @@
>   
>   #define FIXED_POINT_PRECISION		100
>   #define CMRR_PRECISION_TOLERANCE	10
> +#define DCB_CORRECTION_SENSITIVITY	30
> +#define DCB_CORRECTION_AGGRESSIVENESS	1000
> +#define DCB_BLANK_TARGET		50

It would be good to document that whether these values are based on some 
experimentation or some golden values.


>   
>   bool intel_vrr_is_capable(struct intel_connector *connector)
>   {
> @@ -409,6 +412,24 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>   			(crtc_state->hw.adjusted_mode.crtc_vtotal -
>   			 crtc_state->hw.adjusted_mode.vsync_end);
>   	}
> +
> +	if (crtc_state->vrr.dc_balance.enable && HAS_DC_BALANCE(display)) {

Perhaps check for HAS_DC_BALANCE() first.

Regards,

Ankit

> +		crtc_state->vrr.dc_balance.vmax = crtc_state->vrr.vmax;
> +		crtc_state->vrr.dc_balance.vmin = crtc_state->vrr.vmin;
> +		crtc_state->vrr.dc_balance.max_increase =
> +			crtc_state->vrr.vmax - crtc_state->vrr.vmin;
> +		crtc_state->vrr.dc_balance.max_decrease =
> +			crtc_state->vrr.vmax - crtc_state->vrr.vmin;
> +		crtc_state->vrr.dc_balance.guardband =
> +		DIV_ROUND_UP(crtc_state->vrr.dc_balance.vmax * DCB_CORRECTION_SENSITIVITY,
> +			     100);
> +		crtc_state->vrr.dc_balance.slope =
> +			DIV_ROUND_UP(DCB_CORRECTION_AGGRESSIVENESS * 10,
> +				     crtc_state->vrr.dc_balance.guardband);
> +		crtc_state->vrr.dc_balance.vblank_target =
> +		DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) * DCB_BLANK_TARGET,
> +			     100);
> +	}
>   }
>   
>   void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)

Re: [PATCH v2 07/13] drm/i915: Extract vrr_vblank_start()

[Nautiyal, Ankit K]

On 4/21/2025 9:18 PM, Mitul Golani wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Initialise delayed vblank position for evasion logic.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_vblank.c | 13 +++++++++----
>   1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
> index 139fa5deba80..680013f00fc0 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -642,6 +642,14 @@ intel_pre_commit_crtc_state(struct intel_atomic_state *state,
>   	return pre_commit_crtc_state(old_crtc_state, new_crtc_state);
>   }
>   
> +static int vrr_vblank_start(const struct intel_crtc_state *crtc_state)
> +{
> +	if (intel_vrr_is_push_sent(crtc_state))
> +		return intel_vrr_vmin_vblank_start(crtc_state);
> +	else
> +		return intel_vrr_vmax_vblank_start(crtc_state);
> +}
> +
>   void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
>   			     const struct intel_crtc_state *new_crtc_state,
>   			     struct intel_vblank_evade_ctx *evade)
> @@ -668,10 +676,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
>   		drm_WARN_ON(crtc->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
>   			    new_crtc_state->update_m_n || new_crtc_state->update_lrr);
>   
> -		if (intel_vrr_is_push_sent(crtc_state))
> -			evade->vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
> -		else
> -			evade->vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
> +		evade->vblank_start = vrr_vblank_start(crtc_state);
>   
>   		vblank_delay = intel_vrr_vblank_delay(crtc_state);
>   	} else {

Re: [PATCH v2 08/13] drm/i915/vrr: Implement vblank evasion with DC balancing

[Nautiyal, Ankit K]

On 4/21/2025 9:18 PM, Mitul Golani wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add vblank evasion logic when vrr is already enabled along with
> dc balance is computed.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_dsb.c    | 31 ++++++++++++++++++++-
>   drivers/gpu/drm/i915/display/intel_vblank.c | 26 +++++++++++++++--
>   2 files changed, 53 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 72fe390c5af2..ffd10ee96e29 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -577,7 +577,36 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
>   	if (crtc_state->has_psr)
>   		intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0);
>   
> -	if (pre_commit_is_vrr_active(state, crtc)) {
> +	if (pre_commit_is_vrr_active(state, crtc) && crtc_state->vrr.dc_balance.enable) {
> +		int vblank_delay = intel_vrr_vblank_delay(crtc_state);
> +		int vmin_vblank_start, vmax_vblank_start;
> +
> +		vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
> +
> +		if (vmin_vblank_start >= 0) {
> +			end = vmin_vblank_start;
> +			start = end - vblank_delay - latency;
> +			intel_dsb_wait_scanline_out(state, dsb, start, end);
> +		}
> +
> +		vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state);
> +
> +		if (vmax_vblank_start >= 0) {
> +			end = vmax_vblank_start;
> +			start = end - vblank_delay - latency;
> +			intel_dsb_wait_scanline_out(state, dsb, start, end);
> +		}
> +
> +		vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state);
> +		end = vmin_vblank_start;
> +		start = end - vblank_delay - latency;
> +		intel_dsb_wait_scanline_out(state, dsb, start, end);
> +
> +		vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state);
> +		end = vmax_vblank_start;
> +		start = end - vblank_delay - latency;
> +		intel_dsb_wait_scanline_out(state, dsb, start, end);
> +	} else if (pre_commit_is_vrr_active(state, crtc)) {
>   		int vblank_delay = intel_vrr_vblank_delay(crtc_state);
>   
>   		end = intel_vrr_vmin_vblank_start(crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
> index 680013f00fc0..eb74d08d6690 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -644,10 +644,30 @@ intel_pre_commit_crtc_state(struct intel_atomic_state *state,
>   
>   static int vrr_vblank_start(const struct intel_crtc_state *crtc_state)
>   {
> -	if (intel_vrr_is_push_sent(crtc_state))
> -		return intel_vrr_vmin_vblank_start(crtc_state);
> +	bool is_push_sent = intel_vrr_is_push_sent(crtc_state);
> +	int vblank_start;
> +
> +	if (!crtc_state->vrr.dc_balance.enable) {
> +		if (is_push_sent)
> +			return intel_vrr_vmin_vblank_start(crtc_state);
> +		else
> +			return intel_vrr_vmax_vblank_start(crtc_state);
> +	}
> +
> +	if (is_push_sent)
> +		vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state);
>   	else
> -		return intel_vrr_vmax_vblank_start(crtc_state);
> +		vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state);
> +
> +	if (vblank_start >= 0)
> +		return vblank_start;
> +
> +	if (is_push_sent)
> +		vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state);
> +	else
> +		vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state);
> +
> +	return vblank_start;
>   }
>   
>   void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,

Re: [PATCH v2 09/13] drm/i915/dsb: Add pipedmc dc balance enable/disable

[Nautiyal, Ankit K]

On 4/21/2025 9:18 PM, Mitul Golani wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add function to control DC balance enable/disable bit via DSB.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_dmc.c      | 24 +++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_dmc.h      |  5 ++++
>   drivers/gpu/drm/i915/display/intel_dmc_regs.h |  9 +++++++
>   3 files changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index ff2b97a752b1..e32599a4f68f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -30,6 +30,7 @@
>   #include "intel_de.h"
>   #include "intel_display_rpm.h"
>   #include "intel_display_power_well.h"
> +#include "intel_display_types.h"
>   #include "intel_dmc.h"
>   #include "intel_dmc_regs.h"
>   #include "intel_step.h"
> @@ -1355,3 +1356,26 @@ void intel_dmc_debugfs_register(struct intel_display *display)
>   	debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root,
>   			    display, &intel_dmc_debugfs_status_fops);
>   }
> +
> +void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	struct intel_crtc_state *crtc_state =
> +		to_intel_crtc_state(crtc->base.state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	intel_de_write_dsb(display, dsb,
> +			   PIPEDMC_DCB_CTL(display, cpu_transcoder),
> +			   PIPEDMC_ADAPTIVE_DCB_ENABLE);
> +}
> +
> +void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	struct intel_crtc_state *crtc_state =
> +		to_intel_crtc_state(crtc->base.state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	intel_de_write_dsb(display, dsb,
> +			   PIPEDMC_DCB_CTL(display, cpu_transcoder), 0);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
> index c78426eb4cd5..74dcd142f5b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> @@ -10,8 +10,10 @@
>   
>   enum pipe;
>   struct drm_printer;
> +struct intel_crtc;
>   struct intel_display;
>   struct intel_dmc_snapshot;
> +struct intel_dsb;
>   
>   void intel_dmc_init(struct intel_display *display);
>   void intel_dmc_load_program(struct intel_display *display);
> @@ -30,4 +32,7 @@ void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool star
>   
>   void assert_dmc_loaded(struct intel_display *display);
>   
> +void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc);
> +void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc);
> +
>   #endif /* __INTEL_DMC_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> index 39e4f70005ab..6788afb816ea 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> @@ -174,4 +174,13 @@
>   #define _PIPEDMC_DCB_VMAX_F			0x555A8
>   #define PIPEDMC_DCB_VMAX(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_VMAX_A)
>   
> +#define _PIPEDMC_DCB_CTL_A			0x5F1A0
> +#define _PIPEDMC_DCB_CTL_B			0x5F5A0
> +#define _PIPEDMC_DCB_CTL_C			0x5F9A0
> +#define _PIPEDMC_DCB_CTL_D			0x5FDA0
> +#define _PIPEDMC_DCB_CTL_E			0x551A0
> +#define _PIPEDMC_DCB_CTL_F			0x555A0
> +#define PIPEDMC_DCB_CTL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _PIPEDMC_DCB_CTL_A)
> +#define PIPEDMC_ADAPTIVE_DCB_ENABLE		REG_BIT(31)
> +
>   #endif /* __INTEL_DMC_REGS_H__ */

Re: [PATCH v2 10/13] drm/i915/vrr: Pause DC balancing for DSB commits

[Nautiyal, Ankit K]

On 4/21/2025 9:18 PM, Mitul Golani wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Pause the DMC DC balancing for the remainder of the
> commit so that vmin/vmax won't change after we've baked
> them into the DSB vblank evasion commands.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_display.c  | 13 +++++++
>   drivers/gpu/drm/i915/display/intel_vrr.c      | 38 +++++++++++++------
>   drivers/gpu/drm/i915/display/intel_vrr_regs.h | 12 ++++++
>   3 files changed, 51 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 33c09999c42e..274d01552ccf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7194,6 +7194,17 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
>   	}
>   
>   	if (new_crtc_state->use_dsb) {
> +		/*
> +		 * Pause the DMC DC balancing for the remainder of the
> +		 * commit so that vmin/vmax won't change after we've baked
> +		 * them into the DSB vblank evasion commands.
> +		 *
> +		 * FIXME maybe need a small delay here to make sure DMC has
> +		 * finished updating the values? Or we need a better DMC<->driver
> +		 * protocol that gives is real guarantees about that...
> +		 */
> +		intel_pipedmc_dcb_disable(NULL, crtc);
> +
>   		if (intel_crtc_needs_color_update(new_crtc_state))
>   			intel_color_commit_noarm(new_crtc_state->dsb_commit,
>   						 new_crtc_state);
> @@ -7230,6 +7241,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
>   			intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state);
>   			intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit);
>   			intel_vrr_check_push_sent(new_crtc_state->dsb_commit, new_crtc_state);
> +			if (new_crtc_state->vrr.dc_balance.enable)
> +				intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit, crtc);
>   			intel_dsb_interrupt(new_crtc_state->dsb_commit);
>   		}
>   	}
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 383024dc2784..fb96d03bbf03 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -9,6 +9,7 @@
>   #include "i915_reg.h"
>   #include "intel_de.h"
>   #include "intel_display_types.h"
> +#include "intel_dmc.h"
>   #include "intel_dp.h"
>   #include "intel_dmc_regs.h"
>   #include "intel_vrr.h"
> @@ -598,7 +599,9 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display)
>   void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 ctl;
>   
>   	if (!crtc_state->vrr.enable)
>   		return;
> @@ -609,20 +612,19 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>   		       crtc_state->vrr.vmax - 1);
>   	intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
>   		       crtc_state->vrr.flipline - 1);
> +	if (!intel_vrr_always_use_vrr_tg(display))
> +		intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN);

This doesn't make any sense. Perhaps a typo.


>   
>   	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
>   		       TRANS_PUSH_EN);
>   
> -	if (!intel_vrr_always_use_vrr_tg(display)) {
> -		if (crtc_state->cmrr.enable) {
> -			intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> -				       VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
> -				       trans_vrr_ctl(crtc_state));
> -		} else {
> -			intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> -				       VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
> -		}
> -	}
> +	ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
> +	if (crtc_state->cmrr.enable)
> +		ctl |= VRR_CTL_CMRR_ENABLE;
> +	if (crtc_state->vrr.dc_balance.enable)
> +		ctl |= VRR_CTL_DCB_ADJ_ENABLE;
This seems to be doing couple of things at a time. Is it possible to 
break this into 2 patches?

Can the setting of VRR_CTL_DCB_ADJ_ENABLE bit and setting 
ADAPTIVE_SYNC_COUNTER_EN in reg TRANS_ADAPTIVE_SYNC_DCB_CTL be a 
separate patch?

Regards,

Ankit

> +
> +	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl);
>   
>   	if (crtc_state->vrr.dc_balance.enable && HAS_DC_BALANCE(display)) {
>   		intel_de_write(display, PIPEDMC_DCB_VMIN(display, cpu_transcoder),
> @@ -639,18 +641,26 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>   			       crtc_state->vrr.dc_balance.slope);
>   		intel_de_write(display, PIPEDMC_DCB_VBLANK(display, cpu_transcoder),
>   			       crtc_state->vrr.dc_balance.vblank_target);
> +		/* FIXME reset counters? */
> +		intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(display, cpu_transcoder),
> +			       ADAPTIVE_SYNC_COUNTER_EN);
> +		/* FIMXE configure pipedmc DC balance parameters somewhere */
> +		intel_pipedmc_dcb_enable(NULL, crtc);
>   	}
>   }
>   
>   void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(old_crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>   	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
> +	u32 ctl;
>   
>   	if (!old_crtc_state->vrr.enable)
>   		return;
>   
>   	if (old_crtc_state->vrr.dc_balance.enable && HAS_DC_BALANCE(display)) {
> +		intel_pipedmc_dcb_disable(NULL, crtc);
>   		intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(display, cpu_transcoder), 0);
>   		intel_de_write(display, PIPEDMC_DCB_VMIN(display, cpu_transcoder), 0);
>   		intel_de_write(display, PIPEDMC_DCB_VMAX(display, cpu_transcoder), 0);
> @@ -661,9 +671,13 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
>   		intel_de_write(display, PIPEDMC_DCB_VBLANK(display, cpu_transcoder), 0);
>   	}
>   
> +	ctl = trans_vrr_ctl(old_crtc_state);
> +	if (intel_vrr_always_use_vrr_tg(display))
> +		ctl |= VRR_CTL_VRR_ENABLE;
> +
> +	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl);
> +
>   	if (!intel_vrr_always_use_vrr_tg(display)) {
> -		intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> -			       trans_vrr_ctl(old_crtc_state));
>   		intel_de_wait_for_clear(display,
>   					TRANS_VRR_STATUS(display, cpu_transcoder),
>   					VRR_STATUS_VRR_EN_LIVE, 1000);
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> index 2db477325c83..a88fcd69111f 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> @@ -63,6 +63,17 @@
>   								     trans, \
>   								     _TRANS_ADAPTIVE_SYNC_DCB_CTL_A)
>   
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A			0x604C0
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B			0x614C0
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_C			0x624C0
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_D			0x634C0
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_E			0x6B4C0
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_F			0x6C4C0
> +#define TRANS_ADAPTIVE_SYNC_DCB_CTL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, \
> +								     trans, \
> +								     _TRANS_ADAPTIVE_SYNC_DCB_CTL_A)
> +#define  ADAPTIVE_SYNC_COUNTER_EN			REG_BIT(31)
> +
>   #define _TRANS_VRR_CTL_A			0x60420
>   #define _TRANS_VRR_CTL_B			0x61420
>   #define _TRANS_VRR_CTL_C			0x62420
> @@ -71,6 +82,7 @@
>   #define  VRR_CTL_VRR_ENABLE			REG_BIT(31)
>   #define  VRR_CTL_IGN_MAX_SHIFT			REG_BIT(30)
>   #define  VRR_CTL_FLIP_LINE_EN			REG_BIT(29)
> +#define  VRR_CTL_DCB_ADJ_ENABLE			REG_BIT(28)
>   #define  VRR_CTL_PIPELINE_FULL_MASK		REG_GENMASK(10, 3)
>   #define  VRR_CTL_PIPELINE_FULL(x)		REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
>   #define  VRR_CTL_PIPELINE_FULL_OVERRIDE		REG_BIT(0)

Re: [PATCH v2 11/13] drm/i915/vrr: Add state checker for dc balance params

[Nautiyal, Ankit K]

On 4/21/2025 9:18 PM, Mitul Golani wrote:
> Add state checker for dc balance params. Also add macro to
> check source support.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_display.c |  7 +++++++
>   drivers/gpu/drm/i915/display/intel_vrr.c     | 20 +++++++++++++++++++-
>   2 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 274d01552ccf..4a21acb88aa7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5402,6 +5402,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>   		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
>   		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
>   		PIPE_CONF_CHECK_BOOL(cmrr.enable);
> +		PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
Add check for vrr.dc_balance.enable?
> +		PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
> +		PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
> +		PIPE_CONF_CHECK_I(vrr.dc_balance.slope);
> +		PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase);
> +		PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease);
> +		PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target);
>   	}
>   
>   	if (!fastset || intel_vrr_always_use_vrr_tg(display)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index fb96d03bbf03..e8802348e5fa 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -740,7 +740,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
>   	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> -	u32 trans_vrr_ctl, trans_vrr_vsync;
> +	u32 trans_vrr_ctl, trans_vrr_vsync, dcb_ctl;
>   	bool vrr_enable;
>   
>   	trans_vrr_ctl = intel_de_read(display,
> @@ -802,6 +802,24 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>   	else
>   		crtc_state->vrr.enable = vrr_enable;
>   
> +	if (HAS_DC_BALANCE(display)) {
> +		dcb_ctl = intel_de_read(display, PIPEDMC_DCB_CTL(display, cpu_transcoder));

dsb_ctl is not used. Need to use it for vrr.dc_balance.enable.


IMO we can introduce the new members (which is done in Patch#4), readout 
and state checker in one patch.

Regards,

Ankit


> +		crtc_state->vrr.dc_balance.vmin =
> +			intel_de_read(display, PIPEDMC_DCB_VMIN(display, cpu_transcoder)) + 1;
> +		crtc_state->vrr.dc_balance.vmax =
> +			intel_de_read(display, PIPEDMC_DCB_VMAX(display, cpu_transcoder)) + 1;
> +		crtc_state->vrr.dc_balance.guardband =
> +			intel_de_read(display, PIPEDMC_DCB_GUARDBAND(display, cpu_transcoder));
> +		crtc_state->vrr.dc_balance.max_increase =
> +			intel_de_read(display, PIPEDMC_DCB_MAX_INCREASE(display, cpu_transcoder));
> +		crtc_state->vrr.dc_balance.max_decrease =
> +			intel_de_read(display, PIPEDMC_DCB_MAX_DECREASE(display, cpu_transcoder));
> +		crtc_state->vrr.dc_balance.slope =
> +			intel_de_read(display, PIPEDMC_DCB_SLOPE(display, cpu_transcoder));
> +		crtc_state->vrr.dc_balance.vblank_target =
> +			intel_de_read(display, PIPEDMC_DCB_VBLANK(display, cpu_transcoder));
> +	}
> +
>   	/*
>   	 * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags.
>   	 * Since CMRR is currently disabled, set this flag for VRR for now.

Re: [PATCH v2 12/13] drm/i915/display: Prepare state checker for dc balance enable

[Nautiyal, Ankit K]

On 4/21/2025 9:18 PM, Mitul Golani wrote:
> Prepare state check param for enabling dc balance enable bit.

This patch can be squashed into the previous patch.

Regards,

Ankit

>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_display.c | 1 +
>   drivers/gpu/drm/i915/display/intel_vrr.c     | 1 +
>   2 files changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 4a21acb88aa7..0bb39134f52d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5402,6 +5402,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>   		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
>   		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
>   		PIPE_CONF_CHECK_BOOL(cmrr.enable);
> +		PIPE_CONF_CHECK_BOOL(vrr.dc_balance.enable);
>   		PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
>   		PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
>   		PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index e8802348e5fa..7c09f384a684 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -804,6 +804,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>   
>   	if (HAS_DC_BALANCE(display)) {
>   		dcb_ctl = intel_de_read(display, PIPEDMC_DCB_CTL(display, cpu_transcoder));
> +		crtc_state->vrr.dc_balance.enable = dcb_ctl & PIPEDMC_ADAPTIVE_DCB_ENABLE;
>   		crtc_state->vrr.dc_balance.vmin =
>   			intel_de_read(display, PIPEDMC_DCB_VMIN(display, cpu_transcoder)) + 1;
>   		crtc_state->vrr.dc_balance.vmax =

Re: [PATCH v2 13/13] drm/i915/vrr: enable dc balance bit

[Nautiyal, Ankit K]

On 4/21/2025 9:19 PM, Mitul Golani wrote:
> enable dc balance from vrr compute config when vrr is
s/enable/Enable
> enabled in adaptive vtotal mode

Nitpick: Add fullstop.

With above fixed:

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 5 +++++
>   1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 7c09f384a684..a21dbbce9ac7 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -255,7 +255,12 @@ void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
>   static
>   void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state)
>   {
> +	struct intel_display *display = to_intel_display(crtc_state);
>   	crtc_state->vrr.enable = true;
> +
> +	if (HAS_DC_BALANCE(display))
> +		crtc_state->vrr.dc_balance.enable = true;
> +
>   	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>   }
>   

Re: [PATCH v2 06/13] drm/i915/vrr: Add state dump for dc balance params

[Nautiyal, Ankit K]

On 4/21/2025 9:18 PM, Mitul Golani wrote:
> Add state dump for dc balance params to track dc balance
> crtc state config.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 9 ++++++++-
>   1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index 0c7f91046996..9baafc63d9ea 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -304,7 +304,14 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
>   	drm_printf(&p, "vrr: vmin vblank: %d, vmax vblank: %d, vmin vtotal: %d, vmax vtotal: %d\n",
>   		   intel_vrr_vmin_vblank_start(pipe_config), intel_vrr_vmax_vblank_start(pipe_config),
>   		   intel_vrr_vmin_vtotal(pipe_config), intel_vrr_vmax_vtotal(pipe_config));
> -
> +	drm_printf(&p, "vrr: dc balance: %s, vmin: %d vmax: %d guardband: %d, slope: %d max increase: %d max decrease: %d Vblank target: %d\n",
> +		   str_yes_no(pipe_config->vrr.dc_balance.enable),
> +		   pipe_config->vrr.dc_balance.vmin, pipe_config->vrr.dc_balance.vmax,
> +		   pipe_config->vrr.dc_balance.guardband,
> +		   pipe_config->vrr.dc_balance.slope,
> +		   pipe_config->vrr.dc_balance.max_increase,
> +		   pipe_config->vrr.dc_balance.max_decrease,
> +		   pipe_config->vrr.dc_balance.vblank_target);
>   	drm_printf(&p, "requested mode: " DRM_MODE_FMT "\n",
>   		   DRM_MODE_ARG(&pipe_config->hw.mode));
>   	drm_printf(&p, "adjusted mode: " DRM_MODE_FMT "\n",

Re: [PATCH v2 11/13] drm/i915/vrr: Add state checker for dc balance params

[Jani Nikula]

On Wed, 23 Apr 2025, "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com> wrote:
> On 4/21/2025 9:18 PM, Mitul Golani wrote:
>> Add state checker for dc balance params. Also add macro to
>> check source support.
>>
>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c |  7 +++++++
>>   drivers/gpu/drm/i915/display/intel_vrr.c     | 20 +++++++++++++++++++-
>>   2 files changed, 26 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 274d01552ccf..4a21acb88aa7 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -5402,6 +5402,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>>   		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
>>   		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
>>   		PIPE_CONF_CHECK_BOOL(cmrr.enable);
>> +		PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
> Add check for vrr.dc_balance.enable?

They should match regardless, no? Something's wrong if they differ.

>> +		PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
>> +		PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
>> +		PIPE_CONF_CHECK_I(vrr.dc_balance.slope);
>> +		PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase);
>> +		PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease);
>> +		PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target);
>>   	}
>>   
>>   	if (!fastset || intel_vrr_always_use_vrr_tg(display)) {
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index fb96d03bbf03..e8802348e5fa 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -740,7 +740,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>>   {
>>   	struct intel_display *display = to_intel_display(crtc_state);
>>   	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> -	u32 trans_vrr_ctl, trans_vrr_vsync;
>> +	u32 trans_vrr_ctl, trans_vrr_vsync, dcb_ctl;
>>   	bool vrr_enable;
>>   
>>   	trans_vrr_ctl = intel_de_read(display,
>> @@ -802,6 +802,24 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>>   	else
>>   		crtc_state->vrr.enable = vrr_enable;
>>   
>> +	if (HAS_DC_BALANCE(display)) {
>> +		dcb_ctl = intel_de_read(display, PIPEDMC_DCB_CTL(display, cpu_transcoder));
>
> dsb_ctl is not used. Need to use it for vrr.dc_balance.enable.
>
>
> IMO we can introduce the new members (which is done in Patch#4), readout 
> and state checker in one patch.
>
> Regards,
>
> Ankit
>
>
>> +		crtc_state->vrr.dc_balance.vmin =
>> +			intel_de_read(display, PIPEDMC_DCB_VMIN(display, cpu_transcoder)) + 1;
>> +		crtc_state->vrr.dc_balance.vmax =
>> +			intel_de_read(display, PIPEDMC_DCB_VMAX(display, cpu_transcoder)) + 1;
>> +		crtc_state->vrr.dc_balance.guardband =
>> +			intel_de_read(display, PIPEDMC_DCB_GUARDBAND(display, cpu_transcoder));
>> +		crtc_state->vrr.dc_balance.max_increase =
>> +			intel_de_read(display, PIPEDMC_DCB_MAX_INCREASE(display, cpu_transcoder));
>> +		crtc_state->vrr.dc_balance.max_decrease =
>> +			intel_de_read(display, PIPEDMC_DCB_MAX_DECREASE(display, cpu_transcoder));
>> +		crtc_state->vrr.dc_balance.slope =
>> +			intel_de_read(display, PIPEDMC_DCB_SLOPE(display, cpu_transcoder));
>> +		crtc_state->vrr.dc_balance.vblank_target =
>> +			intel_de_read(display, PIPEDMC_DCB_VBLANK(display, cpu_transcoder));
>> +	}
>> +
>>   	/*
>>   	 * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags.
>>   	 * Since CMRR is currently disabled, set this flag for VRR for now.

-- 
Jani Nikula, Intel

Re: [PATCH v2 11/13] drm/i915/vrr: Add state checker for dc balance params

[Nautiyal, Ankit K]

On 4/23/2025 3:51 PM, Jani Nikula wrote:
> On Wed, 23 Apr 2025, "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com> wrote:
>> On 4/21/2025 9:18 PM, Mitul Golani wrote:
>>> Add state checker for dc balance params. Also add macro to
>>> check source support.
>>>
>>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/display/intel_display.c |  7 +++++++
>>>    drivers/gpu/drm/i915/display/intel_vrr.c     | 20 +++++++++++++++++++-
>>>    2 files changed, 26 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>>> index 274d01552ccf..4a21acb88aa7 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>> @@ -5402,6 +5402,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>>>    		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
>>>    		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
>>>    		PIPE_CONF_CHECK_BOOL(cmrr.enable);
>>> +		PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
>> Add check for vrr.dc_balance.enable?
> They should match regardless, no? Something's wrong if they differ.


Hmm... as I understand when we are in fixed refresh rate mode this will 
not be enabled.

This gets enabled only when VRR is enabled from the user-space, so they 
can be different.

Regards,

Ankit



>
>>> +		PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
>>> +		PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
>>> +		PIPE_CONF_CHECK_I(vrr.dc_balance.slope);
>>> +		PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase);
>>> +		PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease);
>>> +		PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target);
>>>    	}
>>>    
>>>    	if (!fastset || intel_vrr_always_use_vrr_tg(display)) {
>>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>>> index fb96d03bbf03..e8802348e5fa 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>>> @@ -740,7 +740,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>>>    {
>>>    	struct intel_display *display = to_intel_display(crtc_state);
>>>    	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>>> -	u32 trans_vrr_ctl, trans_vrr_vsync;
>>> +	u32 trans_vrr_ctl, trans_vrr_vsync, dcb_ctl;
>>>    	bool vrr_enable;
>>>    
>>>    	trans_vrr_ctl = intel_de_read(display,
>>> @@ -802,6 +802,24 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>>>    	else
>>>    		crtc_state->vrr.enable = vrr_enable;
>>>    
>>> +	if (HAS_DC_BALANCE(display)) {
>>> +		dcb_ctl = intel_de_read(display, PIPEDMC_DCB_CTL(display, cpu_transcoder));
>> dsb_ctl is not used. Need to use it for vrr.dc_balance.enable.
>>
>>
>> IMO we can introduce the new members (which is done in Patch#4), readout
>> and state checker in one patch.
>>
>> Regards,
>>
>> Ankit
>>
>>
>>> +		crtc_state->vrr.dc_balance.vmin =
>>> +			intel_de_read(display, PIPEDMC_DCB_VMIN(display, cpu_transcoder)) + 1;
>>> +		crtc_state->vrr.dc_balance.vmax =
>>> +			intel_de_read(display, PIPEDMC_DCB_VMAX(display, cpu_transcoder)) + 1;
>>> +		crtc_state->vrr.dc_balance.guardband =
>>> +			intel_de_read(display, PIPEDMC_DCB_GUARDBAND(display, cpu_transcoder));
>>> +		crtc_state->vrr.dc_balance.max_increase =
>>> +			intel_de_read(display, PIPEDMC_DCB_MAX_INCREASE(display, cpu_transcoder));
>>> +		crtc_state->vrr.dc_balance.max_decrease =
>>> +			intel_de_read(display, PIPEDMC_DCB_MAX_DECREASE(display, cpu_transcoder));
>>> +		crtc_state->vrr.dc_balance.slope =
>>> +			intel_de_read(display, PIPEDMC_DCB_SLOPE(display, cpu_transcoder));
>>> +		crtc_state->vrr.dc_balance.vblank_target =
>>> +			intel_de_read(display, PIPEDMC_DCB_VBLANK(display, cpu_transcoder));
>>> +	}
>>> +
>>>    	/*
>>>    	 * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags.
>>>    	 * Since CMRR is currently disabled, set this flag for VRR for now.

Re: [PATCH v2 02/13] drm/i915/vrr: Add functions to read out vmin/vmax stuff

[Nautiyal, Ankit K]

On 4/21/2025 9:18 PM, Mitul Golani wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Calculate delayed vblank start position with the help of added
> vmin/vmax stuff for next frame and final computation.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c      | 57 +++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_vrr.h      |  5 ++
>   drivers/gpu/drm/i915/display/intel_vrr_regs.h | 44 ++++++++++++++
>   3 files changed, 106 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index adfd231eb578..1c0eaa08927b 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -746,3 +746,60 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
>   	if (crtc_state->vrr.enable)
>   		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>   }
> +
> +int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 tmp;
> +
> +	tmp = intel_de_read(display,
> +			    TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(display, cpu_transcoder));

These might be needing a check for HAS_DC_BALANCE. This might explain 
the BAT issues.

Regards,

Ankit

> +
> +	if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0)
> +		return -1;
> +
> +	return intel_vrr_vblank_start(crtc_state,
> +				      REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_MASK, tmp) + 1);
> +}
> +
> +int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 tmp;
> +
> +	tmp = intel_de_read(display,
> +			    TRANS_VRR_DCB_ADJ_VMAX_CFG(display, cpu_transcoder));
> +
> +	if (REG_FIELD_GET(VRR_DCB_ADJ_VMAX_CNT_MASK, tmp) == 0)
> +		return -1;
> +
> +	return intel_vrr_vblank_start(crtc_state,
> +				      REG_FIELD_GET(VRR_DCB_ADJ_VMAX_MASK, tmp) + 1);
> +}
> +
> +int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 tmp;
> +
> +	tmp = intel_de_read(display,
> +			    TRANS_VRR_FLIPLINE_DCB(display, cpu_transcoder));
> +
> +	return intel_vrr_vblank_start(crtc_state,
> +				      REG_FIELD_GET(VRR_FLIPLINE_DCB_MASK, tmp) + 1);
> +}
> +
> +int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 tmp;
> +
> +	tmp = intel_de_read(display, TRANS_VRR_VMAX_DCB(display, cpu_transcoder));
> +
> +	return intel_vrr_vblank_start(crtc_state,
> +				      REG_FIELD_GET(VRR_VMAX_DCB_MASK, tmp) + 1);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index 38bf9996b883..e62b8b50aec6 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -42,4 +42,9 @@ void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
>   void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
>   bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
>   
> +int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state);
> +int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state);
> +int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
> +int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
> +
>   #endif /* __INTEL_VRR_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> index 6ed0e0dc97e7..2214c10d4084 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> @@ -9,6 +9,50 @@
>   #include "intel_display_reg_defs.h"
>   
>   /* VRR registers */
> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A		0x604D4
> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B		0x614D4
> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_C		0x624D4
> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_D		0x634D4
> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_E		0x6B4D4
> +#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(dev_priv, trans)	\
> +					_MMIO_TRANS2(dev_priv, \
> +						     trans, \
> +						     _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A)
> +
> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A			0x604D8
> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B			0x614D8
> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_C			0x624D8
> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_D			0x634D8
> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_E			0x6B4D8
> +#define TRANS_VRR_DCB_ADJ_VMAX_CFG(dev_priv, trans)	_MMIO_TRANS2(dev_priv, \
> +								     trans, \
> +								     _TRANS_VRR_DCB_ADJ_VMAX_CFG_A)
> +
> +#define _TRANS_VRR_FLIPLINE_DCB_A		0x60418
> +#define _TRANS_VRR_FLIPLINE_DCB_B		0x61418
> +#define _TRANS_VRR_FLIPLINE_DCB_C		0x62418
> +#define _TRANS_VRR_FLIPLINE_DCB_D		0x63418
> +#define _TRANS_VRR_FLIPLINE_DCB_E		0x6B418
> +#define TRANS_VRR_FLIPLINE_DCB(dev_priv, trans) _MMIO_TRANS2(dev_priv, \
> +							     trans, \
> +							     _TRANS_VRR_FLIPLINE_DCB_A)
> +
> +#define _TRANS_VRR_VMAX_DCB_A			0x60414
> +#define _TRANS_VRR_VMAX_DCB_B			0x61414
> +#define _TRANS_VRR_VMAX_DCB_C			0x62414
> +#define _TRANS_VRR_VMAX_DCB_D			0x63414
> +#define _TRANS_VRR_VMAX_DCB_E			0x6B414
> +#define TRANS_VRR_VMAX_DCB(dev_priv, trans)	_MMIO_TRANS2(dev_priv, \
> +							     trans, \
> +							     _TRANS_VRR_VMAX_DCB_A)
> +
> +#define VRR_DCB_ADJ_FLIPLINE_CNT_MASK		REG_GENMASK(31, 24)
> +#define VRR_DCB_ADJ_FLIPLINE_MASK		REG_GENMASK(19, 0)
> +#define VRR_DCB_ADJ_VMAX_CNT_MASK		REG_GENMASK(31, 24)
> +#define VRR_DCB_ADJ_VMAX_MASK			REG_GENMASK(19, 0)
> +#define VRR_FLIPLINE_DCB_MASK			REG_GENMASK(19, 0)
> +#define VRR_VMAX_DCB_MASK			REG_GENMASK(19, 0)
> +
>   #define _TRANS_VRR_CTL_A			0x60420
>   #define _TRANS_VRR_CTL_B			0x61420
>   #define _TRANS_VRR_CTL_C			0x62420

Re: [PATCH v2 02/13] drm/i915/vrr: Add functions to read out vmin/vmax stuff

[Nautiyal, Ankit K]

On 4/23/2025 6:47 PM, Nautiyal, Ankit K wrote:
>
> On 4/21/2025 9:18 PM, Mitul Golani wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Calculate delayed vblank start position with the help of added
>> vmin/vmax stuff for next frame and final computation.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_vrr.c      | 57 +++++++++++++++++++
>>   drivers/gpu/drm/i915/display/intel_vrr.h      |  5 ++
>>   drivers/gpu/drm/i915/display/intel_vrr_regs.h | 44 ++++++++++++++
>>   3 files changed, 106 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
>> b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index adfd231eb578..1c0eaa08927b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -746,3 +746,60 @@ void intel_vrr_get_config(struct 
>> intel_crtc_state *crtc_state)
>>       if (crtc_state->vrr.enable)
>>           crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>>   }
>> +
>> +int intel_vrr_dcb_vmin_vblank_start_next(const struct 
>> intel_crtc_state *crtc_state)
>> +{
>> +    struct intel_display *display = to_intel_display(crtc_state);
>> +    enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> +    u32 tmp;
>> +
>> +    tmp = intel_de_read(display,
>> +                TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(display, 
>> cpu_transcoder));
>
> These might be needing a check for HAS_DC_BALANCE. This might explain 
> the BAT issues.


Scratch that, these are used only when vrr.dc_balance.enable is set, so 
these might not be the cause.


>
> Regards,
>
> Ankit
>
>> +
>> +    if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0)
>> +        return -1;
>> +
>> +    return intel_vrr_vblank_start(crtc_state,
>> +                      REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_MASK, tmp) 
>> + 1);
>> +}
>> +
>> +int intel_vrr_dcb_vmax_vblank_start_next(const struct 
>> intel_crtc_state *crtc_state)
>> +{
>> +    struct intel_display *display = to_intel_display(crtc_state);
>> +    enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> +    u32 tmp;
>> +
>> +    tmp = intel_de_read(display,
>> +                TRANS_VRR_DCB_ADJ_VMAX_CFG(display, cpu_transcoder));
>> +
>> +    if (REG_FIELD_GET(VRR_DCB_ADJ_VMAX_CNT_MASK, tmp) == 0)
>> +        return -1;
>> +
>> +    return intel_vrr_vblank_start(crtc_state,
>> +                      REG_FIELD_GET(VRR_DCB_ADJ_VMAX_MASK, tmp) + 1);
>> +}
>> +
>> +int intel_vrr_dcb_vmin_vblank_start_final(const struct 
>> intel_crtc_state *crtc_state)
>> +{
>> +    struct intel_display *display = to_intel_display(crtc_state);
>> +    enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> +    u32 tmp;
>> +
>> +    tmp = intel_de_read(display,
>> +                TRANS_VRR_FLIPLINE_DCB(display, cpu_transcoder));
>> +
>> +    return intel_vrr_vblank_start(crtc_state,
>> +                      REG_FIELD_GET(VRR_FLIPLINE_DCB_MASK, tmp) + 1);
>> +}
>> +
>> +int intel_vrr_dcb_vmax_vblank_start_final(const struct 
>> intel_crtc_state *crtc_state)
>> +{
>> +    struct intel_display *display = to_intel_display(crtc_state);
>> +    enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> +    u32 tmp;
>> +
>> +    tmp = intel_de_read(display, TRANS_VRR_VMAX_DCB(display, 
>> cpu_transcoder));
>> +
>> +    return intel_vrr_vblank_start(crtc_state,
>> +                      REG_FIELD_GET(VRR_VMAX_DCB_MASK, tmp) + 1);
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h 
>> b/drivers/gpu/drm/i915/display/intel_vrr.h
>> index 38bf9996b883..e62b8b50aec6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
>> @@ -42,4 +42,9 @@ void intel_vrr_transcoder_disable(const struct 
>> intel_crtc_state *crtc_state);
>>   void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state 
>> *crtc_state);
>>   bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
>>   +int intel_vrr_dcb_vmin_vblank_start_next(const struct 
>> intel_crtc_state *crtc_state);
>> +int intel_vrr_dcb_vmax_vblank_start_next(const struct 
>> intel_crtc_state *crtc_state);
>> +int intel_vrr_dcb_vmin_vblank_start_final(const struct 
>> intel_crtc_state *crtc_state);
>> +int intel_vrr_dcb_vmax_vblank_start_final(const struct 
>> intel_crtc_state *crtc_state);
>> +
>>   #endif /* __INTEL_VRR_H__ */
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h 
>> b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
>> index 6ed0e0dc97e7..2214c10d4084 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
>> @@ -9,6 +9,50 @@
>>   #include "intel_display_reg_defs.h"
>>     /* VRR registers */
>> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A        0x604D4
>> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B        0x614D4
>> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_C        0x624D4
>> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_D        0x634D4
>> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_E        0x6B4D4
>> +#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(dev_priv, trans)    \
>> +                    _MMIO_TRANS2(dev_priv, \
>> +                             trans, \
>> +                             _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A)
>> +
>> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A            0x604D8
>> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B            0x614D8
>> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_C            0x624D8
>> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_D            0x634D8
>> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_E            0x6B4D8
>> +#define TRANS_VRR_DCB_ADJ_VMAX_CFG(dev_priv, trans) 
>> _MMIO_TRANS2(dev_priv, \
>> +                                     trans, \
>> + _TRANS_VRR_DCB_ADJ_VMAX_CFG_A)
>> +
>> +#define _TRANS_VRR_FLIPLINE_DCB_A        0x60418
>> +#define _TRANS_VRR_FLIPLINE_DCB_B        0x61418
>> +#define _TRANS_VRR_FLIPLINE_DCB_C        0x62418
>> +#define _TRANS_VRR_FLIPLINE_DCB_D        0x63418
>> +#define _TRANS_VRR_FLIPLINE_DCB_E        0x6B418
>> +#define TRANS_VRR_FLIPLINE_DCB(dev_priv, trans) 
>> _MMIO_TRANS2(dev_priv, \
>> +                                 trans, \
>> +                                 _TRANS_VRR_FLIPLINE_DCB_A)
>> +
>> +#define _TRANS_VRR_VMAX_DCB_A            0x60414
>> +#define _TRANS_VRR_VMAX_DCB_B            0x61414
>> +#define _TRANS_VRR_VMAX_DCB_C            0x62414
>> +#define _TRANS_VRR_VMAX_DCB_D            0x63414
>> +#define _TRANS_VRR_VMAX_DCB_E            0x6B414
>> +#define TRANS_VRR_VMAX_DCB(dev_priv, trans) _MMIO_TRANS2(dev_priv, \
>> +                                 trans, \
>> +                                 _TRANS_VRR_VMAX_DCB_A)
>> +
>> +#define VRR_DCB_ADJ_FLIPLINE_CNT_MASK        REG_GENMASK(31, 24)
>> +#define VRR_DCB_ADJ_FLIPLINE_MASK        REG_GENMASK(19, 0)
>> +#define VRR_DCB_ADJ_VMAX_CNT_MASK        REG_GENMASK(31, 24)
>> +#define VRR_DCB_ADJ_VMAX_MASK            REG_GENMASK(19, 0)
>> +#define VRR_FLIPLINE_DCB_MASK            REG_GENMASK(19, 0)
>> +#define VRR_VMAX_DCB_MASK            REG_GENMASK(19, 0)
>> +
>>   #define _TRANS_VRR_CTL_A            0x60420
>>   #define _TRANS_VRR_CTL_B            0x61420
>>   #define _TRANS_VRR_CTL_C            0x62420

Re: [PATCH v2 01/13] drm/i915/vrr: Refactor vmin/vmax stuff

[Nautiyal, Ankit K]

On 4/23/2025 12:19 PM, Nautiyal, Ankit K wrote:
>
> On 4/21/2025 9:18 PM, Mitul Golani wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Refactor vmin/vmax functions for better computation.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_vrr.c | 41 +++++++++++-------------
>>   1 file changed, 19 insertions(+), 22 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
>> b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index c6565baf815a..adfd231eb578 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -146,37 +146,41 @@ static int intel_vrr_vblank_exit_length(const 
>> struct intel_crtc_state *crtc_stat
>>           return crtc_state->vrr.pipeline_full + 
>> crtc_state->framestart_delay + 1;
>>   }
>>   -int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
>> +static int intel_vrr_vtotal(const struct intel_crtc_state 
>> *crtc_state, int vmin_vmax)
>>   {
>>       struct intel_display *display = to_intel_display(crtc_state);
>>   -    /* Min vblank actually determined by flipline */
>>       if (DISPLAY_VER(display) >= 13)
>> -        return intel_vrr_vmin_flipline(crtc_state);
>> +        return vmin_vmax;
>>       else
>> -        return intel_vrr_vmin_flipline(crtc_state) +
>> -            intel_vrr_real_vblank_delay(crtc_state);
>> +        return vmin_vmax + intel_vrr_real_vblank_delay(crtc_state);
>>   }
>>   -int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
>> +static int intel_vrr_vblank_start(const struct intel_crtc_state 
>> *crtc_state,
>> +                  int vmin_vmax)
>>   {
>> -    struct intel_display *display = to_intel_display(crtc_state);
>> +    return intel_vrr_vtotal(crtc_state, vmin_vmax) -
>> +            intel_vrr_vblank_exit_length(crtc_state);
>> +}
>>   -    if (DISPLAY_VER(display) >= 13)
>> -        return crtc_state->vrr.vmax;
>> -    else
>> -        return crtc_state->vrr.vmax +
>> -            intel_vrr_real_vblank_delay(crtc_state);
>> +int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state)
>> +{
>> +    return intel_vrr_vtotal(crtc_state, 
>> intel_vrr_vmin_flipline(crtc_state));
>> +}
>> +
>> +int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state)
>> +{
>> +    return intel_vrr_vtotal(crtc_state, crtc_state->vrr.vmax);
>>   }
>>     int intel_vrr_vmin_vblank_start(const struct intel_crtc_state 
>> *crtc_state)
>>   {
>> -    return intel_vrr_vmin_vtotal(crtc_state) - 
>> intel_vrr_vblank_exit_length(crtc_state);
>> +    return intel_vrr_vblank_start(crtc_state, 
>> intel_vrr_vmin_flipline(crtc_state));
>>   }
>>     int intel_vrr_vmax_vblank_start(const struct intel_crtc_state 
>> *crtc_state)
>>   {
>> -    return intel_vrr_vmax_vtotal(crtc_state) - 
>> intel_vrr_vblank_exit_length(crtc_state);
>> +    return intel_vrr_vblank_start(crtc_state, crtc_state->vrr.vmax);
>>   }
>>     static bool
>> @@ -257,14 +261,7 @@ void intel_vrr_compute_vrr_timings(struct 
>> intel_crtc_state *crtc_state)
>>   static
>>   int intel_vrr_fixed_rr_vtotal(const struct intel_crtc_state 
>> *crtc_state)
>>   {
>> -    struct intel_display *display = to_intel_display(crtc_state);
>> -    int crtc_vtotal = crtc_state->hw.adjusted_mode.crtc_vtotal;
>> -
>> -    if (DISPLAY_VER(display) >= 13)
>> -        return crtc_vtotal;
>> -    else
>> -        return crtc_vtotal -
>> -            intel_vrr_real_vblank_delay(crtc_state);
>> +    return intel_vrr_vtotal(crtc_state, 
>> crtc_state->hw.adjusted_mode.crtc_vtotal);
>
> This seems to be off for Display < 13.
>
> If I see it correctly, instead of subtracting we are now adding 
> intel_vrr_real_vblank_delay(crtc_state);


I think the vblank delay should be added for platforms < 13, and not 
subtracted.

Perhaps need a separate fix for this.

Regards,

Ankit

>
>
> Can this be rechecked? or I am missing something?
>
> Rest of the changes seem fine.
>
>
> Regards,
>
> Ankit
>
>
>
>>   }
>>     static