Re: [Intel-gfx] [PATCH 1/4] drm/i915/dsi/xelpd: Fix the bit mask for wakeup GB

[Jani Nikula <jani.nikula@intel.com>]

On Mon, 18 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:

Commit message goes here.

> Fixes: f87c46c43175 ("drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardband")
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
>  drivers/gpu/drm/i915/i915_reg.h        | 3 ++-
>  2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 9ee62707ec72..8c166f92f8bd 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1271,7 +1271,7 @@ static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
>  	if (DISPLAY_VER(i915) == 13) {
>  		for_each_dsi_port(port, intel_dsi->ports)
>  			intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
> -				     TGL_DSI_CHKN_LSHS_GB, 0x4);
> +				     TGL_DSI_CHKN_LSHS_GB_MASK, TGL_DSI_CHKN_LSHS_GB_MASK);

I think you mean the value should be TGL_DSI_CHKN_LSHS_GB.

BR,
Jani.

>  	}
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a897f4abea0c..e4b1f80ca5eb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11728,7 +11728,8 @@ enum skl_power_gate {
>  #define TGL_DSI_CHKN_REG(port)		_MMIO_PORT(port,	\
>  						    _TGL_DSI_CHKN_REG_0, \
>  						    _TGL_DSI_CHKN_REG_1)
> -#define TGL_DSI_CHKN_LSHS_GB			REG_GENMASK(15, 12)
> +#define TGL_DSI_CHKN_LSHS_GB_MASK		REG_GENMASK(15, 12)
> +#define TGL_DSI_CHKN_LSHS_GB			REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, 4)
>  
>  /* Display Stream Splitter Control */
>  #define DSS_CTL1				_MMIO(0x67400)

-- 
Jani Nikula, Intel Open Source Graphics Center