Re: [Intel-gfx] [PATCH 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support

[Jani Nikula <jani.nikula@intel.com>]

On Tue, 19 Oct 2021, "Kulkarni, Vandita" <vandita.kulkarni@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani <jani.nikula@intel.com>
>> Sent: Tuesday, October 19, 2021 3:44 PM
>> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Cc: Deak, Imre <imre.deak@intel.com>; Roper, Matthew D
>> <matthew.d.roper@intel.com>; Kulkarni, Vandita
>> <vandita.kulkarni@intel.com>
>> Subject: Re: [PATCH 2/4] drm/i915/dsi/xelpd: Add DSI transcoder support
>> 
>> On Mon, 18 Oct 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
>> > Update ADL_P device info to support DSI0, DSI1
>> >
>> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/i915_pci.c | 31 ++++++++++++++++++++++++++++-
>> --
>> >  1 file changed, 28 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_pci.c
>> > b/drivers/gpu/drm/i915/i915_pci.c index 169837de395d..a2dd5a38fdf5
>> > 100644
>> > --- a/drivers/gpu/drm/i915/i915_pci.c
>> > +++ b/drivers/gpu/drm/i915/i915_pci.c
>> > @@ -932,8 +932,6 @@ static const struct intel_device_info adl_s_info =
>> > {  #define XE_LPD_FEATURES \
>> >  	.abox_mask = GENMASK(1, 0),
>> 	\
>> >  	.color = { .degamma_lut_size = 0, .gamma_lut_size = 0 },
>> 	\
>> > -	.cpu_transcoder_mask = BIT(TRANSCODER_A) |
>> BIT(TRANSCODER_B) |		\
>> > -		BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
>> 		\
>> >  	.dbuf.size = 4096,
>> 	\
>> >  	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |
>> 		\
>> >  		BIT(DBUF_S4),
>> 	\
>> > @@ -950,23 +948,49 @@ static const struct intel_device_info adl_s_info = {
>> >  	.display.has_psr = 1,
>> 	\
>> >  	.display.ver = 13,
>> 	\
>> >  	.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
>> 	\
>> > +	XE_LPD_CURSOR_OFFSETS
>> > +
>> > +#define ADLP_TRANSCODERS \
>> > +	.cpu_transcoder_mask = BIT(TRANSCODER_A) |
>> BIT(TRANSCODER_B) |		\
>> > +		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
>> 		\
>> > +		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
>> 		\
>> >  	.pipe_offsets = {
>> 	\
>> >  		[TRANSCODER_A] = PIPE_A_OFFSET,
>> 		\
>> >  		[TRANSCODER_B] = PIPE_B_OFFSET,
>> 		\
>> >  		[TRANSCODER_C] = PIPE_C_OFFSET,
>> 		\
>> >  		[TRANSCODER_D] = PIPE_D_OFFSET,
>> 		\
>> > +		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,
>> 		\
>> > +		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,
>> 		\
>> >  	},
>> 	\
>> >  	.trans_offsets = {
>> 	\
>> >  		[TRANSCODER_A] = TRANSCODER_A_OFFSET,
>> 		\
>> >  		[TRANSCODER_B] = TRANSCODER_B_OFFSET,
>> 		\
>> >  		[TRANSCODER_C] = TRANSCODER_C_OFFSET,
>> 		\
>> >  		[TRANSCODER_D] = TRANSCODER_D_OFFSET,
>> 		\
>> > +		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,
>> 		\
>> > +		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,
>> 		\
>> 
>> I think you could just add these changes to XE_LPD_FEATURES, and have
>> separate .cpu_transcoder_mask initialization for ADLP and DG2.
>
> Okay got it. So its ok to have the pipe_offsets  or transcoder offsets added unless we are not defining it in the .cpu_transcoder_mask
> Will make this change.

Yeah, the *_offsets are only used if referenced, and having them should
not make a difference. It's the .cpu_transcoder_mask and .pipe_mask that
matter.

BR,
Hani.

>
> Thanks,
> Vandita
>> 
>> Compare GEN12_FEATURES.
>> 
>> BR,
>> Jani.
>> 
>> > +	}
>> 	\
>> > +
>> > +#define DG2_TRANSCODERS \
>> > +	.cpu_transcoder_mask = BIT(TRANSCODER_A) |
>> BIT(TRANSCODER_B) |		\
>> > +		BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
>> 		\
>> > +	.pipe_offsets = {
>> 	\
>> > +		[TRANSCODER_A] = PIPE_A_OFFSET,
>> 		\
>> > +		[TRANSCODER_B] = PIPE_B_OFFSET,
>> 		\
>> > +		[TRANSCODER_C] = PIPE_C_OFFSET,
>> 		\
>> > +		[TRANSCODER_D] = PIPE_D_OFFSET,
>> 		\
>> >  	},
>> 	\
>> > -	XE_LPD_CURSOR_OFFSETS
>> > +	.trans_offsets = {
>> 	\
>> > +		[TRANSCODER_A] = TRANSCODER_A_OFFSET,
>> 		\
>> > +		[TRANSCODER_B] = TRANSCODER_B_OFFSET,
>> 		\
>> > +		[TRANSCODER_C] = TRANSCODER_C_OFFSET,
>> 		\
>> > +		[TRANSCODER_D] = TRANSCODER_D_OFFSET,
>> 		\
>> > +	}
>> 	\
>> >
>> >  static const struct intel_device_info adl_p_info = {
>> >  	GEN12_FEATURES,
>> >  	XE_LPD_FEATURES,
>> > +	ADLP_TRANSCODERS,
>> >  	PLATFORM(INTEL_ALDERLAKE_P),
>> >  	.require_force_probe = 1,
>> >  	.display.has_cdclk_crawl = 1,
>> > @@ -1029,6 +1053,7 @@ static const struct intel_device_info dg2_info = {
>> >  	XE_HP_FEATURES,
>> >  	XE_HPM_FEATURES,
>> >  	XE_LPD_FEATURES,
>> > +	DG2_TRANSCODERS,
>> >  	DGFX_FEATURES,
>> >  	.graphics_rel = 55,
>> >  	.media_rel = 55,
>> 
>> --
>> Jani Nikula, Intel Open Source Graphics Center

-- 
Jani Nikula, Intel Open Source Graphics Center