* [PATCH] i915: Expose panel power cycle delay to i915_panel_timings
@ 2019-11-18 16:33 Anshuman Gupta
2019-11-18 16:33 ` [Intel-gfx] " Anshuman Gupta
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Anshuman Gupta @ 2019-11-18 16:33 UTC (permalink / raw)
To: intel-gfx
Putting down the AUX power domain reference count in
edp vdd off async sequence takes too much of time
(relative to panel power cycle delay) therefore it make sense
to expose the panel power cycle delay to i915_panel_timings
along with other delays.
It can be use by DC state IGT to wait for strict power cycle delay
in order to check for various DC state counters.
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index cab632791f73..c075cc2b7bb5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4436,6 +4436,8 @@ static int i915_panel_show(struct seq_file *m, void *data)
intel_dp->panel_power_up_delay);
seq_printf(m, "Panel power down delay: %d\n",
intel_dp->panel_power_down_delay);
+ seq_printf(m, "Panel power cycle delay: %d\n",
+ intel_dp->panel_power_cycle_delay);
seq_printf(m, "Backlight on delay: %d\n",
intel_dp->backlight_on_delay);
seq_printf(m, "Backlight off delay: %d\n",
--
2.24.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Intel-gfx] [PATCH] i915: Expose panel power cycle delay to i915_panel_timings 2019-11-18 16:33 [PATCH] i915: Expose panel power cycle delay to i915_panel_timings Anshuman Gupta @ 2019-11-18 16:33 ` Anshuman Gupta 2019-11-18 19:08 ` ✗ Fi.CI.BAT: failure for " Patchwork 2019-11-28 14:05 ` [PATCH] " Jani Nikula 2 siblings, 0 replies; 10+ messages in thread From: Anshuman Gupta @ 2019-11-18 16:33 UTC (permalink / raw) To: intel-gfx Putting down the AUX power domain reference count in edp vdd off async sequence takes too much of time (relative to panel power cycle delay) therefore it make sense to expose the panel power cycle delay to i915_panel_timings along with other delays. It can be use by DC state IGT to wait for strict power cycle delay in order to check for various DC state counters. Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index cab632791f73..c075cc2b7bb5 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4436,6 +4436,8 @@ static int i915_panel_show(struct seq_file *m, void *data) intel_dp->panel_power_up_delay); seq_printf(m, "Panel power down delay: %d\n", intel_dp->panel_power_down_delay); + seq_printf(m, "Panel power cycle delay: %d\n", + intel_dp->panel_power_cycle_delay); seq_printf(m, "Backlight on delay: %d\n", intel_dp->backlight_on_delay); seq_printf(m, "Backlight off delay: %d\n", -- 2.24.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
* ✗ Fi.CI.BAT: failure for i915: Expose panel power cycle delay to i915_panel_timings 2019-11-18 16:33 [PATCH] i915: Expose panel power cycle delay to i915_panel_timings Anshuman Gupta 2019-11-18 16:33 ` [Intel-gfx] " Anshuman Gupta @ 2019-11-18 19:08 ` Patchwork 2019-11-18 19:08 ` [Intel-gfx] " Patchwork 2019-11-28 14:05 ` [PATCH] " Jani Nikula 2 siblings, 1 reply; 10+ messages in thread From: Patchwork @ 2019-11-18 19:08 UTC (permalink / raw) To: Anshuman Gupta; +Cc: intel-gfx == Series Details == Series: i915: Expose panel power cycle delay to i915_panel_timings URL : https://patchwork.freedesktop.org/series/69633/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7365 -> Patchwork_15316 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_15316 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15316, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15316/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_15316: ### IGT changes ### #### Possible regressions #### * igt@i915_module_load@reload-with-fault-injection: - fi-skl-6770hq: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7365/fi-skl-6770hq/igt@i915_module_load@reload-with-fault-injection.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15316/fi-skl-6770hq/igt@i915_module_load@reload-with-fault-injection.html Known issues ------------ Here are the changes found in Patchwork_15316 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live_hangcheck: - fi-hsw-4770r: [PASS][3] -> [DMESG-FAIL][4] ([fdo#111991]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7365/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15316/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html #### Possible fixes #### * igt@i915_pm_rpm@module-reload: - fi-skl-lmem: [DMESG-WARN][5] ([fdo#112261]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7365/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15316/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html * igt@i915_selftest@live_gem_contexts: - fi-bsw-nick: [INCOMPLETE][7] ([fdo# 111542]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7365/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15316/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][9] ([fdo#111045] / [fdo#111096]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7365/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15316/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542 [fdo#109964]: https://bugs.freedesktop.org/show_bug.cgi?id=109964 [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#111991]: https://bugs.freedesktop.org/show_bug.cgi?id=111991 [fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261 [fdo#112298]: https://bugs.freedesktop.org/show_bug.cgi?id=112298 Participating hosts (50 -> 44) ------------------------------ Missing (6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7365 -> Patchwork_15316 CI-20190529: 20190529 CI_DRM_7365: ae28c3736610ca3c242ea9d0af8cbc767a0ddeba @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5292: ea9cd47fdb72c16d5ec84c04a85122c451c30025 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_15316: 6a11f70287e214fcfe486b81ddd21f1dfaaed91d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6a11f70287e2 i915: Expose panel power cycle delay to i915_panel_timings == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15316/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: Expose panel power cycle delay to i915_panel_timings 2019-11-18 19:08 ` ✗ Fi.CI.BAT: failure for " Patchwork @ 2019-11-18 19:08 ` Patchwork 0 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2019-11-18 19:08 UTC (permalink / raw) To: Anshuman Gupta; +Cc: intel-gfx == Series Details == Series: i915: Expose panel power cycle delay to i915_panel_timings URL : https://patchwork.freedesktop.org/series/69633/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7365 -> Patchwork_15316 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_15316 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15316, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15316/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_15316: ### IGT changes ### #### Possible regressions #### * igt@i915_module_load@reload-with-fault-injection: - fi-skl-6770hq: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7365/fi-skl-6770hq/igt@i915_module_load@reload-with-fault-injection.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15316/fi-skl-6770hq/igt@i915_module_load@reload-with-fault-injection.html Known issues ------------ Here are the changes found in Patchwork_15316 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live_hangcheck: - fi-hsw-4770r: [PASS][3] -> [DMESG-FAIL][4] ([fdo#111991]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7365/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15316/fi-hsw-4770r/igt@i915_selftest@live_hangcheck.html #### Possible fixes #### * igt@i915_pm_rpm@module-reload: - fi-skl-lmem: [DMESG-WARN][5] ([fdo#112261]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7365/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15316/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html * igt@i915_selftest@live_gem_contexts: - fi-bsw-nick: [INCOMPLETE][7] ([fdo# 111542]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7365/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15316/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][9] ([fdo#111045] / [fdo#111096]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7365/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15316/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542 [fdo#109964]: https://bugs.freedesktop.org/show_bug.cgi?id=109964 [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#111991]: https://bugs.freedesktop.org/show_bug.cgi?id=111991 [fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261 [fdo#112298]: https://bugs.freedesktop.org/show_bug.cgi?id=112298 Participating hosts (50 -> 44) ------------------------------ Missing (6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7365 -> Patchwork_15316 CI-20190529: 20190529 CI_DRM_7365: ae28c3736610ca3c242ea9d0af8cbc767a0ddeba @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5292: ea9cd47fdb72c16d5ec84c04a85122c451c30025 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_15316: 6a11f70287e214fcfe486b81ddd21f1dfaaed91d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6a11f70287e2 i915: Expose panel power cycle delay to i915_panel_timings == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15316/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] i915: Expose panel power cycle delay to i915_panel_timings 2019-11-18 16:33 [PATCH] i915: Expose panel power cycle delay to i915_panel_timings Anshuman Gupta 2019-11-18 16:33 ` [Intel-gfx] " Anshuman Gupta 2019-11-18 19:08 ` ✗ Fi.CI.BAT: failure for " Patchwork @ 2019-11-28 14:05 ` Jani Nikula 2019-11-28 14:05 ` [Intel-gfx] " Jani Nikula 2019-12-03 6:13 ` Anshuamn Gupta 2 siblings, 2 replies; 10+ messages in thread From: Jani Nikula @ 2019-11-28 14:05 UTC (permalink / raw) To: Anshuman Gupta, intel-gfx On Mon, 18 Nov 2019, Anshuman Gupta <anshuman.gupta@intel.com> wrote: > Putting down the AUX power domain reference count in > edp vdd off async sequence takes too much of time > (relative to panel power cycle delay) therefore it make sense > to expose the panel power cycle delay to i915_panel_timings > along with other delays. > It can be use by DC state IGT to wait for strict power cycle delay > in order to check for various DC state counters. Catching up on review, are you suggesting to look at this kind of debugfs files for tests? Please find another way. I don't mind having the debugfs info per se. BR, Jani. > > Cc: Imre Deak <imre.deak@intel.com> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index cab632791f73..c075cc2b7bb5 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -4436,6 +4436,8 @@ static int i915_panel_show(struct seq_file *m, void *data) > intel_dp->panel_power_up_delay); > seq_printf(m, "Panel power down delay: %d\n", > intel_dp->panel_power_down_delay); > + seq_printf(m, "Panel power cycle delay: %d\n", > + intel_dp->panel_power_cycle_delay); > seq_printf(m, "Backlight on delay: %d\n", > intel_dp->backlight_on_delay); > seq_printf(m, "Backlight off delay: %d\n", -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] i915: Expose panel power cycle delay to i915_panel_timings 2019-11-28 14:05 ` [PATCH] " Jani Nikula @ 2019-11-28 14:05 ` Jani Nikula 2019-12-03 6:13 ` Anshuamn Gupta 1 sibling, 0 replies; 10+ messages in thread From: Jani Nikula @ 2019-11-28 14:05 UTC (permalink / raw) To: Anshuman Gupta, intel-gfx On Mon, 18 Nov 2019, Anshuman Gupta <anshuman.gupta@intel.com> wrote: > Putting down the AUX power domain reference count in > edp vdd off async sequence takes too much of time > (relative to panel power cycle delay) therefore it make sense > to expose the panel power cycle delay to i915_panel_timings > along with other delays. > It can be use by DC state IGT to wait for strict power cycle delay > in order to check for various DC state counters. Catching up on review, are you suggesting to look at this kind of debugfs files for tests? Please find another way. I don't mind having the debugfs info per se. BR, Jani. > > Cc: Imre Deak <imre.deak@intel.com> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index cab632791f73..c075cc2b7bb5 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -4436,6 +4436,8 @@ static int i915_panel_show(struct seq_file *m, void *data) > intel_dp->panel_power_up_delay); > seq_printf(m, "Panel power down delay: %d\n", > intel_dp->panel_power_down_delay); > + seq_printf(m, "Panel power cycle delay: %d\n", > + intel_dp->panel_power_cycle_delay); > seq_printf(m, "Backlight on delay: %d\n", > intel_dp->backlight_on_delay); > seq_printf(m, "Backlight off delay: %d\n", -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] i915: Expose panel power cycle delay to i915_panel_timings 2019-11-28 14:05 ` [PATCH] " Jani Nikula 2019-11-28 14:05 ` [Intel-gfx] " Jani Nikula @ 2019-12-03 6:13 ` Anshuamn Gupta 2019-12-03 6:13 ` [Intel-gfx] " Anshuamn Gupta 2019-12-03 7:59 ` Jani Nikula 1 sibling, 2 replies; 10+ messages in thread From: Anshuamn Gupta @ 2019-12-03 6:13 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On 2019-11-28 at 16:05:03 +0200, Jani Nikula wrote: > On Mon, 18 Nov 2019, Anshuman Gupta <anshuman.gupta@intel.com> wrote: > > Putting down the AUX power domain reference count in > > edp vdd off async sequence takes too much of time > > (relative to panel power cycle delay) therefore it make sense > > to expose the panel power cycle delay to i915_panel_timings > > along with other delays. > > It can be use by DC state IGT to wait for strict power cycle delay > > in order to check for various DC state counters. > > Catching up on review, are you suggesting to look at this kind of > debugfs files for tests? Please find another way. Actually on few panels power cycle delay is too much that it is required to wait for 6 seconds in igt for an timeout, but this could really affect CI execution time on panel with lesser power cycle delay. (https://patchwork.freedesktop.org/series/68478/) For this specific reason i thought it may be good to expose panel power cycle delay with other panel delay and use that in igt. Thanks , Anshuman. > > I don't mind having the debugfs info per se. > > BR, > Jani. > > > > > Cc: Imre Deak <imre.deak@intel.com> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > > --- > > drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > > index cab632791f73..c075cc2b7bb5 100644 > > --- a/drivers/gpu/drm/i915/i915_debugfs.c > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > > @@ -4436,6 +4436,8 @@ static int i915_panel_show(struct seq_file *m, void *data) > > intel_dp->panel_power_up_delay); > > seq_printf(m, "Panel power down delay: %d\n", > > intel_dp->panel_power_down_delay); > > + seq_printf(m, "Panel power cycle delay: %d\n", > > + intel_dp->panel_power_cycle_delay); > > seq_printf(m, "Backlight on delay: %d\n", > > intel_dp->backlight_on_delay); > > seq_printf(m, "Backlight off delay: %d\n", > > -- > Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] i915: Expose panel power cycle delay to i915_panel_timings 2019-12-03 6:13 ` Anshuamn Gupta @ 2019-12-03 6:13 ` Anshuamn Gupta 2019-12-03 7:59 ` Jani Nikula 1 sibling, 0 replies; 10+ messages in thread From: Anshuamn Gupta @ 2019-12-03 6:13 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On 2019-11-28 at 16:05:03 +0200, Jani Nikula wrote: > On Mon, 18 Nov 2019, Anshuman Gupta <anshuman.gupta@intel.com> wrote: > > Putting down the AUX power domain reference count in > > edp vdd off async sequence takes too much of time > > (relative to panel power cycle delay) therefore it make sense > > to expose the panel power cycle delay to i915_panel_timings > > along with other delays. > > It can be use by DC state IGT to wait for strict power cycle delay > > in order to check for various DC state counters. > > Catching up on review, are you suggesting to look at this kind of > debugfs files for tests? Please find another way. Actually on few panels power cycle delay is too much that it is required to wait for 6 seconds in igt for an timeout, but this could really affect CI execution time on panel with lesser power cycle delay. (https://patchwork.freedesktop.org/series/68478/) For this specific reason i thought it may be good to expose panel power cycle delay with other panel delay and use that in igt. Thanks , Anshuman. > > I don't mind having the debugfs info per se. > > BR, > Jani. > > > > > Cc: Imre Deak <imre.deak@intel.com> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > > --- > > drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > > index cab632791f73..c075cc2b7bb5 100644 > > --- a/drivers/gpu/drm/i915/i915_debugfs.c > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > > @@ -4436,6 +4436,8 @@ static int i915_panel_show(struct seq_file *m, void *data) > > intel_dp->panel_power_up_delay); > > seq_printf(m, "Panel power down delay: %d\n", > > intel_dp->panel_power_down_delay); > > + seq_printf(m, "Panel power cycle delay: %d\n", > > + intel_dp->panel_power_cycle_delay); > > seq_printf(m, "Backlight on delay: %d\n", > > intel_dp->backlight_on_delay); > > seq_printf(m, "Backlight off delay: %d\n", > > -- > Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] i915: Expose panel power cycle delay to i915_panel_timings 2019-12-03 6:13 ` Anshuamn Gupta 2019-12-03 6:13 ` [Intel-gfx] " Anshuamn Gupta @ 2019-12-03 7:59 ` Jani Nikula 2019-12-03 7:59 ` [Intel-gfx] " Jani Nikula 1 sibling, 1 reply; 10+ messages in thread From: Jani Nikula @ 2019-12-03 7:59 UTC (permalink / raw) To: Anshuamn Gupta; +Cc: intel-gfx On Tue, 03 Dec 2019, Anshuamn Gupta <anshuman.gupta@intel.com> wrote: > On 2019-11-28 at 16:05:03 +0200, Jani Nikula wrote: >> On Mon, 18 Nov 2019, Anshuman Gupta <anshuman.gupta@intel.com> wrote: >> > Putting down the AUX power domain reference count in >> > edp vdd off async sequence takes too much of time >> > (relative to panel power cycle delay) therefore it make sense >> > to expose the panel power cycle delay to i915_panel_timings >> > along with other delays. >> > It can be use by DC state IGT to wait for strict power cycle delay >> > in order to check for various DC state counters. >> >> Catching up on review, are you suggesting to look at this kind of >> debugfs files for tests? Please find another way. > Actually on few panels power cycle delay is too much that it is required > to wait for 6 seconds in igt for an timeout, but this could really affect > CI execution time on panel with lesser power cycle delay. > (https://patchwork.freedesktop.org/series/68478/) > For this specific reason i thought it may be good to expose > panel power cycle delay with other panel delay and use that > in igt. Fix the kernel driver to DTRT instead of exposing the guts and having igt work around it. BR, Jani. > Thanks , > Anshuman. >> >> I don't mind having the debugfs info per se. >> >> BR, >> Jani. >> >> > >> > Cc: Imre Deak <imre.deak@intel.com> >> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> >> > --- >> > drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ >> > 1 file changed, 2 insertions(+) >> > >> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c >> > index cab632791f73..c075cc2b7bb5 100644 >> > --- a/drivers/gpu/drm/i915/i915_debugfs.c >> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c >> > @@ -4436,6 +4436,8 @@ static int i915_panel_show(struct seq_file *m, void *data) >> > intel_dp->panel_power_up_delay); >> > seq_printf(m, "Panel power down delay: %d\n", >> > intel_dp->panel_power_down_delay); >> > + seq_printf(m, "Panel power cycle delay: %d\n", >> > + intel_dp->panel_power_cycle_delay); >> > seq_printf(m, "Backlight on delay: %d\n", >> > intel_dp->backlight_on_delay); >> > seq_printf(m, "Backlight off delay: %d\n", >> >> -- >> Jani Nikula, Intel Open Source Graphics Center -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] i915: Expose panel power cycle delay to i915_panel_timings 2019-12-03 7:59 ` Jani Nikula @ 2019-12-03 7:59 ` Jani Nikula 0 siblings, 0 replies; 10+ messages in thread From: Jani Nikula @ 2019-12-03 7:59 UTC (permalink / raw) To: Anshuamn Gupta; +Cc: intel-gfx On Tue, 03 Dec 2019, Anshuamn Gupta <anshuman.gupta@intel.com> wrote: > On 2019-11-28 at 16:05:03 +0200, Jani Nikula wrote: >> On Mon, 18 Nov 2019, Anshuman Gupta <anshuman.gupta@intel.com> wrote: >> > Putting down the AUX power domain reference count in >> > edp vdd off async sequence takes too much of time >> > (relative to panel power cycle delay) therefore it make sense >> > to expose the panel power cycle delay to i915_panel_timings >> > along with other delays. >> > It can be use by DC state IGT to wait for strict power cycle delay >> > in order to check for various DC state counters. >> >> Catching up on review, are you suggesting to look at this kind of >> debugfs files for tests? Please find another way. > Actually on few panels power cycle delay is too much that it is required > to wait for 6 seconds in igt for an timeout, but this could really affect > CI execution time on panel with lesser power cycle delay. > (https://patchwork.freedesktop.org/series/68478/) > For this specific reason i thought it may be good to expose > panel power cycle delay with other panel delay and use that > in igt. Fix the kernel driver to DTRT instead of exposing the guts and having igt work around it. BR, Jani. > Thanks , > Anshuman. >> >> I don't mind having the debugfs info per se. >> >> BR, >> Jani. >> >> > >> > Cc: Imre Deak <imre.deak@intel.com> >> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> >> > --- >> > drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ >> > 1 file changed, 2 insertions(+) >> > >> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c >> > index cab632791f73..c075cc2b7bb5 100644 >> > --- a/drivers/gpu/drm/i915/i915_debugfs.c >> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c >> > @@ -4436,6 +4436,8 @@ static int i915_panel_show(struct seq_file *m, void *data) >> > intel_dp->panel_power_up_delay); >> > seq_printf(m, "Panel power down delay: %d\n", >> > intel_dp->panel_power_down_delay); >> > + seq_printf(m, "Panel power cycle delay: %d\n", >> > + intel_dp->panel_power_cycle_delay); >> > seq_printf(m, "Backlight on delay: %d\n", >> > intel_dp->backlight_on_delay); >> > seq_printf(m, "Backlight off delay: %d\n", >> >> -- >> Jani Nikula, Intel Open Source Graphics Center -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-12-03 8:00 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-11-18 16:33 [PATCH] i915: Expose panel power cycle delay to i915_panel_timings Anshuman Gupta 2019-11-18 16:33 ` [Intel-gfx] " Anshuman Gupta 2019-11-18 19:08 ` ✗ Fi.CI.BAT: failure for " Patchwork 2019-11-18 19:08 ` [Intel-gfx] " Patchwork 2019-11-28 14:05 ` [PATCH] " Jani Nikula 2019-11-28 14:05 ` [Intel-gfx] " Jani Nikula 2019-12-03 6:13 ` Anshuamn Gupta 2019-12-03 6:13 ` [Intel-gfx] " Anshuamn Gupta 2019-12-03 7:59 ` Jani Nikula 2019-12-03 7:59 ` [Intel-gfx] " Jani Nikula
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