[PATCH 0/3] drm/i915/dp: refactoring + respect vbt max dp rate

[PATCH 0/3] drm/i915/dp: refactoring + respect vbt max dp rate

[Jani Nikula]

Hi Rodrigo, this is what I had in mind for the DP CNL and VBT rate limiting, I
hope you don't mind me writing the patches. It was easier to express myself in C
than English.

BR,
Jani.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

Jani Nikula (3):
  drm/i915/dp: abstract rate array length limiting
  drm/i915/dp: clean up source rate limiting for cnl
  drm/i915/dp: limit DP link rate based on VBT on CNL+

 drivers/gpu/drm/i915/i915_drv.h       |  1 +
 drivers/gpu/drm/i915/intel_bios.c     | 21 ++++++++++++
 drivers/gpu/drm/i915/intel_dp.c       | 63 ++++++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_vbt_defs.h |  5 +++
 4 files changed, 67 insertions(+), 23 deletions(-)

-- 
2.11.0

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[PATCH 1/3] drm/i915/dp: abstract rate array length limiting

[Jani Nikula]

This will be useful later on. Also move the functions around to not need
forward declarations in subsequent patches. No functional changes.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 38 ++++++++++++++++++++++----------------
 1 file changed, 22 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 03d86ff9b805..3c1c11c1cd30 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -157,6 +157,28 @@ static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 	intel_dp->num_sink_rates = i;
 }
 
+/* Get length of rates array potentially limited by max_rate. */
+static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
+{
+	int i;
+
+	/* Limit results by potentially reduced max rate */
+	for (i = 0; i < len; i++) {
+		if (rates[len - i - 1] <= max_rate)
+			return len - i;
+	}
+
+	return 0;
+}
+
+/* Get length of common rates array potentially limited by max_rate. */
+static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
+					  int max_rate)
+{
+	return intel_dp_rate_limit_len(intel_dp->common_rates,
+				       intel_dp->num_common_rates, max_rate);
+}
+
 /* Theoretical max between source and sink */
 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 {
@@ -328,22 +350,6 @@ static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 	}
 }
 
-/* get length of common rates potentially limited by max_rate */
-static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp,
-					  int max_rate)
-{
-	const int *common_rates = intel_dp->common_rates;
-	int i, common_len = intel_dp->num_common_rates;
-
-	/* Limit results by potentially reduced max rate */
-	for (i = 0; i < common_len; i++) {
-		if (common_rates[common_len - i - 1] <= max_rate)
-			return common_len - i;
-	}
-
-	return 0;
-}
-
 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 				       uint8_t lane_count)
 {
-- 
2.11.0

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Re: [PATCH 1/3] drm/i915/dp: abstract rate array length limiting

[Rodrigo Vivi]

On Thu, Feb 01, 2018 at 11:03:41AM +0000, Jani Nikula wrote:
> This will be useful later on. Also move the functions around to not need
> forward declarations in subsequent patches. No functional changes.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 38 ++++++++++++++++++++++----------------
>  1 file changed, 22 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 03d86ff9b805..3c1c11c1cd30 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -157,6 +157,28 @@ static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
>  	intel_dp->num_sink_rates = i;
>  }
>  
> +/* Get length of rates array potentially limited by max_rate. */
> +static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
> +{
> +	int i;
> +
> +	/* Limit results by potentially reduced max rate */
> +	for (i = 0; i < len; i++) {
> +		if (rates[len - i - 1] <= max_rate)
> +			return len - i;
> +	}
> +
> +	return 0;
> +}
> +
> +/* Get length of common rates array potentially limited by max_rate. */
> +static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
> +					  int max_rate)
> +{
> +	return intel_dp_rate_limit_len(intel_dp->common_rates,
> +				       intel_dp->num_common_rates, max_rate);
> +}
> +
>  /* Theoretical max between source and sink */
>  static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
>  {
> @@ -328,22 +350,6 @@ static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
>  	}
>  }
>  
> -/* get length of common rates potentially limited by max_rate */
> -static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp,
> -					  int max_rate)
> -{
> -	const int *common_rates = intel_dp->common_rates;
> -	int i, common_len = intel_dp->num_common_rates;
> -
> -	/* Limit results by potentially reduced max rate */
> -	for (i = 0; i < common_len; i++) {
> -		if (common_rates[common_len - i - 1] <= max_rate)
> -			return common_len - i;
> -	}
> -
> -	return 0;
> -}
> -
>  static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
>  				       uint8_t lane_count)
>  {
> -- 
> 2.11.0
> 
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[PATCH 2/3] drm/i915/dp: clean up source rate limiting for cnl

[Jani Nikula]

Make the limiting rate based instead of messing with the array size.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3c1c11c1cd30..8bef858919c8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -242,7 +242,7 @@ intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 	return max_dotclk;
 }
 
-static int cnl_adjusted_max_rate(struct intel_dp *intel_dp, int size)
+static int cnl_max_source_rate(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
@@ -252,17 +252,17 @@ static int cnl_adjusted_max_rate(struct intel_dp *intel_dp, int size)
 
 	/* Low voltage SKUs are limited to max of 5.4G */
 	if (voltage == VOLTAGE_INFO_0_85V)
-		return size - 2;
+		return 540000;
 
 	/* For this SKU 8.1G is supported in all ports */
 	if (IS_CNL_WITH_PORT_F(dev_priv))
-		return size;
+		return 810000;
 
 	/* For other SKUs, max rate on ports A and B is 5.4G */
 	if (port == PORT_A || port == PORT_D)
-		return size - 2;
+		return 540000;
 
-	return size;
+	return 810000;
 }
 
 static void
@@ -271,7 +271,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 	const int *source_rates;
-	int size;
+	int size, max_rate = 0;
 
 	/* This should only be done once */
 	WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
@@ -281,7 +281,8 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
 		size = ARRAY_SIZE(bxt_rates);
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		source_rates = cnl_rates;
-		size = cnl_adjusted_max_rate(intel_dp, ARRAY_SIZE(cnl_rates));
+		size = ARRAY_SIZE(cnl_rates);
+		max_rate = cnl_max_source_rate(intel_dp);
 	} else if (IS_GEN9_BC(dev_priv)) {
 		source_rates = skl_rates;
 		size = ARRAY_SIZE(skl_rates);
@@ -294,6 +295,9 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
 		size = ARRAY_SIZE(default_rates) - 1;
 	}
 
+	if (max_rate)
+		size = intel_dp_rate_limit_len(source_rates, size, max_rate);
+
 	intel_dp->source_rates = source_rates;
 	intel_dp->num_source_rates = size;
 }
-- 
2.11.0

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Re: [PATCH 2/3] drm/i915/dp: clean up source rate limiting for cnl

[Rodrigo Vivi]

On Thu, Feb 01, 2018 at 11:03:42AM +0000, Jani Nikula wrote:
> Make the limiting rate based instead of messing with the array size.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 18 +++++++++++-------
>  1 file changed, 11 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 3c1c11c1cd30..8bef858919c8 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -242,7 +242,7 @@ intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
>  	return max_dotclk;
>  }
>  
> -static int cnl_adjusted_max_rate(struct intel_dp *intel_dp, int size)
> +static int cnl_max_source_rate(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> @@ -252,17 +252,17 @@ static int cnl_adjusted_max_rate(struct intel_dp *intel_dp, int size)
>  
>  	/* Low voltage SKUs are limited to max of 5.4G */
>  	if (voltage == VOLTAGE_INFO_0_85V)
> -		return size - 2;
> +		return 540000;
>  
>  	/* For this SKU 8.1G is supported in all ports */
>  	if (IS_CNL_WITH_PORT_F(dev_priv))
> -		return size;
> +		return 810000;
>  
>  	/* For other SKUs, max rate on ports A and B is 5.4G */
>  	if (port == PORT_A || port == PORT_D)
> -		return size - 2;
> +		return 540000;
>  
> -	return size;
> +	return 810000;
>  }
>  
>  static void
> @@ -271,7 +271,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>  	const int *source_rates;
> -	int size;
> +	int size, max_rate = 0;
>  
>  	/* This should only be done once */
>  	WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
> @@ -281,7 +281,8 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  		size = ARRAY_SIZE(bxt_rates);
>  	} else if (IS_CANNONLAKE(dev_priv)) {
>  		source_rates = cnl_rates;
> -		size = cnl_adjusted_max_rate(intel_dp, ARRAY_SIZE(cnl_rates));
> +		size = ARRAY_SIZE(cnl_rates);
> +		max_rate = cnl_max_source_rate(intel_dp);
>  	} else if (IS_GEN9_BC(dev_priv)) {
>  		source_rates = skl_rates;
>  		size = ARRAY_SIZE(skl_rates);
> @@ -294,6 +295,9 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  		size = ARRAY_SIZE(default_rates) - 1;
>  	}
>  
> +	if (max_rate)
> +		size = intel_dp_rate_limit_len(source_rates, size, max_rate);
> +
>  	intel_dp->source_rates = source_rates;
>  	intel_dp->num_source_rates = size;
>  }
> -- 
> 2.11.0
> 
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[PATCH 3/3] drm/i915/dp: limit DP link rate based on VBT on CNL+

[Jani Nikula]

We have the max DP link rate info available in VBT since BDB version
216, included in child device config since commit c4fb60b9aba9
("drm/i915/bios: add DP max link rate to VBT child device
struct"). Parse it and use it.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |  1 +
 drivers/gpu/drm/i915/intel_bios.c     | 21 +++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dp.c       |  9 ++++++++-
 drivers/gpu/drm/i915/intel_vbt_defs.h |  5 +++++
 4 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c676269ed843..26b91c25b8a0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1282,6 +1282,7 @@ struct ddi_vbt_port_info {
 
 	uint8_t dp_boost_level;
 	uint8_t hdmi_boost_level;
+	int dp_max_link_rate;		/* 0 for not limited by VBT */
 };
 
 enum psr_lines_to_wait {
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index cf3f8f1ba6f7..4e74aa2f16bc 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -1274,6 +1274,27 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
 		DRM_DEBUG_KMS("VBT HDMI boost level for port %c: %d\n",
 			      port_name(port), info->hdmi_boost_level);
 	}
+
+	/* DP max link rate for CNL+ */
+	if (bdb_version >= 216) {
+		switch (child->dp_max_link_rate) {
+		default:
+		case VBT_DP_MAX_LINK_RATE_HBR3:
+			info->dp_max_link_rate = 810000;
+			break;
+		case VBT_DP_MAX_LINK_RATE_HBR2:
+			info->dp_max_link_rate = 540000;
+			break;
+		case VBT_DP_MAX_LINK_RATE_HBR:
+			info->dp_max_link_rate = 270000;
+			break;
+		case VBT_DP_MAX_LINK_RATE_LBR:
+			info->dp_max_link_rate = 162000;
+			break;
+		}
+		DRM_DEBUG_KMS("VBT DP max link rate for port %c: %d\n",
+			      port_name(port), info->dp_max_link_rate);
+	}
 }
 
 static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8bef858919c8..9a610d4783d8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -270,8 +270,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+	const struct ddi_vbt_port_info *info =
+		&dev_priv->vbt.ddi_port_info[dig_port->base.port];
 	const int *source_rates;
-	int size, max_rate = 0;
+	int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 
 	/* This should only be done once */
 	WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
@@ -295,6 +297,11 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
 		size = ARRAY_SIZE(default_rates) - 1;
 	}
 
+	if (max_rate && vbt_max_rate)
+		max_rate = min(max_rate, vbt_max_rate);
+	else if (vbt_max_rate)
+		max_rate = vbt_max_rate;
+
 	if (max_rate)
 		size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 
diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
index 3d3feee9b5dd..458468237b5f 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -320,6 +320,11 @@ enum vbt_gmbus_ddi {
 	DDC_BUS_DDI_F,
 };
 
+#define VBT_DP_MAX_LINK_RATE_HBR3	0
+#define VBT_DP_MAX_LINK_RATE_HBR2	1
+#define VBT_DP_MAX_LINK_RATE_HBR	2
+#define VBT_DP_MAX_LINK_RATE_LBR	3
+
 /*
  * The child device config, aka the display device data structure, provides a
  * description of a port and its configuration on the platform.
-- 
2.11.0

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Re: [PATCH 3/3] drm/i915/dp: limit DP link rate based on VBT on CNL+

[Ville Syrjälä]

On Thu, Feb 01, 2018 at 01:03:43PM +0200, Jani Nikula wrote:
> We have the max DP link rate info available in VBT since BDB version
> 216, included in child device config since commit c4fb60b9aba9
> ("drm/i915/bios: add DP max link rate to VBT child device
> struct"). Parse it and use it.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  1 +
>  drivers/gpu/drm/i915/intel_bios.c     | 21 +++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_dp.c       |  9 ++++++++-
>  drivers/gpu/drm/i915/intel_vbt_defs.h |  5 +++++
>  4 files changed, 35 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c676269ed843..26b91c25b8a0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1282,6 +1282,7 @@ struct ddi_vbt_port_info {
>  
>  	uint8_t dp_boost_level;
>  	uint8_t hdmi_boost_level;
> +	int dp_max_link_rate;		/* 0 for not limited by VBT */
>  };
>  
>  enum psr_lines_to_wait {
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index cf3f8f1ba6f7..4e74aa2f16bc 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -1274,6 +1274,27 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
>  		DRM_DEBUG_KMS("VBT HDMI boost level for port %c: %d\n",
>  			      port_name(port), info->hdmi_boost_level);
>  	}
> +
> +	/* DP max link rate for CNL+ */
> +	if (bdb_version >= 216) {
> +		switch (child->dp_max_link_rate) {
> +		default:
> +		case VBT_DP_MAX_LINK_RATE_HBR3:
> +			info->dp_max_link_rate = 810000;
> +			break;
> +		case VBT_DP_MAX_LINK_RATE_HBR2:
> +			info->dp_max_link_rate = 540000;
> +			break;
> +		case VBT_DP_MAX_LINK_RATE_HBR:
> +			info->dp_max_link_rate = 270000;
> +			break;
> +		case VBT_DP_MAX_LINK_RATE_LBR:
> +			info->dp_max_link_rate = 162000;
> +			break;
> +		}
> +		DRM_DEBUG_KMS("VBT DP max link rate for port %c: %d\n",
> +			      port_name(port), info->dp_max_link_rate);
> +	}
>  }
>  
>  static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 8bef858919c8..9a610d4783d8 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -270,8 +270,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> +	const struct ddi_vbt_port_info *info =
> +		&dev_priv->vbt.ddi_port_info[dig_port->base.port];
>  	const int *source_rates;
> -	int size, max_rate = 0;
> +	int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
>  
>  	/* This should only be done once */
>  	WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
> @@ -295,6 +297,11 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  		size = ARRAY_SIZE(default_rates) - 1;
>  	}
>  
> +	if (max_rate && vbt_max_rate)
> +		max_rate = min(max_rate, vbt_max_rate);
> +	else if (vbt_max_rate)
> +		max_rate = vbt_max_rate;

I kinda wish this would look exactly like the hdmi version, but
can't do that without populating max_rate for every platform. So
I guess we'll go with this.

Series looks good to me:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +
>  	if (max_rate)
>  		size = intel_dp_rate_limit_len(source_rates, size, max_rate);
>  
> diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
> index 3d3feee9b5dd..458468237b5f 100644
> --- a/drivers/gpu/drm/i915/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
> @@ -320,6 +320,11 @@ enum vbt_gmbus_ddi {
>  	DDC_BUS_DDI_F,
>  };
>  
> +#define VBT_DP_MAX_LINK_RATE_HBR3	0
> +#define VBT_DP_MAX_LINK_RATE_HBR2	1
> +#define VBT_DP_MAX_LINK_RATE_HBR	2
> +#define VBT_DP_MAX_LINK_RATE_LBR	3
> +
>  /*
>   * The child device config, aka the display device data structure, provides a
>   * description of a port and its configuration on the platform.
> -- 
> 2.11.0

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 3/3] drm/i915/dp: limit DP link rate based on VBT on CNL+

[Jani Nikula]

On Thu, 01 Feb 2018, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Feb 01, 2018 at 01:03:43PM +0200, Jani Nikula wrote:
>> We have the max DP link rate info available in VBT since BDB version
>> 216, included in child device config since commit c4fb60b9aba9
>> ("drm/i915/bios: add DP max link rate to VBT child device
>> struct"). Parse it and use it.
>> 
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h       |  1 +
>>  drivers/gpu/drm/i915/intel_bios.c     | 21 +++++++++++++++++++++
>>  drivers/gpu/drm/i915/intel_dp.c       |  9 ++++++++-
>>  drivers/gpu/drm/i915/intel_vbt_defs.h |  5 +++++
>>  4 files changed, 35 insertions(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index c676269ed843..26b91c25b8a0 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1282,6 +1282,7 @@ struct ddi_vbt_port_info {
>>  
>>  	uint8_t dp_boost_level;
>>  	uint8_t hdmi_boost_level;
>> +	int dp_max_link_rate;		/* 0 for not limited by VBT */
>>  };
>>  
>>  enum psr_lines_to_wait {
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
>> index cf3f8f1ba6f7..4e74aa2f16bc 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -1274,6 +1274,27 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
>>  		DRM_DEBUG_KMS("VBT HDMI boost level for port %c: %d\n",
>>  			      port_name(port), info->hdmi_boost_level);
>>  	}
>> +
>> +	/* DP max link rate for CNL+ */
>> +	if (bdb_version >= 216) {
>> +		switch (child->dp_max_link_rate) {
>> +		default:
>> +		case VBT_DP_MAX_LINK_RATE_HBR3:
>> +			info->dp_max_link_rate = 810000;
>> +			break;
>> +		case VBT_DP_MAX_LINK_RATE_HBR2:
>> +			info->dp_max_link_rate = 540000;
>> +			break;
>> +		case VBT_DP_MAX_LINK_RATE_HBR:
>> +			info->dp_max_link_rate = 270000;
>> +			break;
>> +		case VBT_DP_MAX_LINK_RATE_LBR:
>> +			info->dp_max_link_rate = 162000;
>> +			break;
>> +		}
>> +		DRM_DEBUG_KMS("VBT DP max link rate for port %c: %d\n",
>> +			      port_name(port), info->dp_max_link_rate);
>> +	}
>>  }
>>  
>>  static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version)
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 8bef858919c8..9a610d4783d8 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -270,8 +270,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>>  {
>>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>>  	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>> +	const struct ddi_vbt_port_info *info =
>> +		&dev_priv->vbt.ddi_port_info[dig_port->base.port];
>>  	const int *source_rates;
>> -	int size, max_rate = 0;
>> +	int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
>>  
>>  	/* This should only be done once */
>>  	WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
>> @@ -295,6 +297,11 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>>  		size = ARRAY_SIZE(default_rates) - 1;
>>  	}
>>  
>> +	if (max_rate && vbt_max_rate)
>> +		max_rate = min(max_rate, vbt_max_rate);
>> +	else if (vbt_max_rate)
>> +		max_rate = vbt_max_rate;
>
> I kinda wish this would look exactly like the hdmi version, but
> can't do that without populating max_rate for every platform. So
> I guess we'll go with this.

I thought about that, but it's not as useful here as in hdmi because of
the varying number of intermediate rates. So you'll need several arrays
anyway. Some of it could be done, and later on I presume default_rates
will need to get updated for HBR3, so there's room for follow-up.

Pushed this series for now, thanks for the reviews.

BR,
Jani.


>
> Series looks good to me:
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>> +
>>  	if (max_rate)
>>  		size = intel_dp_rate_limit_len(source_rates, size, max_rate);
>>  
>> diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
>> index 3d3feee9b5dd..458468237b5f 100644
>> --- a/drivers/gpu/drm/i915/intel_vbt_defs.h
>> +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
>> @@ -320,6 +320,11 @@ enum vbt_gmbus_ddi {
>>  	DDC_BUS_DDI_F,
>>  };
>>  
>> +#define VBT_DP_MAX_LINK_RATE_HBR3	0
>> +#define VBT_DP_MAX_LINK_RATE_HBR2	1
>> +#define VBT_DP_MAX_LINK_RATE_HBR	2
>> +#define VBT_DP_MAX_LINK_RATE_LBR	3
>> +
>>  /*
>>   * The child device config, aka the display device data structure, provides a
>>   * description of a port and its configuration on the platform.
>> -- 
>> 2.11.0

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH 3/3] drm/i915/dp: limit DP link rate based on VBT on CNL+

[Rodrigo Vivi]

On Thu, Feb 01, 2018 at 11:03:43AM +0000, Jani Nikula wrote:
> We have the max DP link rate info available in VBT since BDB version
> 216, included in child device config since commit c4fb60b9aba9
> ("drm/i915/bios: add DP max link rate to VBT child device
> struct"). Parse it and use it.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  1 +
>  drivers/gpu/drm/i915/intel_bios.c     | 21 +++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_dp.c       |  9 ++++++++-
>  drivers/gpu/drm/i915/intel_vbt_defs.h |  5 +++++
>  4 files changed, 35 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c676269ed843..26b91c25b8a0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1282,6 +1282,7 @@ struct ddi_vbt_port_info {
>  
>  	uint8_t dp_boost_level;
>  	uint8_t hdmi_boost_level;
> +	int dp_max_link_rate;		/* 0 for not limited by VBT */
>  };
>  
>  enum psr_lines_to_wait {
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index cf3f8f1ba6f7..4e74aa2f16bc 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -1274,6 +1274,27 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
>  		DRM_DEBUG_KMS("VBT HDMI boost level for port %c: %d\n",
>  			      port_name(port), info->hdmi_boost_level);
>  	}
> +
> +	/* DP max link rate for CNL+ */
> +	if (bdb_version >= 216) {
> +		switch (child->dp_max_link_rate) {
> +		default:
> +		case VBT_DP_MAX_LINK_RATE_HBR3:
> +			info->dp_max_link_rate = 810000;
> +			break;
> +		case VBT_DP_MAX_LINK_RATE_HBR2:
> +			info->dp_max_link_rate = 540000;
> +			break;
> +		case VBT_DP_MAX_LINK_RATE_HBR:
> +			info->dp_max_link_rate = 270000;
> +			break;
> +		case VBT_DP_MAX_LINK_RATE_LBR:
> +			info->dp_max_link_rate = 162000;
> +			break;

oh! I was missing this conversion....


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>



> +		}
> +		DRM_DEBUG_KMS("VBT DP max link rate for port %c: %d\n",
> +			      port_name(port), info->dp_max_link_rate);
> +	}
>  }
>  
>  static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 8bef858919c8..9a610d4783d8 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -270,8 +270,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> +	const struct ddi_vbt_port_info *info =
> +		&dev_priv->vbt.ddi_port_info[dig_port->base.port];
>  	const int *source_rates;
> -	int size, max_rate = 0;
> +	int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
>  
>  	/* This should only be done once */
>  	WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
> @@ -295,6 +297,11 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  		size = ARRAY_SIZE(default_rates) - 1;
>  	}
>  
> +	if (max_rate && vbt_max_rate)
> +		max_rate = min(max_rate, vbt_max_rate);
> +	else if (vbt_max_rate)
> +		max_rate = vbt_max_rate;
> +
>  	if (max_rate)
>  		size = intel_dp_rate_limit_len(source_rates, size, max_rate);
>  
> diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h b/drivers/gpu/drm/i915/intel_vbt_defs.h
> index 3d3feee9b5dd..458468237b5f 100644
> --- a/drivers/gpu/drm/i915/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
> @@ -320,6 +320,11 @@ enum vbt_gmbus_ddi {
>  	DDC_BUS_DDI_F,
>  };
>  
> +#define VBT_DP_MAX_LINK_RATE_HBR3	0
> +#define VBT_DP_MAX_LINK_RATE_HBR2	1
> +#define VBT_DP_MAX_LINK_RATE_HBR	2
> +#define VBT_DP_MAX_LINK_RATE_LBR	3
> +
>  /*
>   * The child device config, aka the display device data structure, provides a
>   * description of a port and its configuration on the platform.
> -- 
> 2.11.0
> 
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✓ Fi.CI.BAT: success for drm/i915/dp: refactoring + respect vbt max dp rate

[Patchwork]

== Series Details ==

Series: drm/i915/dp: refactoring + respect vbt max dp rate
URL   : https://patchwork.freedesktop.org/series/37475/
State : success

== Summary ==

Series 37475v1 drm/i915/dp: refactoring + respect vbt max dp rate
https://patchwork.freedesktop.org/api/1.0/series/37475/revisions/1/mbox/

Test debugfs_test:
        Subgroup read_all_entries:
                dmesg-fail -> PASS       (fi-elk-e7500) fdo#103989 +10
Test gem_ringfill:
        Subgroup basic-default-hang:
                incomplete -> DMESG-WARN (fi-pnv-d510) fdo#101600
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-b:
                incomplete -> PASS       (fi-snb-2520m) fdo#103713

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:421s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:420s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:374s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:488s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:280s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:477s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:487s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:463s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:453s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:570s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:407s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:280s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:513s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:388s
fi-hsw-4770r     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:397s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:408s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:455s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:411s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:458s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:495s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:452s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:498s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:585s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:429s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:503s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:527s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:484s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:478s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:414s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:431s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:528s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:392s
Blacklisted hosts:
fi-glk-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:471s

3c4e44925b6039250a27f1e0fbd385af0928d3f4 drm-tip: 2018y-02m-01d-10h-29m-46s UTC integration manifest
536a82fd1591 drm/i915/dp: limit DP link rate based on VBT on CNL+
568878614f42 drm/i915/dp: clean up source rate limiting for cnl
e3c6e87de241 drm/i915/dp: abstract rate array length limiting

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7850/issues.html
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✓ Fi.CI.IGT: success for drm/i915/dp: refactoring + respect vbt max dp rate

[Patchwork]

== Series Details ==

Series: drm/i915/dp: refactoring + respect vbt max dp rate
URL   : https://patchwork.freedesktop.org/series/37475/
State : success

== Summary ==

Test gem_exec_schedule:
        Subgroup preempt-other-vebox:
                pass       -> FAIL       (shard-apl) fdo#102848
Test kms_flip:
        Subgroup plain-flip-fb-recreate:
                pass       -> FAIL       (shard-hsw) fdo#100368
Test kms_cursor_crc:
        Subgroup cursor-128x128-suspend:
                pass       -> SKIP       (shard-snb) fdo#103880
Test perf:
        Subgroup buffer-fill:
                fail       -> PASS       (shard-apl) fdo#103755
Test pm_rps:
        Subgroup waitboost:
                pass       -> FAIL       (shard-apl) fdo#102250

fdo#102848 https://bugs.freedesktop.org/show_bug.cgi?id=102848
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103880 https://bugs.freedesktop.org/show_bug.cgi?id=103880
fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755
fdo#102250 https://bugs.freedesktop.org/show_bug.cgi?id=102250

shard-apl        total:2838 pass:1748 dwarn:1   dfail:0   fail:25  skip:1064 time:12638s
shard-hsw        total:2838 pass:1734 dwarn:1   dfail:0   fail:12  skip:1090 time:11965s
shard-snb        total:2838 pass:1329 dwarn:1   dfail:0   fail:10  skip:1498 time:6527s
Blacklisted hosts:
shard-kbl        total:2817 pass:1845 dwarn:12  dfail:1   fail:23  skip:935 time:9496s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7850/shards.html
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Re: [PATCH 0/3] drm/i915/dp: refactoring + respect vbt max dp rate

[Rodrigo Vivi]

On Thu, Feb 01, 2018 at 11:03:40AM +0000, Jani Nikula wrote:
> Hi Rodrigo, this is what I had in mind for the DP CNL and VBT rate limiting, I
> hope you don't mind me writing the patches. It was easier to express myself in C
> than English.

of course I don't mind. Thanks for the clean version.

> 
> BR,
> Jani.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> 
> Jani Nikula (3):
>   drm/i915/dp: abstract rate array length limiting
>   drm/i915/dp: clean up source rate limiting for cnl
>   drm/i915/dp: limit DP link rate based on VBT on CNL+
> 
>  drivers/gpu/drm/i915/i915_drv.h       |  1 +
>  drivers/gpu/drm/i915/intel_bios.c     | 21 ++++++++++++
>  drivers/gpu/drm/i915/intel_dp.c       | 63 ++++++++++++++++++++++-------------
>  drivers/gpu/drm/i915/intel_vbt_defs.h |  5 +++
>  4 files changed, 67 insertions(+), 23 deletions(-)
> 
> -- 
> 2.11.0
> 
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