Re: [Intel-gfx] [PATCH 1/4] drm/i915/dg2: Add Wa_14010547955

[Jani Nikula <jani.nikula@linux.intel.com>]

On Thu, 11 Nov 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
> This workaround is documented a bit strangely in the bspec; it's listed
> as an A0 workaround, but the description clarifies that the workaround
> is implicitly handled by the hardware and what the driver really needs
> to do is program a chicken bit to reenable some internal behavior.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 4 ++++
>  drivers/gpu/drm/i915/i915_reg.h              | 5 +++--
>  2 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 0ceee8ac6671..5d50d06f4eb7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -988,6 +988,10 @@ static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
>  	else if (DISPLAY_VER(dev_priv) >= 13)
>  		tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
>  
> +	/* Wa_14010547955:dg2 */
> +	if (IS_DG2_DISP_STEP(dev_priv, STEP_B0, STEP_FOREVER))

How did we end up with _DISP_ for DG2 when everything else has
_DISPLAY_?

BR,
Jani.


> +		tmp |= DG2_RENDER_CCSTAG_4_3_EN;
> +
>  	intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 07d6cf76c389..680ace373e00 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8480,8 +8480,9 @@ enum {
>  							   _PIPEB_CHICKEN)
>  #define   UNDERRUN_RECOVERY_DISABLE_ADLP	REG_BIT(30)
>  #define   UNDERRUN_RECOVERY_ENABLE_DG2		REG_BIT(30)
> -#define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
> -#define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
> +#define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU	REG_BIT(15)
> +#define   DG2_RENDER_CCSTAG_4_3_EN		REG_BIT(12)
> +#define   PER_PIXEL_ALPHA_BYPASS_EN		REG_BIT(7)
>  
>  #define FF_MODE2			_MMIO(0x6604)
>  #define   FF_MODE2_GS_TIMER_MASK	REG_GENMASK(31, 24)

-- 
Jani Nikula, Intel Open Source Graphics Center