[PATCH 1/5] drm/i915: Supply the extended state flags for forced context load

[PATCH 1/5] drm/i915: Supply the extended state flags for forced context load

[Chris Wilson]

Provide the extended state (or resource streamer bits for Haswell) flags
when doing a forced restore of the current context by temporarily loading
the kernel context.

Fixes: 1fc719d13ac0 ("drm/i915/ringbuffer: Brute force context restore")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index dda671e0a680..4a9f44c61edd 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1556,7 +1556,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
 		*cs++ = MI_SET_CONTEXT;
 		*cs++ = i915_ggtt_offset(to_intel_context(i915->kernel_context,
 							  engine)->state) |
-			MI_MM_SPACE_GTT |
+			flags |
 			MI_RESTORE_INHIBIT;
 	}
 
-- 
2.17.1

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[PATCH 2/5] drm/i915: Dump the ringbuffer of the active request for debugging

[Chris Wilson]

Sometimes we need to see what instructions we emitted for a request to
try and gather a glimmer of insight into what the GPU is doing when it
stops responding.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 35 ++++++++++++++++++++++----
 1 file changed, 30 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index d278fed8cb31..d7f757fb8401 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1443,12 +1443,10 @@ void intel_engine_dump(struct intel_engine_cs *engine,
 
 	rq = i915_gem_find_active_request(engine);
 	if (rq) {
+		void *ring;
+		int size;
+
 		print_request(m, rq, "\t\tactive ");
-		drm_printf(m,
-			   "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
-			   rq->head, rq->postfix, rq->tail,
-			   rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
-			   rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
 		drm_printf(m, "\t\tring->start:  0x%08x\n",
 			   i915_ggtt_offset(rq->ring->vma));
 		drm_printf(m, "\t\tring->head:   0x%08x\n",
@@ -1459,6 +1457,33 @@ void intel_engine_dump(struct intel_engine_cs *engine,
 			   rq->ring->emit);
 		drm_printf(m, "\t\tring->space:  0x%08x\n",
 			   rq->ring->space);
+
+		drm_printf(m,
+			   "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n",
+			   rq->head, rq->postfix, rq->tail,
+			   rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
+			   rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
+
+		size = rq->tail - rq->head;
+		if (rq->tail < rq->head)
+			size += rq->ring->size;
+
+		ring = kmalloc(size, GFP_ATOMIC);
+		if (ring) {
+			const void *vaddr = rq->ring->vaddr;
+			unsigned int head = rq->head;
+			unsigned int len = 0;
+
+			if (rq->tail < head) {
+				len = rq->ring->size - head;
+				memcpy(ring, vaddr + head, len);
+				head = 0;
+			}
+			memcpy(ring + len, vaddr + head, size - len);
+
+			hexdump(m, ring, size);
+			kfree(ring);
+		}
 	}
 
 	rcu_read_unlock();
-- 
2.17.1

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Re: [PATCH 2/5] drm/i915: Dump the ringbuffer of the active request for debugging

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Sometimes we need to see what instructions we emitted for a request to
> try and gather a glimmer of insight into what the GPU is doing when it
> stops responding.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 35 ++++++++++++++++++++++----
>  1 file changed, 30 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index d278fed8cb31..d7f757fb8401 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1443,12 +1443,10 @@ void intel_engine_dump(struct intel_engine_cs *engine,
>  
>  	rq = i915_gem_find_active_request(engine);
>  	if (rq) {
> +		void *ring;
> +		int size;
> +
>  		print_request(m, rq, "\t\tactive ");
> -		drm_printf(m,
> -			   "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
> -			   rq->head, rq->postfix, rq->tail,
> -			   rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
> -			   rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
>  		drm_printf(m, "\t\tring->start:  0x%08x\n",
>  			   i915_ggtt_offset(rq->ring->vma));
>  		drm_printf(m, "\t\tring->head:   0x%08x\n",
> @@ -1459,6 +1457,33 @@ void intel_engine_dump(struct intel_engine_cs *engine,
>  			   rq->ring->emit);
>  		drm_printf(m, "\t\tring->space:  0x%08x\n",
>  			   rq->ring->space);
> +
> +		drm_printf(m,
> +			   "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n",
> +			   rq->head, rq->postfix, rq->tail,
> +			   rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
> +			   rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);

While you are here, you might want to add the new rq->infix to the mix.

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> +
> +		size = rq->tail - rq->head;
> +		if (rq->tail < rq->head)
> +			size += rq->ring->size;
> +
> +		ring = kmalloc(size, GFP_ATOMIC);
> +		if (ring) {
> +			const void *vaddr = rq->ring->vaddr;
> +			unsigned int head = rq->head;
> +			unsigned int len = 0;
> +
> +			if (rq->tail < head) {
> +				len = rq->ring->size - head;
> +				memcpy(ring, vaddr + head, len);
> +				head = 0;
> +			}
> +			memcpy(ring + len, vaddr + head, size - len);
> +
> +			hexdump(m, ring, size);
> +			kfree(ring);
> +		}
>  	}
>  
>  	rcu_read_unlock();
> -- 
> 2.17.1
>
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[PATCH 3/5] drm/i915: Make the hexdump row offset visually distinct

[Chris Wilson]

Currently we use %08x for the row offset, and %08x for the binary
contents of the buffer. This makes it very easily to confuse the two, so
switch to using [%04x] for the start-of-row offset.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index d7f757fb8401..875bd466f3bf 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1258,7 +1258,7 @@ static void hexdump(struct drm_printer *m, const void *buf, size_t len)
 						rowsize, sizeof(u32),
 						line, sizeof(line),
 						false) >= sizeof(line));
-		drm_printf(m, "%08zx %s\n", pos, line);
+		drm_printf(m, "[%04zx] %s\n", pos, line);
 
 		prev = buf + pos;
 		skip = false;
-- 
2.17.1

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Re: [PATCH 3/5] drm/i915: Make the hexdump row offset visually distinct

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Currently we use %08x for the row offset, and %08x for the binary
> contents of the buffer. This makes it very easily to confuse the two, so
> switch to using [%04x] for the start-of-row offset.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index d7f757fb8401..875bd466f3bf 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1258,7 +1258,7 @@ static void hexdump(struct drm_printer *m, const void *buf, size_t len)
>  						rowsize, sizeof(u32),
>  						line, sizeof(line),
>  						false) >= sizeof(line));
> -		drm_printf(m, "%08zx %s\n", pos, line);
> +		drm_printf(m, "[%04zx] %s\n", pos, line);
>  
>  		prev = buf + pos;
>  		skip = false;
> -- 
> 2.17.1
>
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[PATCH 4/5] drm/i915: Show CCID in engine dumps

[Chris Wilson]

For debugging context issues, knowing what context the GPU is
loading/using is helpful.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 875bd466f3bf..5a663dda9fdc 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1273,6 +1273,8 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
 		&engine->execlists;
 	u64 addr;
 
+	if (engine->id == RCS && IS_GEN(dev_priv, 5, 7))
+		drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID));
 	drm_printf(m, "\tRING_START: 0x%08x\n",
 		   I915_READ(RING_START(engine->mmio_base)));
 	drm_printf(m, "\tRING_HEAD:  0x%08x\n",
-- 
2.17.1

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Re: [PATCH 4/5] drm/i915: Show CCID in engine dumps

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> For debugging context issues, knowing what context the GPU is
> loading/using is helpful.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 875bd466f3bf..5a663dda9fdc 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1273,6 +1273,8 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
>  		&engine->execlists;
>  	u64 addr;
>  
> +	if (engine->id == RCS && IS_GEN(dev_priv, 5, 7))
> +		drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID));

You do seem to have an option for other engines as well, but
not through +180 offset :O

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

>  	drm_printf(m, "\tRING_START: 0x%08x\n",
>  		   I915_READ(RING_START(engine->mmio_base)));
>  	drm_printf(m, "\tRING_HEAD:  0x%08x\n",
> -- 
> 2.17.1
>
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[PATCH 5/5] drm/i915/gtt: Only keep gen6 page directories pinned while active

[Chris Wilson]

In order to be able to evict the gen6 ppgtt, we have to unpin it at some
point. We can simply use our context activity tracking to know when the
ppgtt is no longer in use by hardware, and so only keep it pinned while
being used a request.

For the kernel_context (and thus aliasing_ppgtt), it remains pinned at
all times, as the kernel_context itself is pinned at all times.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c     | 36 ++++++++++++++-----------
 drivers/gpu/drm/i915/i915_gem_gtt.h     |  5 ++++
 drivers/gpu/drm/i915/intel_ringbuffer.c | 28 +++++++++++++++++++
 3 files changed, 54 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c6949da3423f..317f27a9d78e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1912,7 +1912,6 @@ static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
 {
 	struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(i915_vm_to_ppgtt(vm));
 
-	i915_vma_unpin(ppgtt->vma);
 	i915_vma_destroy(ppgtt->vma);
 
 	gen6_ppgtt_free_pd(ppgtt);
@@ -1998,10 +1997,19 @@ static struct i915_vma *pd_vma_create(struct gen6_hw_ppgtt *ppgtt, int size)
 	return vma;
 }
 
-static int gen6_ppgtt_pin(struct i915_hw_ppgtt *base)
+int gen6_ppgtt_pin(struct i915_hw_ppgtt *base)
 {
 	struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
 
+	/*
+	 * Workaround the limited maximum vma->pin_count and the aliasing_ppgtt
+	 * which will be pinned into every active context.
+	 * (When vma->pin_count becomes atomic, I expect we will naturally
+	 * need a larger, unpacked, type and kill this redundancy.)
+	 */
+	if (ppgtt->pin_count++)
+		return 0;
+
 	/*
 	 * PPGTT PDEs reside in the GGTT and consists of 512 entries. The
 	 * allocator works in address space sizes, so it's multiplied by page
@@ -2012,6 +2020,17 @@ static int gen6_ppgtt_pin(struct i915_hw_ppgtt *base)
 			    PIN_GLOBAL | PIN_HIGH);
 }
 
+void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base)
+{
+	struct gen6_hw_ppgtt *ppgtt = to_gen6_ppgtt(base);
+
+	GEM_BUG_ON(!ppgtt->pin_count);
+	if (--ppgtt->pin_count)
+		return;
+
+	i915_vma_unpin(ppgtt->vma);
+}
+
 static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
 {
 	struct i915_ggtt * const ggtt = &i915->ggtt;
@@ -2053,21 +2072,8 @@ static struct i915_hw_ppgtt *gen6_ppgtt_create(struct drm_i915_private *i915)
 	if (err)
 		goto err_vma;
 
-	err = gen6_ppgtt_pin(&ppgtt->base);
-	if (err)
-		goto err_pd;
-
-	DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
-			 ppgtt->vma->node.size >> 20,
-			 ppgtt->vma->node.start / PAGE_SIZE);
-
-	DRM_DEBUG_DRIVER("Adding PPGTT at offset %x\n",
-			 ppgtt->base.pd.base.ggtt_offset << 10);
-
 	return &ppgtt->base;
 
-err_pd:
-	gen6_ppgtt_free_pd(ppgtt);
 err_vma:
 	i915_vma_destroy(ppgtt->vma);
 err_scratch:
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 6e9acd99ecc6..d7b7b4afe060 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -412,6 +412,8 @@ struct gen6_hw_ppgtt {
 
 	struct i915_vma *vma;
 	gen6_pte_t __iomem *pd_addr;
+
+	unsigned int pin_count;
 };
 
 #define __to_gen6_ppgtt(base) container_of(base, struct gen6_hw_ppgtt, base)
@@ -625,6 +627,9 @@ static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt)
 		kref_put(&ppgtt->ref, i915_ppgtt_release);
 }
 
+int gen6_ppgtt_pin(struct i915_hw_ppgtt *base);
+void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base);
+
 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv);
 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv);
 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 4a9f44c61edd..06a1b61bee42 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1181,6 +1181,27 @@ static void intel_ring_context_destroy(struct intel_context *ce)
 		__i915_gem_object_release_unless_active(ce->state->obj);
 }
 
+static int __context_pin_ppgtt(struct i915_gem_context *ctx)
+{
+	struct i915_hw_ppgtt *ppgtt;
+	int err = 0;
+
+	ppgtt = ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt;
+	if (ppgtt)
+		err = gen6_ppgtt_pin(ppgtt);
+
+	return err;
+}
+
+static void __context_unpin_ppgtt(struct i915_gem_context *ctx)
+{
+	struct i915_hw_ppgtt *ppgtt;
+
+	ppgtt = ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt;
+	if (ppgtt)
+		gen6_ppgtt_unpin(ppgtt);
+}
+
 static int __context_pin(struct intel_context *ce)
 {
 	struct i915_vma *vma;
@@ -1229,6 +1250,7 @@ static void __context_unpin(struct intel_context *ce)
 
 static void intel_ring_context_unpin(struct intel_context *ce)
 {
+	__context_unpin_ppgtt(ce->gem_context);
 	__context_unpin(ce);
 
 	i915_gem_context_put(ce->gem_context);
@@ -1326,6 +1348,10 @@ __ring_context_pin(struct intel_engine_cs *engine,
 	if (err)
 		goto err;
 
+	err = __context_pin_ppgtt(ce->gem_context);
+	if (err)
+		goto err_unpin;
+
 	i915_gem_context_get(ctx);
 
 	/* One ringbuffer to rule them all */
@@ -1334,6 +1360,8 @@ __ring_context_pin(struct intel_engine_cs *engine,
 
 	return ce;
 
+err_unpin:
+	__context_unpin(ce);
 err:
 	ce->pin_count = 0;
 	return ERR_PTR(err);
-- 
2.17.1

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✗ Fi.CI.BAT: failure for series starting with [1/5] drm/i915: Supply the extended state flags for forced context load

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915: Supply the extended state flags for forced context load
URL   : https://patchwork.freedesktop.org/series/44703/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4310 -> Patchwork_9287 =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_9287 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9287, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/44703/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9287:

  === IGT changes ===

    ==== Possible regressions ====

    igt@gem_exec_suspend@basic-s4-devices:
      fi-snb-2520m:       PASS -> DMESG-WARN

    
== Known issues ==

  Here are the changes found in Patchwork_9287 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_exec_gttfill@basic:
      fi-byt-n2820:       PASS -> FAIL (fdo#106744)

    igt@gem_exec_suspend@basic-s4-devices:
      fi-hsw-peppy:       PASS -> FAIL (fdo#105900)
      fi-hsw-4770r:       PASS -> FAIL (fdo#105900)

    igt@kms_chamelium@dp-crc-fast:
      fi-kbl-7500u:       PASS -> FAIL (fdo#103841)

    igt@kms_flip@basic-flip-vs-dpms:
      fi-skl-6700hq:      PASS -> DMESG-WARN (fdo#105998)
      fi-glk-j4005:       PASS -> DMESG-WARN (fdo#106000)

    igt@kms_flip@basic-plain-flip:
      fi-glk-j4005:       PASS -> DMESG-WARN (fdo#106097)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
      fi-snb-2520m:       PASS -> INCOMPLETE (fdo#103713)

    igt@prime_vgem@basic-fence-flip:
      fi-ilk-650:         PASS -> FAIL (fdo#104008)

    
    ==== Possible fixes ====

    igt@gem_ctx_create@basic-files:
      fi-glk-j4005:       DMESG-WARN (fdo#105719) -> PASS

    igt@kms_flip@basic-flip-vs-modeset:
      fi-skl-6700hq:      DMESG-WARN (fdo#105998) -> PASS

    
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
  fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719
  fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900
  fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
  fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000
  fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097
  fdo#106744 https://bugs.freedesktop.org/show_bug.cgi?id=106744


== Participating hosts (43 -> 38) ==

  Missing    (5): fi-ctg-p8600 fi-byt-squawks fi-ilk-m540 fi-bxt-dsi fi-bsw-cyan 


== Build changes ==

    * Linux: CI_DRM_4310 -> Patchwork_9287

  CI_DRM_4310: 5945ab6707472bde0c3bc12836252b487ecfeb72 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4518: e4908004547b63131352fbc0ddcdb1d3d55480e0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9287: c1384e70203bbbde6f9fc4db21f2a608f75d1d3d @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

c1384e70203b drm/i915/gtt: Only keep gen6 page directories pinned while active
7c612ae91cd5 drm/i915: Show CCID in engine dumps
584d28cba8b8 drm/i915: Make the hexdump row offset visually distinct
68bdd66e124a drm/i915: Dump the ringbuffer of the active request for debugging
cc8b1343f906 drm/i915: Supply the extended state flags for forced context load

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9287/issues.html
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[PATCH 1/5] drm/i915: Move GEM sanitize from resume_early to resume

[Chris Wilson]

This should be a no-op in terms of our control flow, we move the
sanitization (GPU reset) from the bottom of the early resume phase to
the top of the next. However, following hibernation debug, the power
code skips the early resume phase, but as we are about to completely
restore the GTT mappings, we first need to stop the GPU using them i.e.
perform a GPU reset (i915_gem_sanitize()).

Testcase: igt/gem_exec_suspend/basic-S4-devices
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6e6413c1d068..7423d78f38f4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1698,6 +1698,8 @@ static int i915_drm_resume(struct drm_device *dev)
 	disable_rpm_wakeref_asserts(dev_priv);
 	intel_sanitize_gt_powersave(dev_priv);
 
+	i915_gem_sanitize(dev_priv);
+
 	ret = i915_ggtt_enable_hw(dev_priv);
 	if (ret)
 		DRM_ERROR("failed to re-enable GGTT\n");
@@ -1839,8 +1841,6 @@ static int i915_drm_resume_early(struct drm_device *dev)
 	else
 		intel_display_set_init_power(dev_priv, true);
 
-	i915_gem_sanitize(dev_priv);
-
 	enable_rpm_wakeref_asserts(dev_priv);
 
 out:
-- 
2.17.1

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[PATCH 4/5] drm/i915: Show CCID in engine dumps

[Chris Wilson]

For debugging context issues, knowing what context the GPU is
loading/using is helpful.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 875bd466f3bf..5a663dda9fdc 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1273,6 +1273,8 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine,
 		&engine->execlists;
 	u64 addr;
 
+	if (engine->id == RCS && IS_GEN(dev_priv, 5, 7))
+		drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID));
 	drm_printf(m, "\tRING_START: 0x%08x\n",
 		   I915_READ(RING_START(engine->mmio_base)));
 	drm_printf(m, "\tRING_HEAD:  0x%08x\n",
-- 
2.17.1

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Re: [PATCH 4/5] drm/i915: Show CCID in engine dumps

[Joonas Lahtinen]

Quoting Chris Wilson (2018-06-14 12:41:02)
> For debugging context issues, knowing what context the GPU is
> loading/using is helpful.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

On the GPU error state, we capture point blank if INTEL_GEN() >= 5, any
specific reason to differ from there?

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas
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Re: [PATCH 4/5] drm/i915: Show CCID in engine dumps

[Chris Wilson]

Quoting Joonas Lahtinen (2018-06-14 13:14:09)
> Quoting Chris Wilson (2018-06-14 12:41:02)
> > For debugging context issues, knowing what context the GPU is
> > loading/using is helpful.
> > 
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> 
> On the GPU error state, we capture point blank if INTEL_GEN() >= 5, any
> specific reason to differ from there?

That I need to work out what we need to capture for execlists. Is CCID
per-engine on gen8+, although iirc CCID is gone on gen8. Yup, all 0s.

So CCID is not what we want, but we do want something :)
Maybe it's execlists debug status?
-Chris
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