* [PATCH] drm/i915/psr: Implement WA to help reach PC10
2024-09-09 6:32 [PATCH] drm/i915/psr: Implment " Suraj Kandpal
@ 2024-09-20 9:12 ` Suraj Kandpal
2024-09-20 11:45 ` Hogander, Jouni
0 siblings, 1 reply; 13+ messages in thread
From: Suraj Kandpal @ 2024-09-20 9:12 UTC (permalink / raw)
To: intel-gfx; +Cc: uma.shankar, jouni.hogander, Suraj Kandpal
To reach PC10 when PKG_C_LATENCY is configure we must do the following
things
1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
2) Allow PSR2 deep sleep when DC5 can be entered
3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
not happening.
--v2
-Switch condition and do an early return [Jani]
-Do some checks in compute_config [Jani]
-Do not use register reads as a method of checking states for
DPKGC or delayed vblank [Jani]
-Use another way to see is vblank interrupts are disabled or not [Jani]
--v3
-Use has_psr to check if psr can be enabled or not for dc5_entry cond
[Uma]
-Move the dc5 entry computation to psr_compute_config [Jouni]
-No need to change sequence of enabled and activate,
so dont make hsw_psr1_activate return anything [Jouni]
-Use has_psr to stop psr1 activation [Jouni]
-Use lineage no. in WA
-Add the display ver restrictions for WA
--v4
-use more appropriate name for check_vblank_limit() [Jouni]
-Cover the case for idle frames when dpkgc is not configured [Jouni]
-Check psr only for edp [Jouni]
--v5
-move psr1 handling to plane update [Jouni]
-add todo for cases when vblank is enabled when psr enabled [Jouni]
-use intel_display instead of drm_i915_private
--v6
-check target_dc_state [Jouni]
-fix condition in pre/post plane update [Jouni]
--v7
-fix has_psr condition [Uma]
-fix typo in commit subject [Uma]
-put psr1_wa check in its own helper [Uma]
-fix the dc_entry check [Jouni]
-use HAS_PSR() to cover two edp one with psr and one nonpsr [Jouni]
WA: 22019444797
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/display/intel_psr.c | 119 +++++++++++++++++-
2 files changed, 121 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 3e694c1204db..2d790abee76e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1577,6 +1577,9 @@ struct intel_psr {
#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
u32 debug;
+ bool is_dpkgc_configured;
+ bool is_dc5_entry_possible;
+ bool is_wa_delayed_vblank_limit;
bool sink_support;
bool source_support;
bool enabled;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 5b355d0a3565..b882ff25fb92 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -26,6 +26,7 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_damage_helper.h>
#include <drm/drm_debugfs.h>
+#include <drm/drm_vblank.h>
#include "i915_drv.h"
#include "i915_reg.h"
@@ -895,6 +896,89 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
return idle_frames;
}
+static bool
+intel_psr_check_wa_delayed_vblank(const struct drm_display_mode *adjusted_mode)
+{
+ return (adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay) >= 6;
+}
+
+/*
+ * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
+ * VRR is not enabled
+ */
+static bool intel_psr_is_dpkgc_configured(struct intel_display *display,
+ struct intel_atomic_state *state)
+{
+ struct intel_crtc *intel_crtc;
+ struct intel_crtc_state *crtc_state;
+ int i;
+
+ if (DISPLAY_VER(display) < 20)
+ return false;
+
+ for_each_new_intel_crtc_in_state(state, intel_crtc, crtc_state, i) {
+ if (!intel_crtc->active)
+ continue;
+
+ if (crtc_state->vrr.enable)
+ return false;
+ }
+
+ return true;
+}
+
+static bool wa_22019444797_psr1_check(const struct intel_crtc_state *crtc_state,
+ struct intel_psr *psr)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ return DISPLAY_VER(display) == 20 && psr->is_dpkgc_configured &&
+ (psr->is_wa_delayed_vblank_limit || !psr->is_dc5_entry_possible) &&
+ !crtc_state->has_sel_update && !crtc_state->has_panel_replay;
+}
+
+/*
+ * DC5 entry is only possible if vblank interrupt is disabled
+ * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
+ * enabled encoders.
+ */
+static bool
+intel_psr_is_dc5_entry_possible(struct intel_display *display,
+ struct intel_atomic_state *state)
+{
+ struct intel_crtc *intel_crtc;
+ struct intel_crtc_state *crtc_state;
+ int i;
+
+ if ((display->power.domains.target_dc_state &
+ DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
+ return false;
+
+ for_each_new_intel_crtc_in_state(state, intel_crtc, crtc_state, i) {
+ struct drm_crtc *crtc = &intel_crtc->base;
+ struct drm_vblank_crtc *vblank;
+ struct intel_encoder *encoder;
+
+ if (!intel_crtc->active)
+ continue;
+
+ vblank = drm_crtc_vblank_crtc(crtc);
+
+ if (vblank->enabled)
+ return false;
+
+ if (!crtc_state->has_psr)
+ return false;
+
+ for_each_encoder_on_crtc(display->drm, crtc, encoder)
+ if (encoder->type != INTEL_OUTPUT_EDP ||
+ !CAN_PSR(enc_to_intel_dp(encoder)))
+ return false;
+ }
+
+ return true;
+}
+
static void hsw_activate_psr1(struct intel_dp *intel_dp)
{
struct intel_display *display = to_intel_display(intel_dp);
@@ -1007,7 +1091,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
u32 val = EDP_PSR2_ENABLE;
u32 psr_val = 0;
- val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ /*
+ * Wa_22019444797
+ * TODO: Disable idle frames when vblank gets enabled while
+ * PSR2 is enabled
+ */
+ if (DISPLAY_VER(dev_priv) != 20 ||
+ !intel_dp->psr.is_dpkgc_configured ||
+ intel_dp->psr.is_dc5_entry_possible)
+ val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
val |= EDP_SU_TRACK_ENABLE;
@@ -2692,10 +2784,20 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_encoder *encoder;
+ bool dpkgc_configured = false, dc5_entry_possible = false;
+ bool wa_delayed_vblank_limit = false;
if (!HAS_PSR(display))
return;
+ if (DISPLAY_VER(display) == 20) {
+ dpkgc_configured = intel_psr_is_dpkgc_configured(display, state);
+ dc5_entry_possible =
+ intel_psr_is_dc5_entry_possible(display, state);
+ wa_delayed_vblank_limit =
+ intel_psr_check_wa_delayed_vblank(&new_crtc_state->hw.adjusted_mode);
+ }
+
for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
old_crtc_state->uapi.encoder_mask) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2704,6 +2806,12 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
mutex_lock(&psr->lock);
+ if (DISPLAY_VER(i915) == 20) {
+ psr->is_dpkgc_configured = dpkgc_configured;
+ psr->is_dc5_entry_possible = dc5_entry_possible;
+ psr->is_wa_delayed_vblank_limit = wa_delayed_vblank_limit;
+ }
+
/*
* Reasons to disable:
* - PSR disabled in new state
@@ -2711,6 +2819,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
* - Changing between PSR versions
* - Region Early Transport changing
* - Display WA #1136: skl, bxt
+ * - Display WA_22019444797
*/
needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
needs_to_disable |= !new_crtc_state->has_psr;
@@ -2720,6 +2829,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
psr->su_region_et_enabled;
needs_to_disable |= DISPLAY_VER(i915) < 11 &&
new_crtc_state->wm_level_disabled;
+ /* TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled */
+ needs_to_disable |= wa_22019444797_psr1_check(new_crtc_state, psr);
if (psr->enabled && needs_to_disable)
intel_psr_disable_locked(intel_dp);
@@ -2760,6 +2871,12 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
keep_disabled |= DISPLAY_VER(display) < 11 &&
crtc_state->wm_level_disabled;
+ /*
+ * Wa_22019444797
+ * TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled
+ */
+ keep_disabled |= wa_22019444797_psr1_check(crtc_state, psr);
+
if (!psr->enabled && !keep_disabled)
intel_psr_enable_locked(intel_dp, crtc_state);
else if (psr->enabled && !crtc_state->wm_level_disabled)
--
2.43.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/i915/psr: Implement WA to help reach PC10
2024-09-20 9:12 ` [PATCH] drm/i915/psr: Implement " Suraj Kandpal
@ 2024-09-20 11:45 ` Hogander, Jouni
2024-09-23 2:54 ` Kandpal, Suraj
0 siblings, 1 reply; 13+ messages in thread
From: Hogander, Jouni @ 2024-09-20 11:45 UTC (permalink / raw)
To: Kandpal, Suraj, intel-gfx@lists.freedesktop.org; +Cc: Shankar, Uma
On Fri, 2024-09-20 at 14:42 +0530, Suraj Kandpal wrote:
> To reach PC10 when PKG_C_LATENCY is configure we must do the
> following
> things
> 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> entered
> 2) Allow PSR2 deep sleep when DC5 can be entered
> 3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
> eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
> not happening.
One comment below related to PantherLake. Otherwise patch looks ok to
me.
>
> --v2
> -Switch condition and do an early return [Jani]
> -Do some checks in compute_config [Jani]
> -Do not use register reads as a method of checking states for
> DPKGC or delayed vblank [Jani]
> -Use another way to see is vblank interrupts are disabled or not
> [Jani]
>
> --v3
> -Use has_psr to check if psr can be enabled or not for dc5_entry cond
> [Uma]
> -Move the dc5 entry computation to psr_compute_config [Jouni]
> -No need to change sequence of enabled and activate,
> so dont make hsw_psr1_activate return anything [Jouni]
> -Use has_psr to stop psr1 activation [Jouni]
> -Use lineage no. in WA
> -Add the display ver restrictions for WA
>
> --v4
> -use more appropriate name for check_vblank_limit() [Jouni]
> -Cover the case for idle frames when dpkgc is not configured [Jouni]
> -Check psr only for edp [Jouni]
>
> --v5
> -move psr1 handling to plane update [Jouni]
> -add todo for cases when vblank is enabled when psr enabled [Jouni]
> -use intel_display instead of drm_i915_private
>
> --v6
> -check target_dc_state [Jouni]
> -fix condition in pre/post plane update [Jouni]
>
> --v7
> -fix has_psr condition [Uma]
> -fix typo in commit subject [Uma]
> -put psr1_wa check in its own helper [Uma]
> -fix the dc_entry check [Jouni]
> -use HAS_PSR() to cover two edp one with psr and one nonpsr [Jouni]
>
> WA: 22019444797
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 3 +
> drivers/gpu/drm/i915/display/intel_psr.c | 119
> +++++++++++++++++-
> 2 files changed, 121 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 3e694c1204db..2d790abee76e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1577,6 +1577,9 @@ struct intel_psr {
> #define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
>
> u32 debug;
> + bool is_dpkgc_configured;
> + bool is_dc5_entry_possible;
> + bool is_wa_delayed_vblank_limit;
> bool sink_support;
> bool source_support;
> bool enabled;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 5b355d0a3565..b882ff25fb92 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -26,6 +26,7 @@
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_damage_helper.h>
> #include <drm/drm_debugfs.h>
> +#include <drm/drm_vblank.h>
>
> #include "i915_drv.h"
> #include "i915_reg.h"
> @@ -895,6 +896,89 @@ static u8 psr_compute_idle_frames(struct
> intel_dp *intel_dp)
> return idle_frames;
> }
>
> +static bool
> +intel_psr_check_wa_delayed_vblank(const struct drm_display_mode
> *adjusted_mode)
> +{
> + return (adjusted_mode->crtc_vblank_start - adjusted_mode-
> >crtc_vdisplay) >= 6;
> +}
> +
> +/*
> + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> + * VRR is not enabled
> + */
> +static bool intel_psr_is_dpkgc_configured(struct intel_display
> *display,
> + struct intel_atomic_state
> *state)
> +{
> + struct intel_crtc *intel_crtc;
> + struct intel_crtc_state *crtc_state;
> + int i;
> +
> + if (DISPLAY_VER(display) < 20)
> + return false;
> +
> + for_each_new_intel_crtc_in_state(state, intel_crtc,
> crtc_state, i) {
> + if (!intel_crtc->active)
> + continue;
> +
> + if (crtc_state->vrr.enable)
> + return false;
> + }
> +
> + return true;
> +}
> +
> +static bool wa_22019444797_psr1_check(const struct intel_crtc_state
> *crtc_state,
> + struct intel_psr *psr)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> +
> + return DISPLAY_VER(display) == 20 && psr->is_dpkgc_configured
> &&
> + (psr->is_wa_delayed_vblank_limit || !psr-
> >is_dc5_entry_possible) &&
> + !crtc_state->has_sel_update && !crtc_state-
> >has_panel_replay;
> +}
> +
> +/*
> + * DC5 entry is only possible if vblank interrupt is disabled
> + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> + * enabled encoders.
> + */
> +static bool
> +intel_psr_is_dc5_entry_possible(struct intel_display *display,
> + struct intel_atomic_state *state)
> +{
> + struct intel_crtc *intel_crtc;
> + struct intel_crtc_state *crtc_state;
> + int i;
> +
> + if ((display->power.domains.target_dc_state &
> + DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
> + return false;
> +
> + for_each_new_intel_crtc_in_state(state, intel_crtc,
> crtc_state, i) {
> + struct drm_crtc *crtc = &intel_crtc->base;
> + struct drm_vblank_crtc *vblank;
> + struct intel_encoder *encoder;
> +
> + if (!intel_crtc->active)
> + continue;
> +
> + vblank = drm_crtc_vblank_crtc(crtc);
> +
> + if (vblank->enabled)
> + return false;
> +
> + if (!crtc_state->has_psr)
> + return false;
> +
> + for_each_encoder_on_crtc(display->drm, crtc, encoder)
> + if (encoder->type != INTEL_OUTPUT_EDP ||
> + !CAN_PSR(enc_to_intel_dp(encoder)))
> + return false;
> + }
> +
> + return true;
> +}
> +
> static void hsw_activate_psr1(struct intel_dp *intel_dp)
> {
> struct intel_display *display = to_intel_display(intel_dp);
> @@ -1007,7 +1091,15 @@ static void hsw_activate_psr2(struct intel_dp
> *intel_dp)
> u32 val = EDP_PSR2_ENABLE;
> u32 psr_val = 0;
>
> - val |=
> EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> + /*
> + * Wa_22019444797
> + * TODO: Disable idle frames when vblank gets enabled while
> + * PSR2 is enabled
> + */
> + if (DISPLAY_VER(dev_priv) != 20 ||
I think same Workaround is needed by PantherLake but only if stepping
is A0. You could have this here:
(DISPLAY_VER(display) != 20 && !IS_DISPLAY_VER_STEP(display, IP_VER(30,
0), STEP_A0, STEP_B0))
BR,
Jouni Högander
> + !intel_dp->psr.is_dpkgc_configured ||
> + intel_dp->psr.is_dc5_entry_possible)
> + val |=
> EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
>
> if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
> val |= EDP_SU_TRACK_ENABLE;
> @@ -2692,10 +2784,20 @@ void intel_psr_pre_plane_update(struct
> intel_atomic_state *state,
> const struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> struct intel_encoder *encoder;
> + bool dpkgc_configured = false, dc5_entry_possible = false;
> + bool wa_delayed_vblank_limit = false;
>
> if (!HAS_PSR(display))
> return;
>
> + if (DISPLAY_VER(display) == 20) {
> + dpkgc_configured =
> intel_psr_is_dpkgc_configured(display, state);
> + dc5_entry_possible =
> + intel_psr_is_dc5_entry_possible(display,
> state);
> + wa_delayed_vblank_limit =
> + intel_psr_check_wa_delayed_vblank(&new_crtc_s
> tate->hw.adjusted_mode);
> + }
> +
> for_each_intel_encoder_mask_with_psr(state->base.dev,
> encoder,
> old_crtc_state-
> >uapi.encoder_mask) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> @@ -2704,6 +2806,12 @@ void intel_psr_pre_plane_update(struct
> intel_atomic_state *state,
>
> mutex_lock(&psr->lock);
>
> + if (DISPLAY_VER(i915) == 20) {
> + psr->is_dpkgc_configured = dpkgc_configured;
> + psr->is_dc5_entry_possible =
> dc5_entry_possible;
> + psr->is_wa_delayed_vblank_limit =
> wa_delayed_vblank_limit;
> + }
> +
> /*
> * Reasons to disable:
> * - PSR disabled in new state
> @@ -2711,6 +2819,7 @@ void intel_psr_pre_plane_update(struct
> intel_atomic_state *state,
> * - Changing between PSR versions
> * - Region Early Transport changing
> * - Display WA #1136: skl, bxt
> + * - Display WA_22019444797
> */
> needs_to_disable |=
> intel_crtc_needs_modeset(new_crtc_state);
> needs_to_disable |= !new_crtc_state->has_psr;
> @@ -2720,6 +2829,8 @@ void intel_psr_pre_plane_update(struct
> intel_atomic_state *state,
> psr->su_region_et_enabled;
> needs_to_disable |= DISPLAY_VER(i915) < 11 &&
> new_crtc_state->wm_level_disabled;
> + /* TODO: Disable PSR1 when vblank gets enabled while
> PSR1 is enabled */
> + needs_to_disable |=
> wa_22019444797_psr1_check(new_crtc_state, psr);
>
> if (psr->enabled && needs_to_disable)
> intel_psr_disable_locked(intel_dp);
> @@ -2760,6 +2871,12 @@ void intel_psr_post_plane_update(struct
> intel_atomic_state *state,
> keep_disabled |= DISPLAY_VER(display) < 11 &&
> crtc_state->wm_level_disabled;
>
> + /*
> + * Wa_22019444797
> + * TODO: Disable PSR1 when vblank gets enabled while
> PSR1 is enabled
> + */
> + keep_disabled |=
> wa_22019444797_psr1_check(crtc_state, psr);
> +
> if (!psr->enabled && !keep_disabled)
> intel_psr_enable_locked(intel_dp,
> crtc_state);
> else if (psr->enabled && !crtc_state-
> >wm_level_disabled)
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH] drm/i915/psr: Implement WA to help reach PC10
2024-09-20 11:45 ` Hogander, Jouni
@ 2024-09-23 2:54 ` Kandpal, Suraj
2024-09-23 10:23 ` Shankar, Uma
0 siblings, 1 reply; 13+ messages in thread
From: Kandpal, Suraj @ 2024-09-23 2:54 UTC (permalink / raw)
To: Hogander, Jouni, intel-gfx@lists.freedesktop.org, Shankar, Uma
> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Friday, September 20, 2024 5:16 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [PATCH] drm/i915/psr: Implement WA to help reach PC10
>
> On Fri, 2024-09-20 at 14:42 +0530, Suraj Kandpal wrote:
> > To reach PC10 when PKG_C_LATENCY is configure we must do the
> following
> > things
> > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> > entered
> > 2) Allow PSR2 deep sleep when DC5 can be entered
> > 3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
> > eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
> > not happening.
>
> One comment below related to PantherLake. Otherwise patch looks ok to
> me.
>
>
> >
> > --v2
> > -Switch condition and do an early return [Jani] -Do some checks in
> > compute_config [Jani] -Do not use register reads as a method of
> > checking states for DPKGC or delayed vblank [Jani] -Use another way to
> > see is vblank interrupts are disabled or not [Jani]
> >
> > --v3
> > -Use has_psr to check if psr can be enabled or not for dc5_entry cond
> > [Uma] -Move the dc5 entry computation to psr_compute_config [Jouni]
> > -No need to change sequence of enabled and activate, so dont make
> > hsw_psr1_activate return anything [Jouni] -Use has_psr to stop psr1
> > activation [Jouni] -Use lineage no. in WA -Add the display ver
> > restrictions for WA
> >
> > --v4
> > -use more appropriate name for check_vblank_limit() [Jouni] -Cover the
> > case for idle frames when dpkgc is not configured [Jouni] -Check psr
> > only for edp [Jouni]
> >
> > --v5
> > -move psr1 handling to plane update [Jouni] -add todo for cases when
> > vblank is enabled when psr enabled [Jouni] -use intel_display instead
> > of drm_i915_private
> >
> > --v6
> > -check target_dc_state [Jouni]
> > -fix condition in pre/post plane update [Jouni]
> >
> > --v7
> > -fix has_psr condition [Uma]
> > -fix typo in commit subject [Uma]
> > -put psr1_wa check in its own helper [Uma] -fix the dc_entry check
> > [Jouni] -use HAS_PSR() to cover two edp one with psr and one nonpsr
> > [Jouni]
> >
> > WA: 22019444797
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > .../drm/i915/display/intel_display_types.h | 3 +
> > drivers/gpu/drm/i915/display/intel_psr.c | 119
> > +++++++++++++++++-
> > 2 files changed, 121 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 3e694c1204db..2d790abee76e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1577,6 +1577,9 @@ struct intel_psr {
> > #define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
> >
> > u32 debug;
> > + bool is_dpkgc_configured;
> > + bool is_dc5_entry_possible;
> > + bool is_wa_delayed_vblank_limit;
> > bool sink_support;
> > bool source_support;
> > bool enabled;
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 5b355d0a3565..b882ff25fb92 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -26,6 +26,7 @@
> > #include <drm/drm_atomic_helper.h>
> > #include <drm/drm_damage_helper.h>
> > #include <drm/drm_debugfs.h>
> > +#include <drm/drm_vblank.h>
> >
> > #include "i915_drv.h"
> > #include "i915_reg.h"
> > @@ -895,6 +896,89 @@ static u8 psr_compute_idle_frames(struct
> intel_dp
> > *intel_dp)
> > return idle_frames;
> > }
> >
> > +static bool
> > +intel_psr_check_wa_delayed_vblank(const struct drm_display_mode
> > *adjusted_mode)
> > +{
> > + return (adjusted_mode->crtc_vblank_start - adjusted_mode-
> > >crtc_vdisplay) >= 6;
> > +}
> > +
> > +/*
> > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> > + * VRR is not enabled
> > + */
> > +static bool intel_psr_is_dpkgc_configured(struct intel_display
> > *display,
> > + struct intel_atomic_state
> > *state)
> > +{
> > + struct intel_crtc *intel_crtc;
> > + struct intel_crtc_state *crtc_state;
> > + int i;
> > +
> > + if (DISPLAY_VER(display) < 20)
> > + return false;
> > +
> > + for_each_new_intel_crtc_in_state(state, intel_crtc,
> > crtc_state, i) {
> > + if (!intel_crtc->active)
> > + continue;
> > +
> > + if (crtc_state->vrr.enable)
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > +static bool wa_22019444797_psr1_check(const struct intel_crtc_state
> > *crtc_state,
> > + struct intel_psr *psr) {
> > + struct intel_display *display = to_intel_display(crtc_state);
> > +
> > + return DISPLAY_VER(display) == 20 && psr->is_dpkgc_configured
> > &&
> > + (psr->is_wa_delayed_vblank_limit || !psr-
> > >is_dc5_entry_possible) &&
> > + !crtc_state->has_sel_update && !crtc_state-
> > >has_panel_replay;
> > +}
> > +
> > +/*
> > + * DC5 entry is only possible if vblank interrupt is disabled
> > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> > + * enabled encoders.
> > + */
> > +static bool
> > +intel_psr_is_dc5_entry_possible(struct intel_display *display,
> > + struct intel_atomic_state *state) {
> > + struct intel_crtc *intel_crtc;
> > + struct intel_crtc_state *crtc_state;
> > + int i;
> > +
> > + if ((display->power.domains.target_dc_state &
> > + DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
> > + return false;
> > +
> > + for_each_new_intel_crtc_in_state(state, intel_crtc,
> > crtc_state, i) {
> > + struct drm_crtc *crtc = &intel_crtc->base;
> > + struct drm_vblank_crtc *vblank;
> > + struct intel_encoder *encoder;
> > +
> > + if (!intel_crtc->active)
> > + continue;
> > +
> > + vblank = drm_crtc_vblank_crtc(crtc);
> > +
> > + if (vblank->enabled)
> > + return false;
> > +
> > + if (!crtc_state->has_psr)
> > + return false;
> > +
> > + for_each_encoder_on_crtc(display->drm, crtc, encoder)
> > + if (encoder->type != INTEL_OUTPUT_EDP ||
> > + !CAN_PSR(enc_to_intel_dp(encoder)))
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > static void hsw_activate_psr1(struct intel_dp *intel_dp)
> > {
> > struct intel_display *display = to_intel_display(intel_dp); @@
> > -1007,7 +1091,15 @@ static void hsw_activate_psr2(struct intel_dp
> > *intel_dp)
> > u32 val = EDP_PSR2_ENABLE;
> > u32 psr_val = 0;
> >
> > - val |=
> > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > + /*
> > + * Wa_22019444797
> > + * TODO: Disable idle frames when vblank gets enabled while
> > + * PSR2 is enabled
> > + */
> > + if (DISPLAY_VER(dev_priv) != 20 ||
>
>
> I think same Workaround is needed by PantherLake but only if stepping is
> A0. You could have this here:
>
> (DISPLAY_VER(display) != 20 && !IS_DISPLAY_VER_STEP(display, IP_VER(30,
> 0), STEP_A0, STEP_B0))
>
I do see the WA mentioned in bspec 74219 but the I don’t see any individual HSD cloned for it.
Moreover it is for one stepping and a driver temp workaround not sure if I need to implement this
@Shankar, Uma what do you suggest should I float a version implementing this or do this later on requirement
Regards,
Suraj Kandpal
> BR,
>
> Jouni Högander
>
>
> > + !intel_dp->psr.is_dpkgc_configured ||
> > + intel_dp->psr.is_dc5_entry_possible)
> > + val |=
> > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> >
> > if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
> > val |= EDP_SU_TRACK_ENABLE; @@ -2692,10 +2784,20 @@
> > void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> > const struct intel_crtc_state *new_crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > struct intel_encoder *encoder;
> > + bool dpkgc_configured = false, dc5_entry_possible = false;
> > + bool wa_delayed_vblank_limit = false;
> >
> > if (!HAS_PSR(display))
> > return;
> >
> > + if (DISPLAY_VER(display) == 20) {
> > + dpkgc_configured =
> > intel_psr_is_dpkgc_configured(display, state);
> > + dc5_entry_possible =
> > + intel_psr_is_dc5_entry_possible(display,
> > state);
> > + wa_delayed_vblank_limit =
> > + intel_psr_check_wa_delayed_vblank(&new_crtc_s
> > tate->hw.adjusted_mode);
> > + }
> > +
> > for_each_intel_encoder_mask_with_psr(state->base.dev,
> > encoder,
> > old_crtc_state-
> > >uapi.encoder_mask) {
> > struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > @@ -2704,6 +2806,12 @@ void intel_psr_pre_plane_update(struct
> > intel_atomic_state *state,
> >
> > mutex_lock(&psr->lock);
> >
> > + if (DISPLAY_VER(i915) == 20) {
> > + psr->is_dpkgc_configured = dpkgc_configured;
> > + psr->is_dc5_entry_possible =
> > dc5_entry_possible;
> > + psr->is_wa_delayed_vblank_limit =
> > wa_delayed_vblank_limit;
> > + }
> > +
> > /*
> > * Reasons to disable:
> > * - PSR disabled in new state @@ -2711,6 +2819,7 @@
> > void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> > * - Changing between PSR versions
> > * - Region Early Transport changing
> > * - Display WA #1136: skl, bxt
> > + * - Display WA_22019444797
> > */
> > needs_to_disable |=
> > intel_crtc_needs_modeset(new_crtc_state);
> > needs_to_disable |= !new_crtc_state->has_psr; @@
> > -2720,6 +2829,8 @@ void intel_psr_pre_plane_update(struct
> > intel_atomic_state *state,
> > psr->su_region_et_enabled;
> > needs_to_disable |= DISPLAY_VER(i915) < 11 &&
> > new_crtc_state->wm_level_disabled;
> > + /* TODO: Disable PSR1 when vblank gets enabled while
> > PSR1 is enabled */
> > + needs_to_disable |=
> > wa_22019444797_psr1_check(new_crtc_state, psr);
> >
> > if (psr->enabled && needs_to_disable)
> > intel_psr_disable_locked(intel_dp);
> > @@ -2760,6 +2871,12 @@ void intel_psr_post_plane_update(struct
> > intel_atomic_state *state,
> > keep_disabled |= DISPLAY_VER(display) < 11 &&
> > crtc_state->wm_level_disabled;
> >
> > + /*
> > + * Wa_22019444797
> > + * TODO: Disable PSR1 when vblank gets enabled while
> > PSR1 is enabled
> > + */
> > + keep_disabled |=
> > wa_22019444797_psr1_check(crtc_state, psr);
> > +
> > if (!psr->enabled && !keep_disabled)
> > intel_psr_enable_locked(intel_dp, crtc_state);
> > else if (psr->enabled && !crtc_state-
> > >wm_level_disabled)
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH] drm/i915/psr: Implement WA to help reach PC10
2024-09-23 2:54 ` Kandpal, Suraj
@ 2024-09-23 10:23 ` Shankar, Uma
0 siblings, 0 replies; 13+ messages in thread
From: Shankar, Uma @ 2024-09-23 10:23 UTC (permalink / raw)
To: Kandpal, Suraj, Hogander, Jouni, intel-gfx@lists.freedesktop.org
> > On Fri, 2024-09-20 at 14:42 +0530, Suraj Kandpal wrote:
> > > To reach PC10 when PKG_C_LATENCY is configure we must do the
> > following
> > > things
> > > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> > > entered
> > > 2) Allow PSR2 deep sleep when DC5 can be entered
> > > 3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
> > > eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
> > > not happening.
> >
> > One comment below related to PantherLake. Otherwise patch looks ok to
> > me.
> > > --v2
> > > -Switch condition and do an early return [Jani] -Do some checks in
> > > compute_config [Jani] -Do not use register reads as a method of
> > > checking states for DPKGC or delayed vblank [Jani] -Use another way
> > > to see is vblank interrupts are disabled or not [Jani]
> > >
> > > --v3
> > > -Use has_psr to check if psr can be enabled or not for dc5_entry
> > > cond [Uma] -Move the dc5 entry computation to psr_compute_config
> > > [Jouni] -No need to change sequence of enabled and activate, so dont
> > > make hsw_psr1_activate return anything [Jouni] -Use has_psr to stop
> > > psr1 activation [Jouni] -Use lineage no. in WA -Add the display ver
> > > restrictions for WA
> > >
> > > --v4
> > > -use more appropriate name for check_vblank_limit() [Jouni] -Cover
> > > the case for idle frames when dpkgc is not configured [Jouni] -Check
> > > psr only for edp [Jouni]
> > >
> > > --v5
> > > -move psr1 handling to plane update [Jouni] -add todo for cases when
> > > vblank is enabled when psr enabled [Jouni] -use intel_display
> > > instead of drm_i915_private
> > >
> > > --v6
> > > -check target_dc_state [Jouni]
> > > -fix condition in pre/post plane update [Jouni]
> > >
> > > --v7
> > > -fix has_psr condition [Uma]
> > > -fix typo in commit subject [Uma]
> > > -put psr1_wa check in its own helper [Uma] -fix the dc_entry check
> > > [Jouni] -use HAS_PSR() to cover two edp one with psr and one nonpsr
> > > [Jouni]
> > >
> > > WA: 22019444797
> > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > ---
> > > .../drm/i915/display/intel_display_types.h | 3 +
> > > drivers/gpu/drm/i915/display/intel_psr.c | 119
> > > +++++++++++++++++-
> > > 2 files changed, 121 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 3e694c1204db..2d790abee76e 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -1577,6 +1577,9 @@ struct intel_psr {
> > > #define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
> > >
> > > u32 debug;
> > > + bool is_dpkgc_configured;
> > > + bool is_dc5_entry_possible;
> > > + bool is_wa_delayed_vblank_limit;
> > > bool sink_support;
> > > bool source_support;
> > > bool enabled;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 5b355d0a3565..b882ff25fb92 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -26,6 +26,7 @@
> > > #include <drm/drm_atomic_helper.h>
> > > #include <drm/drm_damage_helper.h>
> > > #include <drm/drm_debugfs.h>
> > > +#include <drm/drm_vblank.h>
> > >
> > > #include "i915_drv.h"
> > > #include "i915_reg.h"
> > > @@ -895,6 +896,89 @@ static u8 psr_compute_idle_frames(struct
> > intel_dp
> > > *intel_dp)
> > > return idle_frames;
> > > }
> > >
> > > +static bool
> > > +intel_psr_check_wa_delayed_vblank(const struct drm_display_mode
> > > *adjusted_mode)
> > > +{
> > > + return (adjusted_mode->crtc_vblank_start - adjusted_mode-
> > > >crtc_vdisplay) >= 6;
> > > +}
> > > +
> > > +/*
> > > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> > > + * VRR is not enabled
> > > + */
> > > +static bool intel_psr_is_dpkgc_configured(struct intel_display
> > > *display,
> > > + struct intel_atomic_state
> > > *state)
> > > +{
> > > + struct intel_crtc *intel_crtc;
> > > + struct intel_crtc_state *crtc_state;
> > > + int i;
> > > +
> > > + if (DISPLAY_VER(display) < 20)
> > > + return false;
> > > +
> > > + for_each_new_intel_crtc_in_state(state, intel_crtc,
> > > crtc_state, i) {
> > > + if (!intel_crtc->active)
> > > + continue;
> > > +
> > > + if (crtc_state->vrr.enable)
> > > + return false;
> > > + }
> > > +
> > > + return true;
> > > +}
> > > +
> > > +static bool wa_22019444797_psr1_check(const struct intel_crtc_state
> > > *crtc_state,
> > > + struct intel_psr *psr) {
> > > + struct intel_display *display =
> > > +to_intel_display(crtc_state);
> > > +
> > > + return DISPLAY_VER(display) == 20 &&
> > > +psr->is_dpkgc_configured
> > > &&
> > > + (psr->is_wa_delayed_vblank_limit || !psr-
> > > >is_dc5_entry_possible) &&
> > > + !crtc_state->has_sel_update && !crtc_state-
> > > >has_panel_replay;
> > > +}
> > > +
> > > +/*
> > > + * DC5 entry is only possible if vblank interrupt is disabled
> > > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> > > + * enabled encoders.
> > > + */
> > > +static bool
> > > +intel_psr_is_dc5_entry_possible(struct intel_display *display,
> > > + struct intel_atomic_state *state) {
> > > + struct intel_crtc *intel_crtc;
> > > + struct intel_crtc_state *crtc_state;
> > > + int i;
> > > +
> > > + if ((display->power.domains.target_dc_state &
> > > + DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
> > > + return false;
> > > +
> > > + for_each_new_intel_crtc_in_state(state, intel_crtc,
> > > crtc_state, i) {
> > > + struct drm_crtc *crtc = &intel_crtc->base;
> > > + struct drm_vblank_crtc *vblank;
> > > + struct intel_encoder *encoder;
> > > +
> > > + if (!intel_crtc->active)
> > > + continue;
> > > +
> > > + vblank = drm_crtc_vblank_crtc(crtc);
> > > +
> > > + if (vblank->enabled)
> > > + return false;
> > > +
> > > + if (!crtc_state->has_psr)
> > > + return false;
> > > +
> > > + for_each_encoder_on_crtc(display->drm, crtc,
> > > +encoder)
> > > + if (encoder->type != INTEL_OUTPUT_EDP ||
> > > + !CAN_PSR(enc_to_intel_dp(encoder)))
> > > + return false;
> > > + }
> > > +
> > > + return true;
> > > +}
> > > +
> > > static void hsw_activate_psr1(struct intel_dp *intel_dp)
> > > {
> > > struct intel_display *display = to_intel_display(intel_dp);
> > > @@
> > > -1007,7 +1091,15 @@ static void hsw_activate_psr2(struct intel_dp
> > > *intel_dp)
> > > u32 val = EDP_PSR2_ENABLE;
> > > u32 psr_val = 0;
> > >
> > > - val |=
> > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > > + /*
> > > + * Wa_22019444797
> > > + * TODO: Disable idle frames when vblank gets enabled while
> > > + * PSR2 is enabled
> > > + */
> > > + if (DISPLAY_VER(dev_priv) != 20 ||
> >
> >
> > I think same Workaround is needed by PantherLake but only if stepping
> > is A0. You could have this here:
> >
> > (DISPLAY_VER(display) != 20 && !IS_DISPLAY_VER_STEP(display,
> > IP_VER(30, 0), STEP_A0, STEP_B0))
> >
>
> I do see the WA mentioned in bspec 74219 but the I don’t see any individual HSD
> cloned for it.
> Moreover it is for one stepping and a driver temp workaround not sure if I need to
> implement this @Shankar, Uma what do you suggest should I float a version
> implementing this or do this later on requirement
Yeah, its needed for PTL but gets fixed later in hardware. I would suggest we can limit
this to LNL for now and don't add a stepping check in upstream.
Overall patch looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Regards,
Uma Shankar
> Regards,
> Suraj Kandpal
>
> > BR,
> >
> > Jouni Högander
> >
> >
> > > + !intel_dp->psr.is_dpkgc_configured ||
> > > + intel_dp->psr.is_dc5_entry_possible)
> > > + val |=
> > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > >
> > > if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
> > > val |= EDP_SU_TRACK_ENABLE; @@ -2692,10 +2784,20 @@
> > > void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> > > const struct intel_crtc_state *new_crtc_state =
> > > intel_atomic_get_new_crtc_state(state, crtc);
> > > struct intel_encoder *encoder;
> > > + bool dpkgc_configured = false, dc5_entry_possible = false;
> > > + bool wa_delayed_vblank_limit = false;
> > >
> > > if (!HAS_PSR(display))
> > > return;
> > >
> > > + if (DISPLAY_VER(display) == 20) {
> > > + dpkgc_configured =
> > > intel_psr_is_dpkgc_configured(display, state);
> > > + dc5_entry_possible =
> > > + intel_psr_is_dc5_entry_possible(display,
> > > state);
> > > + wa_delayed_vblank_limit =
> > > +
> > > +intel_psr_check_wa_delayed_vblank(&new_crtc_s
> > > tate->hw.adjusted_mode);
> > > + }
> > > +
> > > for_each_intel_encoder_mask_with_psr(state->base.dev,
> > > encoder,
> > > old_crtc_state-
> > > >uapi.encoder_mask) {
> > > struct intel_dp *intel_dp =
> > > enc_to_intel_dp(encoder); @@ -2704,6 +2806,12 @@ void
> > > intel_psr_pre_plane_update(struct intel_atomic_state *state,
> > >
> > > mutex_lock(&psr->lock);
> > >
> > > + if (DISPLAY_VER(i915) == 20) {
> > > + psr->is_dpkgc_configured = dpkgc_configured;
> > > + psr->is_dc5_entry_possible =
> > > dc5_entry_possible;
> > > + psr->is_wa_delayed_vblank_limit =
> > > wa_delayed_vblank_limit;
> > > + }
> > > +
> > > /*
> > > * Reasons to disable:
> > > * - PSR disabled in new state @@ -2711,6 +2819,7 @@
> > > void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> > > * - Changing between PSR versions
> > > * - Region Early Transport changing
> > > * - Display WA #1136: skl, bxt
> > > + * - Display WA_22019444797
> > > */
> > > needs_to_disable |=
> > > intel_crtc_needs_modeset(new_crtc_state);
> > > needs_to_disable |= !new_crtc_state->has_psr; @@
> > > -2720,6 +2829,8 @@ void intel_psr_pre_plane_update(struct
> > > intel_atomic_state *state,
> > > psr->su_region_et_enabled;
> > > needs_to_disable |= DISPLAY_VER(i915) < 11 &&
> > > new_crtc_state->wm_level_disabled;
> > > + /* TODO: Disable PSR1 when vblank gets enabled while
> > > PSR1 is enabled */
> > > + needs_to_disable |=
> > > wa_22019444797_psr1_check(new_crtc_state, psr);
> > >
> > > if (psr->enabled && needs_to_disable)
> > > intel_psr_disable_locked(intel_dp);
> > > @@ -2760,6 +2871,12 @@ void intel_psr_post_plane_update(struct
> > > intel_atomic_state *state,
> > > keep_disabled |= DISPLAY_VER(display) < 11 &&
> > > crtc_state->wm_level_disabled;
> > >
> > > + /*
> > > + * Wa_22019444797
> > > + * TODO: Disable PSR1 when vblank gets enabled while
> > > PSR1 is enabled
> > > + */
> > > + keep_disabled |=
> > > wa_22019444797_psr1_check(crtc_state, psr);
> > > +
> > > if (!psr->enabled && !keep_disabled)
> > > intel_psr_enable_locked(intel_dp,
> > > crtc_state);
> > > else if (psr->enabled && !crtc_state-
> > > >wm_level_disabled)
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH] drm/i915/psr: Implement WA to help reach PC10
@ 2024-10-03 14:53 Suraj Kandpal
2024-10-06 16:53 ` Suraj Kandpal
2024-10-17 7:54 ` Suraj Kandpal
0 siblings, 2 replies; 13+ messages in thread
From: Suraj Kandpal @ 2024-10-03 14:53 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: uma.shankar, jouni.hogander, Suraj Kandpal
To reach PC10 when PKG_C_LATENCY is configure we must do the following
things
1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
2) Allow PSR2 deep sleep when DC5 can be entered
3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
not happening.
WA: 22019444797
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/display/intel_psr.c | 108 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_psr.h | 2 +
4 files changed, 115 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index fe1ded6707f9..cbd71c136c8d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4368,6 +4368,9 @@ static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
}
+ if (intel_encoder_is_dp(encoder))
+ intel_psr_compute_config_late(encoder, crtc_state);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 17fc21f6ae36..7fb3eeb0e0f2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1576,6 +1576,9 @@ struct intel_psr {
#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
u32 debug;
+ bool is_dpkgc_configured;
+ bool is_dc5_entry_possible;
+ bool is_wa_delayed_vblank_limit;
bool sink_support;
bool source_support;
bool enabled;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 8e9f068b9b2b..2136737429b4 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -26,6 +26,7 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_damage_helper.h>
#include <drm/drm_debugfs.h>
+#include <drm/drm_vblank.h>
#include "i915_drv.h"
#include "i915_reg.h"
@@ -896,6 +897,76 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
return idle_frames;
}
+static bool
+intel_psr_check_wa_delayed_vblank(const struct drm_display_mode *adjusted_mode)
+{
+ return (adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay) >= 6;
+}
+
+/*
+ * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
+ * VRR is not enabled
+ */
+static bool intel_psr_is_dpkgc_configured(struct intel_display *display,
+ struct intel_crtc_state *crtc_state)
+{
+ if (DISPLAY_VER(display) < 20 || crtc_state->vrr.enable)
+ return false;
+
+ return true;
+}
+
+static bool wa_22019444797_psr1_check(const struct intel_crtc_state *crtc_state,
+ struct intel_psr *psr)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ return DISPLAY_VER(display) == 20 && psr->is_dpkgc_configured &&
+ (psr->is_wa_delayed_vblank_limit || !psr->is_dc5_entry_possible) &&
+ !crtc_state->has_sel_update && !crtc_state->has_panel_replay;
+}
+
+/*
+ * DC5 entry is only possible if vblank interrupt is disabled
+ * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
+ * enabled encoders.
+ */
+static bool
+intel_psr_is_dc5_entry_possible(struct intel_display *display,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *intel_crtc;
+
+ if ((display->power.domains.target_dc_state &
+ DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
+ return false;
+
+ if (!crtc_state->has_psr && !crtc_state->has_sel_update &&
+ !crtc_state->has_panel_replay)
+ return false;
+
+ for_each_intel_crtc(display->drm, intel_crtc) {
+ struct drm_crtc *crtc = &intel_crtc->base;
+ struct drm_vblank_crtc *vblank;
+ struct intel_encoder *encoder;
+
+ if (!intel_crtc->active)
+ continue;
+
+ vblank = drm_crtc_vblank_crtc(crtc);
+
+ if (vblank->enabled)
+ return false;
+
+ for_each_encoder_on_crtc(display->drm, crtc, encoder)
+ if (encoder->type != INTEL_OUTPUT_EDP ||
+ !CAN_PSR(enc_to_intel_dp(encoder)))
+ return false;
+ }
+
+ return true;
+}
+
static void hsw_activate_psr1(struct intel_dp *intel_dp)
{
struct intel_display *display = to_intel_display(intel_dp);
@@ -1008,7 +1079,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
u32 val = EDP_PSR2_ENABLE;
u32 psr_val = 0;
- val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ /*
+ * Wa_22019444797
+ * TODO: Disable idle frames when vblank gets enabled while
+ * PSR2 is enabled
+ */
+ if (DISPLAY_VER(dev_priv) != 20 ||
+ !intel_dp->psr.is_dpkgc_configured ||
+ intel_dp->psr.is_dc5_entry_possible)
+ val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
val |= EDP_SU_TRACK_ENABLE;
@@ -1686,6 +1765,24 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
}
+void intel_psr_compute_config_late(struct intel_encoder *intel_encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(intel_encoder);
+ struct intel_dp *dp = enc_to_intel_dp(intel_encoder);
+
+ if (DISPLAY_VER(display) == 20) {
+ mutex_lock(&dp->psr.lock);
+ dp->psr.is_dpkgc_configured =
+ intel_psr_is_dpkgc_configured(display, crtc_state);
+ dp->psr.is_dc5_entry_possible =
+ intel_psr_is_dc5_entry_possible(display, crtc_state);
+ dp->psr.is_wa_delayed_vblank_limit =
+ intel_psr_check_wa_delayed_vblank(&crtc_state->hw.adjusted_mode);
+ mutex_unlock(&dp->psr.lock);
+ }
+}
+
void intel_psr_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
@@ -2742,6 +2839,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
* - Changing between PSR versions
* - Region Early Transport changing
* - Display WA #1136: skl, bxt
+ * - Display WA_22019444797
*/
needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
needs_to_disable |= !new_crtc_state->has_psr;
@@ -2751,6 +2849,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
psr->su_region_et_enabled;
needs_to_disable |= DISPLAY_VER(i915) < 11 &&
new_crtc_state->wm_level_disabled;
+ /* TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled */
+ needs_to_disable |= wa_22019444797_psr1_check(new_crtc_state, psr);
if (psr->enabled && needs_to_disable)
intel_psr_disable_locked(intel_dp);
@@ -2791,6 +2891,12 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
keep_disabled |= DISPLAY_VER(display) < 11 &&
crtc_state->wm_level_disabled;
+ /*
+ * Wa_22019444797
+ * TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled
+ */
+ keep_disabled |= wa_22019444797_psr1_check(crtc_state, psr);
+
if (!psr->enabled && !keep_disabled)
intel_psr_enable_locked(intel_dp, crtc_state);
else if (psr->enabled && !crtc_state->wm_level_disabled)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 5f26f61f82aa..e0fa04952393 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -47,6 +47,8 @@ void intel_psr_init(struct intel_dp *intel_dp);
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state);
+void intel_psr_compute_config_late(struct intel_encoder *intel_encoder,
+ struct intel_crtc_state *crtc_state);
void intel_psr_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
--
2.43.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH] drm/i915/psr: Implement WA to help reach PC10
2024-10-03 14:53 Suraj Kandpal
@ 2024-10-06 16:53 ` Suraj Kandpal
2024-10-17 7:54 ` Suraj Kandpal
1 sibling, 0 replies; 13+ messages in thread
From: Suraj Kandpal @ 2024-10-06 16:53 UTC (permalink / raw)
To: intel-gfx; +Cc: Suraj Kandpal
To reach PC10 when PKG_C_LATENCY is configure we must do the following
things
1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
2) Allow PSR2 deep sleep when DC5 can be entered
3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
not happening.
--v2
-Add debug prints
WA: 22019444797
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/display/intel_psr.c | 117 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_psr.h | 2 +
4 files changed, 124 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index fe1ded6707f9..cbd71c136c8d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4368,6 +4368,9 @@ static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
}
+ if (intel_encoder_is_dp(encoder))
+ intel_psr_compute_config_late(encoder, crtc_state);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 17fc21f6ae36..7fb3eeb0e0f2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1576,6 +1576,9 @@ struct intel_psr {
#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
u32 debug;
+ bool is_dpkgc_configured;
+ bool is_dc5_entry_possible;
+ bool is_wa_delayed_vblank_limit;
bool sink_support;
bool source_support;
bool enabled;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 8e9f068b9b2b..9b77045df228 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -26,6 +26,7 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_damage_helper.h>
#include <drm/drm_debugfs.h>
+#include <drm/drm_vblank.h>
#include "i915_drv.h"
#include "i915_reg.h"
@@ -896,6 +897,82 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
return idle_frames;
}
+static bool
+intel_psr_check_wa_delayed_vblank(const struct drm_display_mode *adjusted_mode)
+{
+ return (adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay) >= 6;
+}
+
+/*
+ * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
+ * VRR is not enabled
+ */
+static bool intel_psr_is_dpkgc_configured(struct intel_display *display,
+ struct intel_crtc_state *crtc_state)
+{
+ if (DISPLAY_VER(display) < 20 || crtc_state->vrr.enable)
+ return false;
+
+ return true;
+}
+
+static bool wa_22019444797_psr1_check(const struct intel_crtc_state *crtc_state,
+ struct intel_psr *psr)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ if (DISPLAY_VER(display) == 20 && psr->is_dpkgc_configured &&
+ (psr->is_wa_delayed_vblank_limit || !psr->is_dc5_entry_possible) &&
+ !crtc_state->has_sel_update && !crtc_state->has_panel_replay) {
+ drm_dbg_kms(display->drm,
+ "Wa 22019444797 requirement met PSR1 disabled\n");
+ return true;
+ } else {
+ return false;
+ }
+}
+
+/*
+ * DC5 entry is only possible if vblank interrupt is disabled
+ * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
+ * enabled encoders.
+ */
+static bool
+intel_psr_is_dc5_entry_possible(struct intel_display *display,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *intel_crtc;
+
+ if ((display->power.domains.target_dc_state &
+ DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
+ return false;
+
+ if (!crtc_state->has_psr && !crtc_state->has_sel_update &&
+ !crtc_state->has_panel_replay)
+ return false;
+
+ for_each_intel_crtc(display->drm, intel_crtc) {
+ struct drm_crtc *crtc = &intel_crtc->base;
+ struct drm_vblank_crtc *vblank;
+ struct intel_encoder *encoder;
+
+ if (!intel_crtc->active)
+ continue;
+
+ vblank = drm_crtc_vblank_crtc(crtc);
+
+ if (vblank->enabled)
+ return false;
+
+ for_each_encoder_on_crtc(display->drm, crtc, encoder)
+ if (encoder->type != INTEL_OUTPUT_EDP ||
+ !CAN_PSR(enc_to_intel_dp(encoder)))
+ return false;
+ }
+
+ return true;
+}
+
static void hsw_activate_psr1(struct intel_dp *intel_dp)
{
struct intel_display *display = to_intel_display(intel_dp);
@@ -1008,7 +1085,18 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
u32 val = EDP_PSR2_ENABLE;
u32 psr_val = 0;
- val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ /*
+ * Wa_22019444797
+ * TODO: Disable idle frames when vblank gets enabled while
+ * PSR2 is enabled
+ */
+ if (DISPLAY_VER(dev_priv) != 20 ||
+ !intel_dp->psr.is_dpkgc_configured ||
+ intel_dp->psr.is_dc5_entry_possible)
+ val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ else
+ drm_dbg_kms(display->drm,
+ "Wa 22019444797 requirement met PSR2 deep sleep disabled\n");
if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
val |= EDP_SU_TRACK_ENABLE;
@@ -1686,6 +1774,24 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
}
+void intel_psr_compute_config_late(struct intel_encoder *intel_encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(intel_encoder);
+ struct intel_dp *dp = enc_to_intel_dp(intel_encoder);
+
+ if (DISPLAY_VER(display) == 20) {
+ mutex_lock(&dp->psr.lock);
+ dp->psr.is_dpkgc_configured =
+ intel_psr_is_dpkgc_configured(display, crtc_state);
+ dp->psr.is_dc5_entry_possible =
+ intel_psr_is_dc5_entry_possible(display, crtc_state);
+ dp->psr.is_wa_delayed_vblank_limit =
+ intel_psr_check_wa_delayed_vblank(&crtc_state->hw.adjusted_mode);
+ mutex_unlock(&dp->psr.lock);
+ }
+}
+
void intel_psr_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
@@ -2742,6 +2848,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
* - Changing between PSR versions
* - Region Early Transport changing
* - Display WA #1136: skl, bxt
+ * - Display WA_22019444797
*/
needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
needs_to_disable |= !new_crtc_state->has_psr;
@@ -2751,6 +2858,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
psr->su_region_et_enabled;
needs_to_disable |= DISPLAY_VER(i915) < 11 &&
new_crtc_state->wm_level_disabled;
+ /* TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled */
+ needs_to_disable |= wa_22019444797_psr1_check(new_crtc_state, psr);
if (psr->enabled && needs_to_disable)
intel_psr_disable_locked(intel_dp);
@@ -2791,6 +2900,12 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
keep_disabled |= DISPLAY_VER(display) < 11 &&
crtc_state->wm_level_disabled;
+ /*
+ * Wa_22019444797
+ * TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled
+ */
+ keep_disabled |= wa_22019444797_psr1_check(crtc_state, psr);
+
if (!psr->enabled && !keep_disabled)
intel_psr_enable_locked(intel_dp, crtc_state);
else if (psr->enabled && !crtc_state->wm_level_disabled)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 5f26f61f82aa..e0fa04952393 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -47,6 +47,8 @@ void intel_psr_init(struct intel_dp *intel_dp);
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state);
+void intel_psr_compute_config_late(struct intel_encoder *intel_encoder,
+ struct intel_crtc_state *crtc_state);
void intel_psr_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
--
2.43.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH] drm/i915/psr: Implement WA to help reach PC10
2024-10-03 14:53 Suraj Kandpal
2024-10-06 16:53 ` Suraj Kandpal
@ 2024-10-17 7:54 ` Suraj Kandpal
1 sibling, 0 replies; 13+ messages in thread
From: Suraj Kandpal @ 2024-10-17 7:54 UTC (permalink / raw)
To: intel-gfx; +Cc: uma.shankar, jouni.hogander, jani.nikula, Suraj Kandpal
To reach PC10 when PKG_C_LATENCY is configure we must do the following
things
1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
2) Allow PSR2 deep sleep when DC5 can be entered
3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
not happening.
--v2
-Add debug prints
--v3
-use crtc as variable name for intel_crtc [Jani]
-use encoder as variable name for intel_encoder [Jani]
-No changes in intel_dp in compute_config_late [Jani]
WA: 22019444797
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
.../drm/i915/display/intel_display_types.h | 6 +
drivers/gpu/drm/i915/display/intel_psr.c | 131 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_psr.h | 2 +
4 files changed, 141 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index fe1ded6707f9..cbd71c136c8d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4368,6 +4368,9 @@ static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
}
+ if (intel_encoder_is_dp(encoder))
+ intel_psr_compute_config_late(encoder, crtc_state);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 2bb1fa64da2f..c980f21a192d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1089,6 +1089,9 @@ struct intel_crtc_state {
bool req_psr2_sdp_prior_scanline;
bool has_panel_replay;
bool wm_level_disabled;
+ bool is_wa_delayed_vblank_limit;
+ bool is_dpkgc_configured;
+ bool is_dc5_entry_possible;
u32 dc3co_exitline;
u16 su_y_granularity;
@@ -1587,6 +1590,9 @@ struct intel_psr {
#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
u32 debug;
+ bool is_dpkgc_configured;
+ bool is_dc5_entry_possible;
+ bool is_wa_delayed_vblank_limit;
bool sink_support;
bool source_support;
bool enabled;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 3b20325b3f6a..9f6dcac64dc9 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -26,6 +26,7 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_damage_helper.h>
#include <drm/drm_debugfs.h>
+#include <drm/drm_vblank.h>
#include "i915_drv.h"
#include "i915_reg.h"
@@ -896,6 +897,81 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
return idle_frames;
}
+static bool
+intel_psr_check_wa_delayed_vblank(const struct drm_display_mode *adjusted_mode)
+{
+ return (adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay) >= 6;
+}
+
+/*
+ * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
+ * VRR is not enabled
+ */
+static bool intel_psr_is_dpkgc_configured(struct intel_display *display,
+ struct intel_crtc_state *crtc_state)
+{
+ if (DISPLAY_VER(display) < 20 || crtc_state->vrr.enable)
+ return false;
+
+ return true;
+}
+
+static bool wa_22019444797_psr1_check(const struct intel_crtc_state *crtc_state,
+ struct intel_psr *psr)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ if (DISPLAY_VER(display) == 20 && psr->is_dpkgc_configured &&
+ (psr->is_wa_delayed_vblank_limit || !psr->is_dc5_entry_possible) &&
+ !crtc_state->has_sel_update && !crtc_state->has_panel_replay) {
+ drm_dbg_kms(display->drm,
+ "Wa 22019444797 requirement met PSR1 disabled\n");
+ return true;
+ } else {
+ return false;
+ }
+}
+
+/*
+ * DC5 entry is only possible if vblank interrupt is disabled
+ * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
+ * enabled encoders.
+ */
+static bool
+intel_psr_is_dc5_entry_possible(struct intel_display *display,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc;
+
+ if ((display->power.domains.target_dc_state &
+ DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
+ return false;
+
+ if (!crtc_state->has_psr && !crtc_state->has_sel_update &&
+ !crtc_state->has_panel_replay)
+ return false;
+
+ for_each_intel_crtc(display->drm, crtc) {
+ struct drm_vblank_crtc *vblank;
+ struct intel_encoder *encoder;
+
+ if (!crtc->active)
+ continue;
+
+ vblank = drm_crtc_vblank_crtc(&crtc->base);
+
+ if (vblank->enabled)
+ return false;
+
+ for_each_encoder_on_crtc(display->drm, &crtc->base, encoder)
+ if (encoder->type != INTEL_OUTPUT_EDP ||
+ !CAN_PSR(enc_to_intel_dp(encoder)))
+ return false;
+ }
+
+ return true;
+}
+
static void hsw_activate_psr1(struct intel_dp *intel_dp)
{
struct intel_display *display = to_intel_display(intel_dp);
@@ -1008,7 +1084,18 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
u32 val = EDP_PSR2_ENABLE;
u32 psr_val = 0;
- val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ /*
+ * Wa_22019444797
+ * TODO: Disable idle frames when vblank gets enabled while
+ * PSR2 is enabled
+ */
+ if (DISPLAY_VER(dev_priv) != 20 ||
+ !intel_dp->psr.is_dpkgc_configured ||
+ intel_dp->psr.is_dc5_entry_possible)
+ val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ else
+ drm_dbg_kms(display->drm,
+ "Wa 22019444797 requirement met PSR2 deep sleep disabled\n");
if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
val |= EDP_SU_TRACK_ENABLE;
@@ -1686,6 +1773,21 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
}
+void intel_psr_compute_config_late(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(encoder);
+
+ if (DISPLAY_VER(display) == 20) {
+ crtc_state->is_dpkgc_configured =
+ intel_psr_is_dpkgc_configured(display, crtc_state);
+ crtc_state->is_dc5_entry_possible =
+ intel_psr_is_dc5_entry_possible(display, crtc_state);
+ crtc_state->is_wa_delayed_vblank_limit =
+ intel_psr_check_wa_delayed_vblank(&crtc_state->hw.adjusted_mode);
+ }
+}
+
void intel_psr_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
@@ -2757,6 +2859,22 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
return 0;
}
+static void
+wa_22019444797_fill_psr_params(const struct intel_crtc_state *crtc_state,
+ struct intel_psr *psr)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ if (DISPLAY_VER(display) == 20) {
+ psr->is_dpkgc_configured =
+ crtc_state->is_dpkgc_configured;
+ psr->is_dc5_entry_possible =
+ crtc_state->is_dc5_entry_possible;
+ psr->is_wa_delayed_vblank_limit =
+ crtc_state->is_wa_delayed_vblank_limit;
+ }
+}
+
void intel_psr_pre_plane_update(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -2779,6 +2897,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
mutex_lock(&psr->lock);
+ wa_22019444797_fill_psr_params(new_crtc_state, psr);
+
/*
* Reasons to disable:
* - PSR disabled in new state
@@ -2786,6 +2906,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
* - Changing between PSR versions
* - Region Early Transport changing
* - Display WA #1136: skl, bxt
+ * - Display WA_22019444797
*/
needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
needs_to_disable |= !new_crtc_state->has_psr;
@@ -2795,6 +2916,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
psr->su_region_et_enabled;
needs_to_disable |= DISPLAY_VER(i915) < 11 &&
new_crtc_state->wm_level_disabled;
+ /* TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled */
+ needs_to_disable |= wa_22019444797_psr1_check(new_crtc_state, psr);
if (psr->enabled && needs_to_disable)
intel_psr_disable_locked(intel_dp);
@@ -2835,6 +2958,12 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
keep_disabled |= DISPLAY_VER(display) < 11 &&
crtc_state->wm_level_disabled;
+ /*
+ * Wa_22019444797
+ * TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled
+ */
+ keep_disabled |= wa_22019444797_psr1_check(crtc_state, psr);
+
if (!psr->enabled && !keep_disabled)
intel_psr_enable_locked(intel_dp, crtc_state);
else if (psr->enabled && !crtc_state->wm_level_disabled)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 5f26f61f82aa..e0fa04952393 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -47,6 +47,8 @@ void intel_psr_init(struct intel_dp *intel_dp);
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state);
+void intel_psr_compute_config_late(struct intel_encoder *intel_encoder,
+ struct intel_crtc_state *crtc_state);
void intel_psr_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
--
2.47.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH] drm/i915/psr: Implement WA to help reach PC10
@ 2024-11-04 9:12 Suraj Kandpal
2024-11-04 14:18 ` Jani Nikula
` (2 more replies)
0 siblings, 3 replies; 13+ messages in thread
From: Suraj Kandpal @ 2024-11-04 9:12 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: jouni.hogander, Suraj Kandpal
To reach PC10 when PKG_C_LATENCY is configure we must do the following
things
1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
2) Allow PSR2 deep sleep when DC5 can be entered
3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
not happening.
--v2
-Add debug prints
--v3
-use crtc as variable name for intel_crtc [Jani]
-use encoder as variable name for intel_encoder [Jani]
-No changes in intel_dp in compute_config_late [Jani]
--v4
-Remove "check" from naming [Jani]
-Remove intel_encoder variable which is not necessary in
compute_config_late
WA: 22019444797
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
.../drm/i915/display/intel_display_types.h | 6 +
drivers/gpu/drm/i915/display/intel_psr.c | 130 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_psr.h | 1 +
4 files changed, 139 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 0535daed6a9f..8e0fb6bd6211 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4403,6 +4403,9 @@ static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
}
+ if (intel_encoder_is_dp(encoder))
+ intel_psr_compute_config_late(crtc_state);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ff6eb93337e0..dd5f3ea90e5b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1089,6 +1089,9 @@ struct intel_crtc_state {
bool req_psr2_sdp_prior_scanline;
bool has_panel_replay;
bool wm_level_disabled;
+ bool is_wa_delayed_vblank_limit;
+ bool is_dpkgc_configured;
+ bool is_dc5_entry_possible;
u32 dc3co_exitline;
u16 su_y_granularity;
@@ -1587,6 +1590,9 @@ struct intel_psr {
#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
u32 debug;
+ bool is_dpkgc_configured;
+ bool is_dc5_entry_possible;
+ bool is_wa_delayed_vblank_limit;
bool sink_support;
bool source_support;
bool enabled;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index a784c0b81556..b93358a82aa3 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -26,6 +26,7 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_damage_helper.h>
#include <drm/drm_debugfs.h>
+#include <drm/drm_vblank.h>
#include "i915_drv.h"
#include "i915_reg.h"
@@ -898,6 +899,81 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
return idle_frames;
}
+static bool
+intel_psr_wa_delayed_vblank(const struct drm_display_mode *adjusted_mode)
+{
+ return (adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay) >= 6;
+}
+
+/*
+ * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
+ * VRR is not enabled
+ */
+static bool intel_psr_is_dpkgc_configured(struct intel_display *display,
+ struct intel_crtc_state *crtc_state)
+{
+ if (DISPLAY_VER(display) < 20 || crtc_state->vrr.enable)
+ return false;
+
+ return true;
+}
+
+static bool wa_22019444797_psr1(const struct intel_crtc_state *crtc_state,
+ struct intel_psr *psr)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ if (DISPLAY_VER(display) == 20 && psr->is_dpkgc_configured &&
+ (psr->is_wa_delayed_vblank_limit || !psr->is_dc5_entry_possible) &&
+ !crtc_state->has_sel_update && !crtc_state->has_panel_replay) {
+ drm_dbg_kms(display->drm,
+ "Wa 22019444797 requirement met PSR1 disabled\n");
+ return true;
+ } else {
+ return false;
+ }
+}
+
+/*
+ * DC5 entry is only possible if vblank interrupt is disabled
+ * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
+ * enabled encoders.
+ */
+static bool
+intel_psr_is_dc5_entry_possible(struct intel_display *display,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc;
+
+ if ((display->power.domains.target_dc_state &
+ DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
+ return false;
+
+ if (!crtc_state->has_psr && !crtc_state->has_sel_update &&
+ !crtc_state->has_panel_replay)
+ return false;
+
+ for_each_intel_crtc(display->drm, crtc) {
+ struct drm_vblank_crtc *vblank;
+ struct intel_encoder *encoder;
+
+ if (!crtc->active)
+ continue;
+
+ vblank = drm_crtc_vblank_crtc(&crtc->base);
+
+ if (vblank->enabled)
+ return false;
+
+ for_each_encoder_on_crtc(display->drm, &crtc->base, encoder)
+ if (encoder->type != INTEL_OUTPUT_EDP ||
+ !CAN_PSR(enc_to_intel_dp(encoder)))
+ return false;
+ }
+
+ return true;
+}
+
static void hsw_activate_psr1(struct intel_dp *intel_dp)
{
struct intel_display *display = to_intel_display(intel_dp);
@@ -1010,7 +1086,18 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
u32 val = EDP_PSR2_ENABLE;
u32 psr_val = 0;
- val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ /*
+ * Wa_22019444797
+ * TODO: Disable idle frames when vblank gets enabled while
+ * PSR2 is enabled
+ */
+ if (DISPLAY_VER(dev_priv) != 20 ||
+ !intel_dp->psr.is_dpkgc_configured ||
+ intel_dp->psr.is_dc5_entry_possible)
+ val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ else
+ drm_dbg_kms(display->drm,
+ "Wa 22019444797 requirement met PSR2 deep sleep disabled\n");
if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
val |= EDP_SU_TRACK_ENABLE;
@@ -1692,6 +1779,20 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
}
+void intel_psr_compute_config_late(struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ if (DISPLAY_VER(display) == 20) {
+ crtc_state->is_dpkgc_configured =
+ intel_psr_is_dpkgc_configured(display, crtc_state);
+ crtc_state->is_dc5_entry_possible =
+ intel_psr_is_dc5_entry_possible(display, crtc_state);
+ crtc_state->is_wa_delayed_vblank_limit =
+ intel_psr_wa_delayed_vblank(&crtc_state->hw.adjusted_mode);
+ }
+}
+
void intel_psr_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
@@ -2774,6 +2875,22 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
return 0;
}
+static void
+wa_22019444797_fill_psr_params(const struct intel_crtc_state *crtc_state,
+ struct intel_psr *psr)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ if (DISPLAY_VER(display) == 20) {
+ psr->is_dpkgc_configured =
+ crtc_state->is_dpkgc_configured;
+ psr->is_dc5_entry_possible =
+ crtc_state->is_dc5_entry_possible;
+ psr->is_wa_delayed_vblank_limit =
+ crtc_state->is_wa_delayed_vblank_limit;
+ }
+}
+
void intel_psr_pre_plane_update(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -2796,6 +2913,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
mutex_lock(&psr->lock);
+ wa_22019444797_fill_psr_params(new_crtc_state, psr);
+
/*
* Reasons to disable:
* - PSR disabled in new state
@@ -2803,6 +2922,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
* - Changing between PSR versions
* - Region Early Transport changing
* - Display WA #1136: skl, bxt
+ * - Display WA_22019444797
*/
needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
needs_to_disable |= !new_crtc_state->has_psr;
@@ -2812,6 +2932,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
psr->su_region_et_enabled;
needs_to_disable |= DISPLAY_VER(i915) < 11 &&
new_crtc_state->wm_level_disabled;
+ /* TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled */
+ needs_to_disable |= wa_22019444797_psr1(new_crtc_state, psr);
if (psr->enabled && needs_to_disable)
intel_psr_disable_locked(intel_dp);
@@ -2852,6 +2974,12 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
keep_disabled |= DISPLAY_VER(display) < 11 &&
crtc_state->wm_level_disabled;
+ /*
+ * Wa_22019444797
+ * TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled
+ */
+ keep_disabled |= wa_22019444797_psr1(crtc_state, psr);
+
if (!psr->enabled && !keep_disabled)
intel_psr_enable_locked(intel_dp, crtc_state);
else if (psr->enabled && !crtc_state->wm_level_disabled)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 956be263c09e..0923a2f74901 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -47,6 +47,7 @@ void intel_psr_init(struct intel_dp *intel_dp);
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state);
+void intel_psr_compute_config_late(struct intel_crtc_state *crtc_state);
void intel_psr_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH] drm/i915/psr: Implement WA to help reach PC10
2024-11-04 9:12 [PATCH] drm/i915/psr: Implement WA to help reach PC10 Suraj Kandpal
@ 2024-11-04 14:18 ` Jani Nikula
2024-11-06 8:18 ` Kandpal, Suraj
2024-11-04 16:13 ` ✓ Fi.CI.BAT: success for drm/i915/psr: Implement WA to help reach PC10 (rev4) Patchwork
2024-11-05 5:59 ` ✗ Fi.CI.IGT: failure " Patchwork
2 siblings, 1 reply; 13+ messages in thread
From: Jani Nikula @ 2024-11-04 14:18 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx; +Cc: jouni.hogander, Suraj Kandpal
On Mon, 04 Nov 2024, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> To reach PC10 when PKG_C_LATENCY is configure we must do the following
> things
> 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
> 2) Allow PSR2 deep sleep when DC5 can be entered
> 3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
> eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
> not happening.
>
> --v2
> -Add debug prints
>
> --v3
> -use crtc as variable name for intel_crtc [Jani]
> -use encoder as variable name for intel_encoder [Jani]
> -No changes in intel_dp in compute_config_late [Jani]
>
> --v4
> -Remove "check" from naming [Jani]
> -Remove intel_encoder variable which is not necessary in
> compute_config_late
>
> WA: 22019444797
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
> .../drm/i915/display/intel_display_types.h | 6 +
> drivers/gpu/drm/i915/display/intel_psr.c | 130 +++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_psr.h | 1 +
> 4 files changed, 139 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 0535daed6a9f..8e0fb6bd6211 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4403,6 +4403,9 @@ static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
> port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
> }
>
> + if (intel_encoder_is_dp(encoder))
> + intel_psr_compute_config_late(crtc_state);
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index ff6eb93337e0..dd5f3ea90e5b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1089,6 +1089,9 @@ struct intel_crtc_state {
> bool req_psr2_sdp_prior_scanline;
> bool has_panel_replay;
> bool wm_level_disabled;
> + bool is_wa_delayed_vblank_limit;
> + bool is_dpkgc_configured;
> + bool is_dc5_entry_possible;
> u32 dc3co_exitline;
> u16 su_y_granularity;
>
> @@ -1587,6 +1590,9 @@ struct intel_psr {
> #define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
>
> u32 debug;
> + bool is_dpkgc_configured;
> + bool is_dc5_entry_possible;
> + bool is_wa_delayed_vblank_limit;
I don't understand why all of these need to be duplicated in struct
intel_psr.
I get that you don't necessarily have access to the crtc state in all
circumstances. But doesn't the workaround basically boil down to using 0
idle frames in hsw_activate_psr2()?
> bool sink_support;
> bool source_support;
> bool enabled;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index a784c0b81556..b93358a82aa3 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -26,6 +26,7 @@
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_damage_helper.h>
> #include <drm/drm_debugfs.h>
> +#include <drm/drm_vblank.h>
>
> #include "i915_drv.h"
> #include "i915_reg.h"
> @@ -898,6 +899,81 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
> return idle_frames;
> }
>
> +static bool
> +intel_psr_wa_delayed_vblank(const struct drm_display_mode *adjusted_mode)
> +{
> + return (adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay) >= 6;
> +}
> +
> +/*
> + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> + * VRR is not enabled
> + */
> +static bool intel_psr_is_dpkgc_configured(struct intel_display *display,
> + struct intel_crtc_state *crtc_state)
> +{
> + if (DISPLAY_VER(display) < 20 || crtc_state->vrr.enable)
> + return false;
> +
> + return true;
IOW,
return DISPLAY_VER(display) >= 20 && !crtc_state->vrr.enable;
> +}
> +
> +static bool wa_22019444797_psr1(const struct intel_crtc_state *crtc_state,
> + struct intel_psr *psr)
I really dislike function names like this. It doesn't say *anything* to
the reader. It's hard to pronounce. It's hard to talk about. I don't
know what it means.
Something like psr1_needs_wa_22019444797() is already much better, even
if it still contains the wa number. It tells what it's about, and the
reader doesn't have to try to guess.
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> +
> + if (DISPLAY_VER(display) == 20 && psr->is_dpkgc_configured &&
> + (psr->is_wa_delayed_vblank_limit || !psr->is_dc5_entry_possible) &&
> + !crtc_state->has_sel_update && !crtc_state->has_panel_replay) {
> + drm_dbg_kms(display->drm,
> + "Wa 22019444797 requirement met PSR1 disabled\n");
That debug log message is not a sentence. Maybe something like,
"Disabling PSR1 due to wa 22019444797\n".
> + return true;
> + } else {
> + return false;
> + }
> +}
Why is this function looking at struct intel_psr to make decisions?
Shouldn't it use old and new crtc state, and nothing else?
> +
> +/*
> + * DC5 entry is only possible if vblank interrupt is disabled
> + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> + * enabled encoders.
> + */
> +static bool
> +intel_psr_is_dc5_entry_possible(struct intel_display *display,
> + struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc;
> +
> + if ((display->power.domains.target_dc_state &
> + DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
> + return false;
> +
> + if (!crtc_state->has_psr && !crtc_state->has_sel_update &&
> + !crtc_state->has_panel_replay)
> + return false;
> +
> + for_each_intel_crtc(display->drm, crtc) {
> + struct drm_vblank_crtc *vblank;
> + struct intel_encoder *encoder;
> +
> + if (!crtc->active)
> + continue;
> +
> + vblank = drm_crtc_vblank_crtc(&crtc->base);
> +
> + if (vblank->enabled)
> + return false;
> +
> + for_each_encoder_on_crtc(display->drm, &crtc->base, encoder)
> + if (encoder->type != INTEL_OUTPUT_EDP ||
> + !CAN_PSR(enc_to_intel_dp(encoder)))
> + return false;
> + }
> +
> + return true;
> +}
> +
> static void hsw_activate_psr1(struct intel_dp *intel_dp)
> {
> struct intel_display *display = to_intel_display(intel_dp);
> @@ -1010,7 +1086,18 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> u32 val = EDP_PSR2_ENABLE;
> u32 psr_val = 0;
>
> - val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> + /*
> + * Wa_22019444797
> + * TODO: Disable idle frames when vblank gets enabled while
> + * PSR2 is enabled
> + */
> + if (DISPLAY_VER(dev_priv) != 20 ||
> + !intel_dp->psr.is_dpkgc_configured ||
> + intel_dp->psr.is_dc5_entry_possible)
> + val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> + else
> + drm_dbg_kms(display->drm,
> + "Wa 22019444797 requirement met PSR2 deep sleep disabled\n");
What if this was just something like,
if (!intel_dp->psr.disable_idle_frames)
val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
And that was set where needed, and everything else was based on old/new
crtc state.
I'm just feeling really dumb because it's hard for me to follow what's
going on here in this patch. Is it really this complicated?
>
> if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
> val |= EDP_SU_TRACK_ENABLE;
> @@ -1692,6 +1779,20 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
> }
>
> +void intel_psr_compute_config_late(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> +
> + if (DISPLAY_VER(display) == 20) {
> + crtc_state->is_dpkgc_configured =
> + intel_psr_is_dpkgc_configured(display, crtc_state);
> + crtc_state->is_dc5_entry_possible =
> + intel_psr_is_dc5_entry_possible(display, crtc_state);
> + crtc_state->is_wa_delayed_vblank_limit =
> + intel_psr_wa_delayed_vblank(&crtc_state->hw.adjusted_mode);
> + }
> +}
> +
> void intel_psr_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> @@ -2774,6 +2875,22 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> return 0;
> }
>
> +static void
> +wa_22019444797_fill_psr_params(const struct intel_crtc_state *crtc_state,
> + struct intel_psr *psr)
Again, that's a horrible function name. This doesn't have to include the
workaround number in any way.
The rule of thumb: Say the function name aloud, as if you were
discussing the code with someone. If it's difficult to talk about, it's
probably not a good name.
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> +
> + if (DISPLAY_VER(display) == 20) {
I think this part is independent of display version.
> + psr->is_dpkgc_configured =
> + crtc_state->is_dpkgc_configured;
> + psr->is_dc5_entry_possible =
> + crtc_state->is_dc5_entry_possible;
> + psr->is_wa_delayed_vblank_limit =
> + crtc_state->is_wa_delayed_vblank_limit;
> + }
> +}
Again, why do we need all of this duplicated? I think it only boils down
to just one thing in struct intel_psr, unless I'm mistaken.
> +
> void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> @@ -2796,6 +2913,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
>
> mutex_lock(&psr->lock);
>
> + wa_22019444797_fill_psr_params(new_crtc_state, psr);
> +
So you're filling stuff from new_crtc_state into psr.
> /*
> * Reasons to disable:
> * - PSR disabled in new state
> @@ -2803,6 +2922,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> * - Changing between PSR versions
> * - Region Early Transport changing
> * - Display WA #1136: skl, bxt
> + * - Display WA_22019444797
> */
> needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
> needs_to_disable |= !new_crtc_state->has_psr;
> @@ -2812,6 +2932,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> psr->su_region_et_enabled;
> needs_to_disable |= DISPLAY_VER(i915) < 11 &&
> new_crtc_state->wm_level_disabled;
> + /* TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled */
> + needs_to_disable |= wa_22019444797_psr1(new_crtc_state, psr);
And then use it here. I don't get it.
>
> if (psr->enabled && needs_to_disable)
> intel_psr_disable_locked(intel_dp);
> @@ -2852,6 +2974,12 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
> keep_disabled |= DISPLAY_VER(display) < 11 &&
> crtc_state->wm_level_disabled;
>
> + /*
> + * Wa_22019444797
> + * TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled
> + */
> + keep_disabled |= wa_22019444797_psr1(crtc_state, psr);
So this carries it over from pre plane update new crtc state via
psr... but it's all very confusing.
BR,
Jani.
> +
> if (!psr->enabled && !keep_disabled)
> intel_psr_enable_locked(intel_dp, crtc_state);
> else if (psr->enabled && !crtc_state->wm_level_disabled)
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index 956be263c09e..0923a2f74901 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -47,6 +47,7 @@ void intel_psr_init(struct intel_dp *intel_dp);
> void intel_psr_compute_config(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state,
> struct drm_connector_state *conn_state);
> +void intel_psr_compute_config_late(struct intel_crtc_state *crtc_state);
> void intel_psr_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config);
> void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/psr: Implement WA to help reach PC10 (rev4)
2024-11-04 9:12 [PATCH] drm/i915/psr: Implement WA to help reach PC10 Suraj Kandpal
2024-11-04 14:18 ` Jani Nikula
@ 2024-11-04 16:13 ` Patchwork
2024-11-05 5:59 ` ✗ Fi.CI.IGT: failure " Patchwork
2 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2024-11-04 16:13 UTC (permalink / raw)
To: Kandpal, Suraj; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 10754 bytes --]
== Series Details ==
Series: drm/i915/psr: Implement WA to help reach PC10 (rev4)
URL : https://patchwork.freedesktop.org/series/139513/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15627 -> Patchwork_139513v4
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/index.html
Participating hosts (44 -> 44)
------------------------------
Additional (1): bat-arls-1
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_139513v4 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-arls-1: NOTRUN -> [SKIP][1] ([i915#9318])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arls-1/igt@debugfs_test@basic-hwmon.html
* igt@gem_lmem_swapping@basic:
- bat-arls-1: NOTRUN -> [SKIP][2] ([i915#10213] / [i915#11671]) +3 other tests skip
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arls-1/igt@gem_lmem_swapping@basic.html
* igt@gem_mmap@basic:
- bat-arls-1: NOTRUN -> [SKIP][3] ([i915#11343] / [i915#4083])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arls-1/igt@gem_mmap@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-arls-1: NOTRUN -> [SKIP][4] ([i915#10197] / [i915#10211] / [i915#4079])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arls-1/igt@gem_render_tiled_blits@basic.html
* igt@gem_tiled_blits@basic:
- bat-arls-1: NOTRUN -> [SKIP][5] ([i915#12637] / [i915#4077]) +2 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arls-1/igt@gem_tiled_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-arls-1: NOTRUN -> [SKIP][6] ([i915#10206] / [i915#4079])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arls-1/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rps@basic-api:
- bat-arls-1: NOTRUN -> [SKIP][7] ([i915#10209] / [i915#11681])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arls-1/igt@i915_pm_rps@basic-api.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-arls-1: NOTRUN -> [SKIP][8] ([i915#10200] / [i915#12203])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arls-1/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-arls-1: NOTRUN -> [SKIP][9] ([i915#10200]) +8 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arls-1/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-arls-1: NOTRUN -> [SKIP][10] ([i915#10202]) +1 other test skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arls-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-arls-1: NOTRUN -> [SKIP][11] ([i915#9886])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arls-1/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-arls-1: NOTRUN -> [SKIP][12] ([i915#10207])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arls-1/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pm_backlight@basic-brightness:
- bat-arls-1: NOTRUN -> [SKIP][13] ([i915#9812])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arls-1/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_psr@psr-primary-mmap-gtt:
- bat-arls-1: NOTRUN -> [SKIP][14] ([i915#9732]) +3 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arls-1/igt@kms_psr@psr-primary-mmap-gtt.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-arls-1: NOTRUN -> [SKIP][15] ([i915#10208] / [i915#8809])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arls-1/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-read:
- bat-arls-1: NOTRUN -> [SKIP][16] ([i915#10212] / [i915#3708])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arls-1/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-gtt:
- bat-arls-1: NOTRUN -> [SKIP][17] ([i915#12637] / [i915#3708] / [i915#4077]) +1 other test skip
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arls-1/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@basic-read:
- bat-arls-1: NOTRUN -> [SKIP][18] ([i915#10214] / [i915#3708])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arls-1/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-write:
- bat-arls-1: NOTRUN -> [SKIP][19] ([i915#10216] / [i915#3708])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arls-1/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@i915_module_load@load:
- bat-dg2-9: [DMESG-WARN][20] -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/bat-dg2-9/igt@i915_module_load@load.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-dg2-9/igt@i915_module_load@load.html
* igt@i915_selftest@live:
- bat-arlh-3: [ABORT][22] ([i915#12133]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/bat-arlh-3/igt@i915_selftest@live.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arlh-3/igt@i915_selftest@live.html
- bat-arlh-2: [ABORT][24] ([i915#12133]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/bat-arlh-2/igt@i915_selftest@live.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arlh-2/igt@i915_selftest@live.html
* igt@i915_selftest@live@workarounds:
- bat-arlh-3: [ABORT][26] ([i915#12061]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/bat-arlh-3/igt@i915_selftest@live@workarounds.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arlh-3/igt@i915_selftest@live@workarounds.html
- bat-arlh-2: [ABORT][28] ([i915#12061]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/bat-arlh-2/igt@i915_selftest@live@workarounds.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-arlh-2/igt@i915_selftest@live@workarounds.html
#### Warnings ####
* igt@i915_module_load@reload:
- bat-apl-1: [DMESG-WARN][30] ([i915#180]) -> [DMESG-WARN][31] ([i915#180] / [i915#1982])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/bat-apl-1/igt@i915_module_load@reload.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-apl-1/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@module-reload:
- bat-apl-1: [DMESG-WARN][32] ([i915#11621] / [i915#180] / [i915#1982]) -> [DMESG-WARN][33] ([i915#11621] / [i915#180])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/bat-apl-1/igt@i915_pm_rpm@module-reload.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-apl-1/igt@i915_pm_rpm@module-reload.html
* igt@kms_pm_rpm@basic-pci-d3-state:
- bat-apl-1: [DMESG-WARN][34] ([i915#11621] / [i915#180]) -> [DMESG-WARN][35] ([i915#11621] / [i915#180] / [i915#1982]) +2 other tests dmesg-warn
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/bat-apl-1/igt@kms_pm_rpm@basic-pci-d3-state.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/bat-apl-1/igt@kms_pm_rpm@basic-pci-d3-state.html
[i915#10197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10197
[i915#10200]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10200
[i915#10202]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10202
[i915#10206]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10206
[i915#10207]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10207
[i915#10208]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10208
[i915#10209]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10209
[i915#10211]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10211
[i915#10212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10212
[i915#10213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10213
[i915#10214]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10214
[i915#10216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10216
[i915#11343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11343
[i915#11621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11621
[i915#11671]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11671
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12133]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12133
[i915#12203]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12203
[i915#12637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12637
[i915#180]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/180
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
[i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
[i915#9886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9886
Build changes
-------------
* Linux: CI_DRM_15627 -> Patchwork_139513v4
CI-20190529: 20190529
CI_DRM_15627: 0a6cc4357ae4d824f909468ca1deed28ae5ac96f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8093: 8093
Patchwork_139513v4: 0a6cc4357ae4d824f909468ca1deed28ae5ac96f @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/index.html
[-- Attachment #2: Type: text/html, Size: 13360 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915/psr: Implement WA to help reach PC10 (rev4)
2024-11-04 9:12 [PATCH] drm/i915/psr: Implement WA to help reach PC10 Suraj Kandpal
2024-11-04 14:18 ` Jani Nikula
2024-11-04 16:13 ` ✓ Fi.CI.BAT: success for drm/i915/psr: Implement WA to help reach PC10 (rev4) Patchwork
@ 2024-11-05 5:59 ` Patchwork
2 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2024-11-05 5:59 UTC (permalink / raw)
To: Kandpal, Suraj; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 93574 bytes --]
== Series Details ==
Series: drm/i915/psr: Implement WA to help reach PC10 (rev4)
URL : https://patchwork.freedesktop.org/series/139513/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15627_full -> Patchwork_139513v4_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_139513v4_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_139513v4_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_139513v4_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_crc@cursor-suspend:
- shard-tglu: NOTRUN -> [INCOMPLETE][1] +1 other test incomplete
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-9/igt@kms_cursor_crc@cursor-suspend.html
* igt@kms_hdr@brightness-with-hdr:
- shard-dg2: NOTRUN -> [SKIP][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-4/igt@kms_hdr@brightness-with-hdr.html
- shard-rkl: NOTRUN -> [SKIP][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-7/igt@kms_hdr@brightness-with-hdr.html
- shard-tglu: NOTRUN -> [SKIP][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-6/igt@kms_hdr@brightness-with-hdr.html
#### Warnings ####
* igt@kms_hdr@brightness-with-hdr:
- shard-dg1: [SKIP][5] ([i915#1187]) -> [SKIP][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg1-13/igt@kms_hdr@brightness-with-hdr.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-12/igt@kms_hdr@brightness-with-hdr.html
Known issues
------------
Here are the changes found in Patchwork_139513v4_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-purge-cache:
- shard-mtlp: NOTRUN -> [SKIP][7] ([i915#8411])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-mtlp-6/igt@api_intel_bb@blit-reloc-purge-cache.html
* igt@api_intel_bb@crc32:
- shard-rkl: NOTRUN -> [SKIP][8] ([i915#6230])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@api_intel_bb@crc32.html
* igt@drm_fdinfo@virtual-busy-idle:
- shard-dg2: NOTRUN -> [SKIP][9] ([i915#8414])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-4/igt@drm_fdinfo@virtual-busy-idle.html
* igt@gem_bad_reloc@negative-reloc-lut:
- shard-rkl: NOTRUN -> [SKIP][10] ([i915#3281]) +12 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-2/igt@gem_bad_reloc@negative-reloc-lut.html
* igt@gem_busy@close-race:
- shard-rkl: NOTRUN -> [FAIL][11] ([i915#12296] / [i915#12577])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-6/igt@gem_busy@close-race.html
* igt@gem_ccs@ctrl-surf-copy:
- shard-tglu: NOTRUN -> [SKIP][12] ([i915#3555] / [i915#9323])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-3/igt@gem_ccs@ctrl-surf-copy.html
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-tglu-1: NOTRUN -> [SKIP][13] ([i915#9323])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
* igt@gem_close_race@multigpu-basic-process:
- shard-tglu-1: NOTRUN -> [SKIP][14] ([i915#7697])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_create@create-ext-set-pat:
- shard-rkl: NOTRUN -> [SKIP][15] ([i915#8562])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-6/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_engines@invalid-engines:
- shard-tglu-1: NOTRUN -> [FAIL][16] ([i915#12031])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@gem_ctx_engines@invalid-engines.html
* igt@gem_ctx_persistence@hostile:
- shard-tglu-1: NOTRUN -> [FAIL][17] ([i915#11980] / [i915#12580])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@gem_ctx_persistence@hostile.html
- shard-dg1: [PASS][18] -> [FAIL][19] ([i915#11980] / [i915#12580])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg1-14/igt@gem_ctx_persistence@hostile.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-15/igt@gem_ctx_persistence@hostile.html
* igt@gem_ctx_persistence@legacy-engines-mixed-process:
- shard-snb: NOTRUN -> [SKIP][20] ([i915#1099])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-snb7/igt@gem_ctx_persistence@legacy-engines-mixed-process.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-rkl: NOTRUN -> [SKIP][21] ([i915#280]) +1 other test skip
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_eio@unwedge-stress:
- shard-dg2: NOTRUN -> [FAIL][22] ([i915#5784])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-8/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-rkl: NOTRUN -> [SKIP][23] ([i915#4525])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_fair@basic-deadline:
- shard-rkl: NOTRUN -> [FAIL][24] ([i915#2846])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-tglu-1: NOTRUN -> [FAIL][25] ([i915#2842]) +3 other tests fail
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-tglu: NOTRUN -> [FAIL][26] ([i915#2842]) +5 other tests fail
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-5/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-rkl: [PASS][27] -> [FAIL][28] ([i915#2842])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-rkl-7/igt@gem_exec_fair@basic-pace@vecs0.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-3/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-sync:
- shard-dg2: NOTRUN -> [SKIP][29] ([i915#3539]) +2 other tests skip
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-8/igt@gem_exec_fair@basic-sync.html
* igt@gem_exec_reloc@basic-active:
- shard-dg2: NOTRUN -> [SKIP][30] ([i915#3281]) +2 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@gem_exec_reloc@basic-active.html
* igt@gem_exec_schedule@pi-common:
- shard-tglu: NOTRUN -> [FAIL][31] ([i915#12296]) +5 other tests fail
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-5/igt@gem_exec_schedule@pi-common.html
* igt@gem_exec_schedule@pi-common@vecs1:
- shard-dg2: NOTRUN -> [FAIL][32] ([i915#12296]) +7 other tests fail
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@gem_exec_schedule@pi-common@vecs1.html
* igt@gem_exec_schedule@semaphore-power:
- shard-rkl: NOTRUN -> [SKIP][33] ([i915#7276])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-2/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_exec_suspend@basic-s4-devices:
- shard-dg2: NOTRUN -> [ABORT][34] ([i915#7975] / [i915#8213]) +1 other test abort
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-8/igt@gem_exec_suspend@basic-s4-devices.html
- shard-rkl: NOTRUN -> [ABORT][35] ([i915#7975] / [i915#8213]) +2 other tests abort
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-2/igt@gem_exec_suspend@basic-s4-devices.html
* igt@gem_fence_thrash@bo-write-verify-x:
- shard-dg2: NOTRUN -> [SKIP][36] ([i915#4860])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-4/igt@gem_fence_thrash@bo-write-verify-x.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][37] ([i915#4613]) +1 other test skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
* igt@gem_lmem_swapping@heavy-verify-random-ccs:
- shard-tglu: NOTRUN -> [SKIP][38] ([i915#4613]) +2 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-5/igt@gem_lmem_swapping@heavy-verify-random-ccs.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-mtlp: NOTRUN -> [SKIP][39] ([i915#4613])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-mtlp-6/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@random-engines:
- shard-rkl: NOTRUN -> [SKIP][40] ([i915#4613]) +4 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-2/igt@gem_lmem_swapping@random-engines.html
* igt@gem_media_vme:
- shard-rkl: NOTRUN -> [SKIP][41] ([i915#284])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@gem_media_vme.html
* igt@gem_mmap_gtt@isolation:
- shard-dg1: NOTRUN -> [SKIP][42] ([i915#4077])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-17/igt@gem_mmap_gtt@isolation.html
* igt@gem_mmap_wc@bad-object:
- shard-dg2: NOTRUN -> [SKIP][43] ([i915#4083])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-4/igt@gem_mmap_wc@bad-object.html
* igt@gem_mmap_wc@write-cpu-read-wc:
- shard-dg1: NOTRUN -> [SKIP][44] ([i915#4083]) +1 other test skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-17/igt@gem_mmap_wc@write-cpu-read-wc.html
* igt@gem_partial_pwrite_pread@writes-after-reads:
- shard-rkl: NOTRUN -> [SKIP][45] ([i915#3282]) +5 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-7/igt@gem_partial_pwrite_pread@writes-after-reads.html
* igt@gem_pwrite_snooped:
- shard-dg2: NOTRUN -> [SKIP][46] ([i915#3282]) +1 other test skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@gem_pwrite_snooped.html
* igt@gem_pxp@create-valid-protected-context:
- shard-tglu-1: NOTRUN -> [SKIP][47] ([i915#4270]) +2 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@gem_pxp@create-valid-protected-context.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-dg2: NOTRUN -> [SKIP][48] ([i915#4270]) +2 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-8/igt@gem_pxp@regular-baseline-src-copy-readible.html
- shard-rkl: NOTRUN -> [SKIP][49] ([i915#4270]) +4 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-2/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_pxp@reject-modify-context-protection-off-3:
- shard-tglu: NOTRUN -> [SKIP][50] ([i915#4270]) +2 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-3/igt@gem_pxp@reject-modify-context-protection-off-3.html
* igt@gem_pxp@verify-pxp-stale-ctx-execution:
- shard-mtlp: NOTRUN -> [SKIP][51] ([i915#4270])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-mtlp-1/igt@gem_pxp@verify-pxp-stale-ctx-execution.html
* igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][52] ([i915#5190] / [i915#8428]) +3 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-10/igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs.html
* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- shard-dg2: NOTRUN -> [SKIP][53] ([i915#4079])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
* igt@gem_set_tiling_vs_blt@untiled-to-tiled:
- shard-rkl: NOTRUN -> [SKIP][54] ([i915#8411])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
* igt@gem_tiled_blits@basic:
- shard-dg2: NOTRUN -> [SKIP][55] ([i915#4077]) +6 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@gem_tiled_blits@basic.html
* igt@gem_userptr_blits@coherency-sync:
- shard-tglu: NOTRUN -> [SKIP][56] ([i915#3297]) +1 other test skip
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-3/igt@gem_userptr_blits@coherency-sync.html
* igt@gem_userptr_blits@readonly-pwrite-unsync:
- shard-dg2: NOTRUN -> [SKIP][57] ([i915#3297])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@gem_userptr_blits@readonly-pwrite-unsync.html
* igt@gem_userptr_blits@readonly-unsync:
- shard-tglu-1: NOTRUN -> [SKIP][58] ([i915#3297])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@gem_userptr_blits@readonly-unsync.html
* igt@gem_userptr_blits@unsync-unmap:
- shard-rkl: NOTRUN -> [SKIP][59] ([i915#3297])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@gem_userptr_blits@unsync-unmap.html
* igt@gen9_exec_parse@basic-rejected:
- shard-tglu: NOTRUN -> [SKIP][60] ([i915#2527] / [i915#2856]) +2 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-3/igt@gen9_exec_parse@basic-rejected.html
* igt@gen9_exec_parse@bb-secure:
- shard-dg2: NOTRUN -> [SKIP][61] ([i915#2856]) +1 other test skip
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-4/igt@gen9_exec_parse@bb-secure.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-tglu-1: NOTRUN -> [SKIP][62] ([i915#2527] / [i915#2856]) +3 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@gen9_exec_parse@bb-start-cmd.html
* igt@gen9_exec_parse@shadow-peek:
- shard-rkl: NOTRUN -> [SKIP][63] ([i915#2527]) +3 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-6/igt@gen9_exec_parse@shadow-peek.html
* igt@i915_pm_freq_api@freq-reset-multiple:
- shard-tglu: NOTRUN -> [SKIP][64] ([i915#8399])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-5/igt@i915_pm_freq_api@freq-reset-multiple.html
* igt@i915_pm_freq_api@freq-suspend:
- shard-rkl: NOTRUN -> [SKIP][65] ([i915#8399])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@i915_pm_freq_api@freq-suspend.html
* igt@i915_pm_freq_mult@media-freq@gt0:
- shard-tglu: NOTRUN -> [SKIP][66] ([i915#6590]) +1 other test skip
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-3/igt@i915_pm_freq_mult@media-freq@gt0.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-dg1: [PASS][67] -> [FAIL][68] ([i915#12548] / [i915#3591])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-idle.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-12/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0:
- shard-dg1: [PASS][69] -> [FAIL][70] ([i915#3591])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-12/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
* igt@i915_pm_rps@thresholds:
- shard-mtlp: NOTRUN -> [SKIP][71] ([i915#11681])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-mtlp-6/igt@i915_pm_rps@thresholds.html
* igt@i915_pm_sseu@full-enable:
- shard-dg2: NOTRUN -> [SKIP][72] ([i915#4387])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@i915_pm_sseu@full-enable.html
- shard-tglu: NOTRUN -> [SKIP][73] ([i915#4387])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-5/igt@i915_pm_sseu@full-enable.html
* igt@i915_power@sanity:
- shard-rkl: NOTRUN -> [SKIP][74] ([i915#7984])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-7/igt@i915_power@sanity.html
* igt@i915_selftest@live:
- shard-dg2: [PASS][75] -> [DMESG-FAIL][76] ([i915#12133] / [i915#9500])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg2-4/igt@i915_selftest@live.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-11/igt@i915_selftest@live.html
* igt@i915_selftest@live@gt_mocs:
- shard-dg2: [PASS][77] -> [DMESG-FAIL][78] ([i915#9500])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg2-4/igt@i915_selftest@live@gt_mocs.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-11/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@mock@memory_region:
- shard-rkl: NOTRUN -> [DMESG-WARN][79] ([i915#9311]) +1 other test dmesg-warn
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-6/igt@i915_selftest@mock@memory_region.html
* igt@intel_hwmon@hwmon-read:
- shard-tglu-1: NOTRUN -> [SKIP][80] ([i915#7707])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@intel_hwmon@hwmon-read.html
* igt@intel_hwmon@hwmon-write:
- shard-tglu: NOTRUN -> [SKIP][81] ([i915#7707])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-3/igt@intel_hwmon@hwmon-write.html
* igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- shard-dg2: NOTRUN -> [SKIP][82] ([i915#4212])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
* igt@kms_addfb_basic@bo-too-small-due-to-tiling:
- shard-mtlp: NOTRUN -> [SKIP][83] ([i915#4212])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-mtlp-6/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc:
- shard-rkl: NOTRUN -> [SKIP][84] ([i915#8709]) +3 other tests skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-1/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-2-y-rc-ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-1-y-rc-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][85] ([i915#8709]) +7 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-1-y-rc-ccs.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-2-4-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][86] ([i915#8709]) +11 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-11/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-2-4-mc-ccs.html
* igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1:
- shard-tglu: [PASS][87] -> [FAIL][88] ([i915#11808]) +3 other tests fail
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-tglu-4/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-4/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html
* igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1:
- shard-mtlp: [PASS][89] -> [FAIL][90] ([i915#11808] / [i915#5956]) +3 other tests fail
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-mtlp-7/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-mtlp-5/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-0:
- shard-tglu: NOTRUN -> [SKIP][91] ([i915#5286]) +4 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-4/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-addfb:
- shard-rkl: NOTRUN -> [SKIP][92] ([i915#5286]) +5 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-2/igt@kms_big_fb@4-tiled-addfb.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
- shard-tglu-1: NOTRUN -> [SKIP][93] ([i915#5286]) +2 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-mtlp: [PASS][94] -> [FAIL][95] ([i915#5138])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][96] +8 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][97] ([i915#3638]) +6 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-6/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-dg2: NOTRUN -> [SKIP][98] ([i915#4538] / [i915#5190]) +4 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-4/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][99] ([i915#6095]) +35 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-17/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-4.html
* igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-1:
- shard-glk: NOTRUN -> [SKIP][100] +30 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-glk5/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-1.html
* igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [SKIP][101] ([i915#10307] / [i915#6095]) +148 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-10/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs-cc@pipe-a-dp-4.html
* igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][102] ([i915#10307] / [i915#10434] / [i915#6095]) +2 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-4/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
- shard-rkl: NOTRUN -> [SKIP][103] ([i915#12313])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][104] ([i915#6095]) +44 other tests skip
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-5/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-1.html
* igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1:
- shard-tglu-1: NOTRUN -> [SKIP][105] ([i915#6095]) +59 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][106] ([i915#6095]) +83 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-1/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_cdclk@mode-transition:
- shard-rkl: NOTRUN -> [SKIP][107] ([i915#3742])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@kms_cdclk@mode-transition.html
* igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][108] ([i915#7213]) +3 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-1/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html
* igt@kms_cdclk@plane-scaling@pipe-b-dp-4:
- shard-dg2: NOTRUN -> [SKIP][109] ([i915#4087]) +3 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-10/igt@kms_cdclk@plane-scaling@pipe-b-dp-4.html
* igt@kms_chamelium_audio@dp-audio:
- shard-tglu: NOTRUN -> [SKIP][110] ([i915#7828]) +8 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-3/igt@kms_chamelium_audio@dp-audio.html
* igt@kms_chamelium_frames@hdmi-crc-multiple:
- shard-dg2: NOTRUN -> [SKIP][111] ([i915#7828]) +4 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@kms_chamelium_frames@hdmi-crc-multiple.html
* igt@kms_chamelium_frames@hdmi-frame-dump:
- shard-tglu-1: NOTRUN -> [SKIP][112] ([i915#7828]) +5 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_chamelium_frames@hdmi-frame-dump.html
* igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode:
- shard-rkl: NOTRUN -> [SKIP][113] ([i915#7828]) +8 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-6/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html
* igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe:
- shard-dg1: NOTRUN -> [SKIP][114] ([i915#7828])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-17/igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe.html
* igt@kms_content_protection@atomic:
- shard-dg2: NOTRUN -> [SKIP][115] ([i915#7118] / [i915#9424])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-4/igt@kms_content_protection@atomic.html
- shard-rkl: NOTRUN -> [SKIP][116] ([i915#7118] / [i915#9424])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-7/igt@kms_content_protection@atomic.html
- shard-tglu: NOTRUN -> [SKIP][117] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-6/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@atomic-dpms:
- shard-tglu-1: NOTRUN -> [SKIP][118] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424]) +1 other test skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@atomic-dpms@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [TIMEOUT][119] ([i915#7173])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-10/igt@kms_content_protection@atomic-dpms@pipe-a-dp-4.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-dg2: NOTRUN -> [SKIP][120] ([i915#3299])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-4/igt@kms_content_protection@dp-mst-lic-type-1.html
- shard-rkl: NOTRUN -> [SKIP][121] ([i915#3116]) +1 other test skip
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-7/igt@kms_content_protection@dp-mst-lic-type-1.html
- shard-tglu: NOTRUN -> [SKIP][122] ([i915#3116] / [i915#3299])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-6/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@lic-type-0:
- shard-tglu: NOTRUN -> [SKIP][123] ([i915#6944] / [i915#9424]) +1 other test skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-3/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@lic-type-1:
- shard-dg2: NOTRUN -> [SKIP][124] ([i915#9424])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@kms_content_protection@lic-type-1.html
* igt@kms_content_protection@mei-interface:
- shard-rkl: NOTRUN -> [SKIP][125] ([i915#9424])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@kms_content_protection@mei-interface.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-rkl: NOTRUN -> [SKIP][126] ([i915#11453] / [i915#3359])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-random-256x85:
- shard-mtlp: NOTRUN -> [SKIP][127] ([i915#8814])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-mtlp-1/igt@kms_cursor_crc@cursor-random-256x85.html
* igt@kms_cursor_crc@cursor-random-32x10:
- shard-mtlp: NOTRUN -> [SKIP][128] ([i915#3555] / [i915#8814])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-mtlp-6/igt@kms_cursor_crc@cursor-random-32x10.html
* igt@kms_cursor_crc@cursor-random-512x512:
- shard-tglu-1: NOTRUN -> [SKIP][129] ([i915#11453] / [i915#3359]) +2 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_cursor_crc@cursor-random-512x512.html
* igt@kms_cursor_crc@cursor-sliding-32x10:
- shard-rkl: NOTRUN -> [SKIP][130] ([i915#3555]) +7 other tests skip
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@kms_cursor_crc@cursor-sliding-32x10.html
* igt@kms_cursor_edge_walk@64x64-left-edge:
- shard-dg1: [PASS][131] -> [DMESG-WARN][132] ([i915#4423]) +3 other tests dmesg-warn
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg1-16/igt@kms_cursor_edge_walk@64x64-left-edge.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-17/igt@kms_cursor_edge_walk@64x64-left-edge.html
* igt@kms_cursor_edge_walk@64x64-left-edge@pipe-a-hdmi-a-1:
- shard-glk: [PASS][133] -> [DMESG-FAIL][134] ([i915#118]) +1 other test dmesg-fail
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-glk1/igt@kms_cursor_edge_walk@64x64-left-edge@pipe-a-hdmi-a-1.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-glk8/igt@kms_cursor_edge_walk@64x64-left-edge@pipe-a-hdmi-a-1.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [PASS][135] -> [FAIL][136] ([i915#2346])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
- shard-snb: [PASS][137] -> [FAIL][138] ([i915#2346])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-snb6/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-snb2/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-rkl: NOTRUN -> [SKIP][139] ([i915#4103])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
- shard-tglu-1: NOTRUN -> [SKIP][140] ([i915#9723])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
* igt@kms_dsc@dsc-basic:
- shard-dg2: NOTRUN -> [SKIP][141] ([i915#3555] / [i915#3840])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@kms_dsc@dsc-basic.html
- shard-tglu: NOTRUN -> [SKIP][142] ([i915#3555] / [i915#3840])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-5/igt@kms_dsc@dsc-basic.html
* igt@kms_dsc@dsc-fractional-bpp-with-bpc:
- shard-tglu-1: NOTRUN -> [SKIP][143] ([i915#3840])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-rkl: NOTRUN -> [SKIP][144] ([i915#3555] / [i915#3840])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-6/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-tglu: NOTRUN -> [SKIP][145] ([i915#3840] / [i915#9053])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-9/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-rkl: NOTRUN -> [SKIP][146] ([i915#3955]) +1 other test skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-2/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_feature_discovery@display-2x:
- shard-tglu: NOTRUN -> [SKIP][147] ([i915#1839])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-3/igt@kms_feature_discovery@display-2x.html
* igt@kms_feature_discovery@display-4x:
- shard-tglu-1: NOTRUN -> [SKIP][148] ([i915#1839])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_feature_discovery@display-4x.html
* igt@kms_feature_discovery@dp-mst:
- shard-rkl: NOTRUN -> [SKIP][149] ([i915#9337])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-2/igt@kms_feature_discovery@dp-mst.html
* igt@kms_feature_discovery@psr1:
- shard-tglu: NOTRUN -> [SKIP][150] ([i915#658])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-3/igt@kms_feature_discovery@psr1.html
* igt@kms_fence_pin_leak:
- shard-dg1: NOTRUN -> [SKIP][151] ([i915#4881])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-17/igt@kms_fence_pin_leak.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank:
- shard-tglu: NOTRUN -> [SKIP][152] ([i915#3637]) +6 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-3/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html
* igt@kms_flip@2x-flip-vs-modeset:
- shard-tglu-1: NOTRUN -> [SKIP][153] ([i915#3637] / [i915#3966])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_flip@2x-flip-vs-modeset.html
* igt@kms_flip@2x-flip-vs-panning-vs-hang:
- shard-dg2: NOTRUN -> [SKIP][154] ([i915#5354]) +24 other tests skip
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-tglu-1: NOTRUN -> [SKIP][155] ([i915#3637]) +5 other tests skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_flip@2x-plain-flip:
- shard-rkl: NOTRUN -> [SKIP][156] +32 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-7/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@2x-plain-flip-fb-recreate:
- shard-glk: [PASS][157] -> [FAIL][158] ([i915#2122]) +3 other tests fail
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-glk1/igt@kms_flip@2x-plain-flip-fb-recreate.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-glk5/igt@kms_flip@2x-plain-flip-fb-recreate.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
- shard-rkl: NOTRUN -> [FAIL][159] ([i915#2122]) +2 other tests fail
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-hdmi-a2:
- shard-rkl: NOTRUN -> [FAIL][160] ([i915#11961])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-hdmi-a2.html
* igt@kms_flip@flip-vs-panning:
- shard-dg1: NOTRUN -> [INCOMPLETE][161] ([i915#6113]) +2 other tests incomplete
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-19/igt@kms_flip@flip-vs-panning.html
* igt@kms_flip@flip-vs-suspend:
- shard-mtlp: NOTRUN -> [INCOMPLETE][162] ([i915#6113]) +1 other test incomplete
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-mtlp-6/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend@c-hdmi-a2:
- shard-glk: NOTRUN -> [INCOMPLETE][163] ([i915#4839])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-glk2/igt@kms_flip@flip-vs-suspend@c-hdmi-a2.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible:
- shard-tglu: NOTRUN -> [FAIL][164] ([i915#2122]) +1 other test fail
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-3/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
* igt@kms_flip@wf_vblank-ts-check@b-hdmi-a1:
- shard-dg2: [PASS][165] -> [FAIL][166] ([i915#2122])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg2-8/igt@kms_flip@wf_vblank-ts-check@b-hdmi-a1.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-8/igt@kms_flip@wf_vblank-ts-check@b-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling:
- shard-dg1: NOTRUN -> [SKIP][167] ([i915#2672] / [i915#3555])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-17/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][168] ([i915#2587] / [i915#2672])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-17/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
- shard-tglu: NOTRUN -> [SKIP][169] ([i915#2587] / [i915#2672] / [i915#3555])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
- shard-dg2: NOTRUN -> [SKIP][170] ([i915#2672] / [i915#3555] / [i915#5190])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][171] ([i915#2672]) +1 other test skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][172] ([i915#2672]) +5 other tests skip
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling:
- shard-rkl: NOTRUN -> [SKIP][173] ([i915#2672] / [i915#3555]) +5 other tests skip
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling:
- shard-tglu-1: NOTRUN -> [SKIP][174] ([i915#2672] / [i915#3555]) +1 other test skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-valid-mode:
- shard-tglu-1: NOTRUN -> [SKIP][175] ([i915#2587] / [i915#2672]) +1 other test skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
- shard-tglu: NOTRUN -> [SKIP][176] ([i915#2672] / [i915#3555]) +2 other tests skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
- shard-dg2: NOTRUN -> [SKIP][177] ([i915#2672] / [i915#3555])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][178] ([i915#2587] / [i915#2672]) +3 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-5/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render:
- shard-rkl: NOTRUN -> [SKIP][179] ([i915#1825]) +39 other tests skip
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu:
- shard-snb: [PASS][180] -> [SKIP][181] +2 other tests skip
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-snb6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-snb2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- shard-rkl: NOTRUN -> [SKIP][182] ([i915#5439])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
* igt@kms_frontbuffer_tracking@fbc-tiling-y:
- shard-dg2: NOTRUN -> [SKIP][183] ([i915#10055])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-tiling-y.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt:
- shard-dg2: NOTRUN -> [SKIP][184] ([i915#3458]) +8 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-dg1: NOTRUN -> [SKIP][185] +3 other tests skip
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-17/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-dg2: NOTRUN -> [SKIP][186] ([i915#8708]) +8 other tests skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt:
- shard-rkl: NOTRUN -> [SKIP][187] ([i915#3023]) +26 other tests skip
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][188] ([i915#8708]) +1 other test skip
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt:
- shard-mtlp: NOTRUN -> [SKIP][189] ([i915#1825]) +1 other test skip
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-mtlp-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc:
- shard-tglu-1: NOTRUN -> [SKIP][190] +57 other tests skip
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary:
- shard-tglu: NOTRUN -> [SKIP][191] +66 other tests skip
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-6/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-tglu: NOTRUN -> [SKIP][192] ([i915#3555] / [i915#8228]) +1 other test skip
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-4/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-rkl: NOTRUN -> [SKIP][193] ([i915#3555] / [i915#8228])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_hdr@static-toggle-dpms:
- shard-dg2: NOTRUN -> [SKIP][194] ([i915#3555] / [i915#8228])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_hdr@static-toggle-suspend:
- shard-tglu-1: NOTRUN -> [SKIP][195] ([i915#3555] / [i915#8228]) +1 other test skip
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_joiner@basic-force-big-joiner:
- shard-rkl: NOTRUN -> [SKIP][196] ([i915#12388])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@kms_joiner@basic-force-big-joiner.html
* igt@kms_joiner@invalid-modeset-big-joiner:
- shard-tglu: NOTRUN -> [SKIP][197] ([i915#10656])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-3/igt@kms_joiner@invalid-modeset-big-joiner.html
* igt@kms_panel_fitting@legacy:
- shard-rkl: NOTRUN -> [SKIP][198] ([i915#6301])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-6/igt@kms_panel_fitting@legacy.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-tglu-1: NOTRUN -> [SKIP][199] ([i915#6953])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers:
- shard-dg2: NOTRUN -> [SKIP][200] ([i915#12247] / [i915#9423])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-10/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format:
- shard-tglu-1: NOTRUN -> [SKIP][201] ([i915#12247]) +9 other tests skip
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-modifiers@pipe-b:
- shard-snb: NOTRUN -> [SKIP][202] +60 other tests skip
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-snb7/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-modifiers@pipe-b.html
* igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a:
- shard-rkl: NOTRUN -> [SKIP][203] ([i915#12247]) +13 other tests skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-6/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25:
- shard-dg2: NOTRUN -> [SKIP][204] ([i915#12247] / [i915#6953] / [i915#9423])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html
- shard-tglu: NOTRUN -> [SKIP][205] ([i915#12247] / [i915#6953])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-5/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-a:
- shard-dg2: NOTRUN -> [SKIP][206] ([i915#12247]) +7 other tests skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-a.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d:
- shard-tglu: NOTRUN -> [SKIP][207] ([i915#12247]) +3 other tests skip
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-5/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25:
- shard-rkl: NOTRUN -> [SKIP][208] ([i915#12247] / [i915#3555])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html
* igt@kms_pm_backlight@brightness-with-dpms:
- shard-tglu-1: NOTRUN -> [SKIP][209] ([i915#12343])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_pm_backlight@brightness-with-dpms.html
* igt@kms_pm_backlight@fade-with-dpms:
- shard-tglu: NOTRUN -> [SKIP][210] ([i915#9812]) +1 other test skip
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-5/igt@kms_pm_backlight@fade-with-dpms.html
* igt@kms_pm_dc@dc5-psr:
- shard-dg2: NOTRUN -> [SKIP][211] ([i915#9685])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-4/igt@kms_pm_dc@dc5-psr.html
- shard-rkl: NOTRUN -> [SKIP][212] ([i915#9685]) +1 other test skip
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-7/igt@kms_pm_dc@dc5-psr.html
- shard-tglu: NOTRUN -> [SKIP][213] ([i915#9685])
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-6/igt@kms_pm_dc@dc5-psr.html
* igt@kms_pm_dc@dc5-retention-flops:
- shard-tglu-1: NOTRUN -> [SKIP][214] ([i915#3828])
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_pm_dc@dc5-retention-flops.html
* igt@kms_pm_dc@dc6-dpms:
- shard-rkl: NOTRUN -> [FAIL][215] ([i915#9295])
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@kms_pm_dc@dc6-dpms.html
- shard-tglu: [PASS][216] -> [FAIL][217] ([i915#9295])
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-tglu-4/igt@kms_pm_dc@dc6-dpms.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-9/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_dc@dc9-dpms:
- shard-rkl: NOTRUN -> [SKIP][218] ([i915#3361])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-6/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-rkl: [PASS][219] -> [SKIP][220] ([i915#9519])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-rkl-1/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-2/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area:
- shard-glk: NOTRUN -> [SKIP][221] ([i915#11520])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-glk4/igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
- shard-tglu-1: NOTRUN -> [SKIP][222] ([i915#11520]) +5 other tests skip
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area:
- shard-dg2: NOTRUN -> [SKIP][223] ([i915#11520]) +4 other tests skip
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-4/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html
- shard-rkl: NOTRUN -> [SKIP][224] ([i915#11520]) +9 other tests skip
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-7/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html
- shard-tglu: NOTRUN -> [SKIP][225] ([i915#11520]) +5 other tests skip
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-6/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-tglu-1: NOTRUN -> [SKIP][226] ([i915#9683])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-tglu: NOTRUN -> [SKIP][227] ([i915#9683])
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-5/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-dg2: NOTRUN -> [SKIP][228] ([i915#9683]) +1 other test skip
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-10/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-psr-primary-blt:
- shard-dg2: NOTRUN -> [SKIP][229] ([i915#1072] / [i915#9732]) +8 other tests skip
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-4/igt@kms_psr@fbc-psr-primary-blt.html
- shard-rkl: NOTRUN -> [SKIP][230] ([i915#1072] / [i915#9732]) +19 other tests skip
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-7/igt@kms_psr@fbc-psr-primary-blt.html
* igt@kms_psr@fbc-psr2-cursor-blt:
- shard-tglu-1: NOTRUN -> [SKIP][231] ([i915#9732]) +13 other tests skip
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_psr@fbc-psr2-cursor-blt.html
* igt@kms_psr@fbc-psr2-cursor-plane-onoff:
- shard-dg1: NOTRUN -> [SKIP][232] ([i915#1072] / [i915#9732])
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-17/igt@kms_psr@fbc-psr2-cursor-plane-onoff.html
* igt@kms_psr@fbc-psr2-sprite-render:
- shard-tglu: NOTRUN -> [SKIP][233] ([i915#9732]) +14 other tests skip
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-3/igt@kms_psr@fbc-psr2-sprite-render.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-tglu-1: NOTRUN -> [SKIP][234] ([i915#9685])
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@exhaust-fences:
- shard-dg2: NOTRUN -> [SKIP][235] ([i915#4235])
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@kms_rotation_crc@exhaust-fences.html
* igt@kms_rotation_crc@primary-rotation-90:
- shard-dg2: NOTRUN -> [SKIP][236] ([i915#11131] / [i915#4235])
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-4/igt@kms_rotation_crc@primary-rotation-90.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-tglu-1: NOTRUN -> [SKIP][237] ([i915#5289])
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-rkl: NOTRUN -> [SKIP][238] ([i915#5289]) +2 other tests skip
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-7/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
- shard-tglu: NOTRUN -> [SKIP][239] ([i915#5289]) +1 other test skip
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
- shard-dg2: NOTRUN -> [SKIP][240] ([i915#5190])
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-dg2: NOTRUN -> [SKIP][241] ([i915#11131] / [i915#4235] / [i915#5190])
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_scaling_modes@scaling-mode-full:
- shard-tglu: NOTRUN -> [SKIP][242] ([i915#3555]) +4 other tests skip
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-6/igt@kms_scaling_modes@scaling-mode-full.html
* igt@kms_setmode@basic-clone-single-crtc:
- shard-tglu-1: NOTRUN -> [SKIP][243] ([i915#3555]) +4 other tests skip
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_setmode@basic-clone-single-crtc.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-tglu-1: NOTRUN -> [SKIP][244] ([i915#8623])
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_vrr@flip-basic-fastset:
- shard-dg2: NOTRUN -> [SKIP][245] ([i915#9906])
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-4/igt@kms_vrr@flip-basic-fastset.html
- shard-rkl: NOTRUN -> [SKIP][246] ([i915#9906])
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-7/igt@kms_vrr@flip-basic-fastset.html
- shard-tglu: NOTRUN -> [SKIP][247] ([i915#9906])
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-6/igt@kms_vrr@flip-basic-fastset.html
* igt@kms_vrr@flip-dpms:
- shard-dg2: NOTRUN -> [SKIP][248] ([i915#3555]) +4 other tests skip
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-2/igt@kms_vrr@flip-dpms.html
* igt@kms_vrr@lobf:
- shard-tglu-1: NOTRUN -> [SKIP][249] ([i915#11920])
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_vrr@lobf.html
* igt@kms_vrr@negative-basic:
- shard-mtlp: [PASS][250] -> [FAIL][251] ([i915#10393]) +1 other test fail
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-mtlp-8/igt@kms_vrr@negative-basic.html
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-mtlp-5/igt@kms_vrr@negative-basic.html
* igt@kms_vrr@seamless-rr-switch-drrs:
- shard-tglu-1: NOTRUN -> [SKIP][252] ([i915#9906])
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_vrr@seamless-rr-switch-drrs.html
* igt@kms_writeback@writeback-check-output-xrgb2101010:
- shard-dg2: NOTRUN -> [SKIP][253] ([i915#2437] / [i915#9412])
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-4/igt@kms_writeback@writeback-check-output-xrgb2101010.html
- shard-tglu: NOTRUN -> [SKIP][254] ([i915#2437] / [i915#9412])
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-6/igt@kms_writeback@writeback-check-output-xrgb2101010.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-rkl: NOTRUN -> [SKIP][255] ([i915#2437] / [i915#9412]) +1 other test skip
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-tglu-1: NOTRUN -> [SKIP][256] ([i915#2437])
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-1/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf@per-context-mode-unprivileged:
- shard-rkl: NOTRUN -> [SKIP][257] ([i915#2435])
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-2/igt@perf@per-context-mode-unprivileged.html
* igt@perf@unprivileged-single-ctx-counters:
- shard-rkl: NOTRUN -> [SKIP][258] ([i915#2433])
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-6/igt@perf@unprivileged-single-ctx-counters.html
* igt@perf_pmu@cpu-hotplug:
- shard-rkl: NOTRUN -> [SKIP][259] ([i915#8850])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-2/igt@perf_pmu@cpu-hotplug.html
* igt@perf_pmu@rc6-all-gts:
- shard-dg2: NOTRUN -> [SKIP][260] ([i915#8516])
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-4/igt@perf_pmu@rc6-all-gts.html
- shard-rkl: NOTRUN -> [SKIP][261] ([i915#8516])
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-7/igt@perf_pmu@rc6-all-gts.html
- shard-tglu: NOTRUN -> [SKIP][262] ([i915#8516])
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-6/igt@perf_pmu@rc6-all-gts.html
* igt@prime_vgem@basic-gtt:
- shard-mtlp: NOTRUN -> [SKIP][263] ([i915#3708] / [i915#4077])
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-mtlp-1/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@basic-read:
- shard-dg2: NOTRUN -> [SKIP][264] ([i915#3291] / [i915#3708])
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-8/igt@prime_vgem@basic-read.html
- shard-rkl: NOTRUN -> [SKIP][265] ([i915#3291] / [i915#3708])
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-2/igt@prime_vgem@basic-read.html
* igt@sriov_basic@enable-vfs-autoprobe-off:
- shard-tglu: NOTRUN -> [SKIP][266] ([i915#9917])
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-3/igt@sriov_basic@enable-vfs-autoprobe-off.html
* igt@sriov_basic@enable-vfs-bind-unbind-each:
- shard-rkl: NOTRUN -> [SKIP][267] ([i915#9917])
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-2/igt@sriov_basic@enable-vfs-bind-unbind-each.html
* igt@syncobj_wait@invalid-wait-zero-handles:
- shard-dg2: NOTRUN -> [FAIL][268] ([i915#12564] / [i915#9781])
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-4/igt@syncobj_wait@invalid-wait-zero-handles.html
- shard-rkl: NOTRUN -> [FAIL][269] ([i915#12564] / [i915#9781])
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-7/igt@syncobj_wait@invalid-wait-zero-handles.html
- shard-tglu: NOTRUN -> [FAIL][270] ([i915#12564] / [i915#9781])
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-6/igt@syncobj_wait@invalid-wait-zero-handles.html
#### Possible fixes ####
* igt@gem_ctx_engines@invalid-engines:
- shard-mtlp: [FAIL][271] ([i915#12031]) -> [PASS][272]
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-mtlp-3/igt@gem_ctx_engines@invalid-engines.html
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-mtlp-2/igt@gem_ctx_engines@invalid-engines.html
* igt@gem_ctx_freq@sysfs@gt0:
- shard-dg2: [FAIL][273] ([i915#9561]) -> [PASS][274] +1 other test pass
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg2-4/igt@gem_ctx_freq@sysfs@gt0.html
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-11/igt@gem_ctx_freq@sysfs@gt0.html
* igt@gem_exec_fair@basic-pace:
- shard-glk: [FAIL][275] ([i915#2842]) -> [PASS][276] +1 other test pass
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-glk4/igt@gem_exec_fair@basic-pace.html
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-glk6/igt@gem_exec_fair@basic-pace.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [ABORT][277] ([i915#5566]) -> [PASS][278]
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-glk1/igt@gen9_exec_parse@allowed-single.html
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-glk5/igt@gen9_exec_parse@allowed-single.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-tglu: [ABORT][279] ([i915#9820]) -> [PASS][280]
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-tglu-3/igt@i915_module_load@reload-with-fault-injection.html
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-9/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_suspend@basic-s2idle-without-i915:
- shard-dg1: [DMESG-WARN][281] ([i915#4391] / [i915#4423]) -> [PASS][282]
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg1-17/igt@i915_suspend@basic-s2idle-without-i915.html
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-16/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-rkl: [INCOMPLETE][283] ([i915#4817]) -> [PASS][284]
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-rkl-3/igt@i915_suspend@basic-s3-without-i915.html
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-5/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_atomic_transition@modeset-transition-nonblocking:
- shard-glk: [FAIL][285] ([i915#12177]) -> [PASS][286]
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking.html
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-glk2/igt@kms_atomic_transition@modeset-transition-nonblocking.html
* igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs:
- shard-glk: [FAIL][287] ([i915#11859]) -> [PASS][288]
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-glk8/igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs.html
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-glk2/igt@kms_atomic_transition@modeset-transition-nonblocking@2x-outputs.html
* igt@kms_color@ctm-0-50:
- shard-dg1: [DMESG-WARN][289] ([i915#4423]) -> [PASS][290]
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg1-17/igt@kms_color@ctm-0-50.html
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-16/igt@kms_color@ctm-0-50.html
* igt@kms_cursor_crc@cursor-suspend:
- shard-snb: [DMESG-WARN][291] -> [PASS][292] +1 other test pass
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-snb4/igt@kms_cursor_crc@cursor-suspend.html
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-snb6/igt@kms_cursor_crc@cursor-suspend.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc:
- shard-dg2: [SKIP][293] ([i915#3555]) -> [PASS][294]
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg2-5/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-10/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
* igt@kms_flip@2x-plain-flip-fb-recreate@ab-vga1-hdmi-a1:
- shard-snb: [FAIL][295] ([i915#2122]) -> [PASS][296] +7 other tests pass
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-snb6/igt@kms_flip@2x-plain-flip-fb-recreate@ab-vga1-hdmi-a1.html
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-snb1/igt@kms_flip@2x-plain-flip-fb-recreate@ab-vga1-hdmi-a1.html
* igt@kms_flip@flip-vs-absolute-wf_vblank@b-hdmi-a1:
- shard-tglu: [FAIL][297] ([i915#2122]) -> [PASS][298] +3 other tests pass
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-tglu-2/igt@kms_flip@flip-vs-absolute-wf_vblank@b-hdmi-a1.html
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-2/igt@kms_flip@flip-vs-absolute-wf_vblank@b-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-mtlp: [FAIL][299] ([i915#79]) -> [PASS][300] +1 other test pass
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-mtlp-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-mtlp-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-glk: [INCOMPLETE][301] ([i915#4839]) -> [PASS][302] +1 other test pass
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-glk3/igt@kms_flip@flip-vs-suspend-interruptible.html
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-glk3/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a2:
- shard-glk: [INCOMPLETE][303] ([i915#9878]) -> [PASS][304]
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-glk3/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a2.html
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-glk3/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend@b-hdmi-a3:
- shard-dg1: [INCOMPLETE][305] ([i915#6113]) -> [PASS][306]
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg1-13/igt@kms_flip@flip-vs-suspend@b-hdmi-a3.html
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-12/igt@kms_flip@flip-vs-suspend@b-hdmi-a3.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible:
- shard-dg2: [FAIL][307] ([i915#2122]) -> [PASS][308]
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg2-10/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-5/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
* igt@kms_flip@wf_vblank-ts-check:
- shard-dg1: [FAIL][309] ([i915#11989] / [i915#12517] / [i915#2122]) -> [PASS][310]
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg1-14/igt@kms_flip@wf_vblank-ts-check.html
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-17/igt@kms_flip@wf_vblank-ts-check.html
* igt@kms_flip@wf_vblank-ts-check@a-hdmi-a4:
- shard-dg1: [FAIL][311] -> [PASS][312]
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg1-14/igt@kms_flip@wf_vblank-ts-check@a-hdmi-a4.html
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-17/igt@kms_flip@wf_vblank-ts-check@a-hdmi-a4.html
* igt@kms_flip@wf_vblank-ts-check@c-edp1:
- shard-mtlp: [FAIL][313] ([i915#2122]) -> [PASS][314]
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-mtlp-2/igt@kms_flip@wf_vblank-ts-check@c-edp1.html
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-mtlp-8/igt@kms_flip@wf_vblank-ts-check@c-edp1.html
* igt@kms_flip@wf_vblank-ts-check@c-hdmi-a4:
- shard-dg1: [FAIL][315] ([i915#2122]) -> [PASS][316] +1 other test pass
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg1-14/igt@kms_flip@wf_vblank-ts-check@c-hdmi-a4.html
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-17/igt@kms_flip@wf_vblank-ts-check@c-hdmi-a4.html
* igt@kms_frontbuffer_tracking@fbc-tiling-linear:
- shard-dg2: [FAIL][317] ([i915#6880]) -> [PASS][318]
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html
* igt@kms_hdr@static-toggle-suspend:
- shard-dg2: [SKIP][319] ([i915#3555] / [i915#8228]) -> [PASS][320] +1 other test pass
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg2-8/igt@kms_hdr@static-toggle-suspend.html
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-10/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_pm_dc@dc5-dpms:
- shard-mtlp: [FAIL][321] -> [PASS][322]
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-mtlp-2/igt@kms_pm_dc@dc5-dpms.html
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-mtlp-8/igt@kms_pm_dc@dc5-dpms.html
* igt@kms_pm_dc@dc9-dpms:
- shard-tglu: [SKIP][323] ([i915#4281]) -> [PASS][324]
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-tglu-9/igt@kms_pm_dc@dc9-dpms.html
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-tglu-6/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-rkl: [SKIP][325] ([i915#9519]) -> [PASS][326]
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-rkl-2/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-3/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
#### Warnings ####
* igt@i915_pm_rpm@gem-evict-pwrite:
- shard-dg1: [SKIP][327] ([i915#4077] / [i915#4423]) -> [SKIP][328] ([i915#4077])
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg1-17/igt@i915_pm_rpm@gem-evict-pwrite.html
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-16/igt@i915_pm_rpm@gem-evict-pwrite.html
* igt@i915_selftest@mock:
- shard-glk: [DMESG-WARN][329] ([i915#1982] / [i915#9311]) -> [DMESG-WARN][330] ([i915#9311])
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-glk8/igt@i915_selftest@mock.html
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-glk2/igt@i915_selftest@mock.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- shard-dg1: [SKIP][331] ([i915#4212] / [i915#4423]) -> [SKIP][332] ([i915#4212])
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg1-17/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
[332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-16/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_content_protection@atomic-dpms:
- shard-dg2: [SKIP][333] ([i915#7118] / [i915#9424]) -> [TIMEOUT][334] ([i915#7173])
[333]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg2-8/igt@kms_content_protection@atomic-dpms.html
[334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-10/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@lic-type-0:
- shard-dg2: [TIMEOUT][335] ([i915#7173]) -> [SKIP][336] ([i915#9424])
[335]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg2-10/igt@kms_content_protection@lic-type-0.html
[336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-5/igt@kms_content_protection@lic-type-0.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
- shard-dg2: [SKIP][337] ([i915#3458]) -> [SKIP][338] ([i915#10433] / [i915#3458])
[337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg2-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
[338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-blt:
- shard-dg1: [SKIP][339] ([i915#4423]) -> [SKIP][340]
[339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-blt.html
[340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-blt.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][341] ([i915#4070] / [i915#4816]) -> [SKIP][342] ([i915#4816])
[341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-rkl-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-7/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-rkl: [SKIP][343] ([i915#9340]) -> [SKIP][344] ([i915#3828])
[343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-rkl-1/igt@kms_pm_lpsp@kms-lpsp.html
[344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-rkl-7/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_psr@psr2-cursor-blt:
- shard-dg1: [SKIP][345] ([i915#1072] / [i915#4423] / [i915#9732]) -> [SKIP][346] ([i915#1072] / [i915#9732])
[345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15627/shard-dg1-12/igt@kms_psr@psr2-cursor-blt.html
[346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/shard-dg1-17/igt@kms_psr@psr2-cursor-blt.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10055]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10055
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10393]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10393
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
[i915#11131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11131
[i915#11453]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11453
[i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/118
[i915#11808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11808
[i915#11859]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11859
[i915#1187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1187
[i915#11920]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11920
[i915#11961]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11961
[i915#11980]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11980
[i915#11989]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11989
[i915#12031]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12031
[i915#12133]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12133
[i915#12177]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12177
[i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
[i915#12296]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12296
[i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
[i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
[i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388
[i915#12392]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12392
[i915#12517]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12517
[i915#12548]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12548
[i915#12564]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12564
[i915#12577]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12577
[i915#12580]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12580
[i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
[i915#2433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2433
[i915#2435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2435
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
[i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#3955]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3955
[i915#3966]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3966
[i915#4070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4087
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
[i915#4387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4387
[i915#4391]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4391
[i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
[i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
[i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#4879]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4879
[i915#4881]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4881
[i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
[i915#5566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
[i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6113]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6113
[i915#6230]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6230
[i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
[i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590
[i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
[i915#7213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7213
[i915#7276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7276
[i915#7297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7297
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/79
[i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
[i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
[i915#8213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
[i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
[i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
[i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
[i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
[i915#8850]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8850
[i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053
[i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
[i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
[i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9500]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9500
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
[i915#9561]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9561
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9781
[i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
[i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
[i915#9833]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9833
[i915#9878]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9878
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
Build changes
-------------
* Linux: CI_DRM_15627 -> Patchwork_139513v4
CI-20190529: 20190529
CI_DRM_15627: 0a6cc4357ae4d824f909468ca1deed28ae5ac96f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8093: 8093
Patchwork_139513v4: 0a6cc4357ae4d824f909468ca1deed28ae5ac96f @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_139513v4/index.html
[-- Attachment #2: Type: text/html, Size: 115451 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH] drm/i915/psr: Implement WA to help reach PC10
2024-11-04 14:18 ` Jani Nikula
@ 2024-11-06 8:18 ` Kandpal, Suraj
0 siblings, 0 replies; 13+ messages in thread
From: Kandpal, Suraj @ 2024-11-06 8:18 UTC (permalink / raw)
To: Jani Nikula, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: Hogander, Jouni
> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Monday, November 4, 2024 7:48 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Hogander, Jouni <jouni.hogander@intel.com>; Kandpal, Suraj
> <suraj.kandpal@intel.com>
> Subject: Re: [PATCH] drm/i915/psr: Implement WA to help reach PC10
>
> On Mon, 04 Nov 2024, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > To reach PC10 when PKG_C_LATENCY is configure we must do the following
> > things
> > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> > entered
> > 2) Allow PSR2 deep sleep when DC5 can be entered
> > 3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
> > eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
> > not happening.
> >
> > --v2
> > -Add debug prints
> >
> > --v3
> > -use crtc as variable name for intel_crtc [Jani] -use encoder as
> > variable name for intel_encoder [Jani] -No changes in intel_dp in
> > compute_config_late [Jani]
> >
> > --v4
> > -Remove "check" from naming [Jani]
> > -Remove intel_encoder variable which is not necessary in
> > compute_config_late
> >
> > WA: 22019444797
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
> > .../drm/i915/display/intel_display_types.h | 6 +
> > drivers/gpu/drm/i915/display/intel_psr.c | 130 +++++++++++++++++-
> > drivers/gpu/drm/i915/display/intel_psr.h | 1 +
> > 4 files changed, 139 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 0535daed6a9f..8e0fb6bd6211 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4403,6 +4403,9 @@ static int intel_ddi_compute_config_late(struct
> intel_encoder *encoder,
> > port_sync_transcoders & ~BIT(crtc_state-
> >cpu_transcoder);
> > }
> >
> > + if (intel_encoder_is_dp(encoder))
> > + intel_psr_compute_config_late(crtc_state);
> > +
> > return 0;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index ff6eb93337e0..dd5f3ea90e5b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1089,6 +1089,9 @@ struct intel_crtc_state {
> > bool req_psr2_sdp_prior_scanline;
> > bool has_panel_replay;
> > bool wm_level_disabled;
> > + bool is_wa_delayed_vblank_limit;
> > + bool is_dpkgc_configured;
> > + bool is_dc5_entry_possible;
> > u32 dc3co_exitline;
> > u16 su_y_granularity;
> >
> > @@ -1587,6 +1590,9 @@ struct intel_psr {
> > #define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
> >
> > u32 debug;
> > + bool is_dpkgc_configured;
> > + bool is_dc5_entry_possible;
> > + bool is_wa_delayed_vblank_limit;
>
> I don't understand why all of these need to be duplicated in struct intel_psr.
>
> I get that you don't necessarily have access to the crtc state in all
> circumstances. But doesn't the workaround basically boil down to using 0 idle
> frames in hsw_activate_psr2()?
>
> > bool sink_support;
> > bool source_support;
> > bool enabled;
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index a784c0b81556..b93358a82aa3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -26,6 +26,7 @@
> > #include <drm/drm_atomic_helper.h>
> > #include <drm/drm_damage_helper.h>
> > #include <drm/drm_debugfs.h>
> > +#include <drm/drm_vblank.h>
> >
> > #include "i915_drv.h"
> > #include "i915_reg.h"
> > @@ -898,6 +899,81 @@ static u8 psr_compute_idle_frames(struct intel_dp
> *intel_dp)
> > return idle_frames;
> > }
> >
> > +static bool
> > +intel_psr_wa_delayed_vblank(const struct drm_display_mode
> > +*adjusted_mode) {
> > + return (adjusted_mode->crtc_vblank_start -
> > +adjusted_mode->crtc_vdisplay) >= 6; }
> > +
> > +/*
> > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> > + * VRR is not enabled
> > + */
> > +static bool intel_psr_is_dpkgc_configured(struct intel_display *display,
> > + struct intel_crtc_state *crtc_state) {
> > + if (DISPLAY_VER(display) < 20 || crtc_state->vrr.enable)
> > + return false;
> > +
> > + return true;
>
> IOW,
>
> return DISPLAY_VER(display) >= 20 && !crtc_state->vrr.enable;
>
> > +}
> > +
> > +static bool wa_22019444797_psr1(const struct intel_crtc_state *crtc_state,
> > + struct intel_psr *psr)
>
> I really dislike function names like this. It doesn't say *anything* to the reader.
> It's hard to pronounce. It's hard to talk about. I don't know what it means.
>
> Something like psr1_needs_wa_22019444797() is already much better, even if
> it still contains the wa number. It tells what it's about, and the reader doesn't
> have to try to guess.
Sure will fix the name here Jani
>
> > +{
> > + struct intel_display *display = to_intel_display(crtc_state);
> > +
> > + if (DISPLAY_VER(display) == 20 && psr->is_dpkgc_configured &&
> > + (psr->is_wa_delayed_vblank_limit || !psr->is_dc5_entry_possible)
> &&
> > + !crtc_state->has_sel_update && !crtc_state->has_panel_replay) {
> > + drm_dbg_kms(display->drm,
> > + "Wa 22019444797 requirement met PSR1
> disabled\n");
>
> That debug log message is not a sentence. Maybe something like, "Disabling
> PSR1 due to wa 22019444797\n".
Got it will update the debug message to state the above message
>
> > + return true;
> > + } else {
> > + return false;
> > + }
> > +}
>
> Why is this function looking at struct intel_psr to make decisions?
> Shouldn't it use old and new crtc state, and nothing else?
>
> > +
> > +/*
> > + * DC5 entry is only possible if vblank interrupt is disabled
> > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> > + * enabled encoders.
> > + */
> > +static bool
> > +intel_psr_is_dc5_entry_possible(struct intel_display *display,
> > + struct intel_crtc_state *crtc_state) {
> > + struct intel_crtc *crtc;
> > +
> > + if ((display->power.domains.target_dc_state &
> > + DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
> > + return false;
> > +
> > + if (!crtc_state->has_psr && !crtc_state->has_sel_update &&
> > + !crtc_state->has_panel_replay)
> > + return false;
> > +
> > + for_each_intel_crtc(display->drm, crtc) {
> > + struct drm_vblank_crtc *vblank;
> > + struct intel_encoder *encoder;
> > +
> > + if (!crtc->active)
> > + continue;
> > +
> > + vblank = drm_crtc_vblank_crtc(&crtc->base);
> > +
> > + if (vblank->enabled)
> > + return false;
> > +
> > + for_each_encoder_on_crtc(display->drm, &crtc->base,
> encoder)
> > + if (encoder->type != INTEL_OUTPUT_EDP ||
> > + !CAN_PSR(enc_to_intel_dp(encoder)))
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > static void hsw_activate_psr1(struct intel_dp *intel_dp) {
> > struct intel_display *display = to_intel_display(intel_dp); @@
> > -1010,7 +1086,18 @@ static void hsw_activate_psr2(struct intel_dp
> *intel_dp)
> > u32 val = EDP_PSR2_ENABLE;
> > u32 psr_val = 0;
> >
> > - val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > + /*
> > + * Wa_22019444797
> > + * TODO: Disable idle frames when vblank gets enabled while
> > + * PSR2 is enabled
> > + */
> > + if (DISPLAY_VER(dev_priv) != 20 ||
> > + !intel_dp->psr.is_dpkgc_configured ||
> > + intel_dp->psr.is_dc5_entry_possible)
> > + val |=
> EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > + else
> > + drm_dbg_kms(display->drm,
> > + "Wa 22019444797 requirement met PSR2 deep
> sleep disabled\n");
>
> What if this was just something like,
>
> if (!intel_dp->psr.disable_idle_frames)
> val |=
> EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
>
> And that was set where needed, and everything else was based on old/new
> crtc state.
Sure I can work on that.
>
> I'm just feeling really dumb because it's hard for me to follow what's going on
> here in this patch. Is it really this complicated?
It actually became complicated due the multiple conditions each asking us to do different actions for both
Psr1 and psr2 and each of those conditions having its own conditions for example dc5_entry_possible has its
own list of condition to end up being true
>
> >
> > if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
> > val |= EDP_SU_TRACK_ENABLE;
> > @@ -1692,6 +1779,20 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
> > crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp,
> > crtc_state); }
> >
> > +void intel_psr_compute_config_late(struct intel_crtc_state
> > +*crtc_state) {
> > + struct intel_display *display = to_intel_display(crtc_state);
> > +
> > + if (DISPLAY_VER(display) == 20) {
> > + crtc_state->is_dpkgc_configured =
> > + intel_psr_is_dpkgc_configured(display, crtc_state);
> > + crtc_state->is_dc5_entry_possible =
> > + intel_psr_is_dc5_entry_possible(display, crtc_state);
> > + crtc_state->is_wa_delayed_vblank_limit =
> > + intel_psr_wa_delayed_vblank(&crtc_state-
> >hw.adjusted_mode);
> > + }
> > +}
> > +
> > void intel_psr_get_config(struct intel_encoder *encoder,
> > struct intel_crtc_state *pipe_config) { @@ -2774,6
> +2875,22 @@
> > int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > return 0;
> > }
> >
> > +static void
> > +wa_22019444797_fill_psr_params(const struct intel_crtc_state *crtc_state,
> > + struct intel_psr *psr)
>
> Again, that's a horrible function name. This doesn't have to include the
> workaround number in any way.
>
> The rule of thumb: Say the function name aloud, as if you were discussing the
> code with someone. If it's difficult to talk about, it's probably not a good
> name.
Sure will update it and from what I can see from the comments above and below this may
altogether not be needed since we will only have one variable we need to fill and the rest can be
taken care by crtc_state itself.
>
> > +{
> > + struct intel_display *display = to_intel_display(crtc_state);
> > +
> > + if (DISPLAY_VER(display) == 20) {
>
> I think this part is independent of display version.
Okay got it.
>
> > + psr->is_dpkgc_configured =
> > + crtc_state->is_dpkgc_configured;
> > + psr->is_dc5_entry_possible =
> > + crtc_state->is_dc5_entry_possible;
> > + psr->is_wa_delayed_vblank_limit =
> > + crtc_state->is_wa_delayed_vblank_limit;
> > + }
> > +}
>
> Again, why do we need all of this duplicated? I think it only boils down to just
> one thing in struct intel_psr, unless I'm mistaken.
I think as you suggested above having one variable should suffice and that can be set here and later
On used in hsw_psr2_activate
>
> > +
> > void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> > struct intel_crtc *crtc)
> > {
> > @@ -2796,6 +2913,8 @@ void intel_psr_pre_plane_update(struct
> > intel_atomic_state *state,
> >
> > mutex_lock(&psr->lock);
> >
> > + wa_22019444797_fill_psr_params(new_crtc_state, psr);
> > +
>
> So you're filling stuff from new_crtc_state into psr.
>
> > /*
> > * Reasons to disable:
> > * - PSR disabled in new state
> > @@ -2803,6 +2922,7 @@ void intel_psr_pre_plane_update(struct
> intel_atomic_state *state,
> > * - Changing between PSR versions
> > * - Region Early Transport changing
> > * - Display WA #1136: skl, bxt
> > + * - Display WA_22019444797
> > */
> > needs_to_disable |=
> intel_crtc_needs_modeset(new_crtc_state);
> > needs_to_disable |= !new_crtc_state->has_psr; @@ -2812,6
> +2932,8 @@
> > void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> > psr->su_region_et_enabled;
> > needs_to_disable |= DISPLAY_VER(i915) < 11 &&
> > new_crtc_state->wm_level_disabled;
> > + /* TODO: Disable PSR1 when vblank gets enabled while PSR1
> is enabled */
> > + needs_to_disable |= wa_22019444797_psr1(new_crtc_state,
> psr);
>
> And then use it here. I don't get it.
>
> >
> > if (psr->enabled && needs_to_disable)
> > intel_psr_disable_locked(intel_dp);
> > @@ -2852,6 +2974,12 @@ void intel_psr_post_plane_update(struct
> intel_atomic_state *state,
> > keep_disabled |= DISPLAY_VER(display) < 11 &&
> > crtc_state->wm_level_disabled;
> >
> > + /*
> > + * Wa_22019444797
> > + * TODO: Disable PSR1 when vblank gets enabled while PSR1
> is enabled
> > + */
> > + keep_disabled |= wa_22019444797_psr1(crtc_state, psr);
>
> So this carries it over from pre plane update new crtc state via psr... but it's all
> very confusing.
I think this will be solved with the suggestion you made above in the next revision
Regards,
Suraj Kandpal
>
> BR,
> Jani.
>
> > +
> > if (!psr->enabled && !keep_disabled)
> > intel_psr_enable_locked(intel_dp, crtc_state);
> > else if (psr->enabled && !crtc_state->wm_level_disabled) diff
> --git
> > a/drivers/gpu/drm/i915/display/intel_psr.h
> > b/drivers/gpu/drm/i915/display/intel_psr.h
> > index 956be263c09e..0923a2f74901 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > @@ -47,6 +47,7 @@ void intel_psr_init(struct intel_dp *intel_dp);
> > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > struct intel_crtc_state *crtc_state,
> > struct drm_connector_state *conn_state);
> > +void intel_psr_compute_config_late(struct intel_crtc_state
> > +*crtc_state);
> > void intel_psr_get_config(struct intel_encoder *encoder,
> > struct intel_crtc_state *pipe_config); void
> > intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH] drm/i915/psr: Implement WA to help reach PC10
@ 2024-11-06 9:00 Suraj Kandpal
0 siblings, 0 replies; 13+ messages in thread
From: Suraj Kandpal @ 2024-11-06 9:00 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: jouni.hogander, jani.nikula, Suraj Kandpal
To reach PC10 when PKG_C_LATENCY is configure we must do the following
things
1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
2) Allow PSR2 deep sleep when DC5 can be entered
3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
not happening.
--v2
-Add debug prints
--v3
-use crtc as variable name for intel_crtc [Jani]
-use encoder as variable name for intel_encoder [Jani]
-No changes in intel_dp in compute_config_late [Jani]
--v4
-Remove "check" from naming [Jani]
-Remove intel_encoder variable which is not necessary in
compute_config_late
--v5
-Make readable function names [Jani]
-No need to duplicate all variables into intel_psr [Jani]
-Optimize dpkgc_configured function [Jani]
-Use crtc_state only to decide if wa is needed for PSR1 [Jani]
WA: 22019444797
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
.../drm/i915/display/intel_display_types.h | 4 +
drivers/gpu/drm/i915/display/intel_psr.c | 111 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_psr.h | 1 +
4 files changed, 118 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 49b5cc01ce40..61b7dd6a9dc4 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4414,6 +4414,9 @@ static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
}
+ if (intel_encoder_is_dp(encoder))
+ intel_psr_compute_config_late(crtc_state);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ff6eb93337e0..24b95268f42d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1089,6 +1089,9 @@ struct intel_crtc_state {
bool req_psr2_sdp_prior_scanline;
bool has_panel_replay;
bool wm_level_disabled;
+ bool is_dpkgc_configured;
+ bool is_dc5_entry_possible;
+ bool is_wa_delayed_vblank_limit;
u32 dc3co_exitline;
u16 su_y_granularity;
@@ -1587,6 +1590,7 @@ struct intel_psr {
#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
u32 debug;
+ bool disable_idle_frames;
bool sink_support;
bool source_support;
bool enabled;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index a784c0b81556..3cb267437324 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -26,6 +26,7 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_damage_helper.h>
#include <drm/drm_debugfs.h>
+#include <drm/drm_vblank.h>
#include "i915_drv.h"
#include "i915_reg.h"
@@ -898,6 +899,78 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
return idle_frames;
}
+static bool
+intel_psr_wa_delayed_vblank(const struct drm_display_mode *adjusted_mode)
+{
+ return (adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay) >= 6;
+}
+
+/*
+ * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
+ * VRR is not enabled
+ */
+static bool intel_psr_is_dpkgc_configured(struct intel_display *display,
+ struct intel_crtc_state *crtc_state)
+{
+ return DISPLAY_VER(display) >= 20 && !crtc_state->vrr.enable;
+}
+
+static bool
+psr1_needs_wa_22019444797(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ if (DISPLAY_VER(display) == 20 && crtc_state->is_dpkgc_configured &&
+ (crtc_state->is_wa_delayed_vblank_limit || !crtc_state->is_dc5_entry_possible) &&
+ !crtc_state->has_sel_update && !crtc_state->has_panel_replay) {
+ drm_dbg_kms(display->drm,
+ "Disabling PSR1 due to wa 22019444797\n");
+ return true;
+ } else {
+ return false;
+ }
+}
+
+/*
+ * DC5 entry is only possible if vblank interrupt is disabled
+ * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
+ * enabled encoders.
+ */
+static bool
+intel_psr_is_dc5_entry_possible(struct intel_display *display,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc;
+
+ if ((display->power.domains.target_dc_state &
+ DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
+ return false;
+
+ if (!crtc_state->has_psr && !crtc_state->has_sel_update &&
+ !crtc_state->has_panel_replay)
+ return false;
+
+ for_each_intel_crtc(display->drm, crtc) {
+ struct drm_vblank_crtc *vblank;
+ struct intel_encoder *encoder;
+
+ if (!crtc->active)
+ continue;
+
+ vblank = drm_crtc_vblank_crtc(&crtc->base);
+
+ if (vblank->enabled)
+ return false;
+
+ for_each_encoder_on_crtc(display->drm, &crtc->base, encoder)
+ if (encoder->type != INTEL_OUTPUT_EDP ||
+ !CAN_PSR(enc_to_intel_dp(encoder)))
+ return false;
+ }
+
+ return true;
+}
+
static void hsw_activate_psr1(struct intel_dp *intel_dp)
{
struct intel_display *display = to_intel_display(intel_dp);
@@ -1010,7 +1083,16 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
u32 val = EDP_PSR2_ENABLE;
u32 psr_val = 0;
- val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ /*
+ * Wa_22019444797
+ * TODO: Disable idle frames when vblank gets enabled while
+ * PSR2 is enabled
+ */
+ if (!intel_dp->psr.disable_idle_frames)
+ val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ else
+ drm_dbg_kms(display->drm,
+ "Wa 22019444797 requirement met PSR2 deep sleep disabled\n");
if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
val |= EDP_SU_TRACK_ENABLE;
@@ -1692,6 +1774,20 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
}
+void intel_psr_compute_config_late(struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ if (DISPLAY_VER(display) == 20) {
+ crtc_state->is_dpkgc_configured =
+ intel_psr_is_dpkgc_configured(display, crtc_state);
+ crtc_state->is_dc5_entry_possible =
+ intel_psr_is_dc5_entry_possible(display, crtc_state);
+ crtc_state->is_wa_delayed_vblank_limit =
+ intel_psr_wa_delayed_vblank(&crtc_state->hw.adjusted_mode);
+ }
+}
+
void intel_psr_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
@@ -2796,6 +2892,10 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
mutex_lock(&psr->lock);
+ psr->disable_idle_frames = DISPLAY_VER(display) != 20 ||
+ !new_crtc_state->is_dpkgc_configured ||
+ new_crtc_state->is_dc5_entry_possible;
+
/*
* Reasons to disable:
* - PSR disabled in new state
@@ -2803,6 +2903,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
* - Changing between PSR versions
* - Region Early Transport changing
* - Display WA #1136: skl, bxt
+ * - Display WA_22019444797
*/
needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
needs_to_disable |= !new_crtc_state->has_psr;
@@ -2812,6 +2913,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
psr->su_region_et_enabled;
needs_to_disable |= DISPLAY_VER(i915) < 11 &&
new_crtc_state->wm_level_disabled;
+ /* TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled */
+ needs_to_disable |= psr1_needs_wa_22019444797(new_crtc_state);
if (psr->enabled && needs_to_disable)
intel_psr_disable_locked(intel_dp);
@@ -2852,6 +2955,12 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
keep_disabled |= DISPLAY_VER(display) < 11 &&
crtc_state->wm_level_disabled;
+ /*
+ * Wa_22019444797
+ * TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled
+ */
+ keep_disabled |= psr1_needs_wa_22019444797(crtc_state);
+
if (!psr->enabled && !keep_disabled)
intel_psr_enable_locked(intel_dp, crtc_state);
else if (psr->enabled && !crtc_state->wm_level_disabled)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 956be263c09e..0923a2f74901 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -47,6 +47,7 @@ void intel_psr_init(struct intel_dp *intel_dp);
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state);
+void intel_psr_compute_config_late(struct intel_crtc_state *crtc_state);
void intel_psr_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
end of thread, other threads:[~2024-11-06 9:02 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-11-04 9:12 [PATCH] drm/i915/psr: Implement WA to help reach PC10 Suraj Kandpal
2024-11-04 14:18 ` Jani Nikula
2024-11-06 8:18 ` Kandpal, Suraj
2024-11-04 16:13 ` ✓ Fi.CI.BAT: success for drm/i915/psr: Implement WA to help reach PC10 (rev4) Patchwork
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2024-11-06 9:00 [PATCH] drm/i915/psr: Implement WA to help reach PC10 Suraj Kandpal
2024-10-03 14:53 Suraj Kandpal
2024-10-06 16:53 ` Suraj Kandpal
2024-10-17 7:54 ` Suraj Kandpal
2024-09-09 6:32 [PATCH] drm/i915/psr: Implment " Suraj Kandpal
2024-09-20 9:12 ` [PATCH] drm/i915/psr: Implement " Suraj Kandpal
2024-09-20 11:45 ` Hogander, Jouni
2024-09-23 2:54 ` Kandpal, Suraj
2024-09-23 10:23 ` Shankar, Uma
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