* [PATCH] drm/i915/psr: Implment WA to help reach PC10
@ 2024-09-02 5:02 Suraj Kandpal
2024-09-02 6:13 ` ✗ Fi.CI.BAT: failure for " Patchwork
` (13 more replies)
0 siblings, 14 replies; 47+ messages in thread
From: Suraj Kandpal @ 2024-09-02 5:02 UTC (permalink / raw)
To: intel-gfx; +Cc: uma.shankar, jouni.hogander, Suraj Kandpal
To reach PC10 when PKG_C_LATENCY is configure we must do the following
things
1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
2) Allow PSR2 deep sleep when DC5 can be entered
3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
not happening.
--v2
-Switch condition and do an early return [Jani]
-Do some checks in compute_config [Jani]
-Do not use register reads as a method of checking states for
DPKGC or delayed vblank [Jani]
-Use another way to see is vblank interrupts are disabled or not [Jani]
--v3
-Use has_psr to check if psr can be enabled or not for dc5_entry cond
[Uma]
-Move the dc5 entry computation to psr_compute_config [Jouni]
-No need to change sequence of enabled and activate,
so dont make hsw_psr1_activate return anything [Jouni]
-Use has_psr to stop psr1 activation [Jouni]
-Use lineage no. in WA
-Add the display ver restrictions for WA
WA: 22019444797
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
.../drm/i915/display/intel_display_types.h | 2 +
drivers/gpu/drm/i915/display/intel_psr.c | 96 ++++++++++++++++++-
2 files changed, 97 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 868ff8976ed9..5395c1ecde7f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1717,6 +1717,8 @@ struct intel_psr {
bool sink_support;
bool source_support;
bool enabled;
+ bool is_dpkgc_configured;
+ bool is_dc5_entry_possible;
bool paused;
enum pipe pipe;
enum transcoder transcoder;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 257526362b39..1faec76eac32 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -870,6 +870,69 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
return idle_frames;
}
+static bool intel_psr_check_delayed_vblank_limit(struct intel_crtc_state *crtc_state)
+{
+ struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+
+ return (adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay) >= 6;
+}
+
+/*
+ * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
+ * VRR is not enabled
+ */
+static bool intel_psr_is_dpkgc_configured(struct drm_i915_private *i915)
+{
+ struct intel_crtc *intel_crtc;
+
+ if (DISPLAY_VER(i915) < 20)
+ return false;
+
+ for_each_intel_crtc(&i915->drm, intel_crtc) {
+ struct intel_crtc_state *crtc_state;
+
+ if (!intel_crtc->active)
+ continue;
+
+ crtc_state = intel_crtc->config;
+
+ if (crtc_state->vrr.enable)
+ return false;
+ }
+
+ return true;
+}
+
+/*
+ * DC5 entry is only possible if vblank interrupt is disabled
+ * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
+ * enabled encoders.
+ */
+static bool
+intel_psr_is_dc5_entry_possible(struct drm_i915_private *i915,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *intel_crtc;
+
+ if (!(crtc_state->has_psr || crtc_state->has_sel_update))
+ return false;
+
+ for_each_intel_crtc(&i915->drm, intel_crtc) {
+ struct drm_crtc *crtc = &intel_crtc->base;
+ struct drm_vblank_crtc *vblank;
+
+ if (!intel_crtc->active)
+ continue;
+
+ vblank = drm_crtc_vblank_crtc(crtc);
+
+ if (vblank->enabled)
+ return false;
+ }
+
+ return true;
+}
+
static void hsw_activate_psr1(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -980,7 +1043,11 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
u32 val = EDP_PSR2_ENABLE;
u32 psr_val = 0;
- val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ /* Wa_22019444797 */
+ if (DISPLAY_VER(dev_priv) != 20 ||
+ (intel_dp->psr.is_dpkgc_configured &&
+ intel_dp->psr.is_dc5_entry_possible))
+ val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
if (DISPLAY_VER(dev_priv) < 14 && !IS_ALDERLAKE_P(dev_priv))
val |= EDP_SU_TRACK_ENABLE;
@@ -1595,6 +1662,32 @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
return true;
}
+static void wa_22019444797(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ if (DISPLAY_VER(i915) != 20)
+ return;
+
+ intel_dp->psr.is_dpkgc_configured =
+ intel_psr_is_dpkgc_configured(i915);
+ intel_dp->psr.is_dc5_entry_possible =
+ intel_psr_is_dc5_entry_possible(i915, crtc_state);
+
+ /* PSR2 not handled here. Wa not needed for Panel Replay */
+ if (crtc_state->has_sel_update || crtc_state->has_panel_replay)
+ return;
+
+ if (intel_dp->psr.is_dpkgc_configured &&
+ (intel_psr_check_delayed_vblank_limit(crtc_state) ||
+ intel_dp->psr.is_dc5_entry_possible)) {
+ drm_dbg_kms(&i915->drm,
+ "PSR1 not enabled as it doesn't meet requirements of WA: 22019444797\n");
+ crtc_state->has_psr = false;
+ }
+}
+
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
@@ -1641,6 +1734,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
return;
crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
+ wa_22019444797(intel_dp, crtc_state);
}
void intel_psr_get_config(struct intel_encoder *encoder,
--
2.43.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/psr: Implment WA to help reach PC10
2024-09-02 5:02 [PATCH] drm/i915/psr: Implment WA to help reach PC10 Suraj Kandpal
@ 2024-09-02 6:13 ` Patchwork
2024-09-02 9:37 ` [PATCH] " Hogander, Jouni
` (12 subsequent siblings)
13 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2024-09-02 6:13 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4072 bytes --]
== Series Details ==
Series: drm/i915/psr: Implment WA to help reach PC10
URL : https://patchwork.freedesktop.org/series/138065/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15338 -> Patchwork_138065v1
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_138065v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_138065v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v1/index.html
Participating hosts (39 -> 38)
------------------------------
Additional (1): bat-arlh-3
Missing (2): fi-snb-2520m fi-bsw-n3050
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_138065v1:
### IGT changes ###
#### Possible regressions ####
* igt@core_auth@basic-auth:
- bat-adlp-9: [PASS][1] -> [DMESG-WARN][2] +51 other tests dmesg-warn
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15338/bat-adlp-9/igt@core_auth@basic-auth.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v1/bat-adlp-9/igt@core_auth@basic-auth.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_flip@basic-plain-flip@d-edp1:
- {bat-arlh-3}: NOTRUN -> [INCOMPLETE][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v1/bat-arlh-3/igt@kms_flip@basic-plain-flip@d-edp1.html
Known issues
------------
Here are the changes found in Patchwork_138065v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gt_mocs:
- bat-adlm-1: [PASS][4] -> [INCOMPLETE][5] ([i915#9413])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15338/bat-adlm-1/igt@i915_selftest@live@gt_mocs.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v1/bat-adlm-1/igt@i915_selftest@live@gt_mocs.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- bat-arls-2: [DMESG-WARN][6] ([i915#11349]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15338/bat-arls-2/igt@i915_selftest@live@hangcheck.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v1/bat-arls-2/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10196
[i915#11343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11343
[i915#11346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11346
[i915#11349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11349
[i915#11666]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11666
[i915#11724]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11724
[i915#11725]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11725
[i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
[i915#9413]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9413
[i915#9886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9886
Build changes
-------------
* Linux: CI_DRM_15338 -> Patchwork_138065v1
CI-20190529: 20190529
CI_DRM_15338: c689a348137cb6f8934a9be49438bafe413b97d5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8000: fba44baafa5d79b6eed52fa24234781e8e47beb8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_138065v1: c689a348137cb6f8934a9be49438bafe413b97d5 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v1/index.html
[-- Attachment #2: Type: text/html, Size: 4158 bytes --]
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-02 5:02 [PATCH] drm/i915/psr: Implment WA to help reach PC10 Suraj Kandpal
2024-09-02 6:13 ` ✗ Fi.CI.BAT: failure for " Patchwork
@ 2024-09-02 9:37 ` Hogander, Jouni
2024-09-02 10:01 ` Kandpal, Suraj
2024-09-02 10:02 ` Hogander, Jouni
2024-09-03 8:24 ` Suraj Kandpal
` (11 subsequent siblings)
13 siblings, 2 replies; 47+ messages in thread
From: Hogander, Jouni @ 2024-09-02 9:37 UTC (permalink / raw)
To: Kandpal, Suraj, intel-gfx@lists.freedesktop.org; +Cc: Shankar, Uma
On Mon, 2024-09-02 at 10:32 +0530, Suraj Kandpal wrote:
> To reach PC10 when PKG_C_LATENCY is configure we must do the
> following
> things
> 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> entered
> 2) Allow PSR2 deep sleep when DC5 can be entered
> 3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
> eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
> not happening.
>
> --v2
> -Switch condition and do an early return [Jani]
> -Do some checks in compute_config [Jani]
> -Do not use register reads as a method of checking states for
> DPKGC or delayed vblank [Jani]
> -Use another way to see is vblank interrupts are disabled or not
> [Jani]
>
> --v3
> -Use has_psr to check if psr can be enabled or not for dc5_entry cond
> [Uma]
> -Move the dc5 entry computation to psr_compute_config [Jouni]
> -No need to change sequence of enabled and activate,
> so dont make hsw_psr1_activate return anything [Jouni]
> -Use has_psr to stop psr1 activation [Jouni]
> -Use lineage no. in WA
> -Add the display ver restrictions for WA
>
> WA: 22019444797
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 2 +
> drivers/gpu/drm/i915/display/intel_psr.c | 96
> ++++++++++++++++++-
> 2 files changed, 97 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 868ff8976ed9..5395c1ecde7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1717,6 +1717,8 @@ struct intel_psr {
> bool sink_support;
> bool source_support;
> bool enabled;
> + bool is_dpkgc_configured;
> + bool is_dc5_entry_possible;
> bool paused;
> enum pipe pipe;
> enum transcoder transcoder;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 257526362b39..1faec76eac32 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -870,6 +870,69 @@ static u8 psr_compute_idle_frames(struct
> intel_dp *intel_dp)
> return idle_frames;
> }
>
> +static bool intel_psr_check_delayed_vblank_limit(struct
> intel_crtc_state *crtc_state)
You could add some context here in the name. This is somehow telling
it's some generic delayed vblank limit while it is actually limit for
this workaround.
> +{
> + struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
> +
> + return (adjusted_mode->crtc_vblank_start - adjusted_mode-
> >crtc_vdisplay) >= 6;
> +}
> +
> +/*
> + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> + * VRR is not enabled
> + */
> +static bool intel_psr_is_dpkgc_configured(struct drm_i915_private
> *i915)
> +{
> + struct intel_crtc *intel_crtc;
> +
> + if (DISPLAY_VER(i915) < 20)
> + return false;
> +
> + for_each_intel_crtc(&i915->drm, intel_crtc) {
> + struct intel_crtc_state *crtc_state;
> +
> + if (!intel_crtc->active)
> + continue;
> +
> + crtc_state = intel_crtc->config;
> +
> + if (crtc_state->vrr.enable)
> + return false;
> + }
> +
> + return true;
> +}
> +
> +/*
> + * DC5 entry is only possible if vblank interrupt is disabled
> + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> + * enabled encoders.
> + */
> +static bool
> +intel_psr_is_dc5_entry_possible(struct drm_i915_private *i915,
> + struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *intel_crtc;
> +
> + if (!(crtc_state->has_psr || crtc_state->has_sel_update))
> + return false;
Currently this is not returning for DP2.1 PR. This would better match
with comment above:
if (!crtc_state->has_psr || !intel_dp_is_edp(intel_dp))
return false;
Still "_all_ enabled encoders" is not handled...
BR,
Jouni Högander
> +
> + for_each_intel_crtc(&i915->drm, intel_crtc) {
> + struct drm_crtc *crtc = &intel_crtc->base;
> + struct drm_vblank_crtc *vblank;
> +
> + if (!intel_crtc->active)
> + continue;
> +
> + vblank = drm_crtc_vblank_crtc(crtc);
> +
> + if (vblank->enabled)
> + return false;
> + }
> +
> + return true;
> +}
> +
> static void hsw_activate_psr1(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> @@ -980,7 +1043,11 @@ static void hsw_activate_psr2(struct intel_dp
> *intel_dp)
> u32 val = EDP_PSR2_ENABLE;
> u32 psr_val = 0;
>
> - val |=
> EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> + /* Wa_22019444797 */
> + if (DISPLAY_VER(dev_priv) != 20 ||
> + (intel_dp->psr.is_dpkgc_configured &&
> + intel_dp->psr.is_dc5_entry_possible))
> + val |=
> EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
>
> if (DISPLAY_VER(dev_priv) < 14 && !IS_ALDERLAKE_P(dev_priv))
> val |= EDP_SU_TRACK_ENABLE;
> @@ -1595,6 +1662,32 @@ _panel_replay_compute_config(struct intel_dp
> *intel_dp,
> return true;
> }
>
> +static void wa_22019444797(struct intel_dp *intel_dp,
> + struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +
> + if (DISPLAY_VER(i915) != 20)
> + return;
> +
> + intel_dp->psr.is_dpkgc_configured =
> + intel_psr_is_dpkgc_configured(i915);
> + intel_dp->psr.is_dc5_entry_possible =
> + intel_psr_is_dc5_entry_possible(i915, crtc_state);
> +
> + /* PSR2 not handled here. Wa not needed for Panel Replay */
> + if (crtc_state->has_sel_update || crtc_state-
> >has_panel_replay)
> + return;
> +
> + if (intel_dp->psr.is_dpkgc_configured &&
> + (intel_psr_check_delayed_vblank_limit(crtc_state) ||
> + intel_dp->psr.is_dc5_entry_possible)) {
> + drm_dbg_kms(&i915->drm,
> + "PSR1 not enabled as it doesn't meet
> requirements of WA: 22019444797\n");
> + crtc_state->has_psr = false;
> + }
> +}
> +
> void intel_psr_compute_config(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state,
> struct drm_connector_state *conn_state)
> @@ -1641,6 +1734,7 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
> return;
>
> crtc_state->has_sel_update =
> intel_sel_update_config_valid(intel_dp, crtc_state);
> + wa_22019444797(intel_dp, crtc_state);
> }
>
> void intel_psr_get_config(struct intel_encoder *encoder,
^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-02 9:37 ` [PATCH] " Hogander, Jouni
@ 2024-09-02 10:01 ` Kandpal, Suraj
2024-09-03 7:42 ` Hogander, Jouni
2024-09-02 10:02 ` Hogander, Jouni
1 sibling, 1 reply; 47+ messages in thread
From: Kandpal, Suraj @ 2024-09-02 10:01 UTC (permalink / raw)
To: Hogander, Jouni, intel-gfx@lists.freedesktop.org; +Cc: Shankar, Uma
> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Monday, September 2, 2024 3:07 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
>
> On Mon, 2024-09-02 at 10:32 +0530, Suraj Kandpal wrote:
> > To reach PC10 when PKG_C_LATENCY is configure we must do the
> following
> > things
> > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> > entered
> > 2) Allow PSR2 deep sleep when DC5 can be entered
> > 3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
> > eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
> > not happening.
> >
> > --v2
> > -Switch condition and do an early return [Jani] -Do some checks in
> > compute_config [Jani] -Do not use register reads as a method of
> > checking states for DPKGC or delayed vblank [Jani] -Use another way to
> > see is vblank interrupts are disabled or not [Jani]
> >
> > --v3
> > -Use has_psr to check if psr can be enabled or not for dc5_entry cond
> > [Uma] -Move the dc5 entry computation to psr_compute_config [Jouni]
> > -No need to change sequence of enabled and activate, so dont make
> > hsw_psr1_activate return anything [Jouni] -Use has_psr to stop psr1
> > activation [Jouni] -Use lineage no. in WA -Add the display ver
> > restrictions for WA
> >
> > WA: 22019444797
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > .../drm/i915/display/intel_display_types.h | 2 +
> > drivers/gpu/drm/i915/display/intel_psr.c | 96
> > ++++++++++++++++++-
> > 2 files changed, 97 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 868ff8976ed9..5395c1ecde7f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1717,6 +1717,8 @@ struct intel_psr {
> > bool sink_support;
> > bool source_support;
> > bool enabled;
> > + bool is_dpkgc_configured;
> > + bool is_dc5_entry_possible;
> > bool paused;
> > enum pipe pipe;
> > enum transcoder transcoder;
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 257526362b39..1faec76eac32 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -870,6 +870,69 @@ static u8 psr_compute_idle_frames(struct
> intel_dp
> > *intel_dp)
> > return idle_frames;
> > }
> >
> > +static bool intel_psr_check_delayed_vblank_limit(struct
> > intel_crtc_state *crtc_state)
>
> You could add some context here in the name. This is somehow telling it's
> some generic delayed vblank limit while it is actually limit for this
> workaround.
Sure will fix in next revision
How about something like check_wa_delayed_vblank()
>
> > +{
> > + struct drm_display_mode *adjusted_mode = &crtc_state-
> > >hw.adjusted_mode;
> > +
> > + return (adjusted_mode->crtc_vblank_start - adjusted_mode-
> > >crtc_vdisplay) >= 6;
> > +}
> > +
> > +/*
> > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> > + * VRR is not enabled
> > + */
> > +static bool intel_psr_is_dpkgc_configured(struct drm_i915_private
> > *i915)
> > +{
> > + struct intel_crtc *intel_crtc;
> > +
> > + if (DISPLAY_VER(i915) < 20)
> > + return false;
> > +
> > + for_each_intel_crtc(&i915->drm, intel_crtc) {
> > + struct intel_crtc_state *crtc_state;
> > +
> > + if (!intel_crtc->active)
> > + continue;
> > +
> > + crtc_state = intel_crtc->config;
> > +
> > + if (crtc_state->vrr.enable)
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > +/*
> > + * DC5 entry is only possible if vblank interrupt is disabled
> > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> > + * enabled encoders.
> > + */
> > +static bool
> > +intel_psr_is_dc5_entry_possible(struct drm_i915_private *i915,
> > + struct intel_crtc_state *crtc_state) {
> > + struct intel_crtc *intel_crtc;
> > +
> > + if (!(crtc_state->has_psr || crtc_state->has_sel_update))
> > + return false;
>
> Currently this is not returning for DP2.1 PR. This would better match with
> comment above:
>
> if (!crtc_state->has_psr || !intel_dp_is_edp(intel_dp))
> return false;
>
> Still "_all_ enabled encoders" is not handled...
>
How about in the below loop I add a encoder loop that checks if intel_dp_is_edp
If the encoder is active and the psr check is taken care of by checking crtc_state->has_psr ?
Previously I used to check if psr->enabled but since this is now called in psr compute config I only have has_psr to check
If psr can be enabled on that encoder .
Regards,
Suraj Kandpal
> BR,
>
> Jouni Högander
>
> > +
> > + for_each_intel_crtc(&i915->drm, intel_crtc) {
> > + struct drm_crtc *crtc = &intel_crtc->base;
> > + struct drm_vblank_crtc *vblank;
> > +
> > + if (!intel_crtc->active)
> > + continue;
> > +
> > + vblank = drm_crtc_vblank_crtc(crtc);
> > +
> > + if (vblank->enabled)
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > static void hsw_activate_psr1(struct intel_dp *intel_dp)
> > {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@
> > -980,7 +1043,11 @@ static void hsw_activate_psr2(struct intel_dp
> > *intel_dp)
> > u32 val = EDP_PSR2_ENABLE;
> > u32 psr_val = 0;
> >
> > - val |=
> > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > + /* Wa_22019444797 */
> > + if (DISPLAY_VER(dev_priv) != 20 ||
> > + (intel_dp->psr.is_dpkgc_configured &&
> > + intel_dp->psr.is_dc5_entry_possible))
> > + val |=
> > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> >
> > if (DISPLAY_VER(dev_priv) < 14 && !IS_ALDERLAKE_P(dev_priv))
> > val |= EDP_SU_TRACK_ENABLE; @@ -1595,6 +1662,32 @@
> > _panel_replay_compute_config(struct intel_dp *intel_dp,
> > return true;
> > }
> >
> > +static void wa_22019444797(struct intel_dp *intel_dp,
> > + struct intel_crtc_state *crtc_state) {
> > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > +
> > + if (DISPLAY_VER(i915) != 20)
> > + return;
> > +
> > + intel_dp->psr.is_dpkgc_configured =
> > + intel_psr_is_dpkgc_configured(i915);
> > + intel_dp->psr.is_dc5_entry_possible =
> > + intel_psr_is_dc5_entry_possible(i915, crtc_state);
> > +
> > + /* PSR2 not handled here. Wa not needed for Panel Replay */
> > + if (crtc_state->has_sel_update || crtc_state-
> > >has_panel_replay)
> > + return;
> > +
> > + if (intel_dp->psr.is_dpkgc_configured &&
> > + (intel_psr_check_delayed_vblank_limit(crtc_state) ||
> > + intel_dp->psr.is_dc5_entry_possible)) {
> > + drm_dbg_kms(&i915->drm,
> > + "PSR1 not enabled as it doesn't meet
> > requirements of WA: 22019444797\n");
> > + crtc_state->has_psr = false;
> > + }
> > +}
> > +
> > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > struct intel_crtc_state *crtc_state,
> > struct drm_connector_state *conn_state)
> > @@ -1641,6 +1734,7 @@ void intel_psr_compute_config(struct intel_dp
> > *intel_dp,
> > return;
> >
> > crtc_state->has_sel_update =
> > intel_sel_update_config_valid(intel_dp, crtc_state);
> > + wa_22019444797(intel_dp, crtc_state);
> > }
> >
> > void intel_psr_get_config(struct intel_encoder *encoder,
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-02 9:37 ` [PATCH] " Hogander, Jouni
2024-09-02 10:01 ` Kandpal, Suraj
@ 2024-09-02 10:02 ` Hogander, Jouni
2024-09-02 10:14 ` Kandpal, Suraj
1 sibling, 1 reply; 47+ messages in thread
From: Hogander, Jouni @ 2024-09-02 10:02 UTC (permalink / raw)
To: Kandpal, Suraj, intel-gfx@lists.freedesktop.org; +Cc: Shankar, Uma
On Mon, 2024-09-02 at 12:37 +0300, Hogander, Jouni wrote:
> On Mon, 2024-09-02 at 10:32 +0530, Suraj Kandpal wrote:
> > To reach PC10 when PKG_C_LATENCY is configure we must do the
> > following
> > things
> > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> > entered
> > 2) Allow PSR2 deep sleep when DC5 can be entered
> > 3) DC5 can be entered when all transocoder have either PSR1, PSR2
> > or
> > eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes
> > are
> > not happening.
> >
> > --v2
> > -Switch condition and do an early return [Jani]
> > -Do some checks in compute_config [Jani]
> > -Do not use register reads as a method of checking states for
> > DPKGC or delayed vblank [Jani]
> > -Use another way to see is vblank interrupts are disabled or not
> > [Jani]
> >
> > --v3
> > -Use has_psr to check if psr can be enabled or not for dc5_entry
> > cond
> > [Uma]
> > -Move the dc5 entry computation to psr_compute_config [Jouni]
> > -No need to change sequence of enabled and activate,
> > so dont make hsw_psr1_activate return anything [Jouni]
> > -Use has_psr to stop psr1 activation [Jouni]
> > -Use lineage no. in WA
> > -Add the display ver restrictions for WA
> >
> > WA: 22019444797
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > .../drm/i915/display/intel_display_types.h | 2 +
> > drivers/gpu/drm/i915/display/intel_psr.c | 96
> > ++++++++++++++++++-
> > 2 files changed, 97 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 868ff8976ed9..5395c1ecde7f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1717,6 +1717,8 @@ struct intel_psr {
> > bool sink_support;
> > bool source_support;
> > bool enabled;
> > + bool is_dpkgc_configured;
> > + bool is_dc5_entry_possible;
> > bool paused;
> > enum pipe pipe;
> > enum transcoder transcoder;
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 257526362b39..1faec76eac32 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -870,6 +870,69 @@ static u8 psr_compute_idle_frames(struct
> > intel_dp *intel_dp)
> > return idle_frames;
> > }
> >
> > +static bool intel_psr_check_delayed_vblank_limit(struct
> > intel_crtc_state *crtc_state)
>
> You could add some context here in the name. This is somehow telling
> it's some generic delayed vblank limit while it is actually limit for
> this workaround.
>
> > +{
> > + struct drm_display_mode *adjusted_mode = &crtc_state-
> > > hw.adjusted_mode;
> > +
> > + return (adjusted_mode->crtc_vblank_start - adjusted_mode-
> > > crtc_vdisplay) >= 6;
> > +}
> > +
> > +/*
> > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> > + * VRR is not enabled
> > + */
> > +static bool intel_psr_is_dpkgc_configured(struct drm_i915_private
> > *i915)
> > +{
> > + struct intel_crtc *intel_crtc;
> > +
> > + if (DISPLAY_VER(i915) < 20)
> > + return false;
> > +
> > + for_each_intel_crtc(&i915->drm, intel_crtc) {
> > + struct intel_crtc_state *crtc_state;
> > +
> > + if (!intel_crtc->active)
> > + continue;
> > +
> > + crtc_state = intel_crtc->config;
> > +
> > + if (crtc_state->vrr.enable)
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > +/*
> > + * DC5 entry is only possible if vblank interrupt is disabled
> > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> > + * enabled encoders.
> > + */
> > +static bool
> > +intel_psr_is_dc5_entry_possible(struct drm_i915_private *i915,
> > + struct intel_crtc_state
> > *crtc_state)
> > +{
> > + struct intel_crtc *intel_crtc;
> > +
> > + if (!(crtc_state->has_psr || crtc_state->has_sel_update))
> > + return false;
>
> Currently this is not returning for DP2.1 PR. This would better match
> with comment above:
>
> if (!crtc_state->has_psr || !intel_dp_is_edp(intel_dp))
> return false;
>
> Still "_all_ enabled encoders" is not handled...
>
> BR,
>
> Jouni Högander
>
> > +
> > + for_each_intel_crtc(&i915->drm, intel_crtc) {
> > + struct drm_crtc *crtc = &intel_crtc->base;
> > + struct drm_vblank_crtc *vblank;
> > +
> > + if (!intel_crtc->active)
> > + continue;
> > +
> > + vblank = drm_crtc_vblank_crtc(crtc);
> > +
> > + if (vblank->enabled)
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > static void hsw_activate_psr1(struct intel_dp *intel_dp)
> > {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > @@ -980,7 +1043,11 @@ static void hsw_activate_psr2(struct intel_dp
> > *intel_dp)
> > u32 val = EDP_PSR2_ENABLE;
> > u32 psr_val = 0;
> >
> > - val |=
> > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > + /* Wa_22019444797 */
> > + if (DISPLAY_VER(dev_priv) != 20 ||
I think this is wrong. It will not configure idle frames for display
version other than 20.
BR,
Jouni Högander
> > + (intel_dp->psr.is_dpkgc_configured &&
> > + intel_dp->psr.is_dc5_entry_possible))
> > + val |=
> > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> >
> > if (DISPLAY_VER(dev_priv) < 14 &&
> > !IS_ALDERLAKE_P(dev_priv))
> > val |= EDP_SU_TRACK_ENABLE;
> > @@ -1595,6 +1662,32 @@ _panel_replay_compute_config(struct intel_dp
> > *intel_dp,
> > return true;
> > }
> >
> > +static void wa_22019444797(struct intel_dp *intel_dp,
> > + struct intel_crtc_state *crtc_state)
> > +{
> > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > +
> > + if (DISPLAY_VER(i915) != 20)
> > + return;
> > +
> > + intel_dp->psr.is_dpkgc_configured =
> > + intel_psr_is_dpkgc_configured(i915);
> > + intel_dp->psr.is_dc5_entry_possible =
> > + intel_psr_is_dc5_entry_possible(i915, crtc_state);
> > +
> > + /* PSR2 not handled here. Wa not needed for Panel Replay */
> > + if (crtc_state->has_sel_update || crtc_state-
> > > has_panel_replay)
> > + return;
> > +
> > + if (intel_dp->psr.is_dpkgc_configured &&
> > + (intel_psr_check_delayed_vblank_limit(crtc_state) ||
> > + intel_dp->psr.is_dc5_entry_possible)) {
> > + drm_dbg_kms(&i915->drm,
> > + "PSR1 not enabled as it doesn't meet
> > requirements of WA: 22019444797\n");
> > + crtc_state->has_psr = false;
> > + }
> > +}
> > +
> > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > struct intel_crtc_state *crtc_state,
> > struct drm_connector_state
> > *conn_state)
> > @@ -1641,6 +1734,7 @@ void intel_psr_compute_config(struct intel_dp
> > *intel_dp,
> > return;
> >
> > crtc_state->has_sel_update =
> > intel_sel_update_config_valid(intel_dp, crtc_state);
> > + wa_22019444797(intel_dp, crtc_state);
> > }
> >
> > void intel_psr_get_config(struct intel_encoder *encoder,
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-02 10:02 ` Hogander, Jouni
@ 2024-09-02 10:14 ` Kandpal, Suraj
2024-09-02 11:02 ` Hogander, Jouni
0 siblings, 1 reply; 47+ messages in thread
From: Kandpal, Suraj @ 2024-09-02 10:14 UTC (permalink / raw)
To: Hogander, Jouni, intel-gfx@lists.freedesktop.org; +Cc: Shankar, Uma
> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Monday, September 2, 2024 3:32 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
>
> On Mon, 2024-09-02 at 12:37 +0300, Hogander, Jouni wrote:
> > On Mon, 2024-09-02 at 10:32 +0530, Suraj Kandpal wrote:
> > > To reach PC10 when PKG_C_LATENCY is configure we must do the
> > > following things
> > > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> > > entered
> > > 2) Allow PSR2 deep sleep when DC5 can be entered
> > > 3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
> > > eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
> > > not happening.
> > >
> > > --v2
> > > -Switch condition and do an early return [Jani] -Do some checks in
> > > compute_config [Jani] -Do not use register reads as a method of
> > > checking states for DPKGC or delayed vblank [Jani] -Use another way
> > > to see is vblank interrupts are disabled or not [Jani]
> > >
> > > --v3
> > > -Use has_psr to check if psr can be enabled or not for dc5_entry
> > > cond [Uma] -Move the dc5 entry computation to psr_compute_config
> > > [Jouni] -No need to change sequence of enabled and activate, so dont
> > > make hsw_psr1_activate return anything [Jouni] -Use has_psr to stop
> > > psr1 activation [Jouni] -Use lineage no. in WA -Add the display ver
> > > restrictions for WA
> > >
> > > WA: 22019444797
> > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > ---
> > > .../drm/i915/display/intel_display_types.h | 2 +
> > > drivers/gpu/drm/i915/display/intel_psr.c | 96
> > > ++++++++++++++++++-
> > > 2 files changed, 97 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 868ff8976ed9..5395c1ecde7f 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -1717,6 +1717,8 @@ struct intel_psr {
> > > bool sink_support;
> > > bool source_support;
> > > bool enabled;
> > > + bool is_dpkgc_configured;
> > > + bool is_dc5_entry_possible;
> > > bool paused;
> > > enum pipe pipe;
> > > enum transcoder transcoder;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 257526362b39..1faec76eac32 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -870,6 +870,69 @@ static u8 psr_compute_idle_frames(struct
> > > intel_dp *intel_dp)
> > > return idle_frames;
> > > }
> > >
> > > +static bool intel_psr_check_delayed_vblank_limit(struct
> > > intel_crtc_state *crtc_state)
> >
> > You could add some context here in the name. This is somehow telling
> > it's some generic delayed vblank limit while it is actually limit for
> > this workaround.
> >
> > > +{
> > > + struct drm_display_mode *adjusted_mode = &crtc_state-
> > > > hw.adjusted_mode;
> > > +
> > > + return (adjusted_mode->crtc_vblank_start - adjusted_mode-
> > > > crtc_vdisplay) >= 6;
> > > +}
> > > +
> > > +/*
> > > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> > > + * VRR is not enabled
> > > + */
> > > +static bool intel_psr_is_dpkgc_configured(struct drm_i915_private
> > > *i915)
> > > +{
> > > + struct intel_crtc *intel_crtc;
> > > +
> > > + if (DISPLAY_VER(i915) < 20)
> > > + return false;
> > > +
> > > + for_each_intel_crtc(&i915->drm, intel_crtc) {
> > > + struct intel_crtc_state *crtc_state;
> > > +
> > > + if (!intel_crtc->active)
> > > + continue;
> > > +
> > > + crtc_state = intel_crtc->config;
> > > +
> > > + if (crtc_state->vrr.enable)
> > > + return false;
> > > + }
> > > +
> > > + return true;
> > > +}
> > > +
> > > +/*
> > > + * DC5 entry is only possible if vblank interrupt is disabled
> > > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> > > + * enabled encoders.
> > > + */
> > > +static bool
> > > +intel_psr_is_dc5_entry_possible(struct drm_i915_private *i915,
> > > + struct intel_crtc_state
> > > *crtc_state)
> > > +{
> > > + struct intel_crtc *intel_crtc;
> > > +
> > > + if (!(crtc_state->has_psr || crtc_state->has_sel_update))
> > > + return false;
> >
> > Currently this is not returning for DP2.1 PR. This would better match
> > with comment above:
> >
> > if (!crtc_state->has_psr || !intel_dp_is_edp(intel_dp))
> > return false;
> >
> > Still "_all_ enabled encoders" is not handled...
> >
> > BR,
> >
> > Jouni Högander
> >
> > > +
> > > + for_each_intel_crtc(&i915->drm, intel_crtc) {
> > > + struct drm_crtc *crtc = &intel_crtc->base;
> > > + struct drm_vblank_crtc *vblank;
> > > +
> > > + if (!intel_crtc->active)
> > > + continue;
> > > +
> > > + vblank = drm_crtc_vblank_crtc(crtc);
> > > +
> > > + if (vblank->enabled)
> > > + return false;
> > > + }
> > > +
> > > + return true;
> > > +}
> > > +
> > > static void hsw_activate_psr1(struct intel_dp *intel_dp)
> > > {
> > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@
> > > -980,7 +1043,11 @@ static void hsw_activate_psr2(struct intel_dp
> > > *intel_dp)
> > > u32 val = EDP_PSR2_ENABLE;
> > > u32 psr_val = 0;
> > >
> > > - val |=
> > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > > + /* Wa_22019444797 */
> > > + if (DISPLAY_VER(dev_priv) != 20 ||
>
> I think this is wrong. It will not configure idle frames for display version
> other than 20.
Wouldn’t this configure idle frames for all versions except 20
And if it is 20 then if dpkgc is configured and dc5 entry is possible
Only then configure idle frames
Regards,
Suraj Kandpal
>
> BR,
>
> Jouni Högander
>
> > > + (intel_dp->psr.is_dpkgc_configured &&
> > > + intel_dp->psr.is_dc5_entry_possible))
> > > + val |=
> > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > >
> > > if (DISPLAY_VER(dev_priv) < 14 &&
> > > !IS_ALDERLAKE_P(dev_priv))
> > > val |= EDP_SU_TRACK_ENABLE; @@ -1595,6 +1662,32 @@
> > > _panel_replay_compute_config(struct intel_dp *intel_dp,
> > > return true;
> > > }
> > >
> > > +static void wa_22019444797(struct intel_dp *intel_dp,
> > > + struct intel_crtc_state *crtc_state) {
> > > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > > +
> > > + if (DISPLAY_VER(i915) != 20)
> > > + return;
> > > +
> > > + intel_dp->psr.is_dpkgc_configured =
> > > + intel_psr_is_dpkgc_configured(i915);
> > > + intel_dp->psr.is_dc5_entry_possible =
> > > + intel_psr_is_dc5_entry_possible(i915, crtc_state);
> > > +
> > > + /* PSR2 not handled here. Wa not needed for Panel Replay */
> > > + if (crtc_state->has_sel_update || crtc_state-
> > > > has_panel_replay)
> > > + return;
> > > +
> > > + if (intel_dp->psr.is_dpkgc_configured &&
> > > + (intel_psr_check_delayed_vblank_limit(crtc_state) ||
> > > + intel_dp->psr.is_dc5_entry_possible)) {
> > > + drm_dbg_kms(&i915->drm,
> > > + "PSR1 not enabled as it doesn't meet
> > > requirements of WA: 22019444797\n");
> > > + crtc_state->has_psr = false;
> > > + }
> > > +}
> > > +
> > > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > > struct intel_crtc_state *crtc_state,
> > > struct drm_connector_state
> > > *conn_state)
> > > @@ -1641,6 +1734,7 @@ void intel_psr_compute_config(struct intel_dp
> > > *intel_dp,
> > > return;
> > >
> > > crtc_state->has_sel_update =
> > > intel_sel_update_config_valid(intel_dp, crtc_state);
> > > + wa_22019444797(intel_dp, crtc_state);
> > > }
> > >
> > > void intel_psr_get_config(struct intel_encoder *encoder,
> >
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-02 10:14 ` Kandpal, Suraj
@ 2024-09-02 11:02 ` Hogander, Jouni
2024-09-02 11:07 ` Kandpal, Suraj
0 siblings, 1 reply; 47+ messages in thread
From: Hogander, Jouni @ 2024-09-02 11:02 UTC (permalink / raw)
To: Kandpal, Suraj, intel-gfx@lists.freedesktop.org; +Cc: Shankar, Uma
On Mon, 2024-09-02 at 10:14 +0000, Kandpal, Suraj wrote:
>
>
> > -----Original Message-----
> > From: Hogander, Jouni <jouni.hogander@intel.com>
> > Sent: Monday, September 2, 2024 3:32 PM
> > To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> > gfx@lists.freedesktop.org
> > Cc: Shankar, Uma <uma.shankar@intel.com>
> > Subject: Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
> >
> > On Mon, 2024-09-02 at 12:37 +0300, Hogander, Jouni wrote:
> > > On Mon, 2024-09-02 at 10:32 +0530, Suraj Kandpal wrote:
> > > > To reach PC10 when PKG_C_LATENCY is configure we must do the
> > > > following things
> > > > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> > > > entered
> > > > 2) Allow PSR2 deep sleep when DC5 can be entered
> > > > 3) DC5 can be entered when all transocoder have either PSR1,
> > > > PSR2 or
> > > > eDP 1.5 PR ALPM enabled and VBI is disabled and flips and
> > > > pushes are
> > > > not happening.
> > > >
> > > > --v2
> > > > -Switch condition and do an early return [Jani] -Do some checks
> > > > in
> > > > compute_config [Jani] -Do not use register reads as a method of
> > > > checking states for DPKGC or delayed vblank [Jani] -Use another
> > > > way
> > > > to see is vblank interrupts are disabled or not [Jani]
> > > >
> > > > --v3
> > > > -Use has_psr to check if psr can be enabled or not for
> > > > dc5_entry
> > > > cond [Uma] -Move the dc5 entry computation to
> > > > psr_compute_config
> > > > [Jouni] -No need to change sequence of enabled and activate, so
> > > > dont
> > > > make hsw_psr1_activate return anything [Jouni] -Use has_psr to
> > > > stop
> > > > psr1 activation [Jouni] -Use lineage no. in WA -Add the display
> > > > ver
> > > > restrictions for WA
> > > >
> > > > WA: 22019444797
> > > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > > ---
> > > > .../drm/i915/display/intel_display_types.h | 2 +
> > > > drivers/gpu/drm/i915/display/intel_psr.c | 96
> > > > ++++++++++++++++++-
> > > > 2 files changed, 97 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > index 868ff8976ed9..5395c1ecde7f 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > @@ -1717,6 +1717,8 @@ struct intel_psr {
> > > > bool sink_support;
> > > > bool source_support;
> > > > bool enabled;
> > > > + bool is_dpkgc_configured;
> > > > + bool is_dc5_entry_possible;
> > > > bool paused;
> > > > enum pipe pipe;
> > > > enum transcoder transcoder;
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index 257526362b39..1faec76eac32 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -870,6 +870,69 @@ static u8 psr_compute_idle_frames(struct
> > > > intel_dp *intel_dp)
> > > > return idle_frames;
> > > > }
> > > >
> > > > +static bool intel_psr_check_delayed_vblank_limit(struct
> > > > intel_crtc_state *crtc_state)
> > >
> > > You could add some context here in the name. This is somehow
> > > telling
> > > it's some generic delayed vblank limit while it is actually limit
> > > for
> > > this workaround.
> > >
> > > > +{
> > > > + struct drm_display_mode *adjusted_mode = &crtc_state-
> > > > > hw.adjusted_mode;
> > > > +
> > > > + return (adjusted_mode->crtc_vblank_start -
> > > > adjusted_mode-
> > > > > crtc_vdisplay) >= 6;
> > > > +}
> > > > +
> > > > +/*
> > > > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> > > > + * VRR is not enabled
> > > > + */
> > > > +static bool intel_psr_is_dpkgc_configured(struct
> > > > drm_i915_private
> > > > *i915)
> > > > +{
> > > > + struct intel_crtc *intel_crtc;
> > > > +
> > > > + if (DISPLAY_VER(i915) < 20)
> > > > + return false;
> > > > +
> > > > + for_each_intel_crtc(&i915->drm, intel_crtc) {
> > > > + struct intel_crtc_state *crtc_state;
> > > > +
> > > > + if (!intel_crtc->active)
> > > > + continue;
> > > > +
> > > > + crtc_state = intel_crtc->config;
> > > > +
> > > > + if (crtc_state->vrr.enable)
> > > > + return false;
> > > > + }
> > > > +
> > > > + return true;
> > > > +}
> > > > +
> > > > +/*
> > > > + * DC5 entry is only possible if vblank interrupt is disabled
> > > > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> > > > + * enabled encoders.
> > > > + */
> > > > +static bool
> > > > +intel_psr_is_dc5_entry_possible(struct drm_i915_private *i915,
> > > > + struct intel_crtc_state
> > > > *crtc_state)
> > > > +{
> > > > + struct intel_crtc *intel_crtc;
> > > > +
> > > > + if (!(crtc_state->has_psr || crtc_state-
> > > > >has_sel_update))
> > > > + return false;
> > >
> > > Currently this is not returning for DP2.1 PR. This would better
> > > match
> > > with comment above:
> > >
> > > if (!crtc_state->has_psr || !intel_dp_is_edp(intel_dp))
> > > return false;
> > >
> > > Still "_all_ enabled encoders" is not handled...
> > >
> > > BR,
> > >
> > > Jouni Högander
> > >
> > > > +
> > > > + for_each_intel_crtc(&i915->drm, intel_crtc) {
> > > > + struct drm_crtc *crtc = &intel_crtc->base;
> > > > + struct drm_vblank_crtc *vblank;
> > > > +
> > > > + if (!intel_crtc->active)
> > > > + continue;
> > > > +
> > > > + vblank = drm_crtc_vblank_crtc(crtc);
> > > > +
> > > > + if (vblank->enabled)
> > > > + return false;
> > > > + }
> > > > +
> > > > + return true;
> > > > +}
> > > > +
> > > > static void hsw_activate_psr1(struct intel_dp *intel_dp)
> > > > {
> > > > struct drm_i915_private *dev_priv =
> > > > dp_to_i915(intel_dp); @@
> > > > -980,7 +1043,11 @@ static void hsw_activate_psr2(struct
> > > > intel_dp
> > > > *intel_dp)
> > > > u32 val = EDP_PSR2_ENABLE;
> > > > u32 psr_val = 0;
> > > >
> > > > - val |=
> > > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > > > + /* Wa_22019444797 */
> > > > + if (DISPLAY_VER(dev_priv) != 20 ||
> >
> > I think this is wrong. It will not configure idle frames for
> > display version
> > other than 20.
>
> Wouldn’t this configure idle frames for all versions except 20
> And if it is 20 then if dpkgc is configured and dc5 entry is possible
> Only then configure idle frames
Yes. My bad. sorry for that. This should be ok for display version !=
20. Another thing here. WA description is:
"When PKG_C_LATENCY is configured (not all 1s), enable PSR2 deep sleep
(PSR2_CTL Idle Frames != 0) only when DC5 can be entered."
How about case where PKG_C_LATENCY is not configured? Do we need to
care about it?
BR,
Jouni Högander
>
> Regards,
> Suraj Kandpal
> >
> > BR,
> >
> > Jouni Högander
> >
> > > > + (intel_dp->psr.is_dpkgc_configured &&
> > > > + intel_dp->psr.is_dc5_entry_possible))
> > > > + val |=
> > > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > > >
> > > > if (DISPLAY_VER(dev_priv) < 14 &&
> > > > !IS_ALDERLAKE_P(dev_priv))
> > > > val |= EDP_SU_TRACK_ENABLE; @@ -1595,6 +1662,32
> > > > @@
> > > > _panel_replay_compute_config(struct intel_dp *intel_dp,
> > > > return true;
> > > > }
> > > >
> > > > +static void wa_22019444797(struct intel_dp *intel_dp,
> > > > + struct intel_crtc_state *crtc_state)
> > > > {
> > > > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > > > +
> > > > + if (DISPLAY_VER(i915) != 20)
> > > > + return;
> > > > +
> > > > + intel_dp->psr.is_dpkgc_configured =
> > > > + intel_psr_is_dpkgc_configured(i915);
> > > > + intel_dp->psr.is_dc5_entry_possible =
> > > > + intel_psr_is_dc5_entry_possible(i915,
> > > > crtc_state);
> > > > +
> > > > + /* PSR2 not handled here. Wa not needed for Panel
> > > > Replay */
> > > > + if (crtc_state->has_sel_update || crtc_state-
> > > > > has_panel_replay)
> > > > + return;
> > > > +
> > > > + if (intel_dp->psr.is_dpkgc_configured &&
> > > > + (intel_psr_check_delayed_vblank_limit(crtc_state)
> > > > ||
> > > > + intel_dp->psr.is_dc5_entry_possible)) {
> > > > + drm_dbg_kms(&i915->drm,
> > > > + "PSR1 not enabled as it doesn't
> > > > meet
> > > > requirements of WA: 22019444797\n");
> > > > + crtc_state->has_psr = false;
> > > > + }
> > > > +}
> > > > +
> > > > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > > > struct intel_crtc_state
> > > > *crtc_state,
> > > > struct drm_connector_state
> > > > *conn_state)
> > > > @@ -1641,6 +1734,7 @@ void intel_psr_compute_config(struct
> > > > intel_dp
> > > > *intel_dp,
> > > > return;
> > > >
> > > > crtc_state->has_sel_update =
> > > > intel_sel_update_config_valid(intel_dp, crtc_state);
> > > > + wa_22019444797(intel_dp, crtc_state);
> > > > }
> > > >
> > > > void intel_psr_get_config(struct intel_encoder *encoder,
> > >
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-02 11:02 ` Hogander, Jouni
@ 2024-09-02 11:07 ` Kandpal, Suraj
2024-09-02 11:13 ` Hogander, Jouni
0 siblings, 1 reply; 47+ messages in thread
From: Kandpal, Suraj @ 2024-09-02 11:07 UTC (permalink / raw)
To: Hogander, Jouni, intel-gfx@lists.freedesktop.org; +Cc: Shankar, Uma
> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Monday, September 2, 2024 4:32 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
>
> On Mon, 2024-09-02 at 10:14 +0000, Kandpal, Suraj wrote:
> >
> >
> > > -----Original Message-----
> > > From: Hogander, Jouni <jouni.hogander@intel.com>
> > > Sent: Monday, September 2, 2024 3:32 PM
> > > To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> > > gfx@lists.freedesktop.org
> > > Cc: Shankar, Uma <uma.shankar@intel.com>
> > > Subject: Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
> > >
> > > On Mon, 2024-09-02 at 12:37 +0300, Hogander, Jouni wrote:
> > > > On Mon, 2024-09-02 at 10:32 +0530, Suraj Kandpal wrote:
> > > > > To reach PC10 when PKG_C_LATENCY is configure we must do the
> > > > > following things
> > > > > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> > > > > entered
> > > > > 2) Allow PSR2 deep sleep when DC5 can be entered
> > > > > 3) DC5 can be entered when all transocoder have either PSR1,
> > > > > PSR2 or
> > > > > eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes
> > > > > are not happening.
> > > > >
> > > > > --v2
> > > > > -Switch condition and do an early return [Jani] -Do some checks
> > > > > in compute_config [Jani] -Do not use register reads as a method
> > > > > of checking states for DPKGC or delayed vblank [Jani] -Use
> > > > > another way to see is vblank interrupts are disabled or not
> > > > > [Jani]
> > > > >
> > > > > --v3
> > > > > -Use has_psr to check if psr can be enabled or not for dc5_entry
> > > > > cond [Uma] -Move the dc5 entry computation to psr_compute_config
> > > > > [Jouni] -No need to change sequence of enabled and activate, so
> > > > > dont make hsw_psr1_activate return anything [Jouni] -Use has_psr
> > > > > to stop
> > > > > psr1 activation [Jouni] -Use lineage no. in WA -Add the display
> > > > > ver restrictions for WA
> > > > >
> > > > > WA: 22019444797
> > > > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > > > ---
> > > > > .../drm/i915/display/intel_display_types.h | 2 +
> > > > > drivers/gpu/drm/i915/display/intel_psr.c | 96
> > > > > ++++++++++++++++++-
> > > > > 2 files changed, 97 insertions(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > index 868ff8976ed9..5395c1ecde7f 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > @@ -1717,6 +1717,8 @@ struct intel_psr {
> > > > > bool sink_support;
> > > > > bool source_support;
> > > > > bool enabled;
> > > > > + bool is_dpkgc_configured;
> > > > > + bool is_dc5_entry_possible;
> > > > > bool paused;
> > > > > enum pipe pipe;
> > > > > enum transcoder transcoder; diff --git
> > > > > a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > index 257526362b39..1faec76eac32 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > @@ -870,6 +870,69 @@ static u8 psr_compute_idle_frames(struct
> > > > > intel_dp *intel_dp)
> > > > > return idle_frames;
> > > > > }
> > > > >
> > > > > +static bool intel_psr_check_delayed_vblank_limit(struct
> > > > > intel_crtc_state *crtc_state)
> > > >
> > > > You could add some context here in the name. This is somehow
> > > > telling it's some generic delayed vblank limit while it is
> > > > actually limit for this workaround.
> > > >
> > > > > +{
> > > > > + struct drm_display_mode *adjusted_mode = &crtc_state-
> > > > > > hw.adjusted_mode;
> > > > > +
> > > > > + return (adjusted_mode->crtc_vblank_start -
> > > > > adjusted_mode-
> > > > > > crtc_vdisplay) >= 6;
> > > > > +}
> > > > > +
> > > > > +/*
> > > > > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> > > > > + * VRR is not enabled
> > > > > + */
> > > > > +static bool intel_psr_is_dpkgc_configured(struct
> > > > > drm_i915_private
> > > > > *i915)
> > > > > +{
> > > > > + struct intel_crtc *intel_crtc;
> > > > > +
> > > > > + if (DISPLAY_VER(i915) < 20)
> > > > > + return false;
> > > > > +
> > > > > + for_each_intel_crtc(&i915->drm, intel_crtc) {
> > > > > + struct intel_crtc_state *crtc_state;
> > > > > +
> > > > > + if (!intel_crtc->active)
> > > > > + continue;
> > > > > +
> > > > > + crtc_state = intel_crtc->config;
> > > > > +
> > > > > + if (crtc_state->vrr.enable)
> > > > > + return false;
> > > > > + }
> > > > > +
> > > > > + return true;
> > > > > +}
> > > > > +
> > > > > +/*
> > > > > + * DC5 entry is only possible if vblank interrupt is disabled
> > > > > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> > > > > + * enabled encoders.
> > > > > + */
> > > > > +static bool
> > > > > +intel_psr_is_dc5_entry_possible(struct drm_i915_private *i915,
> > > > > + struct intel_crtc_state
> > > > > *crtc_state)
> > > > > +{
> > > > > + struct intel_crtc *intel_crtc;
> > > > > +
> > > > > + if (!(crtc_state->has_psr || crtc_state-
> > > > > >has_sel_update))
> > > > > + return false;
> > > >
> > > > Currently this is not returning for DP2.1 PR. This would better
> > > > match with comment above:
> > > >
> > > > if (!crtc_state->has_psr || !intel_dp_is_edp(intel_dp))
> > > > return false;
> > > >
> > > > Still "_all_ enabled encoders" is not handled...
> > > >
> > > > BR,
> > > >
> > > > Jouni Högander
> > > >
> > > > > +
> > > > > + for_each_intel_crtc(&i915->drm, intel_crtc) {
> > > > > + struct drm_crtc *crtc = &intel_crtc->base;
> > > > > + struct drm_vblank_crtc *vblank;
> > > > > +
> > > > > + if (!intel_crtc->active)
> > > > > + continue;
> > > > > +
> > > > > + vblank = drm_crtc_vblank_crtc(crtc);
> > > > > +
> > > > > + if (vblank->enabled)
> > > > > + return false;
> > > > > + }
> > > > > +
> > > > > + return true;
> > > > > +}
> > > > > +
> > > > > static void hsw_activate_psr1(struct intel_dp *intel_dp)
> > > > > {
> > > > > struct drm_i915_private *dev_priv =
> > > > > dp_to_i915(intel_dp); @@
> > > > > -980,7 +1043,11 @@ static void hsw_activate_psr2(struct intel_dp
> > > > > *intel_dp)
> > > > > u32 val = EDP_PSR2_ENABLE;
> > > > > u32 psr_val = 0;
> > > > >
> > > > > - val |=
> > > > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > > > > + /* Wa_22019444797 */
> > > > > + if (DISPLAY_VER(dev_priv) != 20 ||
> > >
> > > I think this is wrong. It will not configure idle frames for display
> > > version other than 20.
> >
> > Wouldn’t this configure idle frames for all versions except 20 And if
> > it is 20 then if dpkgc is configured and dc5 entry is possible Only
> > then configure idle frames
>
> Yes. My bad. sorry for that. This should be ok for display version != 20.
> Another thing here. WA description is:
>
> "When PKG_C_LATENCY is configured (not all 1s), enable PSR2 deep sleep
> (PSR2_CTL Idle Frames != 0) only when DC5 can be entered."
>
> How about case where PKG_C_LATENCY is not configured? Do we need to
> care about it?
No we do not need to care about that the WA states this is only seen when dpkgc is configured
On lnl
Regards,
Suraj Kandpal
>
> BR,
>
> Jouni Högander
>
> >
> > Regards,
> > Suraj Kandpal
> > >
> > > BR,
> > >
> > > Jouni Högander
> > >
> > > > > + (intel_dp->psr.is_dpkgc_configured &&
> > > > > + intel_dp->psr.is_dc5_entry_possible))
> > > > > + val |=
> > > > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > > > >
> > > > > if (DISPLAY_VER(dev_priv) < 14 &&
> > > > > !IS_ALDERLAKE_P(dev_priv))
> > > > > val |= EDP_SU_TRACK_ENABLE; @@ -1595,6 +1662,32
> > > > > @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
> > > > > return true;
> > > > > }
> > > > >
> > > > > +static void wa_22019444797(struct intel_dp *intel_dp,
> > > > > + struct intel_crtc_state *crtc_state)
> > > > > {
> > > > > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > > > > +
> > > > > + if (DISPLAY_VER(i915) != 20)
> > > > > + return;
> > > > > +
> > > > > + intel_dp->psr.is_dpkgc_configured =
> > > > > + intel_psr_is_dpkgc_configured(i915);
> > > > > + intel_dp->psr.is_dc5_entry_possible =
> > > > > + intel_psr_is_dc5_entry_possible(i915,
> > > > > crtc_state);
> > > > > +
> > > > > + /* PSR2 not handled here. Wa not needed for Panel
> > > > > Replay */
> > > > > + if (crtc_state->has_sel_update || crtc_state-
> > > > > > has_panel_replay)
> > > > > + return;
> > > > > +
> > > > > + if (intel_dp->psr.is_dpkgc_configured &&
> > > > > + (intel_psr_check_delayed_vblank_limit(crtc_state)
> > > > > ||
> > > > > + intel_dp->psr.is_dc5_entry_possible)) {
> > > > > + drm_dbg_kms(&i915->drm,
> > > > > + "PSR1 not enabled as it doesn't
> > > > > meet
> > > > > requirements of WA: 22019444797\n");
> > > > > + crtc_state->has_psr = false;
> > > > > + }
> > > > > +}
> > > > > +
> > > > > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > > > > struct intel_crtc_state
> > > > > *crtc_state,
> > > > > struct drm_connector_state
> > > > > *conn_state)
> > > > > @@ -1641,6 +1734,7 @@ void intel_psr_compute_config(struct
> > > > > intel_dp *intel_dp,
> > > > > return;
> > > > >
> > > > > crtc_state->has_sel_update =
> > > > > intel_sel_update_config_valid(intel_dp, crtc_state);
> > > > > + wa_22019444797(intel_dp, crtc_state);
> > > > > }
> > > > >
> > > > > void intel_psr_get_config(struct intel_encoder *encoder,
> > > >
> >
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-02 11:07 ` Kandpal, Suraj
@ 2024-09-02 11:13 ` Hogander, Jouni
2024-09-02 11:16 ` Kandpal, Suraj
0 siblings, 1 reply; 47+ messages in thread
From: Hogander, Jouni @ 2024-09-02 11:13 UTC (permalink / raw)
To: Kandpal, Suraj, intel-gfx@lists.freedesktop.org; +Cc: Shankar, Uma
On Mon, 2024-09-02 at 11:07 +0000, Kandpal, Suraj wrote:
>
>
> > -----Original Message-----
> > From: Hogander, Jouni <jouni.hogander@intel.com>
> > Sent: Monday, September 2, 2024 4:32 PM
> > To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> > gfx@lists.freedesktop.org
> > Cc: Shankar, Uma <uma.shankar@intel.com>
> > Subject: Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
> >
> > On Mon, 2024-09-02 at 10:14 +0000, Kandpal, Suraj wrote:
> > >
> > >
> > > > -----Original Message-----
> > > > From: Hogander, Jouni <jouni.hogander@intel.com>
> > > > Sent: Monday, September 2, 2024 3:32 PM
> > > > To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> > > > gfx@lists.freedesktop.org
> > > > Cc: Shankar, Uma <uma.shankar@intel.com>
> > > > Subject: Re: [PATCH] drm/i915/psr: Implment WA to help reach
> > > > PC10
> > > >
> > > > On Mon, 2024-09-02 at 12:37 +0300, Hogander, Jouni wrote:
> > > > > On Mon, 2024-09-02 at 10:32 +0530, Suraj Kandpal wrote:
> > > > > > To reach PC10 when PKG_C_LATENCY is configure we must do
> > > > > > the
> > > > > > following things
> > > > > > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5
> > > > > > can be
> > > > > > entered
> > > > > > 2) Allow PSR2 deep sleep when DC5 can be entered
> > > > > > 3) DC5 can be entered when all transocoder have either
> > > > > > PSR1,
> > > > > > PSR2 or
> > > > > > eDP 1.5 PR ALPM enabled and VBI is disabled and flips and
> > > > > > pushes
> > > > > > are not happening.
> > > > > >
> > > > > > --v2
> > > > > > -Switch condition and do an early return [Jani] -Do some
> > > > > > checks
> > > > > > in compute_config [Jani] -Do not use register reads as a
> > > > > > method
> > > > > > of checking states for DPKGC or delayed vblank [Jani] -Use
> > > > > > another way to see is vblank interrupts are disabled or not
> > > > > > [Jani]
> > > > > >
> > > > > > --v3
> > > > > > -Use has_psr to check if psr can be enabled or not for
> > > > > > dc5_entry
> > > > > > cond [Uma] -Move the dc5 entry computation to
> > > > > > psr_compute_config
> > > > > > [Jouni] -No need to change sequence of enabled and
> > > > > > activate, so
> > > > > > dont make hsw_psr1_activate return anything [Jouni] -Use
> > > > > > has_psr
> > > > > > to stop
> > > > > > psr1 activation [Jouni] -Use lineage no. in WA -Add the
> > > > > > display
> > > > > > ver restrictions for WA
> > > > > >
> > > > > > WA: 22019444797
> > > > > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > > > > ---
> > > > > > .../drm/i915/display/intel_display_types.h | 2 +
> > > > > > drivers/gpu/drm/i915/display/intel_psr.c | 96
> > > > > > ++++++++++++++++++-
> > > > > > 2 files changed, 97 insertions(+), 1 deletion(-)
> > > > > >
> > > > > > diff --git
> > > > > > a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > index 868ff8976ed9..5395c1ecde7f 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > @@ -1717,6 +1717,8 @@ struct intel_psr {
> > > > > > bool sink_support;
> > > > > > bool source_support;
> > > > > > bool enabled;
> > > > > > + bool is_dpkgc_configured;
> > > > > > + bool is_dc5_entry_possible;
> > > > > > bool paused;
> > > > > > enum pipe pipe;
> > > > > > enum transcoder transcoder; diff --git
> > > > > > a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > index 257526362b39..1faec76eac32 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > @@ -870,6 +870,69 @@ static u8
> > > > > > psr_compute_idle_frames(struct
> > > > > > intel_dp *intel_dp)
> > > > > > return idle_frames;
> > > > > > }
> > > > > >
> > > > > > +static bool intel_psr_check_delayed_vblank_limit(struct
> > > > > > intel_crtc_state *crtc_state)
> > > > >
> > > > > You could add some context here in the name. This is somehow
> > > > > telling it's some generic delayed vblank limit while it is
> > > > > actually limit for this workaround.
> > > > >
> > > > > > +{
> > > > > > + struct drm_display_mode *adjusted_mode =
> > > > > > &crtc_state-
> > > > > > > hw.adjusted_mode;
> > > > > > +
> > > > > > + return (adjusted_mode->crtc_vblank_start -
> > > > > > adjusted_mode-
> > > > > > > crtc_vdisplay) >= 6;
> > > > > > +}
> > > > > > +
> > > > > > +/*
> > > > > > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20
> > > > > > and
> > > > > > + * VRR is not enabled
> > > > > > + */
> > > > > > +static bool intel_psr_is_dpkgc_configured(struct
> > > > > > drm_i915_private
> > > > > > *i915)
> > > > > > +{
> > > > > > + struct intel_crtc *intel_crtc;
> > > > > > +
> > > > > > + if (DISPLAY_VER(i915) < 20)
> > > > > > + return false;
> > > > > > +
> > > > > > + for_each_intel_crtc(&i915->drm, intel_crtc) {
> > > > > > + struct intel_crtc_state *crtc_state;
> > > > > > +
> > > > > > + if (!intel_crtc->active)
> > > > > > + continue;
> > > > > > +
> > > > > > + crtc_state = intel_crtc->config;
> > > > > > +
> > > > > > + if (crtc_state->vrr.enable)
> > > > > > + return false;
> > > > > > + }
> > > > > > +
> > > > > > + return true;
> > > > > > +}
> > > > > > +
> > > > > > +/*
> > > > > > + * DC5 entry is only possible if vblank interrupt is
> > > > > > disabled
> > > > > > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on
> > > > > > all
> > > > > > + * enabled encoders.
> > > > > > + */
> > > > > > +static bool
> > > > > > +intel_psr_is_dc5_entry_possible(struct drm_i915_private
> > > > > > *i915,
> > > > > > + struct intel_crtc_state
> > > > > > *crtc_state)
> > > > > > +{
> > > > > > + struct intel_crtc *intel_crtc;
> > > > > > +
> > > > > > + if (!(crtc_state->has_psr || crtc_state-
> > > > > > > has_sel_update))
> > > > > > + return false;
> > > > >
> > > > > Currently this is not returning for DP2.1 PR. This would
> > > > > better
> > > > > match with comment above:
> > > > >
> > > > > if (!crtc_state->has_psr || !intel_dp_is_edp(intel_dp))
> > > > > return false;
> > > > >
> > > > > Still "_all_ enabled encoders" is not handled...
> > > > >
> > > > > BR,
> > > > >
> > > > > Jouni Högander
> > > > >
> > > > > > +
> > > > > > + for_each_intel_crtc(&i915->drm, intel_crtc) {
> > > > > > + struct drm_crtc *crtc = &intel_crtc->base;
> > > > > > + struct drm_vblank_crtc *vblank;
> > > > > > +
> > > > > > + if (!intel_crtc->active)
> > > > > > + continue;
> > > > > > +
> > > > > > + vblank = drm_crtc_vblank_crtc(crtc);
> > > > > > +
> > > > > > + if (vblank->enabled)
> > > > > > + return false;
> > > > > > + }
> > > > > > +
> > > > > > + return true;
> > > > > > +}
> > > > > > +
> > > > > > static void hsw_activate_psr1(struct intel_dp *intel_dp)
> > > > > > {
> > > > > > struct drm_i915_private *dev_priv =
> > > > > > dp_to_i915(intel_dp); @@
> > > > > > -980,7 +1043,11 @@ static void hsw_activate_psr2(struct
> > > > > > intel_dp
> > > > > > *intel_dp)
> > > > > > u32 val = EDP_PSR2_ENABLE;
> > > > > > u32 psr_val = 0;
> > > > > >
> > > > > > - val |=
> > > > > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > > > > > + /* Wa_22019444797 */
> > > > > > + if (DISPLAY_VER(dev_priv) != 20 ||
> > > >
> > > > I think this is wrong. It will not configure idle frames for
> > > > display
> > > > version other than 20.
> > >
> > > Wouldn’t this configure idle frames for all versions except 20
> > > And if
> > > it is 20 then if dpkgc is configured and dc5 entry is possible
> > > Only
> > > then configure idle frames
> >
> > Yes. My bad. sorry for that. This should be ok for display version
> > != 20.
> > Another thing here. WA description is:
> >
>
> > "When PKG_C_LATENCY is configured (not all 1s), enable PSR2 deep
> > sleep
> > (PSR2_CTL Idle Frames != 0) only when DC5 can be entered."
> >
> > How about case where PKG_C_LATENCY is not configured? Do we need to
> > care about it?
>
> No we do not need to care about that the WA states this is only seen
> when dpkgc is configured
> On lnl
Ok, but you are still applying the WA (i.e. leaving PSR2_CTL[idle
frames] as 0) for case where dpkc is not configured.
BR,
Jouni Högander
>
> Regards,
> Suraj Kandpal
>
> >
> > BR,
> >
> > Jouni Högander
> >
> > >
> > > Regards,
> > > Suraj Kandpal
> > > >
> > > > BR,
> > > >
> > > > Jouni Högander
> > > >
> > > > > > + (intel_dp->psr.is_dpkgc_configured &&
> > > > > > + intel_dp->psr.is_dc5_entry_possible))
> > > > > > + val |=
> > > > > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > > > > >
> > > > > > if (DISPLAY_VER(dev_priv) < 14 &&
> > > > > > !IS_ALDERLAKE_P(dev_priv))
> > > > > > val |= EDP_SU_TRACK_ENABLE; @@ -1595,6
> > > > > > +1662,32
> > > > > > @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
> > > > > > return true;
> > > > > > }
> > > > > >
> > > > > > +static void wa_22019444797(struct intel_dp *intel_dp,
> > > > > > + struct intel_crtc_state
> > > > > > *crtc_state)
> > > > > > {
> > > > > > + struct drm_i915_private *i915 =
> > > > > > dp_to_i915(intel_dp);
> > > > > > +
> > > > > > + if (DISPLAY_VER(i915) != 20)
> > > > > > + return;
> > > > > > +
> > > > > > + intel_dp->psr.is_dpkgc_configured =
> > > > > > + intel_psr_is_dpkgc_configured(i915);
> > > > > > + intel_dp->psr.is_dc5_entry_possible =
> > > > > > + intel_psr_is_dc5_entry_possible(i915,
> > > > > > crtc_state);
> > > > > > +
> > > > > > + /* PSR2 not handled here. Wa not needed for Panel
> > > > > > Replay */
> > > > > > + if (crtc_state->has_sel_update || crtc_state-
> > > > > > > has_panel_replay)
> > > > > > + return;
> > > > > > +
> > > > > > + if (intel_dp->psr.is_dpkgc_configured &&
> > > > > > +
> > > > > > (intel_psr_check_delayed_vblank_limit(crtc_state)
> > > > > > > >
> > > > > > + intel_dp->psr.is_dc5_entry_possible)) {
> > > > > > + drm_dbg_kms(&i915->drm,
> > > > > > + "PSR1 not enabled as it doesn't
> > > > > > meet
> > > > > > requirements of WA: 22019444797\n");
> > > > > > + crtc_state->has_psr = false;
> > > > > > + }
> > > > > > +}
> > > > > > +
> > > > > > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > > > > > struct intel_crtc_state
> > > > > > *crtc_state,
> > > > > > struct drm_connector_state
> > > > > > *conn_state)
> > > > > > @@ -1641,6 +1734,7 @@ void intel_psr_compute_config(struct
> > > > > > intel_dp *intel_dp,
> > > > > > return;
> > > > > >
> > > > > > crtc_state->has_sel_update =
> > > > > > intel_sel_update_config_valid(intel_dp, crtc_state);
> > > > > > + wa_22019444797(intel_dp, crtc_state);
> > > > > > }
> > > > > >
> > > > > > void intel_psr_get_config(struct intel_encoder *encoder,
> > > > >
> > >
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-02 11:13 ` Hogander, Jouni
@ 2024-09-02 11:16 ` Kandpal, Suraj
0 siblings, 0 replies; 47+ messages in thread
From: Kandpal, Suraj @ 2024-09-02 11:16 UTC (permalink / raw)
To: Hogander, Jouni, intel-gfx@lists.freedesktop.org; +Cc: Shankar, Uma
> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Monday, September 2, 2024 4:44 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
>
> On Mon, 2024-09-02 at 11:07 +0000, Kandpal, Suraj wrote:
> >
> >
> > > -----Original Message-----
> > > From: Hogander, Jouni <jouni.hogander@intel.com>
> > > Sent: Monday, September 2, 2024 4:32 PM
> > > To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> > > gfx@lists.freedesktop.org
> > > Cc: Shankar, Uma <uma.shankar@intel.com>
> > > Subject: Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
> > >
> > > On Mon, 2024-09-02 at 10:14 +0000, Kandpal, Suraj wrote:
> > > >
> > > >
> > > > > -----Original Message-----
> > > > > From: Hogander, Jouni <jouni.hogander@intel.com>
> > > > > Sent: Monday, September 2, 2024 3:32 PM
> > > > > To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> > > > > gfx@lists.freedesktop.org
> > > > > Cc: Shankar, Uma <uma.shankar@intel.com>
> > > > > Subject: Re: [PATCH] drm/i915/psr: Implment WA to help reach
> > > > > PC10
> > > > >
> > > > > On Mon, 2024-09-02 at 12:37 +0300, Hogander, Jouni wrote:
> > > > > > On Mon, 2024-09-02 at 10:32 +0530, Suraj Kandpal wrote:
> > > > > > > To reach PC10 when PKG_C_LATENCY is configure we must do the
> > > > > > > following things
> > > > > > > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can
> > > > > > > be entered
> > > > > > > 2) Allow PSR2 deep sleep when DC5 can be entered
> > > > > > > 3) DC5 can be entered when all transocoder have either PSR1,
> > > > > > > PSR2 or
> > > > > > > eDP 1.5 PR ALPM enabled and VBI is disabled and flips and
> > > > > > > pushes are not happening.
> > > > > > >
> > > > > > > --v2
> > > > > > > -Switch condition and do an early return [Jani] -Do some
> > > > > > > checks in compute_config [Jani] -Do not use register reads
> > > > > > > as a method of checking states for DPKGC or delayed vblank
> > > > > > > [Jani] -Use another way to see is vblank interrupts are
> > > > > > > disabled or not [Jani]
> > > > > > >
> > > > > > > --v3
> > > > > > > -Use has_psr to check if psr can be enabled or not for
> > > > > > > dc5_entry cond [Uma] -Move the dc5 entry computation to
> > > > > > > psr_compute_config [Jouni] -No need to change sequence of
> > > > > > > enabled and activate, so dont make hsw_psr1_activate return
> > > > > > > anything [Jouni] -Use has_psr to stop
> > > > > > > psr1 activation [Jouni] -Use lineage no. in WA -Add the
> > > > > > > display ver restrictions for WA
> > > > > > >
> > > > > > > WA: 22019444797
> > > > > > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > > > > > ---
> > > > > > > .../drm/i915/display/intel_display_types.h | 2 +
> > > > > > > drivers/gpu/drm/i915/display/intel_psr.c | 96
> > > > > > > ++++++++++++++++++-
> > > > > > > 2 files changed, 97 insertions(+), 1 deletion(-)
> > > > > > >
> > > > > > > diff --git
> > > > > > > a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > > index 868ff8976ed9..5395c1ecde7f 100644
> > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > > @@ -1717,6 +1717,8 @@ struct intel_psr {
> > > > > > > bool sink_support;
> > > > > > > bool source_support;
> > > > > > > bool enabled;
> > > > > > > + bool is_dpkgc_configured;
> > > > > > > + bool is_dc5_entry_possible;
> > > > > > > bool paused;
> > > > > > > enum pipe pipe;
> > > > > > > enum transcoder transcoder; diff --git
> > > > > > > a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > > index 257526362b39..1faec76eac32 100644
> > > > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > > @@ -870,6 +870,69 @@ static u8
> > > > > > > psr_compute_idle_frames(struct intel_dp *intel_dp)
> > > > > > > return idle_frames;
> > > > > > > }
> > > > > > >
> > > > > > > +static bool intel_psr_check_delayed_vblank_limit(struct
> > > > > > > intel_crtc_state *crtc_state)
> > > > > >
> > > > > > You could add some context here in the name. This is somehow
> > > > > > telling it's some generic delayed vblank limit while it is
> > > > > > actually limit for this workaround.
> > > > > >
> > > > > > > +{
> > > > > > > + struct drm_display_mode *adjusted_mode =
> > > > > > > &crtc_state-
> > > > > > > > hw.adjusted_mode;
> > > > > > > +
> > > > > > > + return (adjusted_mode->crtc_vblank_start -
> > > > > > > adjusted_mode-
> > > > > > > > crtc_vdisplay) >= 6;
> > > > > > > +}
> > > > > > > +
> > > > > > > +/*
> > > > > > > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20
> > > > > > > and
> > > > > > > + * VRR is not enabled
> > > > > > > + */
> > > > > > > +static bool intel_psr_is_dpkgc_configured(struct
> > > > > > > drm_i915_private
> > > > > > > *i915)
> > > > > > > +{
> > > > > > > + struct intel_crtc *intel_crtc;
> > > > > > > +
> > > > > > > + if (DISPLAY_VER(i915) < 20)
> > > > > > > + return false;
> > > > > > > +
> > > > > > > + for_each_intel_crtc(&i915->drm, intel_crtc) {
> > > > > > > + struct intel_crtc_state *crtc_state;
> > > > > > > +
> > > > > > > + if (!intel_crtc->active)
> > > > > > > + continue;
> > > > > > > +
> > > > > > > + crtc_state = intel_crtc->config;
> > > > > > > +
> > > > > > > + if (crtc_state->vrr.enable)
> > > > > > > + return false;
> > > > > > > + }
> > > > > > > +
> > > > > > > + return true;
> > > > > > > +}
> > > > > > > +
> > > > > > > +/*
> > > > > > > + * DC5 entry is only possible if vblank interrupt is
> > > > > > > disabled
> > > > > > > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on
> > > > > > > all
> > > > > > > + * enabled encoders.
> > > > > > > + */
> > > > > > > +static bool
> > > > > > > +intel_psr_is_dc5_entry_possible(struct drm_i915_private
> > > > > > > *i915,
> > > > > > > + struct intel_crtc_state
> > > > > > > *crtc_state)
> > > > > > > +{
> > > > > > > + struct intel_crtc *intel_crtc;
> > > > > > > +
> > > > > > > + if (!(crtc_state->has_psr || crtc_state-
> > > > > > > > has_sel_update))
> > > > > > > + return false;
> > > > > >
> > > > > > Currently this is not returning for DP2.1 PR. This would
> > > > > > better match with comment above:
> > > > > >
> > > > > > if (!crtc_state->has_psr || !intel_dp_is_edp(intel_dp))
> > > > > > return false;
> > > > > >
> > > > > > Still "_all_ enabled encoders" is not handled...
> > > > > >
> > > > > > BR,
> > > > > >
> > > > > > Jouni Högander
> > > > > >
> > > > > > > +
> > > > > > > + for_each_intel_crtc(&i915->drm, intel_crtc) {
> > > > > > > + struct drm_crtc *crtc = &intel_crtc->base;
> > > > > > > + struct drm_vblank_crtc *vblank;
> > > > > > > +
> > > > > > > + if (!intel_crtc->active)
> > > > > > > + continue;
> > > > > > > +
> > > > > > > + vblank = drm_crtc_vblank_crtc(crtc);
> > > > > > > +
> > > > > > > + if (vblank->enabled)
> > > > > > > + return false;
> > > > > > > + }
> > > > > > > +
> > > > > > > + return true;
> > > > > > > +}
> > > > > > > +
> > > > > > > static void hsw_activate_psr1(struct intel_dp *intel_dp)
> > > > > > > {
> > > > > > > struct drm_i915_private *dev_priv =
> > > > > > > dp_to_i915(intel_dp); @@
> > > > > > > -980,7 +1043,11 @@ static void hsw_activate_psr2(struct
> > > > > > > intel_dp
> > > > > > > *intel_dp)
> > > > > > > u32 val = EDP_PSR2_ENABLE;
> > > > > > > u32 psr_val = 0;
> > > > > > >
> > > > > > > - val |=
> > > > > > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > > > > > > + /* Wa_22019444797 */
> > > > > > > + if (DISPLAY_VER(dev_priv) != 20 ||
> > > > >
> > > > > I think this is wrong. It will not configure idle frames for
> > > > > display version other than 20.
> > > >
> > > > Wouldn’t this configure idle frames for all versions except 20 And
> > > > if it is 20 then if dpkgc is configured and dc5 entry is possible
> > > > Only then configure idle frames
> > >
> > > Yes. My bad. sorry for that. This should be ok for display version
> > > != 20.
> > > Another thing here. WA description is:
> > >
> >
> > > "When PKG_C_LATENCY is configured (not all 1s), enable PSR2 deep
> > > sleep (PSR2_CTL Idle Frames != 0) only when DC5 can be entered."
> > >
> > > How about case where PKG_C_LATENCY is not configured? Do we need
> to
> > > care about it?
> >
> > No we do not need to care about that the WA states this is only seen
> > when dpkgc is configured On lnl
>
> Ok, but you are still applying the WA (i.e. leaving PSR2_CTL[idle frames] as
> 0) for case where dpkc is not configured.
Ahh okay got it needed an extra condition which checks || !is_dpkgc_configured
Regards,
Suraj Kandpal
>
> BR,
>
> Jouni Högander
>
> >
> > Regards,
> > Suraj Kandpal
> >
> > >
> > > BR,
> > >
> > > Jouni Högander
> > >
> > > >
> > > > Regards,
> > > > Suraj Kandpal
> > > > >
> > > > > BR,
> > > > >
> > > > > Jouni Högander
> > > > >
> > > > > > > + (intel_dp->psr.is_dpkgc_configured &&
> > > > > > > + intel_dp->psr.is_dc5_entry_possible))
> > > > > > > + val |=
> > > > > > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > > > > > >
> > > > > > > if (DISPLAY_VER(dev_priv) < 14 &&
> > > > > > > !IS_ALDERLAKE_P(dev_priv))
> > > > > > > val |= EDP_SU_TRACK_ENABLE; @@ -1595,6
> > > > > > > +1662,32
> > > > > > > @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
> > > > > > > return true;
> > > > > > > }
> > > > > > >
> > > > > > > +static void wa_22019444797(struct intel_dp *intel_dp,
> > > > > > > + struct intel_crtc_state
> > > > > > > *crtc_state)
> > > > > > > {
> > > > > > > + struct drm_i915_private *i915 =
> > > > > > > dp_to_i915(intel_dp);
> > > > > > > +
> > > > > > > + if (DISPLAY_VER(i915) != 20)
> > > > > > > + return;
> > > > > > > +
> > > > > > > + intel_dp->psr.is_dpkgc_configured =
> > > > > > > + intel_psr_is_dpkgc_configured(i915);
> > > > > > > + intel_dp->psr.is_dc5_entry_possible =
> > > > > > > + intel_psr_is_dc5_entry_possible(i915,
> > > > > > > crtc_state);
> > > > > > > +
> > > > > > > + /* PSR2 not handled here. Wa not needed for Panel
> > > > > > > Replay */
> > > > > > > + if (crtc_state->has_sel_update || crtc_state-
> > > > > > > > has_panel_replay)
> > > > > > > + return;
> > > > > > > +
> > > > > > > + if (intel_dp->psr.is_dpkgc_configured &&
> > > > > > > +
> > > > > > > (intel_psr_check_delayed_vblank_limit(crtc_state)
> > > > > > > > >
> > > > > > > + intel_dp->psr.is_dc5_entry_possible)) {
> > > > > > > + drm_dbg_kms(&i915->drm,
> > > > > > > + "PSR1 not enabled as it doesn't
> > > > > > > meet
> > > > > > > requirements of WA: 22019444797\n");
> > > > > > > + crtc_state->has_psr = false;
> > > > > > > + }
> > > > > > > +}
> > > > > > > +
> > > > > > > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > > > > > > struct intel_crtc_state
> > > > > > > *crtc_state,
> > > > > > > struct drm_connector_state
> > > > > > > *conn_state)
> > > > > > > @@ -1641,6 +1734,7 @@ void intel_psr_compute_config(struct
> > > > > > > intel_dp *intel_dp,
> > > > > > > return;
> > > > > > >
> > > > > > > crtc_state->has_sel_update =
> > > > > > > intel_sel_update_config_valid(intel_dp, crtc_state);
> > > > > > > + wa_22019444797(intel_dp, crtc_state);
> > > > > > > }
> > > > > > >
> > > > > > > void intel_psr_get_config(struct intel_encoder *encoder,
> > > > > >
> > > >
> >
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-02 10:01 ` Kandpal, Suraj
@ 2024-09-03 7:42 ` Hogander, Jouni
2024-09-03 7:46 ` Kandpal, Suraj
0 siblings, 1 reply; 47+ messages in thread
From: Hogander, Jouni @ 2024-09-03 7:42 UTC (permalink / raw)
To: Kandpal, Suraj, intel-gfx@lists.freedesktop.org; +Cc: Shankar, Uma
On Mon, 2024-09-02 at 10:01 +0000, Kandpal, Suraj wrote:
>
>
> > -----Original Message-----
> > From: Hogander, Jouni <jouni.hogander@intel.com>
> > Sent: Monday, September 2, 2024 3:07 PM
> > To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> > gfx@lists.freedesktop.org
> > Cc: Shankar, Uma <uma.shankar@intel.com>
> > Subject: Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
> >
> > On Mon, 2024-09-02 at 10:32 +0530, Suraj Kandpal wrote:
> > > To reach PC10 when PKG_C_LATENCY is configure we must do the
> > following
> > > things
> > > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> > > entered
> > > 2) Allow PSR2 deep sleep when DC5 can be entered
> > > 3) DC5 can be entered when all transocoder have either PSR1, PSR2
> > > or
> > > eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes
> > > are
> > > not happening.
> > >
> > > --v2
> > > -Switch condition and do an early return [Jani] -Do some checks
> > > in
> > > compute_config [Jani] -Do not use register reads as a method of
> > > checking states for DPKGC or delayed vblank [Jani] -Use another
> > > way to
> > > see is vblank interrupts are disabled or not [Jani]
> > >
> > > --v3
> > > -Use has_psr to check if psr can be enabled or not for dc5_entry
> > > cond
> > > [Uma] -Move the dc5 entry computation to psr_compute_config
> > > [Jouni]
> > > -No need to change sequence of enabled and activate, so dont make
> > > hsw_psr1_activate return anything [Jouni] -Use has_psr to stop
> > > psr1
> > > activation [Jouni] -Use lineage no. in WA -Add the display ver
> > > restrictions for WA
> > >
> > > WA: 22019444797
> > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > ---
> > > .../drm/i915/display/intel_display_types.h | 2 +
> > > drivers/gpu/drm/i915/display/intel_psr.c | 96
> > > ++++++++++++++++++-
> > > 2 files changed, 97 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 868ff8976ed9..5395c1ecde7f 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -1717,6 +1717,8 @@ struct intel_psr {
> > > bool sink_support;
> > > bool source_support;
> > > bool enabled;
> > > + bool is_dpkgc_configured;
> > > + bool is_dc5_entry_possible;
> > > bool paused;
> > > enum pipe pipe;
> > > enum transcoder transcoder;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 257526362b39..1faec76eac32 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -870,6 +870,69 @@ static u8 psr_compute_idle_frames(struct
> > intel_dp
> > > *intel_dp)
> > > return idle_frames;
> > > }
> > >
> > > +static bool intel_psr_check_delayed_vblank_limit(struct
> > > intel_crtc_state *crtc_state)
> >
> > You could add some context here in the name. This is somehow
> > telling it's
> > some generic delayed vblank limit while it is actually limit for
> > this
> > workaround.
>
> Sure will fix in next revision
> How about something like check_wa_delayed_vblank()
>
> >
> > > +{
> > > + struct drm_display_mode *adjusted_mode = &crtc_state-
> > > > hw.adjusted_mode;
> > > +
> > > + return (adjusted_mode->crtc_vblank_start - adjusted_mode-
> > > > crtc_vdisplay) >= 6;
> > > +}
> > > +
> > > +/*
> > > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> > > + * VRR is not enabled
> > > + */
> > > +static bool intel_psr_is_dpkgc_configured(struct
> > > drm_i915_private
> > > *i915)
> > > +{
> > > + struct intel_crtc *intel_crtc;
> > > +
> > > + if (DISPLAY_VER(i915) < 20)
> > > + return false;
> > > +
> > > + for_each_intel_crtc(&i915->drm, intel_crtc) {
> > > + struct intel_crtc_state *crtc_state;
> > > +
> > > + if (!intel_crtc->active)
> > > + continue;
> > > +
> > > + crtc_state = intel_crtc->config;
> > > +
> > > + if (crtc_state->vrr.enable)
> > > + return false;
> > > + }
> > > +
> > > + return true;
> > > +}
> > > +
> > > +/*
> > > + * DC5 entry is only possible if vblank interrupt is disabled
> > > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> > > + * enabled encoders.
> > > + */
> > > +static bool
> > > +intel_psr_is_dc5_entry_possible(struct drm_i915_private *i915,
> > > + struct intel_crtc_state
> > > *crtc_state) {
> > > + struct intel_crtc *intel_crtc;
> > > +
> > > + if (!(crtc_state->has_psr || crtc_state->has_sel_update))
> > > + return false;
> >
> > Currently this is not returning for DP2.1 PR. This would better
> > match with
> > comment above:
> >
> > if (!crtc_state->has_psr || !intel_dp_is_edp(intel_dp))
> > return false;
> >
> > Still "_all_ enabled encoders" is not handled...
> >
>
> How about in the below loop I add a encoder loop that checks if
> intel_dp_is_edp
> If the encoder is active and the psr check is taken care of by
> checking crtc_state->has_psr ?
> Previously I used to check if psr->enabled but since this is now
> called in psr compute config I only have has_psr to check
> If psr can be enabled on that encoder .
Loop idea is ok. Also crtc_state->has_psr. Shouldn't you also handle
non-edp as well? If there is any non-edp encoder active I think dc5
will be blocked?
BR,
Jouni Högander
>
> Regards,
> Suraj Kandpal
> > BR,
> >
> > Jouni Högander
> >
> > > +
> > > + for_each_intel_crtc(&i915->drm, intel_crtc) {
> > > + struct drm_crtc *crtc = &intel_crtc->base;
> > > + struct drm_vblank_crtc *vblank;
> > > +
> > > + if (!intel_crtc->active)
> > > + continue;
> > > +
> > > + vblank = drm_crtc_vblank_crtc(crtc);
> > > +
> > > + if (vblank->enabled)
> > > + return false;
> > > + }
> > > +
> > > + return true;
> > > +}
> > > +
> > > static void hsw_activate_psr1(struct intel_dp *intel_dp)
> > > {
> > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > @@
> > > -980,7 +1043,11 @@ static void hsw_activate_psr2(struct intel_dp
> > > *intel_dp)
> > > u32 val = EDP_PSR2_ENABLE;
> > > u32 psr_val = 0;
> > >
> > > - val |=
> > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > > + /* Wa_22019444797 */
> > > + if (DISPLAY_VER(dev_priv) != 20 ||
> > > + (intel_dp->psr.is_dpkgc_configured &&
> > > + intel_dp->psr.is_dc5_entry_possible))
> > > + val |=
> > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > >
> > > if (DISPLAY_VER(dev_priv) < 14 &&
> > > !IS_ALDERLAKE_P(dev_priv))
> > > val |= EDP_SU_TRACK_ENABLE; @@ -1595,6 +1662,32
> > > @@
> > > _panel_replay_compute_config(struct intel_dp *intel_dp,
> > > return true;
> > > }
> > >
> > > +static void wa_22019444797(struct intel_dp *intel_dp,
> > > + struct intel_crtc_state *crtc_state) {
> > > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > > +
> > > + if (DISPLAY_VER(i915) != 20)
> > > + return;
> > > +
> > > + intel_dp->psr.is_dpkgc_configured =
> > > + intel_psr_is_dpkgc_configured(i915);
> > > + intel_dp->psr.is_dc5_entry_possible =
> > > + intel_psr_is_dc5_entry_possible(i915,
> > > crtc_state);
> > > +
> > > + /* PSR2 not handled here. Wa not needed for Panel Replay
> > > */
> > > + if (crtc_state->has_sel_update || crtc_state-
> > > > has_panel_replay)
> > > + return;
> > > +
> > > + if (intel_dp->psr.is_dpkgc_configured &&
> > > + (intel_psr_check_delayed_vblank_limit(crtc_state) ||
> > > + intel_dp->psr.is_dc5_entry_possible)) {
> > > + drm_dbg_kms(&i915->drm,
> > > + "PSR1 not enabled as it doesn't meet
> > > requirements of WA: 22019444797\n");
> > > + crtc_state->has_psr = false;
> > > + }
> > > +}
> > > +
> > > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > > struct intel_crtc_state
> > > *crtc_state,
> > > struct drm_connector_state
> > > *conn_state)
> > > @@ -1641,6 +1734,7 @@ void intel_psr_compute_config(struct
> > > intel_dp
> > > *intel_dp,
> > > return;
> > >
> > > crtc_state->has_sel_update =
> > > intel_sel_update_config_valid(intel_dp, crtc_state);
> > > + wa_22019444797(intel_dp, crtc_state);
> > > }
> > >
> > > void intel_psr_get_config(struct intel_encoder *encoder,
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-03 7:42 ` Hogander, Jouni
@ 2024-09-03 7:46 ` Kandpal, Suraj
0 siblings, 0 replies; 47+ messages in thread
From: Kandpal, Suraj @ 2024-09-03 7:46 UTC (permalink / raw)
To: Hogander, Jouni, intel-gfx@lists.freedesktop.org; +Cc: Shankar, Uma
> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Tuesday, September 3, 2024 1:12 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
>
> On Mon, 2024-09-02 at 10:01 +0000, Kandpal, Suraj wrote:
> >
> >
> > > -----Original Message-----
> > > From: Hogander, Jouni <jouni.hogander@intel.com>
> > > Sent: Monday, September 2, 2024 3:07 PM
> > > To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> > > gfx@lists.freedesktop.org
> > > Cc: Shankar, Uma <uma.shankar@intel.com>
> > > Subject: Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
> > >
> > > On Mon, 2024-09-02 at 10:32 +0530, Suraj Kandpal wrote:
> > > > To reach PC10 when PKG_C_LATENCY is configure we must do the
> > > following
> > > > things
> > > > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> > > > entered
> > > > 2) Allow PSR2 deep sleep when DC5 can be entered
> > > > 3) DC5 can be entered when all transocoder have either PSR1, PSR2
> > > > or eDP 1.5 PR ALPM enabled and VBI is disabled and flips and
> > > > pushes are not happening.
> > > >
> > > > --v2
> > > > -Switch condition and do an early return [Jani] -Do some checks in
> > > > compute_config [Jani] -Do not use register reads as a method of
> > > > checking states for DPKGC or delayed vblank [Jani] -Use another
> > > > way to see is vblank interrupts are disabled or not [Jani]
> > > >
> > > > --v3
> > > > -Use has_psr to check if psr can be enabled or not for dc5_entry
> > > > cond [Uma] -Move the dc5 entry computation to psr_compute_config
> > > > [Jouni] -No need to change sequence of enabled and activate, so
> > > > dont make hsw_psr1_activate return anything [Jouni] -Use has_psr
> > > > to stop
> > > > psr1
> > > > activation [Jouni] -Use lineage no. in WA -Add the display ver
> > > > restrictions for WA
> > > >
> > > > WA: 22019444797
> > > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > > ---
> > > > .../drm/i915/display/intel_display_types.h | 2 +
> > > > drivers/gpu/drm/i915/display/intel_psr.c | 96
> > > > ++++++++++++++++++-
> > > > 2 files changed, 97 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > index 868ff8976ed9..5395c1ecde7f 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > @@ -1717,6 +1717,8 @@ struct intel_psr {
> > > > bool sink_support;
> > > > bool source_support;
> > > > bool enabled;
> > > > + bool is_dpkgc_configured;
> > > > + bool is_dc5_entry_possible;
> > > > bool paused;
> > > > enum pipe pipe;
> > > > enum transcoder transcoder; diff --git
> > > > a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index 257526362b39..1faec76eac32 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -870,6 +870,69 @@ static u8 psr_compute_idle_frames(struct
> > > intel_dp
> > > > *intel_dp)
> > > > return idle_frames;
> > > > }
> > > >
> > > > +static bool intel_psr_check_delayed_vblank_limit(struct
> > > > intel_crtc_state *crtc_state)
> > >
> > > You could add some context here in the name. This is somehow telling
> > > it's some generic delayed vblank limit while it is actually limit
> > > for this workaround.
> >
> > Sure will fix in next revision
> > How about something like check_wa_delayed_vblank()
> >
> > >
> > > > +{
> > > > + struct drm_display_mode *adjusted_mode = &crtc_state-
> > > > > hw.adjusted_mode;
> > > > +
> > > > + return (adjusted_mode->crtc_vblank_start - adjusted_mode-
> > > > > crtc_vdisplay) >= 6;
> > > > +}
> > > > +
> > > > +/*
> > > > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> > > > + * VRR is not enabled
> > > > + */
> > > > +static bool intel_psr_is_dpkgc_configured(struct
> > > > drm_i915_private
> > > > *i915)
> > > > +{
> > > > + struct intel_crtc *intel_crtc;
> > > > +
> > > > + if (DISPLAY_VER(i915) < 20)
> > > > + return false;
> > > > +
> > > > + for_each_intel_crtc(&i915->drm, intel_crtc) {
> > > > + struct intel_crtc_state *crtc_state;
> > > > +
> > > > + if (!intel_crtc->active)
> > > > + continue;
> > > > +
> > > > + crtc_state = intel_crtc->config;
> > > > +
> > > > + if (crtc_state->vrr.enable)
> > > > + return false;
> > > > + }
> > > > +
> > > > + return true;
> > > > +}
> > > > +
> > > > +/*
> > > > + * DC5 entry is only possible if vblank interrupt is disabled
> > > > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> > > > + * enabled encoders.
> > > > + */
> > > > +static bool
> > > > +intel_psr_is_dc5_entry_possible(struct drm_i915_private *i915,
> > > > + struct intel_crtc_state
> > > > *crtc_state) {
> > > > + struct intel_crtc *intel_crtc;
> > > > +
> > > > + if (!(crtc_state->has_psr || crtc_state->has_sel_update))
> > > > + return false;
> > >
> > > Currently this is not returning for DP2.1 PR. This would better
> > > match with comment above:
> > >
> > > if (!crtc_state->has_psr || !intel_dp_is_edp(intel_dp))
> > > return false;
> > >
> > > Still "_all_ enabled encoders" is not handled...
> > >
> >
> > How about in the below loop I add a encoder loop that checks if
> > intel_dp_is_edp If the encoder is active and the psr check is taken
> > care of by checking crtc_state->has_psr ?
> > Previously I used to check if psr->enabled but since this is now
> > called in psr compute config I only have has_psr to check If psr can
> > be enabled on that encoder .
>
> Loop idea is ok. Also crtc_state->has_psr. Shouldn't you also handle non-edp
> as well? If there is any non-edp encoder active I think dc5 will be blocked?
>
Yes since the condition to enter dc5 is to have either psr1,psr2, or edp1.5 alpm pr
Which would mean in the loop we need to check if encoder->type != INTEL_OUTPUT_EDP
We return false.
Regards,
Suraj Kandpal
> BR,
>
> Jouni Högander
>
> >
> > Regards,
> > Suraj Kandpal
> > > BR,
> > >
> > > Jouni Högander
> > >
> > > > +
> > > > + for_each_intel_crtc(&i915->drm, intel_crtc) {
> > > > + struct drm_crtc *crtc = &intel_crtc->base;
> > > > + struct drm_vblank_crtc *vblank;
> > > > +
> > > > + if (!intel_crtc->active)
> > > > + continue;
> > > > +
> > > > + vblank = drm_crtc_vblank_crtc(crtc);
> > > > +
> > > > + if (vblank->enabled)
> > > > + return false;
> > > > + }
> > > > +
> > > > + return true;
> > > > +}
> > > > +
> > > > static void hsw_activate_psr1(struct intel_dp *intel_dp)
> > > > {
> > > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > > @@
> > > > -980,7 +1043,11 @@ static void hsw_activate_psr2(struct intel_dp
> > > > *intel_dp)
> > > > u32 val = EDP_PSR2_ENABLE;
> > > > u32 psr_val = 0;
> > > >
> > > > - val |=
> > > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > > > + /* Wa_22019444797 */
> > > > + if (DISPLAY_VER(dev_priv) != 20 ||
> > > > + (intel_dp->psr.is_dpkgc_configured &&
> > > > + intel_dp->psr.is_dc5_entry_possible))
> > > > + val |=
> > > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > > >
> > > > if (DISPLAY_VER(dev_priv) < 14 &&
> > > > !IS_ALDERLAKE_P(dev_priv))
> > > > val |= EDP_SU_TRACK_ENABLE; @@ -1595,6 +1662,32 @@
> > > > _panel_replay_compute_config(struct intel_dp *intel_dp,
> > > > return true;
> > > > }
> > > >
> > > > +static void wa_22019444797(struct intel_dp *intel_dp,
> > > > + struct intel_crtc_state *crtc_state) {
> > > > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > > > +
> > > > + if (DISPLAY_VER(i915) != 20)
> > > > + return;
> > > > +
> > > > + intel_dp->psr.is_dpkgc_configured =
> > > > + intel_psr_is_dpkgc_configured(i915);
> > > > + intel_dp->psr.is_dc5_entry_possible =
> > > > + intel_psr_is_dc5_entry_possible(i915,
> > > > crtc_state);
> > > > +
> > > > + /* PSR2 not handled here. Wa not needed for Panel Replay
> > > > */
> > > > + if (crtc_state->has_sel_update || crtc_state-
> > > > > has_panel_replay)
> > > > + return;
> > > > +
> > > > + if (intel_dp->psr.is_dpkgc_configured &&
> > > > + (intel_psr_check_delayed_vblank_limit(crtc_state) ||
> > > > + intel_dp->psr.is_dc5_entry_possible)) {
> > > > + drm_dbg_kms(&i915->drm,
> > > > + "PSR1 not enabled as it doesn't meet
> > > > requirements of WA: 22019444797\n");
> > > > + crtc_state->has_psr = false;
> > > > + }
> > > > +}
> > > > +
> > > > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > > > struct intel_crtc_state *crtc_state,
> > > > struct drm_connector_state
> > > > *conn_state)
> > > > @@ -1641,6 +1734,7 @@ void intel_psr_compute_config(struct
> > > > intel_dp *intel_dp,
> > > > return;
> > > >
> > > > crtc_state->has_sel_update =
> > > > intel_sel_update_config_valid(intel_dp, crtc_state);
> > > > + wa_22019444797(intel_dp, crtc_state);
> > > > }
> > > >
> > > > void intel_psr_get_config(struct intel_encoder *encoder,
> >
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-02 5:02 [PATCH] drm/i915/psr: Implment WA to help reach PC10 Suraj Kandpal
2024-09-02 6:13 ` ✗ Fi.CI.BAT: failure for " Patchwork
2024-09-02 9:37 ` [PATCH] " Hogander, Jouni
@ 2024-09-03 8:24 ` Suraj Kandpal
2024-09-05 4:41 ` Suraj Kandpal
2024-09-09 14:12 ` [PATCH] drm/i915/psr: Implment " Ville Syrjälä
2024-09-03 10:25 ` ✓ Fi.CI.BAT: success for drm/i915/psr: Implment WA to help reach PC10 (rev2) Patchwork
` (10 subsequent siblings)
13 siblings, 2 replies; 47+ messages in thread
From: Suraj Kandpal @ 2024-09-03 8:24 UTC (permalink / raw)
To: intel-gfx; +Cc: uma.shankar, jouni.hogander, Suraj Kandpal
To reach PC10 when PKG_C_LATENCY is configure we must do the following
things
1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
2) Allow PSR2 deep sleep when DC5 can be entered
3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
not happening.
--v2
-Switch condition and do an early return [Jani]
-Do some checks in compute_config [Jani]
-Do not use register reads as a method of checking states for
DPKGC or delayed vblank [Jani]
-Use another way to see is vblank interrupts are disabled or not [Jani]
--v3
-Use has_psr to check if psr can be enabled or not for dc5_entry cond
[Uma]
-Move the dc5 entry computation to psr_compute_config [Jouni]
-No need to change sequence of enabled and activate,
so dont make hsw_psr1_activate return anything [Jouni]
-Use has_psr to stop psr1 activation [Jouni]
-Use lineage no. in WA
-Add the display ver restrictions for WA
--v4
-use more appropriate name for check_vblank_limit() [Jouni]
-Cover the case for idle frames when dpkgc is not configured [Jouni]
-Check psr only for edp [Jouni]
WA: 22019444797
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
.../drm/i915/display/intel_display_types.h | 2 +
drivers/gpu/drm/i915/display/intel_psr.c | 101 +++++++++++++++++-
2 files changed, 102 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index fa03157554b2..6b95a59aba2e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1717,6 +1717,8 @@ struct intel_psr {
bool sink_support;
bool source_support;
bool enabled;
+ bool is_dpkgc_configured;
+ bool is_dc5_entry_possible;
bool paused;
enum pipe pipe;
enum transcoder transcoder;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 257526362b39..6eb137ecd49f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -870,6 +870,74 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
return idle_frames;
}
+static bool intel_psr_check_wa_delayed_vblank(struct intel_crtc_state *crtc_state)
+{
+ struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+
+ return (adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay) >= 6;
+}
+
+/*
+ * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
+ * VRR is not enabled
+ */
+static bool intel_psr_is_dpkgc_configured(struct drm_i915_private *i915)
+{
+ struct intel_crtc *intel_crtc;
+
+ if (DISPLAY_VER(i915) < 20)
+ return false;
+
+ for_each_intel_crtc(&i915->drm, intel_crtc) {
+ struct intel_crtc_state *crtc_state;
+
+ if (!intel_crtc->active)
+ continue;
+
+ crtc_state = intel_crtc->config;
+
+ if (crtc_state->vrr.enable)
+ return false;
+ }
+
+ return true;
+}
+
+/*
+ * DC5 entry is only possible if vblank interrupt is disabled
+ * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
+ * enabled encoders.
+ */
+static bool
+intel_psr_is_dc5_entry_possible(struct drm_i915_private *i915,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *intel_crtc;
+
+ if (!crtc_state->has_psr)
+ return false;
+
+ for_each_intel_crtc(&i915->drm, intel_crtc) {
+ struct drm_crtc *crtc = &intel_crtc->base;
+ struct drm_vblank_crtc *vblank;
+ struct intel_encoder *encoder;
+
+ if (!intel_crtc->active)
+ continue;
+
+ vblank = drm_crtc_vblank_crtc(crtc);
+
+ if (vblank->enabled)
+ return false;
+
+ for_each_encoder_on_crtc(&i915->drm, crtc, encoder)
+ if (encoder->type != INTEL_OUTPUT_EDP)
+ return false;
+ }
+
+ return true;
+}
+
static void hsw_activate_psr1(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -980,7 +1048,11 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
u32 val = EDP_PSR2_ENABLE;
u32 psr_val = 0;
- val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ /* Wa_22019444797 */
+ if (DISPLAY_VER(dev_priv) != 20 ||
+ !intel_dp->psr.is_dpkgc_configured ||
+ intel_dp->psr.is_dc5_entry_possible)
+ val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
if (DISPLAY_VER(dev_priv) < 14 && !IS_ALDERLAKE_P(dev_priv))
val |= EDP_SU_TRACK_ENABLE;
@@ -1595,6 +1667,32 @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
return true;
}
+static void wa_22019444797(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ if (DISPLAY_VER(i915) != 20)
+ return;
+
+ intel_dp->psr.is_dpkgc_configured =
+ intel_psr_is_dpkgc_configured(i915);
+ intel_dp->psr.is_dc5_entry_possible =
+ intel_psr_is_dc5_entry_possible(i915, crtc_state);
+
+ /* PSR2 not handled here. Wa not needed for Panel Replay */
+ if (crtc_state->has_sel_update || crtc_state->has_panel_replay)
+ return;
+
+ if (intel_dp->psr.is_dpkgc_configured &&
+ !(intel_psr_check_wa_delayed_vblank(crtc_state) ||
+ intel_dp->psr.is_dc5_entry_possible)) {
+ drm_dbg_kms(&i915->drm,
+ "PSR1 not enabled as it doesn't meet requirements of WA: 22019444797\n");
+ crtc_state->has_psr = false;
+ }
+}
+
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
@@ -1641,6 +1739,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
return;
crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
+ wa_22019444797(intel_dp, crtc_state);
}
void intel_psr_get_config(struct intel_encoder *encoder,
--
2.43.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/psr: Implment WA to help reach PC10 (rev2)
2024-09-02 5:02 [PATCH] drm/i915/psr: Implment WA to help reach PC10 Suraj Kandpal
` (2 preceding siblings ...)
2024-09-03 8:24 ` Suraj Kandpal
@ 2024-09-03 10:25 ` Patchwork
2024-09-04 13:03 ` ✓ Fi.CI.IGT: " Patchwork
` (9 subsequent siblings)
13 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2024-09-03 10:25 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 10083 bytes --]
== Series Details ==
Series: drm/i915/psr: Implment WA to help reach PC10 (rev2)
URL : https://patchwork.freedesktop.org/series/138065/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15349 -> Patchwork_138065v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/index.html
Participating hosts (41 -> 35)
------------------------------
Additional (1): bat-mtlp-6
Missing (7): bat-kbl-2 fi-bsw-n3050 fi-snb-2520m fi-glk-j4005 fi-kbl-8809g bat-dg2-11 bat-jsl-1
Known issues
------------
Here are the changes found in Patchwork_138065v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-mtlp-6: NOTRUN -> [SKIP][1] ([i915#9318])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-mtlp-6/igt@debugfs_test@basic-hwmon.html
* igt@fbdev@info:
- bat-mtlp-6: NOTRUN -> [SKIP][2] ([i915#1849] / [i915#2582])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-mtlp-6/igt@fbdev@info.html
* igt@fbdev@read:
- bat-arls-1: [PASS][3] -> [DMESG-WARN][4] ([i915#12102])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/bat-arls-1/igt@fbdev@read.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-arls-1/igt@fbdev@read.html
* igt@fbdev@write:
- bat-mtlp-6: NOTRUN -> [SKIP][5] ([i915#2582]) +3 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-mtlp-6/igt@fbdev@write.html
* igt@gem_lmem_swapping@verify-random:
- bat-mtlp-6: NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-mtlp-6/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap@basic:
- bat-mtlp-6: NOTRUN -> [SKIP][7] ([i915#4083])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-mtlp-6/igt@gem_mmap@basic.html
* igt@gem_tiled_blits@basic:
- bat-mtlp-6: NOTRUN -> [SKIP][8] ([i915#4077]) +2 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-mtlp-6/igt@gem_tiled_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-mtlp-6: NOTRUN -> [SKIP][9] ([i915#4079]) +1 other test skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-mtlp-6/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rps@basic-api:
- bat-mtlp-6: NOTRUN -> [SKIP][10] ([i915#11681] / [i915#6621])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-mtlp-6/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@hangcheck:
- bat-arls-1: [PASS][11] -> [DMESG-WARN][12] ([i915#11349])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/bat-arls-1/igt@i915_selftest@live@hangcheck.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-arls-1/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@workarounds:
- bat-mtlp-8: [PASS][13] -> [ABORT][14] ([i915#12062])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/bat-mtlp-8/igt@i915_selftest@live@workarounds.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-mtlp-8/igt@i915_selftest@live@workarounds.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-mtlp-6: NOTRUN -> [SKIP][15] ([i915#4212] / [i915#9792]) +8 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-mtlp-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-mtlp-6: NOTRUN -> [SKIP][16] ([i915#5190] / [i915#9792])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-mtlp-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- bat-mtlp-6: NOTRUN -> [SKIP][17] ([i915#9792]) +17 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-mtlp-6/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@kms_flip@basic-flip-vs-dpms:
- bat-mtlp-6: NOTRUN -> [SKIP][18] ([i915#3637] / [i915#9792]) +3 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-mtlp-6/igt@kms_flip@basic-flip-vs-dpms.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-mtlp-6: NOTRUN -> [SKIP][19] ([i915#5274] / [i915#9792])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-mtlp-6/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_frontbuffer_tracking@basic:
- bat-mtlp-6: NOTRUN -> [SKIP][20] ([i915#4342] / [i915#5354] / [i915#9792])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-mtlp-6/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pm_backlight@basic-brightness:
- bat-mtlp-6: NOTRUN -> [SKIP][21] ([i915#5354] / [i915#9792])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-mtlp-6/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_psr@psr-cursor-plane-move:
- bat-mtlp-6: NOTRUN -> [SKIP][22] ([i915#1072] / [i915#9673] / [i915#9732] / [i915#9792]) +3 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-mtlp-6/igt@kms_psr@psr-cursor-plane-move.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-mtlp-6: NOTRUN -> [SKIP][23] ([i915#3555] / [i915#8809] / [i915#9792])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-mtlp-6/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-mtlp-6: NOTRUN -> [SKIP][24] ([i915#3708] / [i915#9792])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-mtlp-6/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-mtlp-6: NOTRUN -> [SKIP][25] ([i915#3708] / [i915#4077]) +1 other test skip
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-mtlp-6/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-read:
- bat-mtlp-6: NOTRUN -> [SKIP][26] ([i915#3708]) +1 other test skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-mtlp-6/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-write:
- bat-mtlp-6: NOTRUN -> [SKIP][27] ([i915#10216] / [i915#3708])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-mtlp-6/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@fbdev@info:
- bat-arls-1: [DMESG-WARN][28] ([i915#12102]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/bat-arls-1/igt@fbdev@info.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-arls-1/igt@fbdev@info.html
#### Warnings ####
* igt@i915_module_load@reload:
- bat-apl-1: [DMESG-WARN][30] ([i915#180]) -> [DMESG-WARN][31] ([i915#180] / [i915#1982])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/bat-apl-1/igt@i915_module_load@reload.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/bat-apl-1/igt@i915_module_load@reload.html
[i915#10216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10216
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#11349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11349
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#12062]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12062
[i915#12102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12102
[i915#180]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/180
[i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#2582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2582
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4342]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4342
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
[i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
[i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
[i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9792]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9792
Build changes
-------------
* Linux: CI_DRM_15349 -> Patchwork_138065v2
CI-20190529: 20190529
CI_DRM_15349: dd987a9431a336ddbfc6bfe9720f4783a6bc94b0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8001: d3a77fc98e89cc94b03be2b0903d44f83480b8a0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_138065v2: dd987a9431a336ddbfc6bfe9720f4783a6bc94b0 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/index.html
[-- Attachment #2: Type: text/html, Size: 12569 bytes --]
^ permalink raw reply [flat|nested] 47+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/psr: Implment WA to help reach PC10 (rev2)
2024-09-02 5:02 [PATCH] drm/i915/psr: Implment WA to help reach PC10 Suraj Kandpal
` (3 preceding siblings ...)
2024-09-03 10:25 ` ✓ Fi.CI.BAT: success for drm/i915/psr: Implment WA to help reach PC10 (rev2) Patchwork
@ 2024-09-04 13:03 ` Patchwork
2024-09-05 5:18 ` ✓ Fi.CI.BAT: success for drm/i915/psr: Implment WA to help reach PC10 (rev3) Patchwork
` (8 subsequent siblings)
13 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2024-09-04 13:03 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 86854 bytes --]
== Series Details ==
Series: drm/i915/psr: Implment WA to help reach PC10 (rev2)
URL : https://patchwork.freedesktop.org/series/138065/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15349_full -> Patchwork_138065v2_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
New tests
---------
New tests have been introduced between CI_DRM_15349_full and Patchwork_138065v2_full:
### New IGT tests (3) ###
* igt@kms_cursor_crc@cursor-offscreen-128x42@pipe-b-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [2.56] s
* igt@kms_cursor_crc@cursor-random-256x256@pipe-b-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [4.06] s
* igt@kms_cursor_crc@cursor-sliding-256x85@pipe-b-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [3.91] s
Known issues
------------
Here are the changes found in Patchwork_138065v2_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@device_reset@cold-reset-bound:
- shard-dg1: NOTRUN -> [SKIP][1] ([i915#11078])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@device_reset@cold-reset-bound.html
- shard-mtlp: NOTRUN -> [SKIP][2] ([i915#11078])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@device_reset@cold-reset-bound.html
- shard-rkl: NOTRUN -> [SKIP][3] ([i915#11078])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-5/igt@device_reset@cold-reset-bound.html
* igt@drm_fdinfo@isolation@vecs0:
- shard-dg1: NOTRUN -> [SKIP][4] ([i915#8414]) +15 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@drm_fdinfo@isolation@vecs0.html
* igt@drm_fdinfo@most-busy-idle-check-all@vecs1:
- shard-dg2: NOTRUN -> [SKIP][5] ([i915#8414]) +20 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@drm_fdinfo@most-busy-idle-check-all@vecs1.html
* igt@gem_bad_reloc@negative-reloc-bltcopy:
- shard-dg2: NOTRUN -> [SKIP][6] ([i915#3281]) +5 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@gem_bad_reloc@negative-reloc-bltcopy.html
* igt@gem_busy@semaphore:
- shard-dg1: NOTRUN -> [SKIP][7] ([i915#3936])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@gem_busy@semaphore.html
- shard-mtlp: NOTRUN -> [SKIP][8] ([i915#3936])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@gem_busy@semaphore.html
* igt@gem_ccs@block-copy-compressed:
- shard-tglu: NOTRUN -> [SKIP][9] ([i915#3555] / [i915#9323])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-9/igt@gem_ccs@block-copy-compressed.html
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-dg1: NOTRUN -> [SKIP][10] ([i915#9323])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
* igt@gem_ctx_engines@invalid-engines:
- shard-rkl: [PASS][11] -> [FAIL][12] ([i915#12027])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-rkl-6/igt@gem_ctx_engines@invalid-engines.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-5/igt@gem_ctx_engines@invalid-engines.html
- shard-tglu: NOTRUN -> [FAIL][13] ([i915#12027])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-9/igt@gem_ctx_engines@invalid-engines.html
* igt@gem_ctx_persistence@heartbeat-hang:
- shard-dg1: NOTRUN -> [SKIP][14] ([i915#8555]) +1 other test skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@gem_ctx_persistence@heartbeat-hang.html
* igt@gem_ctx_persistence@heartbeat-stop:
- shard-mtlp: NOTRUN -> [SKIP][15] ([i915#8555])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-2/igt@gem_ctx_persistence@heartbeat-stop.html
* igt@gem_ctx_sseu@invalid-args:
- shard-dg2: NOTRUN -> [SKIP][16] ([i915#280])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-7/igt@gem_ctx_sseu@invalid-args.html
- shard-rkl: NOTRUN -> [SKIP][17] ([i915#280])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-3/igt@gem_ctx_sseu@invalid-args.html
* igt@gem_eio@reset-stress:
- shard-dg1: [PASS][18] -> [FAIL][19] ([i915#5784])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg1-17/igt@gem_eio@reset-stress.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-13/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@bonded-semaphore:
- shard-dg2: NOTRUN -> [SKIP][20] ([i915#4812])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-2/igt@gem_exec_balancer@bonded-semaphore.html
* igt@gem_exec_fair@basic-none:
- shard-dg1: NOTRUN -> [SKIP][21] ([i915#3539] / [i915#4852]) +4 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-16/igt@gem_exec_fair@basic-none.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: NOTRUN -> [FAIL][22] ([i915#2842]) +3 other tests fail
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-glk6/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglu: [PASS][23] -> [FAIL][24] ([i915#2842])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-tglu-5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-9/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo:
- shard-dg2: NOTRUN -> [SKIP][25] ([i915#3539])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-7/igt@gem_exec_fair@basic-pace-solo.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglu: NOTRUN -> [FAIL][26] ([i915#2842]) +4 other tests fail
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-9/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-rkl: [PASS][27] -> [FAIL][28] ([i915#2842]) +3 other tests fail
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-rkl-6/igt@gem_exec_fair@basic-pace@rcs0.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-5/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fence@submit67:
- shard-mtlp: NOTRUN -> [SKIP][29] ([i915#4812])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@gem_exec_fence@submit67.html
* igt@gem_exec_flush@basic-uc-ro-default:
- shard-dg2: NOTRUN -> [SKIP][30] ([i915#3539] / [i915#4852]) +3 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-7/igt@gem_exec_flush@basic-uc-ro-default.html
* igt@gem_exec_flush@basic-uc-set-default:
- shard-dg1: NOTRUN -> [SKIP][31] ([i915#3539])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@gem_exec_flush@basic-uc-set-default.html
* igt@gem_exec_reloc@basic-cpu-gtt-active:
- shard-mtlp: NOTRUN -> [SKIP][32] ([i915#3281])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@gem_exec_reloc@basic-cpu-gtt-active.html
* igt@gem_exec_reloc@basic-wc-read-noreloc:
- shard-rkl: NOTRUN -> [SKIP][33] ([i915#3281]) +3 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-3/igt@gem_exec_reloc@basic-wc-read-noreloc.html
* igt@gem_exec_reloc@basic-write-read:
- shard-dg1: NOTRUN -> [SKIP][34] ([i915#3281]) +5 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@gem_exec_reloc@basic-write-read.html
* igt@gem_exec_schedule@semaphore-power:
- shard-dg1: NOTRUN -> [SKIP][35] ([i915#4812]) +3 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_fence_thrash@bo-copy:
- shard-mtlp: NOTRUN -> [SKIP][36] ([i915#4860])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@gem_fence_thrash@bo-copy.html
* igt@gem_fenced_exec_thrash@no-spare-fences-busy:
- shard-dg1: NOTRUN -> [SKIP][37] ([i915#4860]) +4 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@gem_fenced_exec_thrash@no-spare-fences-busy.html
* igt@gem_fenced_exec_thrash@too-many-fences:
- shard-dg2: NOTRUN -> [SKIP][38] ([i915#4860])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@gem_fenced_exec_thrash@too-many-fences.html
* igt@gem_lmem_swapping@basic:
- shard-mtlp: NOTRUN -> [SKIP][39] ([i915#4613]) +1 other test skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@heavy-verify-multi:
- shard-rkl: NOTRUN -> [SKIP][40] ([i915#4613]) +3 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-3/igt@gem_lmem_swapping@heavy-verify-multi.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs:
- shard-glk: NOTRUN -> [SKIP][41] ([i915#4613]) +2 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-glk5/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-tglu: NOTRUN -> [SKIP][42] ([i915#4613])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-9/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg1: NOTRUN -> [TIMEOUT][43] ([i915#5493])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_lmem_swapping@verify-random-ccs@lmem0:
- shard-dg1: NOTRUN -> [SKIP][44] ([i915#4565]) +2 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@gem_lmem_swapping@verify-random-ccs@lmem0.html
* igt@gem_madvise@dontneed-before-pwrite:
- shard-rkl: NOTRUN -> [SKIP][45] ([i915#3282]) +1 other test skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-3/igt@gem_madvise@dontneed-before-pwrite.html
* igt@gem_mmap_gtt@fault-concurrent-y:
- shard-mtlp: NOTRUN -> [SKIP][46] ([i915#4077]) +1 other test skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@gem_mmap_gtt@fault-concurrent-y.html
* igt@gem_mmap_gtt@hang:
- shard-dg2: NOTRUN -> [SKIP][47] ([i915#4077]) +5 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@gem_mmap_gtt@hang.html
* igt@gem_mmap_wc@fault-concurrent:
- shard-dg2: NOTRUN -> [SKIP][48] ([i915#4083]) +3 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@gem_mmap_wc@fault-concurrent.html
* igt@gem_mmap_wc@read-write:
- shard-mtlp: NOTRUN -> [SKIP][49] ([i915#4083]) +1 other test skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@gem_mmap_wc@read-write.html
* igt@gem_mmap_wc@write-read:
- shard-dg1: NOTRUN -> [SKIP][50] ([i915#4083]) +5 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@gem_mmap_wc@write-read.html
* igt@gem_pread@exhaustion:
- shard-dg1: NOTRUN -> [SKIP][51] ([i915#3282]) +8 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@gem_pread@exhaustion.html
- shard-glk: NOTRUN -> [WARN][52] ([i915#2658])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-glk1/igt@gem_pread@exhaustion.html
* igt@gem_pread@uncached:
- shard-dg2: NOTRUN -> [SKIP][53] ([i915#3282]) +1 other test skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@gem_pread@uncached.html
* igt@gem_pxp@create-protected-buffer:
- shard-rkl: NOTRUN -> [SKIP][54] ([i915#4270]) +3 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-5/igt@gem_pxp@create-protected-buffer.html
* igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
- shard-dg2: NOTRUN -> [SKIP][55] ([i915#4270]) +2 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-7/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
* igt@gem_pxp@fail-invalid-protected-context:
- shard-tglu: NOTRUN -> [SKIP][56] ([i915#4270])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-9/igt@gem_pxp@fail-invalid-protected-context.html
* igt@gem_pxp@verify-pxp-stale-ctx-execution:
- shard-dg1: NOTRUN -> [SKIP][57] ([i915#4270]) +2 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@gem_pxp@verify-pxp-stale-ctx-execution.html
- shard-mtlp: NOTRUN -> [SKIP][58] ([i915#4270]) +1 other test skip
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@gem_pxp@verify-pxp-stale-ctx-execution.html
* igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][59] ([i915#5190] / [i915#8428]) +3 other tests skip
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs.html
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled:
- shard-mtlp: NOTRUN -> [SKIP][60] ([i915#8428]) +1 other test skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-2/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled.html
* igt@gem_set_tiling_vs_blt@untiled-to-tiled:
- shard-dg1: NOTRUN -> [SKIP][61] ([i915#4079]) +1 other test skip
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
* igt@gem_tiled_partial_pwrite_pread@writes-after-reads:
- shard-dg1: NOTRUN -> [SKIP][62] ([i915#4077]) +6 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@gem_tiled_partial_pwrite_pread@writes-after-reads.html
* igt@gem_tiled_pread_basic:
- shard-dg2: NOTRUN -> [SKIP][63] ([i915#4079]) +1 other test skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@gem_tiled_pread_basic.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-dg1: NOTRUN -> [SKIP][64] ([i915#3297]) +2 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-mtlp: NOTRUN -> [SKIP][65] ([i915#3297]) +1 other test skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@gem_userptr_blits@dmabuf-sync.html
- shard-rkl: NOTRUN -> [SKIP][66] ([i915#3297] / [i915#3323])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-5/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-dg1: NOTRUN -> [SKIP][67] ([i915#3297] / [i915#4880]) +2 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@sd-probe:
- shard-dg2: NOTRUN -> [SKIP][68] ([i915#3297] / [i915#4958])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@gem_userptr_blits@sd-probe.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-dg2: NOTRUN -> [SKIP][69] ([i915#3297])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-tglu: NOTRUN -> [SKIP][70] ([i915#2527] / [i915#2856])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-9/igt@gen9_exec_parse@bb-start-cmd.html
* igt@gen9_exec_parse@shadow-peek:
- shard-dg1: NOTRUN -> [SKIP][71] ([i915#2527]) +1 other test skip
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@gen9_exec_parse@shadow-peek.html
* igt@gen9_exec_parse@valid-registers:
- shard-dg2: NOTRUN -> [SKIP][72] ([i915#2856]) +2 other tests skip
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-2/igt@gen9_exec_parse@valid-registers.html
* igt@i915_fb_tiling:
- shard-mtlp: NOTRUN -> [SKIP][73] ([i915#4881])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@i915_fb_tiling.html
- shard-dg1: NOTRUN -> [SKIP][74] ([i915#4881])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@i915_fb_tiling.html
* igt@i915_module_load@load:
- shard-dg1: NOTRUN -> [SKIP][75] ([i915#6227])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@i915_module_load@load.html
* igt@i915_pm_freq_mult@media-freq@gt0:
- shard-dg1: NOTRUN -> [SKIP][76] ([i915#6590])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@i915_pm_freq_mult@media-freq@gt0.html
* igt@i915_pm_rps@min-max-config-loaded:
- shard-dg2: NOTRUN -> [SKIP][77] ([i915#11681] / [i915#6621])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@i915_pm_rps@min-max-config-loaded.html
* igt@i915_pm_rps@thresholds-idle:
- shard-dg2: NOTRUN -> [SKIP][78] ([i915#11681])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-2/igt@i915_pm_rps@thresholds-idle.html
* igt@i915_pm_sseu@full-enable:
- shard-tglu: NOTRUN -> [SKIP][79] ([i915#4387])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-9/igt@i915_pm_sseu@full-enable.html
* igt@i915_query@hwconfig_table:
- shard-dg1: NOTRUN -> [SKIP][80] ([i915#6245])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@i915_query@hwconfig_table.html
- shard-rkl: NOTRUN -> [SKIP][81] ([i915#6245])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-5/igt@i915_query@hwconfig_table.html
* igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- shard-mtlp: NOTRUN -> [SKIP][82] ([i915#4212])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
- shard-dg1: NOTRUN -> [SKIP][83] ([i915#4212]) +1 other test skip
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- shard-dg2: NOTRUN -> [SKIP][84] ([i915#4212])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-2/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-4-y-rc-ccs:
- shard-dg1: NOTRUN -> [SKIP][85] ([i915#8709]) +7 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-4-y-rc-ccs.html
* igt@kms_async_flips@invalid-async-flip:
- shard-dg2: NOTRUN -> [SKIP][86] ([i915#6228])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-7/igt@kms_async_flips@invalid-async-flip.html
* igt@kms_atomic_transition@modeset-transition-fencing@2x-outputs:
- shard-glk: [PASS][87] -> [FAIL][88] ([i915#11859])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-glk7/igt@kms_atomic_transition@modeset-transition-fencing@2x-outputs.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-glk8/igt@kms_atomic_transition@modeset-transition-fencing@2x-outputs.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-1:
- shard-snb: [PASS][89] -> [FAIL][90] ([i915#5956])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-snb2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-1.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-snb2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-1.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-dg1: NOTRUN -> [SKIP][91] ([i915#1769] / [i915#3555])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-270:
- shard-mtlp: NOTRUN -> [SKIP][92] +7 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-270:
- shard-tglu: NOTRUN -> [SKIP][93] ([i915#5286]) +1 other test skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-9/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-90:
- shard-dg1: NOTRUN -> [SKIP][94] ([i915#4538] / [i915#5286]) +5 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
- shard-dg1: NOTRUN -> [SKIP][95] ([i915#5286])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-rkl: NOTRUN -> [SKIP][96] ([i915#5286]) +2 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][97] ([i915#3638])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-5/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][98] ([i915#4538] / [i915#5190]) +8 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@kms_big_fb@y-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-270:
- shard-dg1: NOTRUN -> [SKIP][99] ([i915#3638]) +4 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-dg2: NOTRUN -> [SKIP][100] ([i915#5190]) +1 other test skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-2/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
- shard-dg1: NOTRUN -> [SKIP][101] ([i915#4538]) +4 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-addfb:
- shard-mtlp: NOTRUN -> [SKIP][102] ([i915#6187])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@kms_big_fb@yf-tiled-addfb.html
* igt@kms_big_joiner@basic-force-joiner:
- shard-dg1: NOTRUN -> [SKIP][103] ([i915#10656])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@kms_big_joiner@basic-force-joiner.html
* igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
- shard-dg2: NOTRUN -> [SKIP][104] ([i915#12042])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html
* igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][105] ([i915#6095]) +15 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-9/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-1.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][106] ([i915#6095]) +111 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-16/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4.html
* igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][107] ([i915#10307] / [i915#6095]) +139 other tests skip
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-5/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-3.html
* igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][108] ([i915#10307] / [i915#10434] / [i915#6095]) +3 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-10/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs:
- shard-dg1: NOTRUN -> [SKIP][109] ([i915#12042]) +1 other test skip
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][110] ([i915#6095]) +15 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-edp-1.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][111] ([i915#6095]) +69 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-1/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_cdclk@mode-transition:
- shard-dg1: NOTRUN -> [SKIP][112] ([i915#3742])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@kms_cdclk@mode-transition.html
* igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][113] ([i915#4087]) +3 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-7/igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3.html
* igt@kms_chamelium_frames@dp-crc-single:
- shard-dg1: NOTRUN -> [SKIP][114] ([i915#7828]) +9 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@kms_chamelium_frames@dp-crc-single.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- shard-dg2: NOTRUN -> [SKIP][115] ([i915#7828]) +7 other tests skip
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-2/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_chamelium_frames@hdmi-crc-multiple:
- shard-mtlp: NOTRUN -> [SKIP][116] ([i915#7828])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@kms_chamelium_frames@hdmi-crc-multiple.html
* igt@kms_chamelium_frames@hdmi-crc-single:
- shard-rkl: NOTRUN -> [SKIP][117] ([i915#7828]) +2 other tests skip
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-3/igt@kms_chamelium_frames@hdmi-crc-single.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- shard-tglu: NOTRUN -> [SKIP][118] ([i915#7828]) +1 other test skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-9/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_content_protection@atomic:
- shard-dg2: NOTRUN -> [SKIP][119] ([i915#7118] / [i915#9424])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-4/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@content-type-change:
- shard-dg2: NOTRUN -> [SKIP][120] ([i915#9424])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-2/igt@kms_content_protection@content-type-change.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-rkl: NOTRUN -> [SKIP][121] ([i915#3116])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-5/igt@kms_content_protection@dp-mst-type-0.html
- shard-dg1: NOTRUN -> [SKIP][122] ([i915#3299]) +1 other test skip
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@kms_content_protection@dp-mst-type-0.html
- shard-mtlp: NOTRUN -> [SKIP][123] ([i915#3299])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_cursor_crc@cursor-offscreen-32x32:
- shard-tglu: NOTRUN -> [SKIP][124] ([i915#3555]) +1 other test skip
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-9/igt@kms_cursor_crc@cursor-offscreen-32x32.html
* igt@kms_cursor_crc@cursor-onscreen-128x42:
- shard-mtlp: NOTRUN -> [SKIP][125] ([i915#8814])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-2/igt@kms_cursor_crc@cursor-onscreen-128x42.html
* igt@kms_cursor_crc@cursor-onscreen-max-size:
- shard-dg2: NOTRUN -> [SKIP][126] ([i915#3555]) +4 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-2/igt@kms_cursor_crc@cursor-onscreen-max-size.html
* igt@kms_cursor_crc@cursor-random-32x32:
- shard-dg1: NOTRUN -> [SKIP][127] ([i915#3555]) +6 other tests skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@kms_cursor_crc@cursor-random-32x32.html
- shard-mtlp: NOTRUN -> [SKIP][128] ([i915#3555] / [i915#8814])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@kms_cursor_crc@cursor-random-32x32.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-dg2: NOTRUN -> [SKIP][129] ([i915#11453])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-mtlp: NOTRUN -> [SKIP][130] ([i915#3359])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@kms_cursor_crc@cursor-sliding-512x170.html
- shard-rkl: NOTRUN -> [SKIP][131] ([i915#11453])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-5/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-dg1: NOTRUN -> [SKIP][132] ([i915#11453]) +3 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-rkl: NOTRUN -> [SKIP][133] ([i915#4103])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
- shard-mtlp: NOTRUN -> [SKIP][134] ([i915#9809])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
* igt@kms_dirtyfb@psr-dirtyfb-ioctl:
- shard-dg2: NOTRUN -> [SKIP][135] ([i915#9833])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
* igt@kms_dp_aux_dev:
- shard-dg2: [PASS][136] -> [SKIP][137] ([i915#1257])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-11/igt@kms_dp_aux_dev.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-4/igt@kms_dp_aux_dev.html
* igt@kms_dsc@dsc-basic:
- shard-tglu: NOTRUN -> [SKIP][138] ([i915#3555] / [i915#3840])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-9/igt@kms_dsc@dsc-basic.html
* igt@kms_dsc@dsc-fractional-bpp-with-bpc:
- shard-dg2: NOTRUN -> [SKIP][139] ([i915#3840])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-dg2: NOTRUN -> [SKIP][140] ([i915#3840] / [i915#9053])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-5/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
- shard-dg1: NOTRUN -> [SKIP][141] ([i915#3840] / [i915#9053])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_feature_discovery@display-2x:
- shard-dg1: NOTRUN -> [SKIP][142] ([i915#1839])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@kms_feature_discovery@display-2x.html
* igt@kms_feature_discovery@display-4x:
- shard-dg2: NOTRUN -> [SKIP][143] ([i915#1839])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-2/igt@kms_feature_discovery@display-4x.html
* igt@kms_feature_discovery@dp-mst:
- shard-dg2: NOTRUN -> [SKIP][144] ([i915#9337])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-7/igt@kms_feature_discovery@dp-mst.html
- shard-rkl: NOTRUN -> [SKIP][145] ([i915#9337])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-3/igt@kms_feature_discovery@dp-mst.html
* igt@kms_feature_discovery@psr1:
- shard-dg2: NOTRUN -> [SKIP][146] ([i915#658])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-2/igt@kms_feature_discovery@psr1.html
* igt@kms_fence_pin_leak:
- shard-dg2: NOTRUN -> [SKIP][147] ([i915#4881])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-2/igt@kms_fence_pin_leak.html
* igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][148] ([i915#3637]) +3 other tests skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html
* igt@kms_flip@2x-flip-vs-modeset-vs-hang:
- shard-dg2: NOTRUN -> [SKIP][149] +8 other tests skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-7/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-tglu: NOTRUN -> [SKIP][150] ([i915#3637]) +2 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-9/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-dg1: NOTRUN -> [SKIP][151] ([i915#9934]) +8 other tests skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip@flip-vs-fences:
- shard-dg2: NOTRUN -> [SKIP][152] ([i915#8381]) +1 other test skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-2/igt@kms_flip@flip-vs-fences.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][153] ([i915#2672])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][154] ([i915#2587] / [i915#2672]) +6 other tests skip
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][155] ([i915#2672]) +2 other tests skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt:
- shard-mtlp: NOTRUN -> [SKIP][156] ([i915#1825]) +5 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render:
- shard-tglu: NOTRUN -> [SKIP][157] +19 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-9/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][158] +18 other tests skip
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][159] ([i915#8708]) +13 other tests skip
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-plflip-blt:
- shard-dg2: NOTRUN -> [SKIP][160] ([i915#5354]) +23 other tests skip
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt:
- shard-rkl: NOTRUN -> [SKIP][161] ([i915#1825]) +16 other tests skip
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-pwrite:
- shard-dg1: NOTRUN -> [SKIP][162] +47 other tests skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@pipe-fbc-rte:
- shard-dg1: NOTRUN -> [SKIP][163] ([i915#9766])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
- shard-rkl: NOTRUN -> [SKIP][164] ([i915#3023]) +8 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][165] ([i915#8708]) +16 other tests skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][166] ([i915#3458]) +9 other tests skip
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][167] ([i915#8708]) +1 other test skip
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite:
- shard-dg1: NOTRUN -> [SKIP][168] ([i915#3458]) +22 other tests skip
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite.html
* igt@kms_hdmi_inject@inject-audio:
- shard-dg1: NOTRUN -> [SKIP][169] ([i915#433])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-dg2: NOTRUN -> [SKIP][170] ([i915#3555] / [i915#8228]) +2 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_panel_fitting@atomic-fastset:
- shard-rkl: NOTRUN -> [SKIP][171] ([i915#6301])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-3/igt@kms_panel_fitting@atomic-fastset.html
* igt@kms_plane_multiple@tiling-yf:
- shard-dg2: NOTRUN -> [SKIP][172] ([i915#3555] / [i915#8806])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-2/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [FAIL][173] ([i915#8292])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-2/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][174] ([i915#9423]) +3 other tests skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-hdmi-a-4.html
* igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][175] ([i915#9423]) +5 other tests skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-5/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-d-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][176] ([i915#9423]) +7 other tests skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-9/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-d-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][177] ([i915#5235]) +1 other test skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-1/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][178] ([i915#5235]) +2 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-16/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c-hdmi-a-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][179] ([i915#9728]) +16 other tests skip
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-13/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-3.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][180] ([i915#9423]) +27 other tests skip
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-3/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][181] ([i915#5235]) +5 other tests skip
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-b-edp-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][182] ([i915#3555] / [i915#5235]) +1 other test skip
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-d-edp-1.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][183] ([i915#9728]) +5 other tests skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-5/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-2.html
* igt@kms_pm_backlight@fade:
- shard-dg1: NOTRUN -> [SKIP][184] ([i915#5354])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@kms_pm_backlight@fade.html
* igt@kms_pm_dc@dc6-dpms:
- shard-dg2: NOTRUN -> [SKIP][185] ([i915#5978])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-2/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-dg2: NOTRUN -> [SKIP][186] ([i915#9340])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@kms_pm_lpsp@kms-lpsp.html
- shard-rkl: NOTRUN -> [SKIP][187] ([i915#9340])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-1/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-dg2: [PASS][188] -> [SKIP][189] ([i915#9519]) +2 other tests skip
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-4/igt@kms_pm_rpm@dpms-lpsp.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-5/igt@kms_pm_rpm@dpms-lpsp.html
- shard-dg1: NOTRUN -> [SKIP][190] ([i915#9519]) +1 other test skip
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@dpms-non-lpsp:
- shard-tglu: NOTRUN -> [SKIP][191] ([i915#9519])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-9/igt@kms_pm_rpm@dpms-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-mtlp: NOTRUN -> [SKIP][192] ([i915#9519])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_prime@basic-modeset-hybrid:
- shard-tglu: NOTRUN -> [SKIP][193] ([i915#6524])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-9/igt@kms_prime@basic-modeset-hybrid.html
* igt@kms_prime@d3hot:
- shard-rkl: NOTRUN -> [SKIP][194] ([i915#6524])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-5/igt@kms_prime@d3hot.html
- shard-dg1: NOTRUN -> [SKIP][195] ([i915#6524])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@kms_prime@d3hot.html
- shard-mtlp: NOTRUN -> [SKIP][196] ([i915#6524])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@kms_prime@d3hot.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf:
- shard-rkl: NOTRUN -> [SKIP][197] ([i915#11520]) +2 other tests skip
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-3/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-sf:
- shard-dg2: NOTRUN -> [SKIP][198] ([i915#11520]) +4 other tests skip
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-snb: NOTRUN -> [SKIP][199] +27 other tests skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-snb6/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
- shard-dg1: NOTRUN -> [SKIP][200] ([i915#11520]) +3 other tests skip
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-tglu: NOTRUN -> [SKIP][201] ([i915#9683])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-9/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-dg1: NOTRUN -> [SKIP][202] ([i915#9683])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@fbc-psr2-cursor-mmap-gtt:
- shard-glk: NOTRUN -> [SKIP][203] +190 other tests skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-glk1/igt@kms_psr@fbc-psr2-cursor-mmap-gtt.html
* igt@kms_psr@fbc-psr2-no-drrs:
- shard-tglu: NOTRUN -> [SKIP][204] ([i915#9732]) +4 other tests skip
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-9/igt@kms_psr@fbc-psr2-no-drrs.html
* igt@kms_psr@pr-cursor-plane-onoff:
- shard-rkl: NOTRUN -> [SKIP][205] ([i915#1072] / [i915#9732]) +9 other tests skip
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-5/igt@kms_psr@pr-cursor-plane-onoff.html
* igt@kms_psr@pr-sprite-blt:
- shard-mtlp: NOTRUN -> [SKIP][206] ([i915#9688]) +3 other tests skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@kms_psr@pr-sprite-blt.html
* igt@kms_psr@psr2-primary-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][207] ([i915#1072] / [i915#9732]) +13 other tests skip
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-2/igt@kms_psr@psr2-primary-mmap-gtt.html
* igt@kms_psr@psr2-sprite-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][208] ([i915#1072] / [i915#9732]) +24 other tests skip
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@kms_psr@psr2-sprite-mmap-gtt.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-dg1: NOTRUN -> [SKIP][209] ([i915#9685]) +1 other test skip
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
- shard-tglu: NOTRUN -> [SKIP][210] ([i915#5289])
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-9/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-rotation-90:
- shard-dg2: NOTRUN -> [SKIP][211] ([i915#11131])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-2/igt@kms_rotation_crc@primary-rotation-90.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-dg1: NOTRUN -> [SKIP][212] ([i915#5289]) +2 other tests skip
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_sysfs_edid_timing:
- shard-dg2: NOTRUN -> [FAIL][213] ([IGT#2])
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@kms_sysfs_edid_timing.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-dg1: NOTRUN -> [SKIP][214] ([i915#8623])
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@kms_tiled_display@basic-test-pattern.html
- shard-glk: NOTRUN -> [FAIL][215] ([i915#10959])
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-glk1/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1:
- shard-tglu: [PASS][216] -> [FAIL][217] ([i915#9196])
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-tglu-7/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-7/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
* igt@kms_vrr@flip-dpms:
- shard-rkl: NOTRUN -> [SKIP][218] ([i915#3555]) +1 other test skip
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-3/igt@kms_vrr@flip-dpms.html
* igt@kms_vrr@lobf:
- shard-dg1: NOTRUN -> [SKIP][219] ([i915#11920])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@kms_vrr@lobf.html
* igt@kms_writeback@writeback-fb-id:
- shard-dg1: NOTRUN -> [SKIP][220] ([i915#2437])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-dg1: NOTRUN -> [SKIP][221] ([i915#2437] / [i915#9412])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-dg2: NOTRUN -> [SKIP][222] ([i915#2437] / [i915#9412])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@blocking@0-rcs0:
- shard-dg2: NOTRUN -> [FAIL][223] ([i915#10538])
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-2/igt@perf@blocking@0-rcs0.html
* igt@perf@gen8-unprivileged-single-ctx-counters:
- shard-dg2: NOTRUN -> [SKIP][224] ([i915#2436])
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@perf@gen8-unprivileged-single-ctx-counters.html
* igt@perf@mi-rpc:
- shard-dg2: NOTRUN -> [SKIP][225] ([i915#2434])
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@perf@mi-rpc.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: NOTRUN -> [FAIL][226] ([i915#7484])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-5/igt@perf@non-zero-reason@0-rcs0.html
* igt@perf_pmu@busy-double-start@vecs0:
- shard-dg1: NOTRUN -> [FAIL][227] ([i915#4349]) +1 other test fail
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-16/igt@perf_pmu@busy-double-start@vecs0.html
* igt@perf_pmu@busy-double-start@vecs1:
- shard-dg2: [PASS][228] -> [FAIL][229] ([i915#4349]) +1 other test fail
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-11/igt@perf_pmu@busy-double-start@vecs1.html
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-4/igt@perf_pmu@busy-double-start@vecs1.html
* igt@perf_pmu@busy-idle@vcs0:
- shard-dg2: NOTRUN -> [FAIL][230] ([i915#4349]) +4 other tests fail
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-2/igt@perf_pmu@busy-idle@vcs0.html
* igt@perf_pmu@enable-race@vecs0:
- shard-glk: [PASS][231] -> [DMESG-WARN][232] ([i915#118])
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-glk1/igt@perf_pmu@enable-race@vecs0.html
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-glk8/igt@perf_pmu@enable-race@vecs0.html
* igt@perf_pmu@rc6@other-idle-gt0:
- shard-dg2: NOTRUN -> [SKIP][233] ([i915#8516]) +1 other test skip
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-5/igt@perf_pmu@rc6@other-idle-gt0.html
- shard-dg1: NOTRUN -> [SKIP][234] ([i915#8516])
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@perf_pmu@rc6@other-idle-gt0.html
* igt@prime_vgem@basic-fence-flip:
- shard-dg2: NOTRUN -> [SKIP][235] ([i915#3708])
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-7/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@coherency-gtt:
- shard-dg1: NOTRUN -> [SKIP][236] ([i915#3708] / [i915#4077])
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@prime_vgem@coherency-gtt.html
* igt@prime_vgem@fence-read-hang:
- shard-dg1: NOTRUN -> [SKIP][237] ([i915#3708])
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@prime_vgem@fence-read-hang.html
* igt@sriov_basic@enable-vfs-autoprobe-off:
- shard-dg2: NOTRUN -> [SKIP][238] ([i915#9917])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-2/igt@sriov_basic@enable-vfs-autoprobe-off.html
* igt@sriov_basic@enable-vfs-autoprobe-on:
- shard-mtlp: NOTRUN -> [SKIP][239] ([i915#9917])
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-4/igt@sriov_basic@enable-vfs-autoprobe-on.html
- shard-rkl: NOTRUN -> [SKIP][240] ([i915#9917]) +1 other test skip
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-5/igt@sriov_basic@enable-vfs-autoprobe-on.html
- shard-dg1: NOTRUN -> [SKIP][241] ([i915#9917])
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-15/igt@sriov_basic@enable-vfs-autoprobe-on.html
* igt@syncobj_timeline@invalid-wait-zero-handles:
- shard-dg2: NOTRUN -> [FAIL][242] ([i915#9781]) +1 other test fail
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-6/igt@syncobj_timeline@invalid-wait-zero-handles.html
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- shard-rkl: [FAIL][243] ([i915#7742]) -> [PASS][244]
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-rkl-4/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-1/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
* igt@gem_ctx_engines@invalid-engines:
- shard-glk: [FAIL][245] ([i915#12027]) -> [PASS][246]
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-glk7/igt@gem_ctx_engines@invalid-engines.html
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-glk8/igt@gem_ctx_engines@invalid-engines.html
* igt@gem_eio@in-flight-suspend:
- shard-dg1: [DMESG-WARN][247] ([i915#4391] / [i915#4423]) -> [PASS][248]
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg1-13/igt@gem_eio@in-flight-suspend.html
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-16/igt@gem_eio@in-flight-suspend.html
* igt@gem_eio@unwedge-stress:
- shard-dg2: [FAIL][249] ([i915#5784]) -> [PASS][250]
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-8/igt@gem_eio@unwedge-stress.html
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-7/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][251] ([i915#2842]) -> [PASS][252]
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_suspend@basic-s0@lmem0:
- shard-dg2: [INCOMPLETE][253] ([i915#11441]) -> [PASS][254]
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-5/igt@gem_exec_suspend@basic-s0@lmem0.html
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-7/igt@gem_exec_suspend@basic-s0@lmem0.html
* igt@gem_mmap_offset@clear@smem0:
- shard-mtlp: [INCOMPLETE][255] ([i915#5493]) -> [PASS][256]
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-mtlp-7/igt@gem_mmap_offset@clear@smem0.html
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-2/igt@gem_mmap_offset@clear@smem0.html
* igt@gem_vm_create@execbuf:
- shard-dg2: [SKIP][257] ([i915#2575]) -> [PASS][258] +8 other tests pass
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-11/igt@gem_vm_create@execbuf.html
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-4/igt@gem_vm_create@execbuf.html
* igt@i915_module_load@reload:
- shard-dg2: [FAIL][259] ([i915#12100]) -> [PASS][260]
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-11/igt@i915_module_load@reload.html
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-4/igt@i915_module_load@reload.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-glk: [ABORT][261] ([i915#9820]) -> [PASS][262]
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-glk6/igt@i915_module_load@reload-with-fault-injection.html
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-glk5/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-bcs0:
- shard-dg1: [FAIL][263] ([i915#3591]) -> [PASS][264] +1 other test pass
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@gt0-bcs0.html
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@gt0-bcs0.html
* igt@i915_pm_rps@reset:
- shard-snb: [INCOMPLETE][265] ([i915#7790]) -> [PASS][266]
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-snb4/igt@i915_pm_rps@reset.html
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-snb6/igt@i915_pm_rps@reset.html
* igt@kms_flip@plain-flip-fb-recreate@a-hdmi-a2:
- shard-rkl: [FAIL][267] ([i915#2122]) -> [PASS][268]
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-rkl-5/igt@kms_flip@plain-flip-fb-recreate@a-hdmi-a2.html
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-5/igt@kms_flip@plain-flip-fb-recreate@a-hdmi-a2.html
* igt@kms_flip@plain-flip-fb-recreate@b-hdmi-a2:
- shard-rkl: [FAIL][269] ([i915#11989]) -> [PASS][270]
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-rkl-5/igt@kms_flip@plain-flip-fb-recreate@b-hdmi-a2.html
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-5/igt@kms_flip@plain-flip-fb-recreate@b-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render:
- shard-dg2: [SKIP][271] -> [PASS][272] +2 other tests pass
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-4/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html
* igt@kms_pm_dc@dc6-dpms:
- shard-tglu: [FAIL][273] ([i915#9295]) -> [PASS][274]
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-tglu-9/igt@kms_pm_dc@dc6-dpms.html
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-6/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-rkl: [SKIP][275] ([i915#9519]) -> [PASS][276] +2 other tests pass
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-rkl-2/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-1/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-mtlp: [INCOMPLETE][277] -> [PASS][278]
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-mtlp-7/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-2/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1:
- shard-tglu: [FAIL][279] ([i915#9196]) -> [PASS][280]
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-tglu-7/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-tglu-7/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
* igt@perf_pmu@busy-double-start@vecs0:
- shard-mtlp: [FAIL][281] ([i915#4349]) -> [PASS][282] +1 other test pass
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-mtlp-6/igt@perf_pmu@busy-double-start@vecs0.html
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-mtlp-3/igt@perf_pmu@busy-double-start@vecs0.html
* igt@perf_pmu@rc6@runtime-pm-gt0:
- shard-dg2: [INCOMPLETE][283] ([i915#9853]) -> [PASS][284]
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-4/igt@perf_pmu@rc6@runtime-pm-gt0.html
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-5/igt@perf_pmu@rc6@runtime-pm-gt0.html
#### Warnings ####
* igt@gem_create@create-ext-cpu-access-big:
- shard-dg2: [SKIP][285] ([i915#2575]) -> [ABORT][286] ([i915#9846])
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-11/igt@gem_create@create-ext-cpu-access-big.html
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-4/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_exec_reloc@basic-cpu-read-active:
- shard-dg2: [SKIP][287] ([i915#2575]) -> [SKIP][288] ([i915#3281])
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-11/igt@gem_exec_reloc@basic-cpu-read-active.html
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-4/igt@gem_exec_reloc@basic-cpu-read-active.html
* igt@gem_exec_reloc@basic-wc-cpu-active:
- shard-dg1: [SKIP][289] ([i915#3281] / [i915#4423]) -> [SKIP][290] ([i915#3281])
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg1-13/igt@gem_exec_reloc@basic-wc-cpu-active.html
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-16/igt@gem_exec_reloc@basic-wc-cpu-active.html
* igt@gem_mmap_gtt@big-copy:
- shard-dg2: [SKIP][291] ([i915#2575]) -> [SKIP][292] ([i915#4077]) +1 other test skip
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-11/igt@gem_mmap_gtt@big-copy.html
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-4/igt@gem_mmap_gtt@big-copy.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-dg2: [SKIP][293] ([i915#2575]) -> [SKIP][294] ([i915#4270])
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-11/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-4/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_render_copy@y-tiled-ccs-to-y-tiled:
- shard-dg2: [SKIP][295] ([i915#2575] / [i915#5190]) -> [SKIP][296] ([i915#5190] / [i915#8428]) +1 other test skip
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-11/igt@gem_render_copy@y-tiled-ccs-to-y-tiled.html
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-4/igt@gem_render_copy@y-tiled-ccs-to-y-tiled.html
* igt@i915_module_load@resize-bar:
- shard-dg1: [SKIP][297] ([i915#4423] / [i915#7178]) -> [SKIP][298] ([i915#7178])
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg1-14/igt@i915_module_load@resize-bar.html
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-16/igt@i915_module_load@resize-bar.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc:
- shard-dg2: [SKIP][299] -> [SKIP][300] ([i915#8708])
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-dg2: [SKIP][301] ([i915#10433] / [i915#3458]) -> [SKIP][302] ([i915#3458]) +1 other test skip
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-move:
- shard-dg2: [SKIP][303] -> [SKIP][304] ([i915#5354])
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-move.html
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary:
- shard-dg2: [SKIP][305] ([i915#3458]) -> [SKIP][306] ([i915#10433] / [i915#3458]) +3 other tests skip
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt:
- shard-dg1: [SKIP][307] ([i915#3458] / [i915#4423]) -> [SKIP][308] ([i915#3458])
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg1-13/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt.html
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt.html
* igt@kms_hdr@static-toggle-dpms:
- shard-dg2: [SKIP][309] ([i915#2575]) -> [SKIP][310] ([i915#3555] / [i915#8228])
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-11/igt@kms_hdr@static-toggle-dpms.html
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-4/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][311] ([i915#4816]) -> [SKIP][312] ([i915#4070] / [i915#4816])
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-rkl-3/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-rkl-2/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_plane_multiple@tiling-y:
- shard-dg2: [SKIP][313] ([i915#2575]) -> [SKIP][314] ([i915#8806])
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-11/igt@kms_plane_multiple@tiling-y.html
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-4/igt@kms_plane_multiple@tiling-y.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-dg2: [SKIP][315] -> [SKIP][316] ([i915#11520])
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-11/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-4/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
* igt@kms_psr@fbc-psr-primary-mmap-cpu:
- shard-dg2: [SKIP][317] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][318] ([i915#1072] / [i915#9732]) +4 other tests skip
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-11/igt@kms_psr@fbc-psr-primary-mmap-cpu.html
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-4/igt@kms_psr@fbc-psr-primary-mmap-cpu.html
* igt@kms_psr@pr-basic:
- shard-dg2: [SKIP][319] -> [SKIP][320] ([i915#1072] / [i915#9732]) +1 other test skip
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-11/igt@kms_psr@pr-basic.html
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-4/igt@kms_psr@pr-basic.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
- shard-dg2: [SKIP][321] ([i915#11131] / [i915#4235] / [i915#5190]) -> [SKIP][322] ([i915#11131] / [i915#5190])
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-11/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-4/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
* igt@kms_setmode@basic-clone-single-crtc:
- shard-dg2: [SKIP][323] ([i915#2575]) -> [SKIP][324] ([i915#3555])
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg2-11/igt@kms_setmode@basic-clone-single-crtc.html
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg2-4/igt@kms_setmode@basic-clone-single-crtc.html
* igt@perf_pmu@busy-double-start@vcs0:
- shard-dg1: [INCOMPLETE][325] ([i915#9853]) -> [FAIL][326] ([i915#4349])
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15349/shard-dg1-13/igt@perf_pmu@busy-double-start@vcs0.html
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/shard-dg1-16/igt@perf_pmu@busy-double-start@vcs0.html
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10538
[i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#10959]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10959
[i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
[i915#11131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11131
[i915#11441]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11441
[i915#11453]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11453
[i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/118
[i915#11859]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11859
[i915#11920]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11920
[i915#11989]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11989
[i915#12027]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12027
[i915#12042]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12042
[i915#12100]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12100
[i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
[i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#2122]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2122
[i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
[i915#2436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#3936]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3936
[i915#4070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4087
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/433
[i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
[i915#4387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4387
[i915#4391]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4391
[i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4881
[i915#4958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4958
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
[i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
[i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
[i915#5978]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5978
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6187
[i915#6227]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6227
[i915#6228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6228
[i915#6245]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6245
[i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590
[i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7178]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7178
[i915#7484]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7484
[i915#7742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7742
[i915#7790]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7790
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8292]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8292
[i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
[i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
[i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
[i915#8806]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8806
[i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
[i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053
[i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
[i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
[i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
[i915#9728]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9728
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
[i915#9781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9781
[i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
[i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
[i915#9833]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9833
[i915#9846]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9846
[i915#9853]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9853
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_15349 -> Patchwork_138065v2
CI-20190529: 20190529
CI_DRM_15349: dd987a9431a336ddbfc6bfe9720f4783a6bc94b0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8001: d3a77fc98e89cc94b03be2b0903d44f83480b8a0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_138065v2: dd987a9431a336ddbfc6bfe9720f4783a6bc94b0 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v2/index.html
[-- Attachment #2: Type: text/html, Size: 107565 bytes --]
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-03 8:24 ` Suraj Kandpal
@ 2024-09-05 4:41 ` Suraj Kandpal
2024-09-09 4:54 ` Suraj Kandpal
2024-09-09 14:12 ` [PATCH] drm/i915/psr: Implment " Ville Syrjälä
1 sibling, 1 reply; 47+ messages in thread
From: Suraj Kandpal @ 2024-09-05 4:41 UTC (permalink / raw)
To: intel-gfx; +Cc: uma.shankar, jouni.hogander, Suraj Kandpal
To reach PC10 when PKG_C_LATENCY is configure we must do the following
things
1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
2) Allow PSR2 deep sleep when DC5 can be entered
3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
not happening.
--v2
-Switch condition and do an early return [Jani]
-Do some checks in compute_config [Jani]
-Do not use register reads as a method of checking states for
DPKGC or delayed vblank [Jani]
-Use another way to see is vblank interrupts are disabled or not [Jani]
--v3
-Use has_psr to check if psr can be enabled or not for dc5_entry cond
[Uma]
-Move the dc5 entry computation to psr_compute_config [Jouni]
-No need to change sequence of enabled and activate,
so dont make hsw_psr1_activate return anything [Jouni]
-Use has_psr to stop psr1 activation [Jouni]
-Use lineage no. in WA
-Add the display ver restrictions for WA
--v4
-use more appropriate name for check_vblank_limit() [Jouni]
-Cover the case for idle frames when dpkgc is not configured [Jouni]
-Check psr only for edp [Jouni]
--v5
-move psr1 handling to plane update [Jouni]
-add todo for cases when vblank is enabled when psr enabled [Jouni]
-use intel_display instead of drm_i915_private
WA: 22019444797
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/display/intel_psr.c | 107 +++++++++++++++++-
2 files changed, 109 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f29e5dc3db91..368da8778f0b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1714,6 +1714,9 @@ struct intel_psr {
#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
u32 debug;
+ bool is_dpkgc_configured;
+ bool is_dc5_entry_possible;
+ bool is_wa_delayed_vblank_limit;
bool sink_support;
bool source_support;
bool enabled;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 1f83b3b67ea6..111917ff1888 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -872,6 +872,74 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
return idle_frames;
}
+static bool
+intel_psr_check_wa_delayed_vblank(const struct drm_display_mode *adjusted_mode)
+{
+ return (adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay) >= 6;
+}
+
+/*
+ * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
+ * VRR is not enabled
+ */
+static bool intel_psr_is_dpkgc_configured(struct intel_display *display,
+ struct intel_atomic_state *state)
+{
+ struct intel_crtc *intel_crtc;
+ struct intel_crtc_state *crtc_state;
+ int i;
+
+ if (DISPLAY_VER(display) < 20)
+ return false;
+
+ for_each_new_intel_crtc_in_state(state, intel_crtc, crtc_state, i) {
+ if (!intel_crtc->active)
+ continue;
+
+ if (crtc_state->vrr.enable)
+ return false;
+ }
+
+ return true;
+}
+
+/*
+ * DC5 entry is only possible if vblank interrupt is disabled
+ * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
+ * enabled encoders.
+ */
+static bool
+intel_psr_is_dc5_entry_possible(struct intel_display *display,
+ struct intel_atomic_state *state)
+{
+ struct intel_crtc *intel_crtc;
+ struct intel_crtc_state *crtc_state;
+ int i;
+
+ for_each_new_intel_crtc_in_state(state, intel_crtc, crtc_state, i) {
+ struct drm_crtc *crtc = &intel_crtc->base;
+ struct drm_vblank_crtc *vblank;
+ struct intel_encoder *encoder;
+
+ if (!intel_crtc->active)
+ continue;
+
+ vblank = drm_crtc_vblank_crtc(crtc);
+
+ if (vblank->enabled)
+ return false;
+
+ if (crtc_state->has_psr)
+ return false;
+
+ for_each_encoder_on_crtc(display->drm, crtc, encoder)
+ if (encoder->type != INTEL_OUTPUT_EDP)
+ return false;
+ }
+
+ return true;
+}
+
static void hsw_activate_psr1(struct intel_dp *intel_dp)
{
struct intel_display *display = to_intel_display(intel_dp);
@@ -984,7 +1052,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
u32 val = EDP_PSR2_ENABLE;
u32 psr_val = 0;
- val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ /*
+ * Wa_22019444797
+ * TODO: Disable idle frames when vblank gets enabled while
+ * PSR2 is enabled
+ */
+ if (DISPLAY_VER(dev_priv) != 20 ||
+ !intel_dp->psr.is_dpkgc_configured ||
+ intel_dp->psr.is_dc5_entry_possible)
+ val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
val |= EDP_SU_TRACK_ENABLE;
@@ -2665,10 +2741,20 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_encoder *encoder;
+ bool dpkgc_configured = false, dc5_entry_possible = false;
+ bool wa_delayed_vblank_limit = false;
if (!HAS_PSR(display))
return;
+ if (DISPLAY_VER(display) == 20) {
+ dpkgc_configured = intel_psr_is_dpkgc_configured(display, state);
+ dc5_entry_possible =
+ intel_psr_is_dc5_entry_possible(display, state);
+ wa_delayed_vblank_limit =
+ intel_psr_check_wa_delayed_vblank(&new_crtc_state->hw.adjusted_mode);
+ }
+
for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
old_crtc_state->uapi.encoder_mask) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2677,6 +2763,12 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
mutex_lock(&psr->lock);
+ if (DISPLAY_VER(i915) == 20) {
+ psr->is_dpkgc_configured = dpkgc_configured;
+ psr->is_dc5_entry_possible = dc5_entry_possible;
+ psr->is_wa_delayed_vblank_limit = wa_delayed_vblank_limit;
+ }
+
/*
* Reasons to disable:
* - PSR disabled in new state
@@ -2684,6 +2776,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
* - Changing between PSR versions
* - Region Early Transport changing
* - Display WA #1136: skl, bxt
+ * - Display WA_22019444797
*/
needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
needs_to_disable |= !new_crtc_state->has_psr;
@@ -2693,6 +2786,10 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
psr->su_region_et_enabled;
needs_to_disable |= DISPLAY_VER(i915) < 11 &&
new_crtc_state->wm_level_disabled;
+ /* TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled */
+ needs_to_disable |= (DISPLAY_VER(display) != 20 || !dpkgc_configured ||
+ wa_delayed_vblank_limit || dc5_entry_possible) &&
+ !(new_crtc_state->has_sel_update || !new_crtc_state->has_panel_replay);
if (psr->enabled && needs_to_disable)
intel_psr_disable_locked(intel_dp);
@@ -2733,6 +2830,14 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
keep_disabled |= DISPLAY_VER(display) < 11 &&
crtc_state->wm_level_disabled;
+ /*
+ * Wa_22019444797
+ * TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled
+ */
+ keep_disabled |= (DISPLAY_VER(display) != 20 || !psr->is_dpkgc_configured ||
+ psr->is_wa_delayed_vblank_limit || psr->is_dc5_entry_possible) &&
+ !(crtc_state->has_sel_update || !crtc_state->has_panel_replay);
+
if (!psr->enabled && !keep_disabled)
intel_psr_enable_locked(intel_dp, crtc_state);
else if (psr->enabled && !crtc_state->wm_level_disabled)
--
2.43.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/psr: Implment WA to help reach PC10 (rev3)
2024-09-02 5:02 [PATCH] drm/i915/psr: Implment WA to help reach PC10 Suraj Kandpal
` (4 preceding siblings ...)
2024-09-04 13:03 ` ✓ Fi.CI.IGT: " Patchwork
@ 2024-09-05 5:18 ` Patchwork
2024-09-06 15:26 ` ✓ Fi.CI.IGT: " Patchwork
` (7 subsequent siblings)
13 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2024-09-05 5:18 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 2710 bytes --]
== Series Details ==
Series: drm/i915/psr: Implment WA to help reach PC10 (rev3)
URL : https://patchwork.freedesktop.org/series/138065/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15359 -> Patchwork_138065v3
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/index.html
Participating hosts (38 -> 35)
------------------------------
Additional (1): fi-bsw-n3050
Missing (4): fi-kbl-7567u bat-dg2-11 fi-snb-2520m fi-elk-e7500
Known issues
------------
Here are the changes found in Patchwork_138065v3 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_lmem_swapping@random-engines:
- fi-bsw-n3050: NOTRUN -> [SKIP][1] +19 other tests skip
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/fi-bsw-n3050/igt@gem_lmem_swapping@random-engines.html
#### Possible fixes ####
* igt@fbdev@write:
- bat-arls-1: [FAIL][2] ([i915#12030]) -> [PASS][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/bat-arls-1/igt@fbdev@write.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/bat-arls-1/igt@fbdev@write.html
* igt@i915_selftest@live@hangcheck:
- bat-arls-1: [DMESG-WARN][4] ([i915#11349]) -> [PASS][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/bat-arls-1/igt@i915_selftest@live@hangcheck.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/bat-arls-1/igt@i915_selftest@live@hangcheck.html
#### Warnings ####
* igt@fbdev@read:
- bat-arls-1: [FAIL][6] ([i915#12030]) -> [DMESG-WARN][7] ([i915#12102])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/bat-arls-1/igt@fbdev@read.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/bat-arls-1/igt@fbdev@read.html
[i915#11349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11349
[i915#12030]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12030
[i915#12102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12102
Build changes
-------------
* Linux: CI_DRM_15359 -> Patchwork_138065v3
CI-20190529: 20190529
CI_DRM_15359: 8b1096500fd6fae573f7d9c4416778d6442e985d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8005: fc3113c8c1e99797b2d4769aaf02265be64a7589 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_138065v3: 8b1096500fd6fae573f7d9c4416778d6442e985d @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/index.html
[-- Attachment #2: Type: text/html, Size: 3465 bytes --]
^ permalink raw reply [flat|nested] 47+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/psr: Implment WA to help reach PC10 (rev3)
2024-09-02 5:02 [PATCH] drm/i915/psr: Implment WA to help reach PC10 Suraj Kandpal
` (5 preceding siblings ...)
2024-09-05 5:18 ` ✓ Fi.CI.BAT: success for drm/i915/psr: Implment WA to help reach PC10 (rev3) Patchwork
@ 2024-09-06 15:26 ` Patchwork
2024-09-09 5:26 ` ✗ Fi.CI.BUILD: failure for drm/i915/psr: Implment WA to help reach PC10 (rev4) Patchwork
` (6 subsequent siblings)
13 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2024-09-06 15:26 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 69410 bytes --]
== Series Details ==
Series: drm/i915/psr: Implment WA to help reach PC10 (rev3)
URL : https://patchwork.freedesktop.org/series/138065/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15359_full -> Patchwork_138065v3_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (8 -> 9)
------------------------------
Additional (1): shard-glk-0
New tests
---------
New tests have been introduced between CI_DRM_15359_full and Patchwork_138065v3_full:
### New IGT tests (15) ###
* igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [2.50] s
* igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-d-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [2.57] s
* igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-3:
- Statuses : 2 pass(s)
- Exec time: [4.35, 4.51] s
* igt@kms_cursor_crc@cursor-random-128x42@pipe-d-hdmi-a-3:
- Statuses : 2 pass(s)
- Exec time: [4.24, 4.42] s
* igt@kms_cursor_crc@cursor-random-64x64@pipe-a-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [4.29] s
* igt@kms_cursor_crc@cursor-random-64x64@pipe-d-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [4.26] s
* igt@kms_cursor_crc@cursor-rapid-movement-128x42@pipe-a-hdmi-a-3:
- Statuses : 2 pass(s)
- Exec time: [0.47, 0.56] s
* igt@kms_cursor_crc@cursor-rapid-movement-128x42@pipe-d-hdmi-a-3:
- Statuses : 2 pass(s)
- Exec time: [0.27, 0.29] s
* igt@kms_cursor_crc@cursor-rapid-movement-256x85@pipe-a-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [0.46] s
* igt@kms_cursor_crc@cursor-rapid-movement-256x85@pipe-d-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [0.27] s
* igt@kms_cursor_crc@cursor-sliding-256x85@pipe-d-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [4.12] s
* igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [4.26] s
* igt@kms_cursor_crc@cursor-sliding-64x21@pipe-d-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [3.99] s
* igt@kms_rmfb@close-fd@pipe-a-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [0.16] s
* igt@kms_rmfb@close-fd@pipe-d-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
Known issues
------------
Here are the changes found in Patchwork_138065v3_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-purge-cache:
- shard-dg2: NOTRUN -> [SKIP][1] ([i915#8411])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@api_intel_bb@blit-reloc-purge-cache.html
* igt@debugfs_test@basic-hwmon:
- shard-rkl: NOTRUN -> [SKIP][2] ([i915#9318])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-4/igt@debugfs_test@basic-hwmon.html
* igt@device_reset@cold-reset-bound:
- shard-dg2: NOTRUN -> [SKIP][3] ([i915#11078])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-7/igt@device_reset@cold-reset-bound.html
* igt@drm_fdinfo@busy-idle@bcs0:
- shard-dg2: NOTRUN -> [SKIP][4] ([i915#8414]) +10 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@drm_fdinfo@busy-idle@bcs0.html
* igt@drm_fdinfo@idle@rcs0:
- shard-rkl: [PASS][5] -> [FAIL][6] ([i915#7742])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-rkl-5/igt@drm_fdinfo@idle@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-3/igt@drm_fdinfo@idle@rcs0.html
* igt@drm_fdinfo@most-busy-check-all@bcs0:
- shard-dg1: NOTRUN -> [SKIP][7] ([i915#8414]) +9 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@drm_fdinfo@most-busy-check-all@bcs0.html
* igt@gem_close_race@multigpu-basic-process:
- shard-dg2: NOTRUN -> [SKIP][8] ([i915#7697])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-7/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_close_race@multigpu-basic-threads:
- shard-rkl: NOTRUN -> [SKIP][9] ([i915#7697])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-6/igt@gem_close_race@multigpu-basic-threads.html
- shard-dg1: NOTRUN -> [SKIP][10] ([i915#7697])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@gem_close_race@multigpu-basic-threads.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-dg2: NOTRUN -> [ABORT][11] ([i915#9846])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-10/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_ctx_freq@sysfs@gt0:
- shard-dg2: NOTRUN -> [FAIL][12] ([i915#9561])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@gem_ctx_freq@sysfs@gt0.html
* igt@gem_ctx_persistence@heartbeat-stop:
- shard-dg1: NOTRUN -> [SKIP][13] ([i915#8555]) +2 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@gem_ctx_persistence@heartbeat-stop.html
* igt@gem_ctx_persistence@legacy-engines-hostile-preempt:
- shard-snb: NOTRUN -> [SKIP][14] ([i915#1099]) +3 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-snb4/igt@gem_ctx_persistence@legacy-engines-hostile-preempt.html
* igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0:
- shard-dg2: NOTRUN -> [SKIP][15] ([i915#5882]) +6 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0.html
* igt@gem_eio@hibernate:
- shard-dg1: NOTRUN -> [ABORT][16] ([i915#7975] / [i915#8213])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@gem_eio@hibernate.html
* igt@gem_exec_balancer@bonded-false-hang:
- shard-dg2: NOTRUN -> [SKIP][17] ([i915#4812]) +3 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@gem_exec_balancer@bonded-false-hang.html
* igt@gem_exec_balancer@bonded-pair:
- shard-dg2: NOTRUN -> [SKIP][18] ([i915#4771])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-10/igt@gem_exec_balancer@bonded-pair.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-rkl: NOTRUN -> [SKIP][19] ([i915#4525])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-5/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_capture@capture-recoverable:
- shard-rkl: NOTRUN -> [SKIP][20] ([i915#6344])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-4/igt@gem_exec_capture@capture-recoverable.html
* igt@gem_exec_capture@capture@vecs0-lmem0:
- shard-dg1: NOTRUN -> [FAIL][21] ([i915#11965]) +1 other test fail
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-18/igt@gem_exec_capture@capture@vecs0-lmem0.html
* igt@gem_exec_fair@basic-deadline:
- shard-dg1: NOTRUN -> [SKIP][22] ([i915#3539] / [i915#4852])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-rkl: [PASS][23] -> [FAIL][24] ([i915#2842]) +1 other test fail
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-rkl-4/igt@gem_exec_fair@basic-flow@rcs0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-1/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-pace-share:
- shard-dg2: NOTRUN -> [SKIP][25] ([i915#3539] / [i915#4852]) +3 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-10/igt@gem_exec_fair@basic-pace-share.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][26] -> [FAIL][27] ([i915#2842])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo:
- shard-dg2: NOTRUN -> [SKIP][28] ([i915#3539]) +2 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-7/igt@gem_exec_fair@basic-pace-solo.html
* igt@gem_exec_params@rsvd2-dirt:
- shard-dg2: NOTRUN -> [SKIP][29] ([i915#5107])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@gem_exec_params@rsvd2-dirt.html
* igt@gem_exec_reloc@basic-active:
- shard-dg2: NOTRUN -> [SKIP][30] ([i915#3281]) +10 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-7/igt@gem_exec_reloc@basic-active.html
* igt@gem_exec_reloc@basic-concurrent0:
- shard-dg1: NOTRUN -> [SKIP][31] ([i915#3281]) +6 other tests skip
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-13/igt@gem_exec_reloc@basic-concurrent0.html
* igt@gem_exec_reloc@basic-scanout:
- shard-rkl: NOTRUN -> [SKIP][32] ([i915#3281]) +6 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-4/igt@gem_exec_reloc@basic-scanout.html
* igt@gem_exec_schedule@preempt-queue-contexts-chain:
- shard-dg2: NOTRUN -> [SKIP][33] ([i915#4537] / [i915#4812]) +1 other test skip
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@gem_exec_schedule@preempt-queue-contexts-chain.html
* igt@gem_exec_schedule@semaphore-power:
- shard-dg1: NOTRUN -> [SKIP][34] ([i915#4812])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-18/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_exec_suspend@basic-s4-devices@smem:
- shard-rkl: NOTRUN -> [ABORT][35] ([i915#7975] / [i915#8213])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-3/igt@gem_exec_suspend@basic-s4-devices@smem.html
* igt@gem_fence_thrash@bo-write-verify-threaded-none:
- shard-dg2: NOTRUN -> [SKIP][36] ([i915#4860]) +1 other test skip
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@gem_fence_thrash@bo-write-verify-threaded-none.html
* igt@gem_fenced_exec_thrash@no-spare-fences-busy:
- shard-dg1: NOTRUN -> [SKIP][37] ([i915#4860]) +2 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@gem_fenced_exec_thrash@no-spare-fences-busy.html
* igt@gem_huc_copy@huc-copy:
- shard-rkl: NOTRUN -> [SKIP][38] ([i915#2190])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-6/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-rkl: NOTRUN -> [SKIP][39] ([i915#4613]) +1 other test skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-4/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@verify-ccs@lmem0:
- shard-dg1: NOTRUN -> [SKIP][40] ([i915#4565])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-13/igt@gem_lmem_swapping@verify-ccs@lmem0.html
* igt@gem_media_vme:
- shard-dg2: NOTRUN -> [SKIP][41] ([i915#284])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@gem_media_vme.html
- shard-rkl: NOTRUN -> [SKIP][42] ([i915#284])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-5/igt@gem_media_vme.html
* igt@gem_mmap_gtt@coherency:
- shard-dg1: NOTRUN -> [SKIP][43] ([i915#4077]) +8 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-13/igt@gem_mmap_gtt@coherency.html
* igt@gem_mmap_gtt@hang:
- shard-dg2: NOTRUN -> [SKIP][44] ([i915#4077]) +12 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-7/igt@gem_mmap_gtt@hang.html
* igt@gem_mmap_wc@copy:
- shard-dg2: NOTRUN -> [SKIP][45] ([i915#4083]) +3 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-7/igt@gem_mmap_wc@copy.html
* igt@gem_mmap_wc@write-read:
- shard-dg1: NOTRUN -> [SKIP][46] ([i915#4083]) +1 other test skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@gem_mmap_wc@write-read.html
* igt@gem_partial_pwrite_pread@reads:
- shard-dg2: NOTRUN -> [SKIP][47] ([i915#3282]) +7 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@gem_partial_pwrite_pread@reads.html
* igt@gem_pread@uncached:
- shard-dg1: NOTRUN -> [SKIP][48] ([i915#3282]) +3 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-13/igt@gem_pread@uncached.html
* igt@gem_pwrite@basic-self:
- shard-rkl: NOTRUN -> [SKIP][49] ([i915#3282]) +5 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-3/igt@gem_pwrite@basic-self.html
* igt@gem_pxp@protected-raw-src-copy-not-readible:
- shard-dg2: NOTRUN -> [SKIP][50] ([i915#4270]) +4 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-10/igt@gem_pxp@protected-raw-src-copy-not-readible.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-dg1: NOTRUN -> [SKIP][51] ([i915#4270])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-13/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-rkl: NOTRUN -> [SKIP][52] ([i915#4270]) +2 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-4/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_render_copy@y-tiled-to-vebox-yf-tiled:
- shard-dg2: NOTRUN -> [SKIP][53] ([i915#5190] / [i915#8428]) +6 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-7/igt@gem_render_copy@y-tiled-to-vebox-yf-tiled.html
* igt@gem_set_tiling_vs_blt@tiled-to-tiled:
- shard-dg1: NOTRUN -> [SKIP][54] ([i915#4079])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html
* igt@gem_set_tiling_vs_blt@untiled-to-tiled:
- shard-rkl: NOTRUN -> [SKIP][55] ([i915#8411])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-3/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
* igt@gem_set_tiling_vs_pwrite:
- shard-dg2: NOTRUN -> [SKIP][56] ([i915#4079])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@gem_set_tiling_vs_pwrite.html
* igt@gem_tiled_swapping@non-threaded:
- shard-glk: [PASS][57] -> [DMESG-WARN][58] ([i915#118])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-glk2/igt@gem_tiled_swapping@non-threaded.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-glk6/igt@gem_tiled_swapping@non-threaded.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-dg2: NOTRUN -> [SKIP][59] ([i915#3297]) +2 other tests skip
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-rkl: NOTRUN -> [SKIP][60] ([i915#3297]) +2 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-5/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gen7_exec_parse@chained-batch:
- shard-rkl: NOTRUN -> [SKIP][61] +23 other tests skip
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-5/igt@gen7_exec_parse@chained-batch.html
* igt@gen9_exec_parse@bb-start-out:
- shard-rkl: NOTRUN -> [SKIP][62] ([i915#2527]) +2 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-4/igt@gen9_exec_parse@bb-start-out.html
* igt@gen9_exec_parse@unaligned-access:
- shard-dg2: NOTRUN -> [SKIP][63] ([i915#2856]) +3 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@gen9_exec_parse@unaligned-access.html
* igt@gen9_exec_parse@valid-registers:
- shard-dg1: NOTRUN -> [SKIP][64] ([i915#2527]) +2 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-18/igt@gen9_exec_parse@valid-registers.html
* igt@i915_module_load@load:
- shard-dg2: NOTRUN -> [SKIP][65] ([i915#6227])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@i915_module_load@load.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-rkl: [PASS][66] -> [ABORT][67] ([i915#9820])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-rkl-6/igt@i915_module_load@reload-with-fault-injection.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-5/igt@i915_module_load@reload-with-fault-injection.html
- shard-dg1: [PASS][68] -> [ABORT][69] ([i915#9820])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-dg1-13/igt@i915_module_load@reload-with-fault-injection.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-18/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rps@basic-api:
- shard-dg1: NOTRUN -> [SKIP][70] ([i915#11681] / [i915#6621])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@i915_pm_rps@basic-api.html
* igt@i915_pm_rps@min-max-config-idle:
- shard-dg2: NOTRUN -> [SKIP][71] ([i915#11681] / [i915#6621])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@i915_pm_rps@min-max-config-idle.html
* igt@i915_pm_rps@thresholds-idle-park:
- shard-dg2: NOTRUN -> [SKIP][72] ([i915#11681])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-7/igt@i915_pm_rps@thresholds-idle-park.html
* igt@i915_selftest@mock@memory_region:
- shard-dg2: NOTRUN -> [DMESG-WARN][73] ([i915#9311])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@i915_selftest@mock@memory_region.html
* igt@intel_hwmon@hwmon-read:
- shard-rkl: NOTRUN -> [SKIP][74] ([i915#7707])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-4/igt@intel_hwmon@hwmon-read.html
* igt@kms_addfb_basic@bo-too-small-due-to-tiling:
- shard-dg1: NOTRUN -> [SKIP][75] ([i915#4212]) +2 other tests skip
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-dp-4-4-rc-ccs-cc:
- shard-dg2: NOTRUN -> [SKIP][76] ([i915#8709]) +11 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-dp-4-4-rc-ccs-cc.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-rkl: NOTRUN -> [SKIP][77] ([i915#1769] / [i915#3555])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
- shard-dg1: NOTRUN -> [SKIP][78] ([i915#1769] / [i915#3555])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-1:
- shard-snb: [PASS][79] -> [FAIL][80] ([i915#5956])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-snb2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-1.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-snb4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-hdmi-a-1.html
* igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3:
- shard-dg2: [PASS][81] -> [FAIL][82] ([i915#5956])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-dg2-5/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-1/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-180:
- shard-rkl: NOTRUN -> [SKIP][83] ([i915#5286]) +5 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-5/igt@kms_big_fb@4-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
- shard-mtlp: [PASS][84] -> [DMESG-FAIL][85] ([i915#2017])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-dg1: NOTRUN -> [SKIP][86] ([i915#4538] / [i915#5286]) +3 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-13/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@linear-64bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][87] ([i915#3638]) +2 other tests skip
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-3/igt@kms_big_fb@linear-64bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- shard-dg1: NOTRUN -> [SKIP][88] ([i915#3638]) +2 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-180:
- shard-dg2: NOTRUN -> [SKIP][89] ([i915#4538] / [i915#5190]) +10 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-dg2: NOTRUN -> [SKIP][90] ([i915#5190])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-7/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
- shard-dg1: NOTRUN -> [SKIP][91] ([i915#4538]) +4 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc@pipe-d-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][92] ([i915#6095]) +75 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc@pipe-d-hdmi-a-4.html
* igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
- shard-dg2: NOTRUN -> [SKIP][93] ([i915#12042]) +1 other test skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
* igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][94] ([i915#10307] / [i915#6095]) +200 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-1/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-3.html
* igt@kms_ccs@crc-primary-basic-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][95] ([i915#10307] / [i915#10434] / [i915#6095]) +2 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-10/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][96] ([i915#6095]) +39 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
- shard-rkl: NOTRUN -> [SKIP][97] ([i915#12042]) +2 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-5/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
- shard-dg1: NOTRUN -> [SKIP][98] ([i915#12042])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-18/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
* igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][99] ([i915#11616] / [i915#7213]) +3 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-8/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1.html
* igt@kms_chamelium_audio@dp-audio-edid:
- shard-dg2: NOTRUN -> [SKIP][100] ([i915#7828]) +10 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_chamelium_audio@dp-audio-edid.html
* igt@kms_chamelium_frames@hdmi-frame-dump:
- shard-dg1: NOTRUN -> [SKIP][101] ([i915#7828]) +5 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-18/igt@kms_chamelium_frames@hdmi-frame-dump.html
* igt@kms_chamelium_hpd@vga-hpd-for-each-pipe:
- shard-rkl: NOTRUN -> [SKIP][102] ([i915#7828]) +5 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-5/igt@kms_chamelium_hpd@vga-hpd-for-each-pipe.html
* igt@kms_content_protection@atomic:
- shard-dg2: NOTRUN -> [SKIP][103] ([i915#7118] / [i915#9424])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-6/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@atomic-dpms:
- shard-rkl: NOTRUN -> [SKIP][104] ([i915#7118] / [i915#9424])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-6/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-dg2: NOTRUN -> [SKIP][105] ([i915#3299])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-7/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@lic-type-1:
- shard-dg1: NOTRUN -> [SKIP][106] ([i915#9424])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@kms_content_protection@lic-type-1.html
* igt@kms_content_protection@mei-interface:
- shard-dg2: NOTRUN -> [SKIP][107] ([i915#9424])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@type1:
- shard-dg1: NOTRUN -> [SKIP][108] ([i915#7116] / [i915#9424]) +1 other test skip
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-13/igt@kms_content_protection@type1.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-dg2: NOTRUN -> [SKIP][109] ([i915#11453]) +1 other test skip
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-10/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-random-512x512:
- shard-dg1: NOTRUN -> [SKIP][110] ([i915#11453]) +1 other test skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@kms_cursor_crc@cursor-random-512x512.html
* igt@kms_cursor_crc@cursor-sliding-max-size:
- shard-dg2: NOTRUN -> [SKIP][111] ([i915#3555]) +3 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_cursor_crc@cursor-sliding-max-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][112] -> [FAIL][113] ([i915#2346])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-dg2: NOTRUN -> [SKIP][114] ([i915#4103] / [i915#4213]) +1 other test skip
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
- shard-rkl: NOTRUN -> [SKIP][115] ([i915#4103])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
- shard-rkl: NOTRUN -> [SKIP][116] ([i915#9723])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-4/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [SKIP][117]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-glk1/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_draw_crc@draw-method-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][118] ([i915#8812]) +1 other test skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@kms_draw_crc@draw-method-mmap-gtt.html
* igt@kms_dsc@dsc-with-formats:
- shard-dg1: NOTRUN -> [SKIP][119] ([i915#3555] / [i915#3840])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-13/igt@kms_dsc@dsc-with-formats.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-dg2: [PASS][120] -> [FAIL][121] ([i915#4767])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-dg2-4/igt@kms_fbcon_fbt@fbc-suspend.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-3/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-dg1: NOTRUN -> [SKIP][122] ([i915#3469])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-18/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_feature_discovery@display-2x:
- shard-dg2: NOTRUN -> [SKIP][123] ([i915#1839]) +1 other test skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_feature_discovery@display-2x.html
* igt@kms_feature_discovery@dp-mst:
- shard-rkl: NOTRUN -> [SKIP][124] ([i915#9337])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-4/igt@kms_feature_discovery@dp-mst.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-dg1: NOTRUN -> [SKIP][125] ([i915#8381])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-13/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@2x-flip-vs-modeset-vs-hang:
- shard-dg2: NOTRUN -> [SKIP][126] +21 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-7/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html
* igt@kms_flip@2x-flip-vs-panning-interruptible:
- shard-dg1: NOTRUN -> [SKIP][127] ([i915#9934]) +3 other tests skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@kms_flip@2x-flip-vs-panning-interruptible.html
* igt@kms_flip@blocking-wf_vblank@a-hdmi-a2:
- shard-rkl: [PASS][128] -> [FAIL][129] ([i915#11961])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-rkl-3/igt@kms_flip@blocking-wf_vblank@a-hdmi-a2.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-5/igt@kms_flip@blocking-wf_vblank@a-hdmi-a2.html
* igt@kms_flip@flip-vs-fences:
- shard-dg2: NOTRUN -> [SKIP][130] ([i915#8381])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_flip@flip-vs-fences.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][131] ([i915#2672]) +2 other tests skip
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][132] ([i915#2672]) +2 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html
- shard-dg1: NOTRUN -> [SKIP][133] ([i915#2587] / [i915#2672]) +4 other tests skip
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-dg2: NOTRUN -> [FAIL][134] ([i915#6880])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- shard-dg2: [PASS][135] -> [FAIL][136] ([i915#6880]) +1 other test fail
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-4/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][137] ([i915#8708]) +9 other tests skip
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-18/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-rte:
- shard-dg2: NOTRUN -> [SKIP][138] ([i915#5354]) +32 other tests skip
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-2p-rte.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt:
- shard-rkl: NOTRUN -> [SKIP][139] ([i915#1825]) +31 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite:
- shard-dg2: NOTRUN -> [SKIP][140] ([i915#3458]) +19 other tests skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-snb: NOTRUN -> [SKIP][141] +89 other tests skip
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-snb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][142] ([i915#8708]) +22 other tests skip
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][143] ([i915#3023]) +20 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@pipe-fbc-rte:
- shard-rkl: NOTRUN -> [SKIP][144] ([i915#9766])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-3/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
- shard-dg1: NOTRUN -> [SKIP][145] ([i915#3458]) +12 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-18/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt:
- shard-dg1: NOTRUN -> [SKIP][146] +33 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt.html
* igt@kms_getfb@getfb-reject-ccs:
- shard-dg2: NOTRUN -> [SKIP][147] ([i915#6118])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_getfb@getfb-reject-ccs.html
* igt@kms_hdr@invalid-metadata-sizes:
- shard-dg2: NOTRUN -> [SKIP][148] ([i915#3555] / [i915#8228]) +1 other test skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-7/igt@kms_hdr@invalid-metadata-sizes.html
* igt@kms_hdr@static-toggle:
- shard-rkl: NOTRUN -> [SKIP][149] ([i915#3555] / [i915#8228])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-4/igt@kms_hdr@static-toggle.html
* igt@kms_hdr@static-toggle-dpms:
- shard-dg1: NOTRUN -> [SKIP][150] ([i915#3555] / [i915#8228])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-13/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: NOTRUN -> [SKIP][151] ([i915#4070] / [i915#4816])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
- shard-dg1: NOTRUN -> [SKIP][152] ([i915#1839])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_panel_fitting@legacy:
- shard-dg2: NOTRUN -> [SKIP][153] ([i915#6301])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_panel_fitting@legacy.html
- shard-rkl: NOTRUN -> [SKIP][154] ([i915#6301])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-5/igt@kms_panel_fitting@legacy.html
* igt@kms_plane@pixel-format-source-clamping@pipe-a-plane-0:
- shard-tglu: [PASS][155] -> [ABORT][156] ([i915#10354])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-tglu-7/igt@kms_plane@pixel-format-source-clamping@pipe-a-plane-0.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-tglu-9/igt@kms_plane@pixel-format-source-clamping@pipe-a-plane-0.html
* igt@kms_plane_lowres@tiling-yf:
- shard-rkl: NOTRUN -> [SKIP][157] ([i915#3555]) +4 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-3/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_multiple@tiling-yf:
- shard-dg2: NOTRUN -> [SKIP][158] ([i915#3555] / [i915#8806])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-3:
- shard-dg1: NOTRUN -> [FAIL][159] ([i915#8292])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-13/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-3.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][160] ([i915#9423]) +7 other tests skip
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-5/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][161] ([i915#9423]) +27 other tests skip
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-1/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-3.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][162] ([i915#9423]) +3 other tests skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-18/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-hdmi-a-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][163] ([i915#9728]) +1 other test skip
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-4/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][164] ([i915#5235]) +1 other test skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][165] ([i915#9728]) +3 other tests skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-18/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-4.html
* igt@kms_pm_backlight@fade-with-dpms:
- shard-dg1: NOTRUN -> [SKIP][166] ([i915#5354])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-18/igt@kms_pm_backlight@fade-with-dpms.html
* igt@kms_pm_dc@dc6-psr:
- shard-dg2: NOTRUN -> [SKIP][167] ([i915#9685])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_pm_dc@dc6-psr.html
- shard-rkl: NOTRUN -> [SKIP][168] ([i915#9685])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-5/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-dg2: NOTRUN -> [SKIP][169] ([i915#9340])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_lpsp@screens-disabled:
- shard-dg1: NOTRUN -> [SKIP][170] ([i915#8430])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-13/igt@kms_pm_lpsp@screens-disabled.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress:
- shard-dg2: [PASS][171] -> [SKIP][172] ([i915#9519])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-dg2-6/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-10/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_prime@basic-crc-hybrid:
- shard-dg2: NOTRUN -> [SKIP][173] ([i915#6524] / [i915#6805])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_prime@basic-crc-vgem:
- shard-dg1: NOTRUN -> [SKIP][174] ([i915#6524])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-18/igt@kms_prime@basic-crc-vgem.html
* igt@kms_prime@basic-modeset-hybrid:
- shard-rkl: NOTRUN -> [SKIP][175] ([i915#6524])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-3/igt@kms_prime@basic-modeset-hybrid.html
* igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-sf:
- shard-dg2: NOTRUN -> [SKIP][176] ([i915#11520]) +3 other tests skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-sf.html
- shard-rkl: NOTRUN -> [SKIP][177] ([i915#11520]) +2 other tests skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-5/igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-dg1: NOTRUN -> [SKIP][178] ([i915#11520]) +1 other test skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-18/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-dg2: NOTRUN -> [SKIP][179] ([i915#9683])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-rkl: NOTRUN -> [SKIP][180] ([i915#9683])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-4/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr-cursor-render:
- shard-dg2: NOTRUN -> [SKIP][181] ([i915#1072] / [i915#9673] / [i915#9732]) +14 other tests skip
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_psr@psr-cursor-render.html
* igt@kms_psr@psr-primary-mmap-cpu:
- shard-rkl: NOTRUN -> [SKIP][182] ([i915#1072] / [i915#9732]) +17 other tests skip
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-5/igt@kms_psr@psr-primary-mmap-cpu.html
* igt@kms_psr@psr2-cursor-blt:
- shard-dg2: NOTRUN -> [SKIP][183] ([i915#1072] / [i915#9732]) +6 other tests skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-7/igt@kms_psr@psr2-cursor-blt.html
* igt@kms_psr@psr2-sprite-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][184] ([i915#1072] / [i915#9732]) +16 other tests skip
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-18/igt@kms_psr@psr2-sprite-mmap-gtt.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-dg1: NOTRUN -> [SKIP][185] ([i915#9685])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-18/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-dg1: NOTRUN -> [SKIP][186] ([i915#5289])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-18/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-rkl: NOTRUN -> [SKIP][187] ([i915#5289]) +1 other test skip
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-dg2: NOTRUN -> [SKIP][188] ([i915#11131] / [i915#4235] / [i915#5190])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_scaling_modes@scaling-mode-none:
- shard-dg1: NOTRUN -> [SKIP][189] ([i915#3555]) +2 other tests skip
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-13/igt@kms_scaling_modes@scaling-mode-none.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1:
- shard-rkl: [PASS][190] -> [FAIL][191] ([i915#9196])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-rkl-4/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-4/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-3:
- shard-dg2: NOTRUN -> [FAIL][192] ([i915#9196])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-1/igt@kms_universal_plane@cursor-fb-leak@pipe-c-hdmi-a-3.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1:
- shard-mtlp: [PASS][193] -> [FAIL][194] ([i915#9196])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-mtlp-6/igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-mtlp-2/igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1.html
* igt@kms_vrr@lobf:
- shard-rkl: NOTRUN -> [SKIP][195] ([i915#11920])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-3/igt@kms_vrr@lobf.html
* igt@kms_vrr@seamless-rr-switch-virtual:
- shard-dg2: NOTRUN -> [SKIP][196] ([i915#9906])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-7/igt@kms_vrr@seamless-rr-switch-virtual.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-rkl: NOTRUN -> [SKIP][197] ([i915#2437] / [i915#9412]) +1 other test skip
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-6/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
- shard-dg1: NOTRUN -> [SKIP][198] ([i915#2437] / [i915#9412])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@prime_vgem@basic-fence-mmap:
- shard-dg1: NOTRUN -> [SKIP][199] ([i915#3708] / [i915#4077])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-13/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-write:
- shard-dg2: NOTRUN -> [SKIP][200] ([i915#3291] / [i915#3708])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@prime_vgem@basic-write.html
* igt@prime_vgem@coherency-gtt:
- shard-dg2: NOTRUN -> [SKIP][201] ([i915#3708] / [i915#4077])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-11/igt@prime_vgem@coherency-gtt.html
* igt@prime_vgem@fence-write-hang:
- shard-rkl: NOTRUN -> [SKIP][202] ([i915#3708])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-6/igt@prime_vgem@fence-write-hang.html
- shard-dg1: NOTRUN -> [SKIP][203] ([i915#3708])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-14/igt@prime_vgem@fence-write-hang.html
* igt@sriov_basic@enable-vfs-bind-unbind-each:
- shard-dg1: NOTRUN -> [SKIP][204] ([i915#9917])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-13/igt@sriov_basic@enable-vfs-bind-unbind-each.html
#### Possible fixes ####
* igt@gem_ctx_engines@invalid-engines:
- shard-rkl: [FAIL][205] ([i915#12027]) -> [PASS][206]
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-rkl-6/igt@gem_ctx_engines@invalid-engines.html
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-2/igt@gem_ctx_engines@invalid-engines.html
- shard-glk: [FAIL][207] ([i915#12027]) -> [PASS][208]
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-glk5/igt@gem_ctx_engines@invalid-engines.html
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-glk1/igt@gem_ctx_engines@invalid-engines.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-rkl: [FAIL][209] ([i915#2842]) -> [PASS][210] +1 other test pass
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-rkl-3/igt@gem_exec_fair@basic-pace@vecs0.html
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-3/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-snb: [ABORT][211] ([i915#9820]) -> [PASS][212]
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-snb2/igt@i915_module_load@reload-with-fault-injection.html
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-snb4/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rps@reset:
- shard-snb: [INCOMPLETE][213] ([i915#7790]) -> [PASS][214]
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-snb5/igt@i915_pm_rps@reset.html
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-snb5/igt@i915_pm_rps@reset.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels@pipe-a-edp-1:
- shard-mtlp: [FAIL][215] ([i915#11808] / [i915#5956]) -> [PASS][216]
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-mtlp-7/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels@pipe-a-edp-1.html
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-mtlp-2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels@pipe-a-edp-1.html
* igt@kms_flip@flip-vs-fences@a-vga1:
- shard-snb: [INCOMPLETE][217] -> [PASS][218]
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-snb6/igt@kms_flip@flip-vs-fences@a-vga1.html
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-snb2/igt@kms_flip@flip-vs-fences@a-vga1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-vga1:
- shard-snb: [FAIL][219] ([i915#2122]) -> [PASS][220] +1 other test pass
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-snb7/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-vga1.html
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-snb5/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-vga1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite:
- shard-dg2: [FAIL][221] ([i915#6880]) -> [PASS][222]
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-rkl: [SKIP][223] ([i915#9519]) -> [PASS][224] +1 other test pass
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-rkl-3/igt@kms_pm_rpm@modeset-lpsp.html
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-dg2: [SKIP][225] ([i915#9519]) -> [PASS][226] +1 other test pass
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-dg2-6/igt@kms_pm_rpm@modeset-lpsp-stress.html
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-4/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-edp-1:
- shard-mtlp: [FAIL][227] ([i915#9196]) -> [PASS][228]
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-mtlp-6/igt@kms_universal_plane@cursor-fb-leak@pipe-b-edp-1.html
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-mtlp-2/igt@kms_universal_plane@cursor-fb-leak@pipe-b-edp-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-3:
- shard-dg1: [FAIL][229] ([i915#9196]) -> [PASS][230]
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-dg1-13/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-3.html
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-13/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-3.html
#### Warnings ####
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg1: [DMESG-WARN][231] ([i915#1982] / [i915#4936] / [i915#5493]) -> [TIMEOUT][232] ([i915#5493])
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-dg1-15/igt@gem_lmem_swapping@smem-oom@lmem0.html
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg1-16/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-glk: [ABORT][233] -> [ABORT][234] ([i915#9820])
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-glk8/igt@i915_module_load@reload-with-fault-injection.html
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-glk1/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite:
- shard-dg2: [SKIP][235] ([i915#3458]) -> [SKIP][236] ([i915#10433] / [i915#3458]) +1 other test skip
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite.html
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt:
- shard-dg2: [SKIP][237] ([i915#10433] / [i915#3458]) -> [SKIP][238] ([i915#3458])
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_psr@fbc-pr-sprite-mmap-gtt:
- shard-dg2: [SKIP][239] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][240] ([i915#1072] / [i915#9732]) +4 other tests skip
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15359/shard-dg2-11/igt@kms_psr@fbc-pr-sprite-mmap-gtt.html
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/shard-dg2-6/igt@kms_psr@fbc-pr-sprite-mmap-gtt.html
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10354
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
[i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
[i915#11131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11131
[i915#11453]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11453
[i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
[i915#11616]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11616
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/118
[i915#11808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11808
[i915#11920]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11920
[i915#11961]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11961
[i915#11965]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11965
[i915#12027]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12027
[i915#12042]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12042
[i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#2017]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2017
[i915#2122]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#4070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#4936]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4936
[i915#5107]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5107
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
[i915#5882]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5882
[i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6118
[i915#6227]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6227
[i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
[i915#6344]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6344
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
[i915#6805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6805
[i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
[i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7213
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
[i915#7742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7742
[i915#7790]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7790
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
[i915#8213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8292]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8292
[i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
[i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
[i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
[i915#8806]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8806
[i915#8812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8812
[i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
[i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
[i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
[i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
[i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9561]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9561
[i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
[i915#9728]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9728
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
[i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
[i915#9846]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9846
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_15359 -> Patchwork_138065v3
CI-20190529: 20190529
CI_DRM_15359: 8b1096500fd6fae573f7d9c4416778d6442e985d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8005: fc3113c8c1e99797b2d4769aaf02265be64a7589 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_138065v3: 8b1096500fd6fae573f7d9c4416778d6442e985d @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v3/index.html
[-- Attachment #2: Type: text/html, Size: 84217 bytes --]
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-05 4:41 ` Suraj Kandpal
@ 2024-09-09 4:54 ` Suraj Kandpal
2024-09-09 6:32 ` Suraj Kandpal
0 siblings, 1 reply; 47+ messages in thread
From: Suraj Kandpal @ 2024-09-09 4:54 UTC (permalink / raw)
To: intel-gfx; +Cc: uma.shankar, jouni.hogander, imre.deak, Suraj Kandpal
To reach PC10 when PKG_C_LATENCY is configure we must do the following
things
1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
2) Allow PSR2 deep sleep when DC5 can be entered
3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
not happening.
--v2
-Switch condition and do an early return [Jani]
-Do some checks in compute_config [Jani]
-Do not use register reads as a method of checking states for
DPKGC or delayed vblank [Jani]
-Use another way to see is vblank interrupts are disabled or not [Jani]
--v3
-Use has_psr to check if psr can be enabled or not for dc5_entry cond
[Uma]
-Move the dc5 entry computation to psr_compute_config [Jouni]
-No need to change sequence of enabled and activate,
so dont make hsw_psr1_activate return anything [Jouni]
-Use has_psr to stop psr1 activation [Jouni]
-Use lineage no. in WA
-Add the display ver restrictions for WA
--v4
-use more appropriate name for check_vblank_limit() [Jouni]
-Cover the case for idle frames when dpkgc is not configured [Jouni]
-Check psr only for edp [Jouni]
--v5
-move psr1 handling to plane update [Jouni]
-add todo for cases when vblank is enabled when psr enabled [Jouni]
-use intel_display instead of drm_i915_private
--v6
-check target_dc_state [Jouni]
-fix condition in pre/post plane update [Jouni]
WA: 22019444797
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/display/intel_psr.c | 111 +++++++++++++++++-
2 files changed, 113 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 733de5edcfdb..59c81f0a3abd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1577,6 +1577,9 @@ struct intel_psr {
#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
u32 debug;
+ bool is_dpkgc_configured;
+ bool is_dc5_entry_possible;
+ bool is_wa_delayed_vblank_limit;
bool sink_support;
bool source_support;
bool enabled;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b30fa067ce6e..d24116b50fab 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -874,6 +874,78 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
return idle_frames;
}
+static bool
+intel_psr_check_wa_delayed_vblank(const struct drm_display_mode *adjusted_mode)
+{
+ return (adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay) >= 6;
+}
+
+/*
+ * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
+ * VRR is not enabled
+ */
+static bool intel_psr_is_dpkgc_configured(struct intel_display *display,
+ struct intel_atomic_state *state)
+{
+ struct intel_crtc *intel_crtc;
+ struct intel_crtc_state *crtc_state;
+ int i;
+
+ if (DISPLAY_VER(display) < 20)
+ return false;
+
+ for_each_new_intel_crtc_in_state(state, intel_crtc, crtc_state, i) {
+ if (!intel_crtc->active)
+ continue;
+
+ if (crtc_state->vrr.enable)
+ return false;
+ }
+
+ return true;
+}
+
+/*
+ * DC5 entry is only possible if vblank interrupt is disabled
+ * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
+ * enabled encoders.
+ */
+static bool
+intel_psr_is_dc5_entry_possible(struct intel_display *display,
+ struct intel_atomic_state *state)
+{
+ struct intel_crtc *intel_crtc;
+ struct intel_crtc_state *crtc_state;
+ int i;
+
+ if ((display->power.domains.target_dc_state &
+ DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
+ return false;
+
+ for_each_new_intel_crtc_in_state(state, intel_crtc, crtc_state, i) {
+ struct drm_crtc *crtc = &intel_crtc->base;
+ struct drm_vblank_crtc *vblank;
+ struct intel_encoder *encoder;
+
+ if (!intel_crtc->active)
+ continue;
+
+ vblank = drm_crtc_vblank_crtc(crtc);
+
+ if (vblank->enabled)
+ return false;
+
+ if (crtc_state->has_psr)
+ return false;
+
+ for_each_encoder_on_crtc(display->drm, crtc, encoder)
+ if (encoder->type != INTEL_OUTPUT_EDP)
+ return false;
+ }
+
+ return true;
+}
+
static void hsw_activate_psr1(struct intel_dp *intel_dp)
{
struct intel_display *display = to_intel_display(intel_dp);
@@ -986,7 +1058,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
u32 val = EDP_PSR2_ENABLE;
u32 psr_val = 0;
- val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ /*
+ * Wa_22019444797
+ * TODO: Disable idle frames when vblank gets enabled while
+ * PSR2 is enabled
+ */
+ if (DISPLAY_VER(dev_priv) != 20 ||
+ !intel_dp->psr.is_dpkgc_configured ||
+ intel_dp->psr.is_dc5_entry_possible)
+ val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
val |= EDP_SU_TRACK_ENABLE;
@@ -2667,10 +2747,20 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_encoder *encoder;
+ bool dpkgc_configured = false, dc5_entry_possible = false;
+ bool wa_delayed_vblank_limit = false;
if (!HAS_PSR(display))
return;
+ if (DISPLAY_VER(display) == 20) {
+ dpkgc_configured = intel_psr_is_dpkgc_configured(display, state);
+ dc5_entry_possible =
+ intel_psr_is_dc5_entry_possible(display, state);
+ wa_delayed_vblank_limit =
+ intel_psr_check_wa_delayed_vblank(&new_crtc_state->hw.adjusted_mode);
+ }
+
for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
old_crtc_state->uapi.encoder_mask) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2679,6 +2769,12 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
mutex_lock(&psr->lock);
+ if (DISPLAY_VER(i915) == 20) {
+ psr->is_dpkgc_configured = dpkgc_configured;
+ psr->is_dc5_entry_possible = dc5_entry_possible;
+ psr->is_wa_delayed_vblank_limit = wa_delayed_vblank_limit;
+ }
+
/*
* Reasons to disable:
* - PSR disabled in new state
@@ -2686,6 +2782,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
* - Changing between PSR versions
* - Region Early Transport changing
* - Display WA #1136: skl, bxt
+ * - Display WA_22019444797
*/
needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
needs_to_disable |= !new_crtc_state->has_psr;
@@ -2695,6 +2792,10 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
psr->su_region_et_enabled;
needs_to_disable |= DISPLAY_VER(i915) < 11 &&
new_crtc_state->wm_level_disabled;
+ /* TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled */
+ needs_to_disable |= DISPLAY_VER(display) == 20 && dpkgc_configured &&
+ (wa_delayed_vblank_limit || dc5_entry_possible) &&
+ !new_crtc_state->has_sel_update && !new_crtc_state->has_panel_replay;
if (psr->enabled && needs_to_disable)
intel_psr_disable_locked(intel_dp);
@@ -2735,6 +2836,14 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
keep_disabled |= DISPLAY_VER(display) < 11 &&
crtc_state->wm_level_disabled;
+ /*
+ * Wa_22019444797
+ * TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled
+ */
+ keep_disabled |= DISPLAY_VER(display) == 20 && psr->is_dpkgc_configured &&
+ (psr->is_wa_delayed_vblank_limit || psr->is_dc5_entry_possible) &&
+ !crtc_state->has_sel_update && !crtc_state->has_panel_replay;
+
if (!psr->enabled && !keep_disabled)
intel_psr_enable_locked(intel_dp, crtc_state);
else if (psr->enabled && !crtc_state->wm_level_disabled)
--
2.43.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* ✗ Fi.CI.BUILD: failure for drm/i915/psr: Implment WA to help reach PC10 (rev4)
2024-09-02 5:02 [PATCH] drm/i915/psr: Implment WA to help reach PC10 Suraj Kandpal
` (6 preceding siblings ...)
2024-09-06 15:26 ` ✓ Fi.CI.IGT: " Patchwork
@ 2024-09-09 5:26 ` Patchwork
2024-09-09 7:28 ` ✓ Fi.CI.BAT: success for drm/i915/psr: Implment WA to help reach PC10 (rev5) Patchwork
` (5 subsequent siblings)
13 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2024-09-09 5:26 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/psr: Implment WA to help reach PC10 (rev4)
URL : https://patchwork.freedesktop.org/series/138065/
State : failure
== Summary ==
Error: make failed
CALL scripts/checksyscalls.sh
DESCEND objtool
INSTALL libsubcmd_headers
CC [M] drivers/gpu/drm/i915/display/intel_psr.o
drivers/gpu/drm/i915/display/intel_psr.c: In function ‘intel_psr_is_dc5_entry_possible’:
drivers/gpu/drm/i915/display/intel_psr.c:933:12: error: implicit declaration of function ‘drm_crtc_vblank_crtc’ [-Werror=implicit-function-declaration]
933 | vblank = drm_crtc_vblank_crtc(crtc);
| ^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_psr.c:933:10: error: assignment to ‘struct drm_vblank_crtc *’ from ‘int’ makes pointer from integer without a cast [-Werror=int-conversion]
933 | vblank = drm_crtc_vblank_crtc(crtc);
| ^
drivers/gpu/drm/i915/display/intel_psr.c:935:13: error: dereferencing pointer to incomplete type ‘struct drm_vblank_crtc’
935 | if (vblank->enabled)
| ^~
cc1: all warnings being treated as errors
make[6]: *** [scripts/Makefile.build:244: drivers/gpu/drm/i915/display/intel_psr.o] Error 1
make[5]: *** [scripts/Makefile.build:485: drivers/gpu/drm/i915] Error 2
make[4]: *** [scripts/Makefile.build:485: drivers/gpu/drm] Error 2
make[3]: *** [scripts/Makefile.build:485: drivers/gpu] Error 2
make[2]: *** [scripts/Makefile.build:485: drivers] Error 2
make[1]: *** [/home/kbuild/kernel/Makefile:1925: .] Error 2
make: *** [Makefile:224: __sub-make] Error 2
Build failed, no error log produced
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-09 4:54 ` Suraj Kandpal
@ 2024-09-09 6:32 ` Suraj Kandpal
2024-09-19 12:14 ` Shankar, Uma
2024-09-20 9:12 ` [PATCH] drm/i915/psr: Implement " Suraj Kandpal
0 siblings, 2 replies; 47+ messages in thread
From: Suraj Kandpal @ 2024-09-09 6:32 UTC (permalink / raw)
To: intel-gfx; +Cc: uma.shankar, jouni.hogander, imre.deak, Suraj Kandpal
To reach PC10 when PKG_C_LATENCY is configure we must do the following
things
1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
2) Allow PSR2 deep sleep when DC5 can be entered
3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
not happening.
--v2
-Switch condition and do an early return [Jani]
-Do some checks in compute_config [Jani]
-Do not use register reads as a method of checking states for
DPKGC or delayed vblank [Jani]
-Use another way to see is vblank interrupts are disabled or not [Jani]
--v3
-Use has_psr to check if psr can be enabled or not for dc5_entry cond
[Uma]
-Move the dc5 entry computation to psr_compute_config [Jouni]
-No need to change sequence of enabled and activate,
so dont make hsw_psr1_activate return anything [Jouni]
-Use has_psr to stop psr1 activation [Jouni]
-Use lineage no. in WA
-Add the display ver restrictions for WA
--v4
-use more appropriate name for check_vblank_limit() [Jouni]
-Cover the case for idle frames when dpkgc is not configured [Jouni]
-Check psr only for edp [Jouni]
--v5
-move psr1 handling to plane update [Jouni]
-add todo for cases when vblank is enabled when psr enabled [Jouni]
-use intel_display instead of drm_i915_private
--v6
-check target_dc_state [Jouni]
-fix condition in pre/post plane update [Jouni]
WA: 22019444797
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/display/intel_psr.c | 112 +++++++++++++++++-
2 files changed, 114 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 733de5edcfdb..59c81f0a3abd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1577,6 +1577,9 @@ struct intel_psr {
#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
u32 debug;
+ bool is_dpkgc_configured;
+ bool is_dc5_entry_possible;
+ bool is_wa_delayed_vblank_limit;
bool sink_support;
bool source_support;
bool enabled;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b30fa067ce6e..e50b476494a0 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -26,6 +26,7 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_damage_helper.h>
#include <drm/drm_debugfs.h>
+#include <drm/drm_vblank.h>
#include "i915_drv.h"
#include "i915_reg.h"
@@ -874,6 +875,78 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
return idle_frames;
}
+static bool
+intel_psr_check_wa_delayed_vblank(const struct drm_display_mode *adjusted_mode)
+{
+ return (adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay) >= 6;
+}
+
+/*
+ * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
+ * VRR is not enabled
+ */
+static bool intel_psr_is_dpkgc_configured(struct intel_display *display,
+ struct intel_atomic_state *state)
+{
+ struct intel_crtc *intel_crtc;
+ struct intel_crtc_state *crtc_state;
+ int i;
+
+ if (DISPLAY_VER(display) < 20)
+ return false;
+
+ for_each_new_intel_crtc_in_state(state, intel_crtc, crtc_state, i) {
+ if (!intel_crtc->active)
+ continue;
+
+ if (crtc_state->vrr.enable)
+ return false;
+ }
+
+ return true;
+}
+
+/*
+ * DC5 entry is only possible if vblank interrupt is disabled
+ * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
+ * enabled encoders.
+ */
+static bool
+intel_psr_is_dc5_entry_possible(struct intel_display *display,
+ struct intel_atomic_state *state)
+{
+ struct intel_crtc *intel_crtc;
+ struct intel_crtc_state *crtc_state;
+ int i;
+
+ if ((display->power.domains.target_dc_state &
+ DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
+ return false;
+
+ for_each_new_intel_crtc_in_state(state, intel_crtc, crtc_state, i) {
+ struct drm_crtc *crtc = &intel_crtc->base;
+ struct drm_vblank_crtc *vblank;
+ struct intel_encoder *encoder;
+
+ if (!intel_crtc->active)
+ continue;
+
+ vblank = drm_crtc_vblank_crtc(crtc);
+
+ if (vblank->enabled)
+ return false;
+
+ if (crtc_state->has_psr)
+ return false;
+
+ for_each_encoder_on_crtc(display->drm, crtc, encoder)
+ if (encoder->type != INTEL_OUTPUT_EDP)
+ return false;
+ }
+
+ return true;
+}
+
static void hsw_activate_psr1(struct intel_dp *intel_dp)
{
struct intel_display *display = to_intel_display(intel_dp);
@@ -986,7 +1059,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
u32 val = EDP_PSR2_ENABLE;
u32 psr_val = 0;
- val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ /*
+ * Wa_22019444797
+ * TODO: Disable idle frames when vblank gets enabled while
+ * PSR2 is enabled
+ */
+ if (DISPLAY_VER(dev_priv) != 20 ||
+ !intel_dp->psr.is_dpkgc_configured ||
+ intel_dp->psr.is_dc5_entry_possible)
+ val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
val |= EDP_SU_TRACK_ENABLE;
@@ -2667,10 +2748,20 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_encoder *encoder;
+ bool dpkgc_configured = false, dc5_entry_possible = false;
+ bool wa_delayed_vblank_limit = false;
if (!HAS_PSR(display))
return;
+ if (DISPLAY_VER(display) == 20) {
+ dpkgc_configured = intel_psr_is_dpkgc_configured(display, state);
+ dc5_entry_possible =
+ intel_psr_is_dc5_entry_possible(display, state);
+ wa_delayed_vblank_limit =
+ intel_psr_check_wa_delayed_vblank(&new_crtc_state->hw.adjusted_mode);
+ }
+
for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
old_crtc_state->uapi.encoder_mask) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2679,6 +2770,12 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
mutex_lock(&psr->lock);
+ if (DISPLAY_VER(i915) == 20) {
+ psr->is_dpkgc_configured = dpkgc_configured;
+ psr->is_dc5_entry_possible = dc5_entry_possible;
+ psr->is_wa_delayed_vblank_limit = wa_delayed_vblank_limit;
+ }
+
/*
* Reasons to disable:
* - PSR disabled in new state
@@ -2686,6 +2783,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
* - Changing between PSR versions
* - Region Early Transport changing
* - Display WA #1136: skl, bxt
+ * - Display WA_22019444797
*/
needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
needs_to_disable |= !new_crtc_state->has_psr;
@@ -2695,6 +2793,10 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
psr->su_region_et_enabled;
needs_to_disable |= DISPLAY_VER(i915) < 11 &&
new_crtc_state->wm_level_disabled;
+ /* TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled */
+ needs_to_disable |= DISPLAY_VER(display) == 20 && dpkgc_configured &&
+ (wa_delayed_vblank_limit || dc5_entry_possible) &&
+ !new_crtc_state->has_sel_update && !new_crtc_state->has_panel_replay;
if (psr->enabled && needs_to_disable)
intel_psr_disable_locked(intel_dp);
@@ -2735,6 +2837,14 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
keep_disabled |= DISPLAY_VER(display) < 11 &&
crtc_state->wm_level_disabled;
+ /*
+ * Wa_22019444797
+ * TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled
+ */
+ keep_disabled |= DISPLAY_VER(display) == 20 && psr->is_dpkgc_configured &&
+ (psr->is_wa_delayed_vblank_limit || psr->is_dc5_entry_possible) &&
+ !crtc_state->has_sel_update && !crtc_state->has_panel_replay;
+
if (!psr->enabled && !keep_disabled)
intel_psr_enable_locked(intel_dp, crtc_state);
else if (psr->enabled && !crtc_state->wm_level_disabled)
--
2.43.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/psr: Implment WA to help reach PC10 (rev5)
2024-09-02 5:02 [PATCH] drm/i915/psr: Implment WA to help reach PC10 Suraj Kandpal
` (7 preceding siblings ...)
2024-09-09 5:26 ` ✗ Fi.CI.BUILD: failure for drm/i915/psr: Implment WA to help reach PC10 (rev4) Patchwork
@ 2024-09-09 7:28 ` Patchwork
2024-09-10 17:15 ` ✗ Fi.CI.IGT: failure " Patchwork
` (4 subsequent siblings)
13 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2024-09-09 7:28 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 2758 bytes --]
== Series Details ==
Series: drm/i915/psr: Implment WA to help reach PC10 (rev5)
URL : https://patchwork.freedesktop.org/series/138065/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15378 -> Patchwork_138065v5
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/index.html
Participating hosts (43 -> 35)
------------------------------
Missing (8): bat-dg1-7 bat-kbl-2 fi-snb-2520m fi-glk-j4005 bat-atsm-1 fi-pnv-d510 bat-mtlp-8 bat-mtlp-6
Known issues
------------
Here are the changes found in Patchwork_138065v5 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@fbdev@read:
- bat-arls-1: [PASS][1] -> [DMESG-FAIL][2] ([i915#12102])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/bat-arls-1/igt@fbdev@read.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/bat-arls-1/igt@fbdev@read.html
* igt@i915_selftest@live:
- bat-arls-1: [PASS][3] -> [DMESG-WARN][4] ([i915#10341])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/bat-arls-1/igt@i915_selftest@live.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/bat-arls-1/igt@i915_selftest@live.html
* igt@i915_selftest@live@hangcheck:
- bat-arls-1: [PASS][5] -> [DMESG-WARN][6] ([i915#11349])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/bat-arls-1/igt@i915_selftest@live@hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/bat-arls-1/igt@i915_selftest@live@hangcheck.html
#### Possible fixes ####
* igt@fbdev@info:
- bat-arls-1: [DMESG-WARN][7] ([i915#12102]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/bat-arls-1/igt@fbdev@info.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/bat-arls-1/igt@fbdev@info.html
[i915#10341]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10341
[i915#11349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11349
[i915#12102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12102
Build changes
-------------
* Linux: CI_DRM_15378 -> Patchwork_138065v5
CI-20190529: 20190529
CI_DRM_15378: 3d2b2701d3c250fff370f5057f5a9d88d8ba6ca6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8011: 26dca87f1252b7f6f0c0f833050256f0244d61e9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_138065v5: 3d2b2701d3c250fff370f5057f5a9d88d8ba6ca6 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/index.html
[-- Attachment #2: Type: text/html, Size: 3511 bytes --]
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-03 8:24 ` Suraj Kandpal
2024-09-05 4:41 ` Suraj Kandpal
@ 2024-09-09 14:12 ` Ville Syrjälä
2024-09-10 4:15 ` Kandpal, Suraj
1 sibling, 1 reply; 47+ messages in thread
From: Ville Syrjälä @ 2024-09-09 14:12 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx, uma.shankar, jouni.hogander
On Tue, Sep 03, 2024 at 01:54:50PM +0530, Suraj Kandpal wrote:
> To reach PC10 when PKG_C_LATENCY is configure we must do the following
> things
> 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
> 2) Allow PSR2 deep sleep when DC5 can be entered
> 3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
> eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
> not happening.
>
> --v2
> -Switch condition and do an early return [Jani]
> -Do some checks in compute_config [Jani]
> -Do not use register reads as a method of checking states for
> DPKGC or delayed vblank [Jani]
> -Use another way to see is vblank interrupts are disabled or not [Jani]
>
> --v3
> -Use has_psr to check if psr can be enabled or not for dc5_entry cond
> [Uma]
> -Move the dc5 entry computation to psr_compute_config [Jouni]
> -No need to change sequence of enabled and activate,
> so dont make hsw_psr1_activate return anything [Jouni]
> -Use has_psr to stop psr1 activation [Jouni]
> -Use lineage no. in WA
> -Add the display ver restrictions for WA
>
> --v4
> -use more appropriate name for check_vblank_limit() [Jouni]
> -Cover the case for idle frames when dpkgc is not configured [Jouni]
> -Check psr only for edp [Jouni]
>
> WA: 22019444797
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 2 +
> drivers/gpu/drm/i915/display/intel_psr.c | 101 +++++++++++++++++-
> 2 files changed, 102 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index fa03157554b2..6b95a59aba2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1717,6 +1717,8 @@ struct intel_psr {
> bool sink_support;
> bool source_support;
> bool enabled;
> + bool is_dpkgc_configured;
> + bool is_dc5_entry_possible;
> bool paused;
> enum pipe pipe;
> enum transcoder transcoder;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 257526362b39..6eb137ecd49f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -870,6 +870,74 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
> return idle_frames;
> }
>
> +static bool intel_psr_check_wa_delayed_vblank(struct intel_crtc_state *crtc_state)
> +{
> + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +
> + return (adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay) >= 6;
> +}
> +
> +/*
> + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> + * VRR is not enabled
> + */
> +static bool intel_psr_is_dpkgc_configured(struct drm_i915_private *i915)
> +{
> + struct intel_crtc *intel_crtc;
> +
> + if (DISPLAY_VER(i915) < 20)
> + return false;
> +
> + for_each_intel_crtc(&i915->drm, intel_crtc) {
> + struct intel_crtc_state *crtc_state;
> +
> + if (!intel_crtc->active)
> + continue;
> +
> + crtc_state = intel_crtc->config;
We are trying to remove all that old junk. Please do not use.
> +
> + if (crtc_state->vrr.enable)
> + return false;
> + }
> +
> + return true;
> +}
> +
> +/*
> + * DC5 entry is only possible if vblank interrupt is disabled
> + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> + * enabled encoders.
> + */
> +static bool
> +intel_psr_is_dc5_entry_possible(struct drm_i915_private *i915,
> + struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *intel_crtc;
> +
> + if (!crtc_state->has_psr)
> + return false;
> +
> + for_each_intel_crtc(&i915->drm, intel_crtc) {
> + struct drm_crtc *crtc = &intel_crtc->base;
> + struct drm_vblank_crtc *vblank;
> + struct intel_encoder *encoder;
> +
> + if (!intel_crtc->active)
> + continue;
> +
> + vblank = drm_crtc_vblank_crtc(crtc);
> +
> + if (vblank->enabled)
> + return false;
> +
> + for_each_encoder_on_crtc(&i915->drm, crtc, encoder)
> + if (encoder->type != INTEL_OUTPUT_EDP)
> + return false;
> + }
> +
> + return true;
> +}
> +
> static void hsw_activate_psr1(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> @@ -980,7 +1048,11 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> u32 val = EDP_PSR2_ENABLE;
> u32 psr_val = 0;
>
> - val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> + /* Wa_22019444797 */
> + if (DISPLAY_VER(dev_priv) != 20 ||
> + !intel_dp->psr.is_dpkgc_configured ||
> + intel_dp->psr.is_dc5_entry_possible)
> + val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
>
> if (DISPLAY_VER(dev_priv) < 14 && !IS_ALDERLAKE_P(dev_priv))
> val |= EDP_SU_TRACK_ENABLE;
> @@ -1595,6 +1667,32 @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
> return true;
> }
>
> +static void wa_22019444797(struct intel_dp *intel_dp,
> + struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +
> + if (DISPLAY_VER(i915) != 20)
> + return;
> +
> + intel_dp->psr.is_dpkgc_configured =
> + intel_psr_is_dpkgc_configured(i915);
> + intel_dp->psr.is_dc5_entry_possible =
> + intel_psr_is_dc5_entry_possible(i915, crtc_state);
> +
> + /* PSR2 not handled here. Wa not needed for Panel Replay */
> + if (crtc_state->has_sel_update || crtc_state->has_panel_replay)
> + return;
> +
> + if (intel_dp->psr.is_dpkgc_configured &&
> + !(intel_psr_check_wa_delayed_vblank(crtc_state) ||
> + intel_dp->psr.is_dc5_entry_possible)) {
> + drm_dbg_kms(&i915->drm,
> + "PSR1 not enabled as it doesn't meet requirements of WA: 22019444797\n");
> + crtc_state->has_psr = false;
> + }
> +}
> +
> void intel_psr_compute_config(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state,
> struct drm_connector_state *conn_state)
> @@ -1641,6 +1739,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> return;
>
> crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
> + wa_22019444797(intel_dp, crtc_state);
> }
>
> void intel_psr_get_config(struct intel_encoder *encoder,
> --
> 2.43.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-09 14:12 ` [PATCH] drm/i915/psr: Implment " Ville Syrjälä
@ 2024-09-10 4:15 ` Kandpal, Suraj
0 siblings, 0 replies; 47+ messages in thread
From: Kandpal, Suraj @ 2024-09-10 4:15 UTC (permalink / raw)
To: Ville Syrjälä
Cc: intel-gfx@lists.freedesktop.org, Shankar, Uma, Hogander, Jouni
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Monday, September 9, 2024 7:42 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Hogander, Jouni <jouni.hogander@intel.com>
> Subject: Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
>
> On Tue, Sep 03, 2024 at 01:54:50PM +0530, Suraj Kandpal wrote:
> > To reach PC10 when PKG_C_LATENCY is configure we must do the following
> > things
> > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> > entered
> > 2) Allow PSR2 deep sleep when DC5 can be entered
> > 3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
> > eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
> > not happening.
> >
> > --v2
> > -Switch condition and do an early return [Jani] -Do some checks in
> > compute_config [Jani] -Do not use register reads as a method of
> > checking states for DPKGC or delayed vblank [Jani] -Use another way to
> > see is vblank interrupts are disabled or not [Jani]
> >
> > --v3
> > -Use has_psr to check if psr can be enabled or not for dc5_entry cond
> > [Uma] -Move the dc5 entry computation to psr_compute_config [Jouni]
> > -No need to change sequence of enabled and activate, so dont make
> > hsw_psr1_activate return anything [Jouni] -Use has_psr to stop psr1
> > activation [Jouni] -Use lineage no. in WA -Add the display ver
> > restrictions for WA
> >
> > --v4
> > -use more appropriate name for check_vblank_limit() [Jouni] -Cover the
> > case for idle frames when dpkgc is not configured [Jouni] -Check psr
> > only for edp [Jouni]
> >
> > WA: 22019444797
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > .../drm/i915/display/intel_display_types.h | 2 +
> > drivers/gpu/drm/i915/display/intel_psr.c | 101 +++++++++++++++++-
> > 2 files changed, 102 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index fa03157554b2..6b95a59aba2e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1717,6 +1717,8 @@ struct intel_psr {
> > bool sink_support;
> > bool source_support;
> > bool enabled;
> > + bool is_dpkgc_configured;
> > + bool is_dc5_entry_possible;
> > bool paused;
> > enum pipe pipe;
> > enum transcoder transcoder;
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 257526362b39..6eb137ecd49f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -870,6 +870,74 @@ static u8 psr_compute_idle_frames(struct intel_dp
> *intel_dp)
> > return idle_frames;
> > }
> >
> > +static bool intel_psr_check_wa_delayed_vblank(struct intel_crtc_state
> > +*crtc_state) {
> > + struct drm_display_mode *adjusted_mode =
> > +&crtc_state->hw.adjusted_mode;
> > +
> > + return (adjusted_mode->crtc_vblank_start -
> > +adjusted_mode->crtc_vdisplay) >= 6; }
> > +
> > +/*
> > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> > + * VRR is not enabled
> > + */
> > +static bool intel_psr_is_dpkgc_configured(struct drm_i915_private
> > +*i915) {
> > + struct intel_crtc *intel_crtc;
> > +
> > + if (DISPLAY_VER(i915) < 20)
> > + return false;
> > +
> > + for_each_intel_crtc(&i915->drm, intel_crtc) {
> > + struct intel_crtc_state *crtc_state;
> > +
> > + if (!intel_crtc->active)
> > + continue;
> > +
> > + crtc_state = intel_crtc->config;
>
> We are trying to remove all that old junk. Please do not use.
>
Hi Ville this has already been taken care of in the latest revision
Regards,
Suraj Kandpal
> > +
> > + if (crtc_state->vrr.enable)
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > +/*
> > + * DC5 entry is only possible if vblank interrupt is disabled
> > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> > + * enabled encoders.
> > + */
> > +static bool
> > +intel_psr_is_dc5_entry_possible(struct drm_i915_private *i915,
> > + struct intel_crtc_state *crtc_state) {
> > + struct intel_crtc *intel_crtc;
> > +
> > + if (!crtc_state->has_psr)
> > + return false;
> > +
> > + for_each_intel_crtc(&i915->drm, intel_crtc) {
> > + struct drm_crtc *crtc = &intel_crtc->base;
> > + struct drm_vblank_crtc *vblank;
> > + struct intel_encoder *encoder;
> > +
> > + if (!intel_crtc->active)
> > + continue;
> > +
> > + vblank = drm_crtc_vblank_crtc(crtc);
> > +
> > + if (vblank->enabled)
> > + return false;
> > +
> > + for_each_encoder_on_crtc(&i915->drm, crtc, encoder)
> > + if (encoder->type != INTEL_OUTPUT_EDP)
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > static void hsw_activate_psr1(struct intel_dp *intel_dp) {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -980,7
> > +1048,11 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> > u32 val = EDP_PSR2_ENABLE;
> > u32 psr_val = 0;
> >
> > - val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > + /* Wa_22019444797 */
> > + if (DISPLAY_VER(dev_priv) != 20 ||
> > + !intel_dp->psr.is_dpkgc_configured ||
> > + intel_dp->psr.is_dc5_entry_possible)
> > + val |=
> EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> >
> > if (DISPLAY_VER(dev_priv) < 14 && !IS_ALDERLAKE_P(dev_priv))
> > val |= EDP_SU_TRACK_ENABLE;
> > @@ -1595,6 +1667,32 @@ _panel_replay_compute_config(struct intel_dp
> *intel_dp,
> > return true;
> > }
> >
> > +static void wa_22019444797(struct intel_dp *intel_dp,
> > + struct intel_crtc_state *crtc_state) {
> > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > +
> > + if (DISPLAY_VER(i915) != 20)
> > + return;
> > +
> > + intel_dp->psr.is_dpkgc_configured =
> > + intel_psr_is_dpkgc_configured(i915);
> > + intel_dp->psr.is_dc5_entry_possible =
> > + intel_psr_is_dc5_entry_possible(i915, crtc_state);
> > +
> > + /* PSR2 not handled here. Wa not needed for Panel Replay */
> > + if (crtc_state->has_sel_update || crtc_state->has_panel_replay)
> > + return;
> > +
> > + if (intel_dp->psr.is_dpkgc_configured &&
> > + !(intel_psr_check_wa_delayed_vblank(crtc_state) ||
> > + intel_dp->psr.is_dc5_entry_possible)) {
> > + drm_dbg_kms(&i915->drm,
> > + "PSR1 not enabled as it doesn't meet requirements of
> WA: 22019444797\n");
> > + crtc_state->has_psr = false;
> > + }
> > +}
> > +
> > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > struct intel_crtc_state *crtc_state,
> > struct drm_connector_state *conn_state) @@ -
> 1641,6 +1739,7
> > @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> > return;
> >
> > crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp,
> > crtc_state);
> > + wa_22019444797(intel_dp, crtc_state);
> > }
> >
> > void intel_psr_get_config(struct intel_encoder *encoder,
> > --
> > 2.43.2
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 47+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915/psr: Implment WA to help reach PC10 (rev5)
2024-09-02 5:02 [PATCH] drm/i915/psr: Implment WA to help reach PC10 Suraj Kandpal
` (8 preceding siblings ...)
2024-09-09 7:28 ` ✓ Fi.CI.BAT: success for drm/i915/psr: Implment WA to help reach PC10 (rev5) Patchwork
@ 2024-09-10 17:15 ` Patchwork
2024-09-20 10:57 ` ✓ Fi.CI.BAT: success for drm/i915/psr: Implment WA to help reach PC10 (rev6) Patchwork
` (3 subsequent siblings)
13 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2024-09-10 17:15 UTC (permalink / raw)
To: Kandpal, Suraj; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 100278 bytes --]
== Series Details ==
Series: drm/i915/psr: Implment WA to help reach PC10 (rev5)
URL : https://patchwork.freedesktop.org/series/138065/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15378_full -> Patchwork_138065v5_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_138065v5_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_138065v5_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 10)
------------------------------
Additional (1): shard-snb-0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_138065v5_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-dg2: NOTRUN -> [FAIL][1] +1 other test fail
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@i915_pm_rc6_residency@rc6-accuracy.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75:
- shard-glk: NOTRUN -> [INCOMPLETE][2] +1 other test incomplete
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-glk8/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75.html
* igt@kms_vblank@wait-idle-hang:
- shard-dg2: NOTRUN -> [INCOMPLETE][3] +1 other test incomplete
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-8/igt@kms_vblank@wait-idle-hang.html
Known issues
------------
Here are the changes found in Patchwork_138065v5_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-dg2: ([FAIL][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23]) -> ([PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-8/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-8/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-8/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-6/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-6/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-6/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-5/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-5/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-5/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-4/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-3/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-2/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-2/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-2/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-1/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-1/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-1/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-1/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-1/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-1/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-2/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-8/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-7/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-7/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-7/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-6/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-6/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-5/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-5/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-4/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-4/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-4/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-3/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-3/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-3/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-10/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-8/boot.html
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@crc32:
- shard-rkl: NOTRUN -> [SKIP][47] ([i915#6230])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@api_intel_bb@crc32.html
* igt@api_intel_bb@object-reloc-purge-cache:
- shard-dg2: NOTRUN -> [SKIP][48] ([i915#8411])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-8/igt@api_intel_bb@object-reloc-purge-cache.html
- shard-dg1: NOTRUN -> [SKIP][49] ([i915#8411])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@api_intel_bb@object-reloc-purge-cache.html
* igt@drm_fdinfo@busy-idle@vecs0:
- shard-mtlp: NOTRUN -> [SKIP][50] ([i915#8414]) +6 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@drm_fdinfo@busy-idle@vecs0.html
* igt@drm_fdinfo@most-busy-check-all@bcs0:
- shard-dg2: NOTRUN -> [SKIP][51] ([i915#8414]) +9 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-4/igt@drm_fdinfo@most-busy-check-all@bcs0.html
* igt@drm_fdinfo@virtual-busy-all:
- shard-dg1: NOTRUN -> [SKIP][52] ([i915#8414]) +1 other test skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-18/igt@drm_fdinfo@virtual-busy-all.html
* igt@gem_ccs@block-multicopy-compressed:
- shard-rkl: NOTRUN -> [SKIP][53] ([i915#9323])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@gem_ccs@block-multicopy-compressed.html
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-dg1: NOTRUN -> [SKIP][54] ([i915#9323])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
* igt@gem_create@create-ext-set-pat:
- shard-tglu: NOTRUN -> [SKIP][55] ([i915#8562])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_persistence@heartbeat-many:
- shard-mtlp: NOTRUN -> [SKIP][56] ([i915#8555])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@gem_ctx_persistence@heartbeat-many.html
* igt@gem_ctx_persistence@heartbeat-stop:
- shard-dg1: NOTRUN -> [SKIP][57] ([i915#8555])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@gem_ctx_persistence@heartbeat-stop.html
- shard-dg2: NOTRUN -> [SKIP][58] ([i915#8555]) +1 other test skip
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-8/igt@gem_ctx_persistence@heartbeat-stop.html
* igt@gem_ctx_persistence@hostile:
- shard-tglu: [PASS][59] -> [FAIL][60] ([i915#11980])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-tglu-5/igt@gem_ctx_persistence@hostile.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-8/igt@gem_ctx_persistence@hostile.html
* igt@gem_ctx_persistence@saturated-hostile-nopreempt:
- shard-dg2: NOTRUN -> [SKIP][61] ([i915#5882]) +7 other tests skip
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@gem_ctx_persistence@saturated-hostile-nopreempt.html
* igt@gem_ctx_sseu@engines:
- shard-dg1: NOTRUN -> [SKIP][62] ([i915#280])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@gem_ctx_sseu@engines.html
- shard-dg2: NOTRUN -> [SKIP][63] ([i915#280])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-8/igt@gem_ctx_sseu@engines.html
* igt@gem_ctx_sseu@mmap-args:
- shard-rkl: NOTRUN -> [SKIP][64] ([i915#280])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_eio@hibernate:
- shard-dg2: NOTRUN -> [ABORT][65] ([i915#10030] / [i915#7975] / [i915#8213])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-5/igt@gem_eio@hibernate.html
- shard-rkl: NOTRUN -> [ABORT][66] ([i915#7975] / [i915#8213])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@gem_eio@hibernate.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-tglu: NOTRUN -> [FAIL][67] ([i915#6117])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_capture@capture-invisible@smem0:
- shard-mtlp: NOTRUN -> [SKIP][68] ([i915#6334]) +1 other test skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@gem_exec_capture@capture-invisible@smem0.html
* igt@gem_exec_fair@basic-flow:
- shard-dg2: NOTRUN -> [SKIP][69] ([i915#3539] / [i915#4852]) +2 other tests skip
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@gem_exec_fair@basic-flow.html
* igt@gem_exec_fair@basic-none-solo:
- shard-tglu: NOTRUN -> [FAIL][70] ([i915#2842]) +3 other tests fail
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@gem_exec_fair@basic-none-solo.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-rkl: NOTRUN -> [FAIL][71] ([i915#2842]) +1 other test fail
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: NOTRUN -> [FAIL][72] ([i915#2842]) +7 other tests fail
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_fence@submit:
- shard-dg2: NOTRUN -> [SKIP][73] ([i915#4812]) +1 other test skip
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-4/igt@gem_exec_fence@submit.html
* igt@gem_exec_flush@basic-uc-prw-default:
- shard-dg1: NOTRUN -> [SKIP][74] ([i915#3539]) +1 other test skip
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@gem_exec_flush@basic-uc-prw-default.html
- shard-dg2: NOTRUN -> [SKIP][75] ([i915#3539])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-8/igt@gem_exec_flush@basic-uc-prw-default.html
* igt@gem_exec_flush@basic-wb-rw-default:
- shard-dg1: NOTRUN -> [SKIP][76] ([i915#3539] / [i915#4852])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@gem_exec_flush@basic-wb-rw-default.html
* igt@gem_exec_params@rsvd2-dirt:
- shard-dg2: NOTRUN -> [SKIP][77] ([i915#5107])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-4/igt@gem_exec_params@rsvd2-dirt.html
* igt@gem_exec_reloc@basic-gtt:
- shard-rkl: NOTRUN -> [SKIP][78] ([i915#3281]) +5 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@gem_exec_reloc@basic-gtt.html
* igt@gem_exec_reloc@basic-wc-gtt-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][79] ([i915#3281]) +1 other test skip
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@gem_exec_reloc@basic-wc-gtt-noreloc.html
* igt@gem_exec_reloc@basic-write-read-active:
- shard-dg2: NOTRUN -> [SKIP][80] ([i915#3281]) +10 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-8/igt@gem_exec_reloc@basic-write-read-active.html
- shard-dg1: NOTRUN -> [SKIP][81] ([i915#3281]) +5 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@gem_exec_reloc@basic-write-read-active.html
* igt@gem_exec_schedule@reorder-wide:
- shard-dg1: NOTRUN -> [SKIP][82] ([i915#4812]) +1 other test skip
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-18/igt@gem_exec_schedule@reorder-wide.html
* igt@gem_fence_thrash@bo-copy:
- shard-mtlp: NOTRUN -> [SKIP][83] ([i915#4860])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@gem_fence_thrash@bo-copy.html
* igt@gem_fenced_exec_thrash@2-spare-fences:
- shard-dg2: NOTRUN -> [SKIP][84] ([i915#4860]) +2 other tests skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-7/igt@gem_fenced_exec_thrash@2-spare-fences.html
* igt@gem_lmem_swapping@heavy-verify-random-ccs:
- shard-dg1: NOTRUN -> [SKIP][85] ([i915#12193])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-18/igt@gem_lmem_swapping@heavy-verify-random-ccs.html
* igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0:
- shard-dg1: NOTRUN -> [SKIP][86] ([i915#4565])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-18/igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0.html
* igt@gem_lmem_swapping@parallel-random:
- shard-glk: NOTRUN -> [SKIP][87] ([i915#4613])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-glk1/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-tglu: NOTRUN -> [SKIP][88] ([i915#4613])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_lmem_swapping@verify:
- shard-rkl: NOTRUN -> [SKIP][89] ([i915#4613]) +2 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@gem_lmem_swapping@verify.html
* igt@gem_media_vme:
- shard-dg2: NOTRUN -> [SKIP][90] ([i915#284])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-1/igt@gem_media_vme.html
- shard-rkl: NOTRUN -> [SKIP][91] ([i915#284])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-6/igt@gem_media_vme.html
* igt@gem_mmap_gtt@coherency:
- shard-dg1: NOTRUN -> [SKIP][92] ([i915#4077]) +4 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-18/igt@gem_mmap_gtt@coherency.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy:
- shard-mtlp: NOTRUN -> [SKIP][93] ([i915#4077]) +4 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@gem_mmap_gtt@cpuset-basic-small-copy.html
* igt@gem_mmap_gtt@hang:
- shard-dg2: NOTRUN -> [SKIP][94] ([i915#4077]) +10 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-4/igt@gem_mmap_gtt@hang.html
* igt@gem_mmap_offset@clear:
- shard-dg1: NOTRUN -> [INCOMPLETE][95] ([i915#10193]) +1 other test incomplete
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@gem_mmap_offset@clear.html
* igt@gem_mmap_wc@read:
- shard-mtlp: NOTRUN -> [SKIP][96] ([i915#4083]) +2 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@gem_mmap_wc@read.html
* igt@gem_mmap_wc@write-prefaulted:
- shard-dg2: NOTRUN -> [SKIP][97] ([i915#4083]) +5 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-8/igt@gem_mmap_wc@write-prefaulted.html
- shard-dg1: NOTRUN -> [SKIP][98] ([i915#4083]) +1 other test skip
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@gem_mmap_wc@write-prefaulted.html
* igt@gem_pread@exhaustion:
- shard-tglu: NOTRUN -> [WARN][99] ([i915#2658])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@gem_pread@exhaustion.html
* igt@gem_pread@snoop:
- shard-dg2: NOTRUN -> [SKIP][100] ([i915#3282]) +6 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@gem_pread@snoop.html
* igt@gem_pwrite@basic-self:
- shard-rkl: NOTRUN -> [SKIP][101] ([i915#3282]) +4 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@gem_pwrite@basic-self.html
* igt@gem_pwrite_snooped:
- shard-dg1: NOTRUN -> [SKIP][102] ([i915#3282]) +1 other test skip
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-18/igt@gem_pwrite_snooped.html
* igt@gem_pxp@display-protected-crc:
- shard-rkl: NOTRUN -> [SKIP][103] ([i915#4270]) +2 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@gem_pxp@display-protected-crc.html
* igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
- shard-dg2: NOTRUN -> [SKIP][104] ([i915#4270]) +1 other test skip
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
* igt@gem_pxp@protected-encrypted-src-copy-not-readible:
- shard-mtlp: NOTRUN -> [SKIP][105] ([i915#4270])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs:
- shard-dg2: NOTRUN -> [SKIP][106] ([i915#5190] / [i915#8428]) +5 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs.html
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled:
- shard-mtlp: NOTRUN -> [SKIP][107] ([i915#8428])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled.html
* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- shard-dg2: NOTRUN -> [SKIP][108] ([i915#4079]) +1 other test skip
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-8/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
- shard-dg1: NOTRUN -> [SKIP][109] ([i915#4079])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
* igt@gem_set_tiling_vs_pwrite:
- shard-mtlp: NOTRUN -> [SKIP][110] ([i915#4079])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@gem_set_tiling_vs_pwrite.html
* igt@gem_userptr_blits@coherency-sync:
- shard-tglu: NOTRUN -> [SKIP][111] ([i915#3297])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@gem_userptr_blits@coherency-sync.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-mtlp: NOTRUN -> [SKIP][112] ([i915#3297])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-dg2: NOTRUN -> [SKIP][113] ([i915#3297]) +2 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-dg2: NOTRUN -> [SKIP][114] ([i915#3297] / [i915#4880]) +1 other test skip
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-7/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@unsync-unmap-after-close:
- shard-rkl: NOTRUN -> [SKIP][115] ([i915#3297])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@gem_userptr_blits@unsync-unmap-after-close.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-rkl: NOTRUN -> [SKIP][116] ([i915#2527]) +1 other test skip
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@gen9_exec_parse@batch-invalid-length.html
* igt@gen9_exec_parse@bb-start-out:
- shard-mtlp: NOTRUN -> [SKIP][117] ([i915#2856])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@gen9_exec_parse@bb-start-out.html
* igt@gen9_exec_parse@unaligned-jump:
- shard-tglu: NOTRUN -> [SKIP][118] ([i915#2527] / [i915#2856]) +1 other test skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@gen9_exec_parse@unaligned-jump.html
* igt@gen9_exec_parse@valid-registers:
- shard-dg2: NOTRUN -> [SKIP][119] ([i915#2856]) +1 other test skip
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-7/igt@gen9_exec_parse@valid-registers.html
* igt@i915_fb_tiling:
- shard-mtlp: NOTRUN -> [SKIP][120] ([i915#4881])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@i915_fb_tiling.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-tglu: [PASS][121] -> [ABORT][122] ([i915#9820])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-tglu-3/igt@i915_module_load@reload-with-fault-injection.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-10/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_module_load@resize-bar:
- shard-dg1: NOTRUN -> [SKIP][123] ([i915#7178])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@i915_module_load@resize-bar.html
* igt@i915_pm_freq_api@freq-suspend:
- shard-rkl: NOTRUN -> [SKIP][124] ([i915#8399]) +1 other test skip
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@i915_pm_freq_api@freq-suspend.html
* igt@i915_pm_rps@thresholds-park:
- shard-dg2: NOTRUN -> [SKIP][125] ([i915#11681]) +1 other test skip
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@i915_pm_rps@thresholds-park.html
* igt@i915_query@query-topology-coherent-slice-mask:
- shard-dg2: NOTRUN -> [SKIP][126] ([i915#6188])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-8/igt@i915_query@query-topology-coherent-slice-mask.html
* igt@i915_selftest@mock:
- shard-tglu: NOTRUN -> [DMESG-WARN][127] ([i915#9311]) +1 other test dmesg-warn
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@i915_selftest@mock.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- shard-dg2: NOTRUN -> [SKIP][128] ([i915#4212]) +1 other test skip
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-8/igt@kms_addfb_basic@basic-x-tiled-legacy.html
- shard-dg1: NOTRUN -> [SKIP][129] ([i915#4212])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@kms_addfb_basic@basic-x-tiled-legacy.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-rkl: NOTRUN -> [SKIP][130] ([i915#1769] / [i915#3555])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_atomic_transition@plane-toggle-modeset-transition:
- shard-snb: [PASS][131] -> [FAIL][132] ([i915#5956]) +1 other test fail
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-snb2/igt@kms_atomic_transition@plane-toggle-modeset-transition.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-snb6/igt@kms_atomic_transition@plane-toggle-modeset-transition.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-180:
- shard-rkl: NOTRUN -> [SKIP][133] ([i915#5286]) +4 other tests skip
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_big_fb@4-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-0:
- shard-dg1: NOTRUN -> [SKIP][134] ([i915#4538] / [i915#5286]) +2 other tests skip
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@kms_big_fb@4-tiled-8bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
- shard-tglu: NOTRUN -> [SKIP][135] ([i915#5286])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@linear-16bpp-rotate-90:
- shard-tglu: NOTRUN -> [SKIP][136] +20 other tests skip
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@kms_big_fb@linear-16bpp-rotate-90.html
* igt@kms_big_fb@linear-64bpp-rotate-90:
- shard-dg1: NOTRUN -> [SKIP][137] ([i915#3638]) +1 other test skip
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@kms_big_fb@linear-64bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][138] +24 other tests skip
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-8/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-180:
- shard-dg2: NOTRUN -> [SKIP][139] ([i915#4538] / [i915#5190]) +10 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-1/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-dg1: NOTRUN -> [SKIP][140] ([i915#4538])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-18/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_joiner@basic:
- shard-rkl: NOTRUN -> [SKIP][141] ([i915#10656]) +2 other tests skip
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_big_joiner@basic.html
* igt@kms_big_joiner@invalid-modeset-force-joiner:
- shard-dg2: NOTRUN -> [SKIP][142] ([i915#10656])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-4/igt@kms_big_joiner@invalid-modeset-force-joiner.html
* igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs:
- shard-mtlp: NOTRUN -> [SKIP][143] ([i915#6095]) +19 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs.html
* igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][144] ([i915#6095]) +64 other tests skip
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-18/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-4.html
* igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][145] ([i915#10307] / [i915#6095]) +171 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-4/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][146] ([i915#6095]) +95 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-2/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
- shard-dg1: NOTRUN -> [SKIP][147] ([i915#12042])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-18/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][148] ([i915#6095]) +14 other tests skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-1.html
* igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][149] ([i915#10307] / [i915#10434] / [i915#6095]) +2 other tests skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-8/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-d-hdmi-a-1.html
* igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][150] ([i915#11616] / [i915#7213]) +4 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-4/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1.html
* igt@kms_cdclk@plane-scaling:
- shard-tglu: NOTRUN -> [SKIP][151] ([i915#3742])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@kms_cdclk@plane-scaling.html
* igt@kms_chamelium_audio@hdmi-audio:
- shard-dg2: NOTRUN -> [SKIP][152] ([i915#7828]) +10 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_chamelium_audio@hdmi-audio.html
* igt@kms_chamelium_color@ctm-max:
- shard-mtlp: NOTRUN -> [SKIP][153] +3 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@kms_chamelium_color@ctm-max.html
* igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k:
- shard-rkl: NOTRUN -> [SKIP][154] ([i915#7828]) +6 other tests skip
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html
* igt@kms_chamelium_frames@dp-crc-single:
- shard-tglu: NOTRUN -> [SKIP][155] ([i915#7828]) +1 other test skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@kms_chamelium_frames@dp-crc-single.html
* igt@kms_chamelium_hpd@vga-hpd-for-each-pipe:
- shard-dg1: NOTRUN -> [SKIP][156] ([i915#7828]) +3 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@kms_chamelium_hpd@vga-hpd-for-each-pipe.html
* igt@kms_chamelium_hpd@vga-hpd-without-ddc:
- shard-mtlp: NOTRUN -> [SKIP][157] ([i915#7828]) +1 other test skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@kms_chamelium_hpd@vga-hpd-without-ddc.html
* igt@kms_content_protection@atomic-dpms:
- shard-tglu: NOTRUN -> [SKIP][158] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-dg2: NOTRUN -> [SKIP][159] ([i915#3299])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-7/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@lic-type-1:
- shard-rkl: NOTRUN -> [SKIP][160] ([i915#9424])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_content_protection@lic-type-1.html
* igt@kms_content_protection@mei-interface:
- shard-dg2: NOTRUN -> [SKIP][161] ([i915#9424]) +1 other test skip
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@srm:
- shard-rkl: NOTRUN -> [SKIP][162] ([i915#7118])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_content_protection@srm.html
* igt@kms_content_protection@uevent@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [FAIL][163] ([i915#1339] / [i915#7173])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_content_protection@uevent@pipe-a-dp-4.html
* igt@kms_cursor_crc@cursor-offscreen-512x170:
- shard-mtlp: NOTRUN -> [SKIP][164] ([i915#3359])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@kms_cursor_crc@cursor-offscreen-512x170.html
* igt@kms_cursor_crc@cursor-random-32x32:
- shard-tglu: NOTRUN -> [SKIP][165] ([i915#3555]) +1 other test skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@kms_cursor_crc@cursor-random-32x32.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-rkl: NOTRUN -> [SKIP][166] ([i915#11453])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-sliding-32x10:
- shard-rkl: NOTRUN -> [SKIP][167] ([i915#3555]) +7 other tests skip
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_cursor_crc@cursor-sliding-32x10.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-dg1: NOTRUN -> [SKIP][168] ([i915#11453])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-18/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_crc@cursor-sliding-max-size:
- shard-mtlp: NOTRUN -> [SKIP][169] ([i915#3555] / [i915#8814])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-4/igt@kms_cursor_crc@cursor-sliding-max-size.html
* igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
- shard-mtlp: NOTRUN -> [SKIP][170] ([i915#9809])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [PASS][171] -> [FAIL][172] ([i915#2346])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
- shard-tglu: NOTRUN -> [SKIP][173] ([i915#9067])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-dg2: NOTRUN -> [SKIP][174] ([i915#4103] / [i915#4213]) +1 other test skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-4/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
- shard-rkl: NOTRUN -> [SKIP][175] ([i915#4103])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_dither@fb-8bpc-vs-panel-8bpc:
- shard-dg1: NOTRUN -> [SKIP][176] ([i915#3555]) +2 other tests skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-18/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
* igt@kms_dp_aux_dev:
- shard-rkl: NOTRUN -> [SKIP][177] ([i915#1257])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_dp_aux_dev.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-tglu: NOTRUN -> [SKIP][178] ([i915#3840])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-dg2: NOTRUN -> [SKIP][179] ([i915#3555] / [i915#3840])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-4/igt@kms_dsc@dsc-with-output-formats.html
- shard-rkl: NOTRUN -> [SKIP][180] ([i915#3555] / [i915#3840])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-tglu: NOTRUN -> [SKIP][181] ([i915#3469])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_feature_discovery@psr1:
- shard-rkl: NOTRUN -> [SKIP][182] ([i915#658])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_feature_discovery@psr1.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-mtlp: NOTRUN -> [SKIP][183] ([i915#3637]) +3 other tests skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][184] -> [FAIL][185] ([i915#79]) +1 other test fail
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-plain-flip:
- shard-rkl: NOTRUN -> [SKIP][186] +24 other tests skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
- shard-snb: [PASS][187] -> [FAIL][188] ([i915#2122]) +1 other test fail
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-snb4/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-snb7/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-dg1: NOTRUN -> [SKIP][189] ([i915#9934]) +2 other tests skip
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip@plain-flip-ts-check@c-hdmi-a3:
- shard-dg2: NOTRUN -> [FAIL][190] ([i915#2122]) +2 other tests fail
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-6/igt@kms_flip@plain-flip-ts-check@c-hdmi-a3.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][191] ([i915#2672]) +2 other tests skip
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling:
- shard-rkl: NOTRUN -> [SKIP][192] ([i915#2672] / [i915#3555]) +2 other tests skip
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling:
- shard-dg1: NOTRUN -> [SKIP][193] ([i915#2672] / [i915#3555])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][194] ([i915#2587] / [i915#2672])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling:
- shard-tglu: NOTRUN -> [SKIP][195] ([i915#2672] / [i915#3555])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][196] ([i915#2587] / [i915#2672])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling:
- shard-dg2: NOTRUN -> [SKIP][197] ([i915#2672] / [i915#3555] / [i915#5190]) +3 other tests skip
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][198] ([i915#2672]) +3 other tests skip
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
- shard-dg1: NOTRUN -> [SKIP][199] +17 other tests skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][200] ([i915#8708]) +2 other tests skip
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][201] ([i915#8708]) +5 other tests skip
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-18/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt:
- shard-rkl: NOTRUN -> [SKIP][202] ([i915#1825]) +23 other tests skip
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
- shard-mtlp: NOTRUN -> [SKIP][203] ([i915#1825]) +8 other tests skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][204] ([i915#3458]) +11 other tests skip
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][205] ([i915#8708]) +13 other tests skip
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
- shard-dg1: NOTRUN -> [SKIP][206] ([i915#3458]) +7 other tests skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-rkl: NOTRUN -> [SKIP][207] ([i915#5439])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@pipe-fbc-rte:
- shard-rkl: NOTRUN -> [SKIP][208] ([i915#9766])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-6/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
- shard-dg2: NOTRUN -> [SKIP][209] ([i915#9766])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-1/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
- shard-rkl: NOTRUN -> [SKIP][210] ([i915#3023]) +18 other tests skip
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
- shard-dg2: NOTRUN -> [SKIP][211] ([i915#10433] / [i915#3458])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][212] ([i915#5354]) +33 other tests skip
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_getfb@getfb-reject-ccs:
- shard-dg2: NOTRUN -> [SKIP][213] ([i915#6118])
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_getfb@getfb-reject-ccs.html
* igt@kms_hdr@invalid-hdr:
- shard-rkl: NOTRUN -> [SKIP][214] ([i915#3555] / [i915#8228]) +1 other test skip
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_hdr@invalid-hdr.html
* igt@kms_hdr@static-toggle:
- shard-mtlp: NOTRUN -> [SKIP][215] ([i915#3555] / [i915#8228])
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@kms_hdr@static-toggle.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-vga-1:
- shard-snb: NOTRUN -> [SKIP][216]
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-snb7/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-vga-1.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [FAIL][217] ([i915#8292])
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-2/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][218] ([i915#9423]) +8 other tests skip
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-16/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-hdmi-a-4.html
* igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][219] ([i915#9423]) +12 other tests skip
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-1/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][220] ([i915#5176] / [i915#9423]) +3 other tests skip
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-16/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-hdmi-a-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][221] ([i915#9728]) +3 other tests skip
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-3/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25:
- shard-dg2: NOTRUN -> [SKIP][222] ([i915#6953] / [i915#9423])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-8/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html
- shard-dg1: NOTRUN -> [SKIP][223] ([i915#6953])
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][224] ([i915#5235] / [i915#9423]) +2 other tests skip
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-8/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][225] ([i915#5235]) +2 other tests skip
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-c-hdmi-a-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][226] ([i915#9728])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-hdmi-a-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-dp-4:
- shard-dg2: NOTRUN -> [SKIP][227] ([i915#9423]) +17 other tests skip
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-dp-4.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5:
- shard-mtlp: NOTRUN -> [SKIP][228] ([i915#5235] / [i915#6953])
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][229] ([i915#5235]) +3 other tests skip
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d-edp-1.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-dg1: NOTRUN -> [SKIP][230] ([i915#9519])
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-dg2: [PASS][231] -> [SKIP][232] ([i915#9519]) +2 other tests skip
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-4/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
- shard-rkl: [PASS][233] -> [SKIP][234] ([i915#9519]) +2 other tests skip
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-rkl-5/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-2/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_prime@basic-crc-hybrid:
- shard-dg2: NOTRUN -> [SKIP][235] ([i915#6524] / [i915#6805])
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-4/igt@kms_prime@basic-crc-hybrid.html
- shard-rkl: NOTRUN -> [SKIP][236] ([i915#6524])
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_prime@d3hot:
- shard-mtlp: NOTRUN -> [SKIP][237] ([i915#6524])
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@kms_prime@d3hot.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-dg1: NOTRUN -> [SKIP][238] ([i915#11520]) +1 other test skip
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-18/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@kms_psr2_sf@fbc-overlay-plane-update-continuous-sf:
- shard-tglu: NOTRUN -> [SKIP][239] ([i915#11520])
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@kms_psr2_sf@fbc-overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@fbc-overlay-plane-update-sf-dmg-area:
- shard-rkl: NOTRUN -> [SKIP][240] ([i915#11520]) +1 other test skip
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_psr2_sf@fbc-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@fbc-overlay-primary-update-sf-dmg-area:
- shard-mtlp: NOTRUN -> [SKIP][241] ([i915#9808]) +2 other tests skip
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@kms_psr2_sf@fbc-overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf:
- shard-dg2: NOTRUN -> [SKIP][242] ([i915#11520]) +2 other tests skip
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-8/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_su@page_flip-p010:
- shard-dg1: NOTRUN -> [SKIP][243] ([i915#9683])
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-18/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-dg2: NOTRUN -> [SKIP][244] ([i915#9683])
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-pr-sprite-plane-onoff:
- shard-rkl: NOTRUN -> [SKIP][245] ([i915#1072] / [i915#9732]) +17 other tests skip
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_psr@fbc-pr-sprite-plane-onoff.html
* igt@kms_psr@fbc-pr-suspend:
- shard-dg2: NOTRUN -> [SKIP][246] ([i915#1072] / [i915#9732]) +15 other tests skip
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-7/igt@kms_psr@fbc-pr-suspend.html
* igt@kms_psr@fbc-psr-dpms:
- shard-dg2: NOTRUN -> [SKIP][247] ([i915#1072] / [i915#9673] / [i915#9732]) +4 other tests skip
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_psr@fbc-psr-dpms.html
* igt@kms_psr@fbc-psr2-no-drrs:
- shard-tglu: NOTRUN -> [SKIP][248] ([i915#9732]) +4 other tests skip
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@kms_psr@fbc-psr2-no-drrs.html
* igt@kms_psr@pr-cursor-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][249] ([i915#9688]) +5 other tests skip
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@kms_psr@pr-cursor-mmap-gtt.html
* igt@kms_psr@psr-no-drrs:
- shard-glk: NOTRUN -> [SKIP][250] +274 other tests skip
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-glk1/igt@kms_psr@psr-no-drrs.html
* igt@kms_psr@psr2-cursor-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][251] ([i915#1072] / [i915#9732]) +8 other tests skip
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@kms_psr@psr2-cursor-mmap-gtt.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-dg2: NOTRUN -> [SKIP][252] ([i915#9685])
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@primary-rotation-90:
- shard-dg2: NOTRUN -> [SKIP][253] ([i915#11131])
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-7/igt@kms_rotation_crc@primary-rotation-90.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-dg1: NOTRUN -> [SKIP][254] ([i915#5289])
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-18/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-mtlp: NOTRUN -> [SKIP][255] ([i915#5289])
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-dg2: NOTRUN -> [SKIP][256] ([i915#11131] / [i915#4235] / [i915#5190])
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-rkl: NOTRUN -> [SKIP][257] ([i915#5289])
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-dg1: [PASS][258] -> [DMESG-WARN][259] ([i915#1982])
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg1-18/igt@kms_rotation_crc@sprite-rotation-90.html
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-14/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@kms_setmode@invalid-clone-exclusive-crtc:
- shard-dg2: NOTRUN -> [SKIP][260] ([i915#3555]) +4 other tests skip
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-1/igt@kms_setmode@invalid-clone-exclusive-crtc.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-rkl: NOTRUN -> [SKIP][261] ([i915#8623])
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_universal_plane@cursor-fb-leak:
- shard-dg2: [PASS][262] -> [FAIL][263] ([i915#9196])
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-6/igt@kms_universal_plane@cursor-fb-leak.html
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-3/igt@kms_universal_plane@cursor-fb-leak.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1:
- shard-tglu: [PASS][264] -> [FAIL][265] ([i915#9196])
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-tglu-10/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-7/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-2:
- shard-dg2: NOTRUN -> [FAIL][266] ([i915#9196])
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-3/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-2.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1:
- shard-snb: [PASS][267] -> [FAIL][268] ([i915#9196]) +1 other test fail
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-snb4/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-snb7/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
* igt@kms_vrr@flipline:
- shard-mtlp: NOTRUN -> [SKIP][269] ([i915#3555] / [i915#8808])
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-2/igt@kms_vrr@flipline.html
* igt@kms_writeback@writeback-check-output-xrgb2101010:
- shard-dg2: NOTRUN -> [SKIP][270] ([i915#2437] / [i915#9412])
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-7/igt@kms_writeback@writeback-check-output-xrgb2101010.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-tglu: NOTRUN -> [SKIP][271] ([i915#2437] / [i915#9412])
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-glk: NOTRUN -> [SKIP][272] ([i915#2437])
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-glk1/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@mi-rpc:
- shard-dg1: NOTRUN -> [SKIP][273] ([i915#2434])
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-18/igt@perf@mi-rpc.html
* igt@perf_pmu@rc6-all-gts:
- shard-dg1: NOTRUN -> [SKIP][274] ([i915#8516])
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@perf_pmu@rc6-all-gts.html
- shard-dg2: NOTRUN -> [SKIP][275] ([i915#8516])
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-8/igt@perf_pmu@rc6-all-gts.html
* igt@perf_pmu@semaphore-busy@vecs0:
- shard-dg2: NOTRUN -> [FAIL][276] ([i915#4349]) +4 other tests fail
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-7/igt@perf_pmu@semaphore-busy@vecs0.html
* igt@prime_vgem@basic-fence-flip:
- shard-dg1: NOTRUN -> [SKIP][277] ([i915#3708])
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-18/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-read:
- shard-dg2: NOTRUN -> [SKIP][278] ([i915#3291] / [i915#3708])
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-7/igt@prime_vgem@basic-read.html
* igt@sriov_basic@bind-unbind-vf:
- shard-rkl: NOTRUN -> [SKIP][279] ([i915#9917]) +1 other test skip
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-4/igt@sriov_basic@bind-unbind-vf.html
* igt@sriov_basic@enable-vfs-bind-unbind-each:
- shard-dg2: NOTRUN -> [SKIP][280] ([i915#9917])
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-7/igt@sriov_basic@enable-vfs-bind-unbind-each.html
* igt@syncobj_timeline@invalid-wait-zero-handles:
- shard-dg1: NOTRUN -> [FAIL][281] ([i915#9781])
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-18/igt@syncobj_timeline@invalid-wait-zero-handles.html
* igt@syncobj_wait@invalid-wait-zero-handles:
- shard-dg2: NOTRUN -> [FAIL][282] ([i915#9781])
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-1/igt@syncobj_wait@invalid-wait-zero-handles.html
- shard-rkl: NOTRUN -> [FAIL][283] ([i915#9781])
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-6/igt@syncobj_wait@invalid-wait-zero-handles.html
- shard-glk: NOTRUN -> [FAIL][284] ([i915#9781])
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-glk6/igt@syncobj_wait@invalid-wait-zero-handles.html
#### Possible fixes ####
* igt@device_reset@unbind-reset-rebind:
- shard-dg2: [SKIP][285] ([i915#11224]) -> [PASS][286]
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@device_reset@unbind-reset-rebind.html
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@device_reset@unbind-reset-rebind.html
* igt@gem_eio@hibernate:
- shard-tglu: [ABORT][287] ([i915#10030] / [i915#7975] / [i915#8213]) -> [PASS][288]
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-tglu-10/igt@gem_eio@hibernate.html
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-3/igt@gem_eio@hibernate.html
* igt@gem_exec_await@wide-contexts:
- shard-dg2: [INCOMPLETE][289] -> [PASS][290]
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-1/igt@gem_exec_await@wide-contexts.html
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-10/igt@gem_exec_await@wide-contexts.html
- shard-dg1: [INCOMPLETE][291] -> [PASS][292]
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg1-13/igt@gem_exec_await@wide-contexts.html
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-18/igt@gem_exec_await@wide-contexts.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-rkl: [FAIL][293] ([i915#2842]) -> [PASS][294]
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-rkl-2/igt@gem_exec_fair@basic-none@vcs0.html
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-3/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [ABORT][295] ([i915#5566]) -> [PASS][296]
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-glk4/igt@gen9_exec_parse@allowed-single.html
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-glk2/igt@gen9_exec_parse@allowed-single.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-rkl: [ABORT][297] ([i915#9697]) -> [PASS][298]
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-rkl-4/igt@i915_module_load@reload-with-fault-injection.html
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-6/igt@i915_module_load@reload-with-fault-injection.html
- shard-glk: [ABORT][299] ([i915#9820]) -> [PASS][300]
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-glk1/igt@i915_module_load@reload-with-fault-injection.html
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-glk6/igt@i915_module_load@reload-with-fault-injection.html
- shard-dg2: [ABORT][301] ([i915#9820]) -> [PASS][302]
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-8/igt@i915_module_load@reload-with-fault-injection.html
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-1/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0:
- shard-dg1: [FAIL][303] ([i915#3591]) -> [PASS][304] +1 other test pass
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
* igt@kms_atomic_transition@modeset-transition-fencing:
- shard-glk: [FAIL][305] -> [PASS][306]
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-glk8/igt@kms_atomic_transition@modeset-transition-fencing.html
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-glk6/igt@kms_atomic_transition@modeset-transition-fencing.html
* igt@kms_atomic_transition@modeset-transition-fencing@2x-outputs:
- shard-glk: [FAIL][307] ([i915#11859]) -> [PASS][308]
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-glk8/igt@kms_atomic_transition@modeset-transition-fencing@2x-outputs.html
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-glk6/igt@kms_atomic_transition@modeset-transition-fencing@2x-outputs.html
* igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1:
- shard-mtlp: [FAIL][309] ([i915#11808] / [i915#5956]) -> [PASS][310] +1 other test pass
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-mtlp-6/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1.html
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-6/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1.html
* igt@kms_big_joiner@basic-force-joiner:
- shard-dg2: [SKIP][311] ([i915#10656]) -> [PASS][312]
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-4/igt@kms_big_joiner@basic-force-joiner.html
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_big_joiner@basic-force-joiner.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [FAIL][313] ([i915#2346]) -> [PASS][314]
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@torture-bo:
- shard-mtlp: [INCOMPLETE][315] -> [PASS][316] +1 other test pass
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-mtlp-8/igt@kms_cursor_legacy@torture-bo.html
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-4/igt@kms_cursor_legacy@torture-bo.html
* igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][317] ([i915#79]) -> [PASS][318] +1 other test pass
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-hdmi-a3:
- shard-dg2: [FAIL][319] ([i915#2122]) -> [PASS][320]
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-6/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-hdmi-a3.html
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-6/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-hdmi-a3.html
* igt@kms_flip@wf_vblank-ts-check-interruptible:
- shard-rkl: [FAIL][321] ([i915#2122]) -> [PASS][322]
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-rkl-5/igt@kms_flip@wf_vblank-ts-check-interruptible.html
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-5/igt@kms_flip@wf_vblank-ts-check-interruptible.html
* igt@kms_flip@wf_vblank-ts-check-interruptible@b-hdmi-a2:
- shard-rkl: [FAIL][323] ([i915#11961]) -> [PASS][324] +1 other test pass
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-rkl-5/igt@kms_flip@wf_vblank-ts-check-interruptible@b-hdmi-a2.html
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-5/igt@kms_flip@wf_vblank-ts-check-interruptible@b-hdmi-a2.html
* igt@kms_hdr@static-toggle-dpms:
- shard-dg2: [SKIP][325] ([i915#3555] / [i915#8228]) -> [PASS][326]
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-4/igt@kms_hdr@static-toggle-dpms.html
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_plane_scaling@plane-scaler-unity-scaling-with-pixel-format:
- shard-dg2: [SKIP][327] ([i915#2575] / [i915#9423]) -> [PASS][328] +1 other test pass
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-pixel-format.html
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-pixel-format.html
* igt@kms_pm_rpm@basic-pci-d3-state:
- shard-dg2: [SKIP][329] -> [PASS][330] +5 other tests pass
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_pm_rpm@basic-pci-d3-state.html
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_pm_rpm@basic-pci-d3-state.html
* igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-dg2: [SKIP][331] ([i915#9519]) -> [PASS][332] +1 other test pass
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-6/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
[332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-4/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@kms_universal_plane@cursor-fb-leak:
- shard-rkl: [FAIL][333] ([i915#9196]) -> [PASS][334]
[333]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-rkl-2/igt@kms_universal_plane@cursor-fb-leak.html
[334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-5/igt@kms_universal_plane@cursor-fb-leak.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1:
- shard-tglu: [FAIL][335] ([i915#9196]) -> [PASS][336]
[335]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-tglu-10/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
[336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-7/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
* igt@kms_vblank@query-forked-hang@pipe-c-hdmi-a-1:
- shard-glk: [INCOMPLETE][337] -> [PASS][338] +1 other test pass
[337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-glk3/igt@kms_vblank@query-forked-hang@pipe-c-hdmi-a-1.html
[338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-glk6/igt@kms_vblank@query-forked-hang@pipe-c-hdmi-a-1.html
* igt@perf@create-destroy-userspace-config:
- shard-dg2: [SKIP][339] ([i915#11692]) -> [PASS][340] +3 other tests pass
[339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@perf@create-destroy-userspace-config.html
[340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@perf@create-destroy-userspace-config.html
* igt@perf_pmu@semaphore-busy@vecs0:
- shard-mtlp: [FAIL][341] ([i915#4349]) -> [PASS][342]
[341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-mtlp-8/igt@perf_pmu@semaphore-busy@vecs0.html
[342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-4/igt@perf_pmu@semaphore-busy@vecs0.html
* igt@syncobj_timeline@wait-all-for-submit-delayed-submit:
- shard-dg2: [SKIP][343] ([i915#2575]) -> [PASS][344] +47 other tests pass
[343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@syncobj_timeline@wait-all-for-submit-delayed-submit.html
[344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@syncobj_timeline@wait-all-for-submit-delayed-submit.html
#### Warnings ####
* igt@gem_exec_balancer@bonded-true-hang:
- shard-dg2: [SKIP][345] ([i915#2575]) -> [SKIP][346] ([i915#4812])
[345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@gem_exec_balancer@bonded-true-hang.html
[346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@gem_exec_balancer@bonded-true-hang.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglu: [FAIL][347] ([i915#2876]) -> [FAIL][348] ([i915#2842])
[347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-tglu-7/igt@gem_exec_fair@basic-pace@rcs0.html
[348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-tglu-6/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_reloc@basic-gtt-cpu-active:
- shard-dg2: [SKIP][349] ([i915#2575]) -> [SKIP][350] ([i915#3281]) +1 other test skip
[349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@gem_exec_reloc@basic-gtt-cpu-active.html
[350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@gem_exec_reloc@basic-gtt-cpu-active.html
* igt@gem_lmem_swapping@smem-oom:
- shard-dg2: [TIMEOUT][351] ([i915#5493]) -> [DMESG-WARN][352] ([i915#5493])
[351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-5/igt@gem_lmem_swapping@smem-oom.html
[352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-7/igt@gem_lmem_swapping@smem-oom.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [TIMEOUT][353] ([i915#5493]) -> [DMESG-WARN][354] ([i915#4936] / [i915#5493])
[353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-5/igt@gem_lmem_swapping@smem-oom@lmem0.html
[354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-7/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-dg2: [SKIP][355] ([i915#2575]) -> [SKIP][356] ([i915#4077]) +3 other tests skip
[355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
[356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
* igt@gem_mmap_wc@close:
- shard-dg2: [SKIP][357] ([i915#2575]) -> [SKIP][358] ([i915#4083]) +1 other test skip
[357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@gem_mmap_wc@close.html
[358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@gem_mmap_wc@close.html
* igt@gem_pread@self:
- shard-dg2: [SKIP][359] ([i915#2575]) -> [SKIP][360] ([i915#3282])
[359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@gem_pread@self.html
[360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@gem_pread@self.html
* igt@gem_render_copy@yf-tiled-to-vebox-linear:
- shard-dg2: [SKIP][361] ([i915#2575] / [i915#5190]) -> [SKIP][362] ([i915#5190] / [i915#8428])
[361]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@gem_render_copy@yf-tiled-to-vebox-linear.html
[362]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@gem_render_copy@yf-tiled-to-vebox-linear.html
* igt@gem_userptr_blits@forbidden-operations:
- shard-dg2: [SKIP][363] ([i915#2575]) -> [SKIP][364] ([i915#3282] / [i915#3297])
[363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@gem_userptr_blits@forbidden-operations.html
[364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@gem_userptr_blits@forbidden-operations.html
* igt@gen9_exec_parse@bb-start-param:
- shard-dg2: [SKIP][365] ([i915#2575]) -> [SKIP][366] ([i915#2856]) +1 other test skip
[365]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@gen9_exec_parse@bb-start-param.html
[366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@gen9_exec_parse@bb-start-param.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-mtlp: [ABORT][367] ([i915#10131] / [i915#10887] / [i915#9820]) -> [ABORT][368] ([i915#10131] / [i915#10887])
[367]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-mtlp-8/igt@i915_module_load@reload-with-fault-injection.html
[368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-mtlp-3/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_selftest@mock:
- shard-dg1: [DMESG-WARN][369] ([i915#1982] / [i915#9311]) -> [DMESG-WARN][370] ([i915#9311])
[369]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg1-13/igt@i915_selftest@mock.html
[370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg1-17/igt@i915_selftest@mock.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-dg2: [SKIP][371] ([i915#2575]) -> [SKIP][372] ([i915#1769] / [i915#3555])
[371]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
[372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-90:
- shard-dg2: [SKIP][373] ([i915#5190]) -> [SKIP][374] ([i915#4538] / [i915#5190]) +2 other tests skip
[373]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
[374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
- shard-dg2: [SKIP][375] -> [SKIP][376] ([i915#12042])
[375]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html
[376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html
* igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc:
- shard-dg2: [SKIP][377] -> [SKIP][378] ([i915#10307] / [i915#6095]) +1 other test skip
[377]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc.html
[378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_chamelium_frames@hdmi-crc-multiple:
- shard-dg2: [SKIP][379] ([i915#2575]) -> [SKIP][380] ([i915#7828]) +1 other test skip
[379]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_chamelium_frames@hdmi-crc-multiple.html
[380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_chamelium_frames@hdmi-crc-multiple.html
* igt@kms_content_protection@uevent:
- shard-dg2: [SKIP][381] ([i915#2575]) -> [FAIL][382] ([i915#1339] / [i915#7173])
[381]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_content_protection@uevent.html
[382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x170:
- shard-dg2: [SKIP][383] ([i915#11453]) -> [SKIP][384] ([i915#11453] / [i915#3359])
[383]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-4/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
[384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
- shard-dg2: [SKIP][385] ([i915#2575]) -> [SKIP][386] ([i915#5354])
[385]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
[386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-dg2: [SKIP][387] ([i915#2575]) -> [SKIP][388] ([i915#4103] / [i915#4213])
[387]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
[388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_dsc@dsc-basic:
- shard-dg2: [SKIP][389] -> [SKIP][390] ([i915#3555] / [i915#3840])
[389]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_dsc@dsc-basic.html
[390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_dsc@dsc-basic.html
* igt@kms_feature_discovery@psr2:
- shard-dg2: [SKIP][391] ([i915#2575]) -> [SKIP][392] ([i915#658])
[391]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_feature_discovery@psr2.html
[392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_feature_discovery@psr2.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-pwrite:
- shard-dg2: [SKIP][393] -> [SKIP][394] ([i915#5354]) +8 other tests skip
[393]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-pwrite.html
[394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2: [SKIP][395] ([i915#3458]) -> [SKIP][396] ([i915#10433] / [i915#3458])
[395]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
[396]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-dg2: [SKIP][397] -> [SKIP][398] ([i915#8708]) +4 other tests skip
[397]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
[398]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
- shard-dg2: [SKIP][399] -> [SKIP][400] ([i915#3458]) +4 other tests skip
[399]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html
[400]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary:
- shard-dg2: [SKIP][401] ([i915#10433] / [i915#3458]) -> [SKIP][402] ([i915#3458]) +1 other test skip
[401]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html
[402]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][403] ([i915#4070] / [i915#4816]) -> [SKIP][404] ([i915#4816])
[403]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-rkl-5/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[404]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-3/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes:
- shard-dg2: [SKIP][405] ([i915#2575]) -> [SKIP][406] +2 other tests skip
[405]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes.html
[406]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-dg2: [FAIL][407] ([i915#8292]) -> [SKIP][408] ([i915#6953] / [i915#9423])
[407]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_plane_scaling@intel-max-src-size.html
[408]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-4/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_pm_dc@dc6-dpms:
- shard-rkl: [FAIL][409] ([i915#9295]) -> [SKIP][410] ([i915#3361])
[409]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-rkl-5/igt@kms_pm_dc@dc6-dpms.html
[410]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-rkl-3/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_dc@dc6-psr:
- shard-dg2: [SKIP][411] -> [SKIP][412] ([i915#9685])
[411]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_pm_dc@dc6-psr.html
[412]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_pm_dc@dc6-psr.html
* igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-fully-sf:
- shard-dg2: [SKIP][413] -> [SKIP][414] ([i915#11520])
[413]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-fully-sf.html
[414]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_psr2_sf@fbc-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-dg2: [SKIP][415] -> [SKIP][416] ([i915#9683])
[415]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_psr2_su@frontbuffer-xrgb8888.html
[416]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@fbc-psr2-sprite-mmap-cpu:
- shard-dg2: [SKIP][417] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][418] ([i915#1072] / [i915#9732]) +4 other tests skip
[417]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_psr@fbc-psr2-sprite-mmap-cpu.html
[418]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-4/igt@kms_psr@fbc-psr2-sprite-mmap-cpu.html
* igt@kms_psr@psr2-primary-blt:
- shard-dg2: [SKIP][419] ([i915#1072] / [i915#9732]) -> [SKIP][420] ([i915#1072] / [i915#9673] / [i915#9732]) +4 other tests skip
[419]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-4/igt@kms_psr@psr2-primary-blt.html
[420]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_psr@psr2-primary-blt.html
* igt@kms_psr@psr2-primary-mmap-gtt:
- shard-dg2: [SKIP][421] -> [SKIP][422] ([i915#1072] / [i915#9673] / [i915#9732]) +4 other tests skip
[421]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_psr@psr2-primary-mmap-gtt.html
[422]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_psr@psr2-primary-mmap-gtt.html
* igt@kms_rotation_crc@bad-tiling:
- shard-dg2: [SKIP][423] ([i915#11131] / [i915#4235]) -> [SKIP][424] ([i915#11131])
[423]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_rotation_crc@bad-tiling.html
[424]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-4/igt@kms_rotation_crc@bad-tiling.html
* igt@kms_rotation_crc@exhaust-fences:
- shard-dg2: [SKIP][425] ([i915#2575]) -> [SKIP][426] ([i915#4235])
[425]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_rotation_crc@exhaust-fences.html
[426]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_rotation_crc@exhaust-fences.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
- shard-dg2: [SKIP][427] ([i915#11131] / [i915#4235] / [i915#5190]) -> [SKIP][428] ([i915#11131] / [i915#5190])
[427]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
[428]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-4/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
* igt@kms_rotation_crc@sprite-rotation-270:
- shard-dg2: [SKIP][429] ([i915#2575]) -> [SKIP][430] ([i915#11131] / [i915#4235])
[429]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_rotation_crc@sprite-rotation-270.html
[430]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_rotation_crc@sprite-rotation-270.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-dg2: [SKIP][431] ([i915#2575]) -> [SKIP][432] ([i915#8623])
[431]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_tiled_display@basic-test-pattern.html
[432]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_vrr@lobf:
- shard-dg2: [SKIP][433] ([i915#2575]) -> [SKIP][434] ([i915#11920])
[433]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@kms_vrr@lobf.html
[434]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@kms_vrr@lobf.html
* igt@prime_vgem@basic-gtt:
- shard-dg2: [SKIP][435] ([i915#2575]) -> [SKIP][436] ([i915#3708] / [i915#4077])
[435]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@prime_vgem@basic-gtt.html
[436]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@prime_vgem@basic-gtt.html
* igt@sriov_basic@enable-vfs-autoprobe-off:
- shard-dg2: [SKIP][437] ([i915#2575]) -> [SKIP][438] ([i915#9917])
[437]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15378/shard-dg2-11/igt@sriov_basic@enable-vfs-autoprobe-off.html
[438]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/shard-dg2-11/igt@sriov_basic@enable-vfs-autoprobe-off.html
[i915#10030]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10030
[i915#10131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10131
[i915#10193]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10193
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#10887]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10887
[i915#11131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11131
[i915#11224]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11224
[i915#11453]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11453
[i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
[i915#11616]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11616
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#11692]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11692
[i915#11808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11808
[i915#11859]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11859
[i915#11920]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11920
[i915#11961]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11961
[i915#11980]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11980
[i915#12042]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12042
[i915#12193]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12193
[i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
[i915#1339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1339
[i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
[i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#2876]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2876
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#4070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4103]: https
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v5/index.html
[-- Attachment #2: Type: text/html, Size: 120015 bytes --]
^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-09 6:32 ` Suraj Kandpal
@ 2024-09-19 12:14 ` Shankar, Uma
2024-09-19 12:44 ` Kandpal, Suraj
2024-09-20 5:36 ` Hogander, Jouni
2024-09-20 9:12 ` [PATCH] drm/i915/psr: Implement " Suraj Kandpal
1 sibling, 2 replies; 47+ messages in thread
From: Shankar, Uma @ 2024-09-19 12:14 UTC (permalink / raw)
To: Kandpal, Suraj, intel-gfx@lists.freedesktop.org, Hogander, Jouni
Cc: Deak, Imre
> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Monday, September 9, 2024 12:02 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Hogander, Jouni
> <jouni.hogander@intel.com>; Deak, Imre <imre.deak@intel.com>; Kandpal, Suraj
> <suraj.kandpal@intel.com>
> Subject: [PATCH] drm/i915/psr: Implment WA to help reach PC10
Not: Typo in implement
> To reach PC10 when PKG_C_LATENCY is configure we must do the following
> things
> 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
> 2) Allow PSR2 deep sleep when DC5 can be entered
> 3) DC5 can be entered when all transocoder have either PSR1, PSR2 or eDP 1.5 PR
> ALPM enabled and VBI is disabled and flips and pushes are not happening.
>
> --v2
> -Switch condition and do an early return [Jani] -Do some checks in
> compute_config [Jani] -Do not use register reads as a method of checking states
> for DPKGC or delayed vblank [Jani] -Use another way to see is vblank interrupts
> are disabled or not [Jani]
>
> --v3
> -Use has_psr to check if psr can be enabled or not for dc5_entry cond [Uma] -
> Move the dc5 entry computation to psr_compute_config [Jouni] -No need to
> change sequence of enabled and activate, so dont make hsw_psr1_activate
> return anything [Jouni] -Use has_psr to stop psr1 activation [Jouni] -Use lineage
> no. in WA -Add the display ver restrictions for WA
>
> --v4
> -use more appropriate name for check_vblank_limit() [Jouni] -Cover the case for
> idle frames when dpkgc is not configured [Jouni] -Check psr only for edp [Jouni]
>
> --v5
> -move psr1 handling to plane update [Jouni] -add todo for cases when vblank is
> enabled when psr enabled [Jouni] -use intel_display instead of drm_i915_private
>
> --v6
> -check target_dc_state [Jouni]
> -fix condition in pre/post plane update [Jouni]
>
> WA: 22019444797
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 3 +
> drivers/gpu/drm/i915/display/intel_psr.c | 112 +++++++++++++++++-
> 2 files changed, 114 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 733de5edcfdb..59c81f0a3abd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1577,6 +1577,9 @@ struct intel_psr {
> #define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
>
> u32 debug;
> + bool is_dpkgc_configured;
> + bool is_dc5_entry_possible;
> + bool is_wa_delayed_vblank_limit;
> bool sink_support;
> bool source_support;
> bool enabled;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index b30fa067ce6e..e50b476494a0 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -26,6 +26,7 @@
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_damage_helper.h>
> #include <drm/drm_debugfs.h>
> +#include <drm/drm_vblank.h>
>
> #include "i915_drv.h"
> #include "i915_reg.h"
> @@ -874,6 +875,78 @@ static u8 psr_compute_idle_frames(struct intel_dp
> *intel_dp)
> return idle_frames;
> }
>
> +static bool
> +intel_psr_check_wa_delayed_vblank(const struct drm_display_mode
> +*adjusted_mode) {
> + return (adjusted_mode->crtc_vblank_start -
> +adjusted_mode->crtc_vdisplay) >= 6; }
> +
> +/*
> + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> + * VRR is not enabled
> + */
> +static bool intel_psr_is_dpkgc_configured(struct intel_display *display,
> + struct intel_atomic_state *state) {
> + struct intel_crtc *intel_crtc;
> + struct intel_crtc_state *crtc_state;
> + int i;
> +
> + if (DISPLAY_VER(display) < 20)
> + return false;
> +
> + for_each_new_intel_crtc_in_state(state, intel_crtc, crtc_state, i) {
> + if (!intel_crtc->active)
> + continue;
> +
> + if (crtc_state->vrr.enable)
> + return false;
> + }
> +
> + return true;
> +}
> +
> +/*
> + * DC5 entry is only possible if vblank interrupt is disabled
> + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> + * enabled encoders.
> + */
> +static bool
> +intel_psr_is_dc5_entry_possible(struct intel_display *display,
> + struct intel_atomic_state *state)
> +{
> + struct intel_crtc *intel_crtc;
> + struct intel_crtc_state *crtc_state;
> + int i;
> +
> + if ((display->power.domains.target_dc_state &
> + DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
> + return false;
> +
> + for_each_new_intel_crtc_in_state(state, intel_crtc, crtc_state, i) {
> + struct drm_crtc *crtc = &intel_crtc->base;
> + struct drm_vblank_crtc *vblank;
> + struct intel_encoder *encoder;
> +
> + if (!intel_crtc->active)
> + continue;
> +
> + vblank = drm_crtc_vblank_crtc(crtc);
> +
> + if (vblank->enabled)
> + return false;
> +
> + if (crtc_state->has_psr)
> + return false;
It should be !has_psr
> +
> + for_each_encoder_on_crtc(display->drm, crtc, encoder)
> + if (encoder->type != INTEL_OUTPUT_EDP)
> + return false;
> + }
> +
> + return true;
> +}
> +
> static void hsw_activate_psr1(struct intel_dp *intel_dp) {
> struct intel_display *display = to_intel_display(intel_dp); @@ -986,7
> +1059,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> u32 val = EDP_PSR2_ENABLE;
> u32 psr_val = 0;
>
> - val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> + /*
> + * Wa_22019444797
> + * TODO: Disable idle frames when vblank gets enabled while
> + * PSR2 is enabled
> + */
> + if (DISPLAY_VER(dev_priv) != 20 ||
> + !intel_dp->psr.is_dpkgc_configured ||
Why ! for dpkgc, Here this can be enabled if dpkgc_configured right ?
> + intel_dp->psr.is_dc5_entry_possible)
> + val |=
> EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
>
> if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
> val |= EDP_SU_TRACK_ENABLE;
> @@ -2667,10 +2748,20 @@ void intel_psr_pre_plane_update(struct
> intel_atomic_state *state,
> const struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> struct intel_encoder *encoder;
> + bool dpkgc_configured = false, dc5_entry_possible = false;
> + bool wa_delayed_vblank_limit = false;
>
> if (!HAS_PSR(display))
> return;
>
> + if (DISPLAY_VER(display) == 20) {
> + dpkgc_configured = intel_psr_is_dpkgc_configured(display,
> state);
> + dc5_entry_possible =
> + intel_psr_is_dc5_entry_possible(display, state);
> + wa_delayed_vblank_limit =
> + intel_psr_check_wa_delayed_vblank(&new_crtc_state-
> >hw.adjusted_mode);
> + }
> +
> for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
> old_crtc_state->uapi.encoder_mask)
> {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder); @@ -
> 2679,6 +2770,12 @@ void intel_psr_pre_plane_update(struct intel_atomic_state
> *state,
>
> mutex_lock(&psr->lock);
>
> + if (DISPLAY_VER(i915) == 20) {
> + psr->is_dpkgc_configured = dpkgc_configured;
> + psr->is_dc5_entry_possible = dc5_entry_possible;
> + psr->is_wa_delayed_vblank_limit =
> wa_delayed_vblank_limit;
We can drop the variables and directly assign this to psr->... and use it subsequently.
Also it would be good to have this done in compute and than just use it here.
> + }
> +
> /*
> * Reasons to disable:
> * - PSR disabled in new state
> @@ -2686,6 +2783,7 @@ void intel_psr_pre_plane_update(struct
> intel_atomic_state *state,
> * - Changing between PSR versions
> * - Region Early Transport changing
> * - Display WA #1136: skl, bxt
> + * - Display WA_22019444797
> */
> needs_to_disable |=
> intel_crtc_needs_modeset(new_crtc_state);
> needs_to_disable |= !new_crtc_state->has_psr; @@ -2695,6
> +2793,10 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> psr->su_region_et_enabled;
> needs_to_disable |= DISPLAY_VER(i915) < 11 &&
> new_crtc_state->wm_level_disabled;
> + /* TODO: Disable PSR1 when vblank gets enabled while PSR1 is
> enabled */
> + needs_to_disable |= DISPLAY_VER(display) == 20 &&
> dpkgc_configured &&
> + (wa_delayed_vblank_limit || dc5_entry_possible) &&
> + !new_crtc_state->has_sel_update &&
> +!new_crtc_state->has_panel_replay;
Good to move this to a small helper function which can be extended if required as well.
Also seems used in post_plane as well.
@Hogander, Jouni Can you also ack if this handling for PSR is ok.
> if (psr->enabled && needs_to_disable)
> intel_psr_disable_locked(intel_dp);
> @@ -2735,6 +2837,14 @@ void intel_psr_post_plane_update(struct
> intel_atomic_state *state,
> keep_disabled |= DISPLAY_VER(display) < 11 &&
> crtc_state->wm_level_disabled;
>
> + /*
> + * Wa_22019444797
> + * TODO: Disable PSR1 when vblank gets enabled while PSR1 is
> enabled
> + */
> + keep_disabled |= DISPLAY_VER(display) == 20 && psr-
> >is_dpkgc_configured &&
> + (psr->is_wa_delayed_vblank_limit || psr-
> >is_dc5_entry_possible) &&
> + !crtc_state->has_sel_update && !crtc_state-
> >has_panel_replay;
> +
> if (!psr->enabled && !keep_disabled)
> intel_psr_enable_locked(intel_dp, crtc_state);
> else if (psr->enabled && !crtc_state->wm_level_disabled)
> --
> 2.43.2
^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-19 12:14 ` Shankar, Uma
@ 2024-09-19 12:44 ` Kandpal, Suraj
2024-09-19 12:55 ` Hogander, Jouni
2024-09-20 5:36 ` Hogander, Jouni
1 sibling, 1 reply; 47+ messages in thread
From: Kandpal, Suraj @ 2024-09-19 12:44 UTC (permalink / raw)
To: Shankar, Uma, intel-gfx@lists.freedesktop.org, Hogander, Jouni; +Cc: Deak, Imre
> -----Original Message-----
> From: Shankar, Uma <uma.shankar@intel.com>
> Sent: Thursday, September 19, 2024 5:44 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> gfx@lists.freedesktop.org; Hogander, Jouni <jouni.hogander@intel.com>
> Cc: Deak, Imre <imre.deak@intel.com>
> Subject: RE: [PATCH] drm/i915/psr: Implment WA to help reach PC10
>
>
>
> > -----Original Message-----
> > From: Kandpal, Suraj <suraj.kandpal@intel.com>
> > Sent: Monday, September 9, 2024 12:02 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Shankar, Uma <uma.shankar@intel.com>; Hogander, Jouni
> > <jouni.hogander@intel.com>; Deak, Imre <imre.deak@intel.com>;
> Kandpal,
> > Suraj <suraj.kandpal@intel.com>
> > Subject: [PATCH] drm/i915/psr: Implment WA to help reach PC10
>
> Not: Typo in implement
Will fix in next revision
>
> > To reach PC10 when PKG_C_LATENCY is configure we must do the
> following
> > things
> > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> > entered
> > 2) Allow PSR2 deep sleep when DC5 can be entered
> > 3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
> > eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are not
> happening.
> >
> > --v2
> > -Switch condition and do an early return [Jani] -Do some checks in
> > compute_config [Jani] -Do not use register reads as a method of
> > checking states for DPKGC or delayed vblank [Jani] -Use another way to
> > see is vblank interrupts are disabled or not [Jani]
> >
> > --v3
> > -Use has_psr to check if psr can be enabled or not for dc5_entry cond
> > [Uma] - Move the dc5 entry computation to psr_compute_config [Jouni]
> > -No need to change sequence of enabled and activate, so dont make
> > hsw_psr1_activate return anything [Jouni] -Use has_psr to stop psr1
> > activation [Jouni] -Use lineage no. in WA -Add the display ver
> > restrictions for WA
> >
> > --v4
> > -use more appropriate name for check_vblank_limit() [Jouni] -Cover the
> > case for idle frames when dpkgc is not configured [Jouni] -Check psr
> > only for edp [Jouni]
> >
> > --v5
> > -move psr1 handling to plane update [Jouni] -add todo for cases when
> > vblank is enabled when psr enabled [Jouni] -use intel_display instead
> > of drm_i915_private
> >
> > --v6
> > -check target_dc_state [Jouni]
> > -fix condition in pre/post plane update [Jouni]
> >
> > WA: 22019444797
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > .../drm/i915/display/intel_display_types.h | 3 +
> > drivers/gpu/drm/i915/display/intel_psr.c | 112 +++++++++++++++++-
> > 2 files changed, 114 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 733de5edcfdb..59c81f0a3abd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1577,6 +1577,9 @@ struct intel_psr {
> > #define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
> >
> > u32 debug;
> > + bool is_dpkgc_configured;
> > + bool is_dc5_entry_possible;
> > + bool is_wa_delayed_vblank_limit;
> > bool sink_support;
> > bool source_support;
> > bool enabled;
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index b30fa067ce6e..e50b476494a0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -26,6 +26,7 @@
> > #include <drm/drm_atomic_helper.h>
> > #include <drm/drm_damage_helper.h>
> > #include <drm/drm_debugfs.h>
> > +#include <drm/drm_vblank.h>
> >
> > #include "i915_drv.h"
> > #include "i915_reg.h"
> > @@ -874,6 +875,78 @@ static u8 psr_compute_idle_frames(struct
> intel_dp
> > *intel_dp)
> > return idle_frames;
> > }
> >
> > +static bool
> > +intel_psr_check_wa_delayed_vblank(const struct drm_display_mode
> > +*adjusted_mode) {
> > + return (adjusted_mode->crtc_vblank_start -
> > +adjusted_mode->crtc_vdisplay) >= 6; }
> > +
> > +/*
> > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> > + * VRR is not enabled
> > + */
> > +static bool intel_psr_is_dpkgc_configured(struct intel_display *display,
> > + struct intel_atomic_state *state) {
> > + struct intel_crtc *intel_crtc;
> > + struct intel_crtc_state *crtc_state;
> > + int i;
> > +
> > + if (DISPLAY_VER(display) < 20)
> > + return false;
> > +
> > + for_each_new_intel_crtc_in_state(state, intel_crtc, crtc_state, i) {
> > + if (!intel_crtc->active)
> > + continue;
> > +
> > + if (crtc_state->vrr.enable)
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > +/*
> > + * DC5 entry is only possible if vblank interrupt is disabled
> > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> > + * enabled encoders.
> > + */
> > +static bool
> > +intel_psr_is_dc5_entry_possible(struct intel_display *display,
> > + struct intel_atomic_state *state) {
> > + struct intel_crtc *intel_crtc;
> > + struct intel_crtc_state *crtc_state;
> > + int i;
> > +
> > + if ((display->power.domains.target_dc_state &
> > + DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
> > + return false;
> > +
> > + for_each_new_intel_crtc_in_state(state, intel_crtc, crtc_state, i) {
> > + struct drm_crtc *crtc = &intel_crtc->base;
> > + struct drm_vblank_crtc *vblank;
> > + struct intel_encoder *encoder;
> > +
> > + if (!intel_crtc->active)
> > + continue;
> > +
> > + vblank = drm_crtc_vblank_crtc(crtc);
> > +
> > + if (vblank->enabled)
> > + return false;
> > +
> > + if (crtc_state->has_psr)
> > + return false;
>
> It should be !has_psr
>
> > +
> > + for_each_encoder_on_crtc(display->drm, crtc, encoder)
> > + if (encoder->type != INTEL_OUTPUT_EDP)
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > static void hsw_activate_psr1(struct intel_dp *intel_dp) {
> > struct intel_display *display = to_intel_display(intel_dp); @@
> > -986,7
> > +1059,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> > u32 val = EDP_PSR2_ENABLE;
> > u32 psr_val = 0;
> >
> > - val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > + /*
> > + * Wa_22019444797
> > + * TODO: Disable idle frames when vblank gets enabled while
> > + * PSR2 is enabled
> > + */
> > + if (DISPLAY_VER(dev_priv) != 20 ||
> > + !intel_dp->psr.is_dpkgc_configured ||
>
> Why ! for dpkgc, Here this can be enabled if dpkgc_configured right ?
>
So we want idle frames to be written in these scenarios display ver !=20 if it is equal to 20
Then we write idle frames if dpkgc is not configured and if dpkgc is confirgured then we write
Idle frames if dc5 entry is possible
> > + intel_dp->psr.is_dc5_entry_possible)
> > + val |=
> > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> >
> > if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
> > val |= EDP_SU_TRACK_ENABLE;
> > @@ -2667,10 +2748,20 @@ void intel_psr_pre_plane_update(struct
> > intel_atomic_state *state,
> > const struct intel_crtc_state *new_crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > struct intel_encoder *encoder;
> > + bool dpkgc_configured = false, dc5_entry_possible = false;
> > + bool wa_delayed_vblank_limit = false;
> >
> > if (!HAS_PSR(display))
> > return;
> >
> > + if (DISPLAY_VER(display) == 20) {
> > + dpkgc_configured = intel_psr_is_dpkgc_configured(display,
> > state);
> > + dc5_entry_possible =
> > + intel_psr_is_dc5_entry_possible(display, state);
> > + wa_delayed_vblank_limit =
> > +
> intel_psr_check_wa_delayed_vblank(&new_crtc_state-
> > >hw.adjusted_mode);
> > + }
> > +
> > for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
> > old_crtc_state-
> >uapi.encoder_mask)
> > {
> > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); @@ -
> > 2679,6 +2770,12 @@ void intel_psr_pre_plane_update(struct
> > intel_atomic_state *state,
> >
> > mutex_lock(&psr->lock);
> >
> > + if (DISPLAY_VER(i915) == 20) {
> > + psr->is_dpkgc_configured = dpkgc_configured;
> > + psr->is_dc5_entry_possible = dc5_entry_possible;
> > + psr->is_wa_delayed_vblank_limit =
> > wa_delayed_vblank_limit;
>
> We can drop the variables and directly assign this to psr->... and use it
> subsequently.
So the reason I had assigned this to variables is I did not want to call the 3 functions
Above inside the for_each_encoder loop since the functions themselves have loops inside them
Which would just increase the cost hence the variables.
> Also it would be good to have this done in compute and than just use it
> here.
It was done in compute a few revisions ago @Hogander, Jouni suggested to move it to
pre_plane_update.
>
> > + }
> > +
> > /*
> > * Reasons to disable:
> > * - PSR disabled in new state
> > @@ -2686,6 +2783,7 @@ void intel_psr_pre_plane_update(struct
> > intel_atomic_state *state,
> > * - Changing between PSR versions
> > * - Region Early Transport changing
> > * - Display WA #1136: skl, bxt
> > + * - Display WA_22019444797
> > */
> > needs_to_disable |=
> > intel_crtc_needs_modeset(new_crtc_state);
> > needs_to_disable |= !new_crtc_state->has_psr; @@ -2695,6
> > +2793,10 @@ void intel_psr_pre_plane_update(struct intel_atomic_state
> > +*state,
> > psr->su_region_et_enabled;
> > needs_to_disable |= DISPLAY_VER(i915) < 11 &&
> > new_crtc_state->wm_level_disabled;
> > + /* TODO: Disable PSR1 when vblank gets enabled while PSR1
> is
> > enabled */
> > + needs_to_disable |= DISPLAY_VER(display) == 20 &&
> > dpkgc_configured &&
> > + (wa_delayed_vblank_limit || dc5_entry_possible)
> &&
> > + !new_crtc_state->has_sel_update &&
> > +!new_crtc_state->has_panel_replay;
>
> Good to move this to a small helper function which can be extended if
> required as well.
> Also seems used in post_plane as well.
Sure will move it into its own helper function
Regards,
Suraj Kandpal
>
> @Hogander, Jouni Can you also ack if this handling for PSR is ok.
>
> > if (psr->enabled && needs_to_disable)
> > intel_psr_disable_locked(intel_dp);
> > @@ -2735,6 +2837,14 @@ void intel_psr_post_plane_update(struct
> > intel_atomic_state *state,
> > keep_disabled |= DISPLAY_VER(display) < 11 &&
> > crtc_state->wm_level_disabled;
> >
> > + /*
> > + * Wa_22019444797
> > + * TODO: Disable PSR1 when vblank gets enabled while PSR1
> is
> > enabled
> > + */
> > + keep_disabled |= DISPLAY_VER(display) == 20 && psr-
> > >is_dpkgc_configured &&
> > + (psr->is_wa_delayed_vblank_limit || psr-
> > >is_dc5_entry_possible) &&
> > + !crtc_state->has_sel_update && !crtc_state-
> > >has_panel_replay;
> > +
> > if (!psr->enabled && !keep_disabled)
> > intel_psr_enable_locked(intel_dp, crtc_state);
> > else if (psr->enabled && !crtc_state->wm_level_disabled)
> > --
> > 2.43.2
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-19 12:44 ` Kandpal, Suraj
@ 2024-09-19 12:55 ` Hogander, Jouni
0 siblings, 0 replies; 47+ messages in thread
From: Hogander, Jouni @ 2024-09-19 12:55 UTC (permalink / raw)
To: Kandpal, Suraj, Shankar, Uma, intel-gfx@lists.freedesktop.org; +Cc: Deak, Imre
On Thu, 2024-09-19 at 12:44 +0000, Kandpal, Suraj wrote:
>
>
> > -----Original Message-----
> > From: Shankar, Uma <uma.shankar@intel.com>
> > Sent: Thursday, September 19, 2024 5:44 PM
> > To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> > gfx@lists.freedesktop.org; Hogander, Jouni
> > <jouni.hogander@intel.com>
> > Cc: Deak, Imre <imre.deak@intel.com>
> > Subject: RE: [PATCH] drm/i915/psr: Implment WA to help reach PC10
> >
> >
> >
> > > -----Original Message-----
> > > From: Kandpal, Suraj <suraj.kandpal@intel.com>
> > > Sent: Monday, September 9, 2024 12:02 PM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: Shankar, Uma <uma.shankar@intel.com>; Hogander, Jouni
> > > <jouni.hogander@intel.com>; Deak, Imre <imre.deak@intel.com>;
> > Kandpal,
> > > Suraj <suraj.kandpal@intel.com>
> > > Subject: [PATCH] drm/i915/psr: Implment WA to help reach PC10
> >
> > Not: Typo in implement
>
> Will fix in next revision
>
> >
> > > To reach PC10 when PKG_C_LATENCY is configure we must do the
> > following
> > > things
> > > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> > > entered
> > > 2) Allow PSR2 deep sleep when DC5 can be entered
> > > 3) DC5 can be entered when all transocoder have either PSR1, PSR2
> > > or
> > > eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes
> > > are not
> > happening.
> > >
> > > --v2
> > > -Switch condition and do an early return [Jani] -Do some checks
> > > in
> > > compute_config [Jani] -Do not use register reads as a method of
> > > checking states for DPKGC or delayed vblank [Jani] -Use another
> > > way to
> > > see is vblank interrupts are disabled or not [Jani]
> > >
> > > --v3
> > > -Use has_psr to check if psr can be enabled or not for dc5_entry
> > > cond
> > > [Uma] - Move the dc5 entry computation to psr_compute_config
> > > [Jouni]
> > > -No need to change sequence of enabled and activate, so dont make
> > > hsw_psr1_activate return anything [Jouni] -Use has_psr to stop
> > > psr1
> > > activation [Jouni] -Use lineage no. in WA -Add the display ver
> > > restrictions for WA
> > >
> > > --v4
> > > -use more appropriate name for check_vblank_limit() [Jouni] -
> > > Cover the
> > > case for idle frames when dpkgc is not configured [Jouni] -Check
> > > psr
> > > only for edp [Jouni]
> > >
> > > --v5
> > > -move psr1 handling to plane update [Jouni] -add todo for cases
> > > when
> > > vblank is enabled when psr enabled [Jouni] -use intel_display
> > > instead
> > > of drm_i915_private
> > >
> > > --v6
> > > -check target_dc_state [Jouni]
> > > -fix condition in pre/post plane update [Jouni]
> > >
> > > WA: 22019444797
> > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > ---
> > > .../drm/i915/display/intel_display_types.h | 3 +
> > > drivers/gpu/drm/i915/display/intel_psr.c | 112
> > > +++++++++++++++++-
> > > 2 files changed, 114 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 733de5edcfdb..59c81f0a3abd 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -1577,6 +1577,9 @@ struct intel_psr {
> > > #define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
> > >
> > > u32 debug;
> > > + bool is_dpkgc_configured;
> > > + bool is_dc5_entry_possible;
> > > + bool is_wa_delayed_vblank_limit;
> > > bool sink_support;
> > > bool source_support;
> > > bool enabled;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index b30fa067ce6e..e50b476494a0 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -26,6 +26,7 @@
> > > #include <drm/drm_atomic_helper.h>
> > > #include <drm/drm_damage_helper.h>
> > > #include <drm/drm_debugfs.h>
> > > +#include <drm/drm_vblank.h>
> > >
> > > #include "i915_drv.h"
> > > #include "i915_reg.h"
> > > @@ -874,6 +875,78 @@ static u8 psr_compute_idle_frames(struct
> > intel_dp
> > > *intel_dp)
> > > return idle_frames;
> > > }
> > >
> > > +static bool
> > > +intel_psr_check_wa_delayed_vblank(const struct drm_display_mode
> > > +*adjusted_mode) {
> > > + return (adjusted_mode->crtc_vblank_start -
> > > +adjusted_mode->crtc_vdisplay) >= 6; }
> > > +
> > > +/*
> > > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> > > + * VRR is not enabled
> > > + */
> > > +static bool intel_psr_is_dpkgc_configured(struct intel_display
> > > *display,
> > > + struct
> > > intel_atomic_state *state) {
> > > + struct intel_crtc *intel_crtc;
> > > + struct intel_crtc_state *crtc_state;
> > > + int i;
> > > +
> > > + if (DISPLAY_VER(display) < 20)
> > > + return false;
> > > +
> > > + for_each_new_intel_crtc_in_state(state, intel_crtc,
> > > crtc_state, i) {
> > > + if (!intel_crtc->active)
> > > + continue;
> > > +
> > > + if (crtc_state->vrr.enable)
> > > + return false;
> > > + }
> > > +
> > > + return true;
> > > +}
> > > +
> > > +/*
> > > + * DC5 entry is only possible if vblank interrupt is disabled
> > > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> > > + * enabled encoders.
> > > + */
> > > +static bool
> > > +intel_psr_is_dc5_entry_possible(struct intel_display *display,
> > > + struct intel_atomic_state *state)
> > > {
> > > + struct intel_crtc *intel_crtc;
> > > + struct intel_crtc_state *crtc_state;
> > > + int i;
> > > +
> > > + if ((display->power.domains.target_dc_state &
> > > + DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
> > > + return false;
> > > +
> > > + for_each_new_intel_crtc_in_state(state, intel_crtc,
> > > crtc_state, i) {
> > > + struct drm_crtc *crtc = &intel_crtc->base;
> > > + struct drm_vblank_crtc *vblank;
> > > + struct intel_encoder *encoder;
> > > +
> > > + if (!intel_crtc->active)
> > > + continue;
> > > +
> > > + vblank = drm_crtc_vblank_crtc(crtc);
> > > +
> > > + if (vblank->enabled)
> > > + return false;
> > > +
> > > + if (crtc_state->has_psr)
> > > + return false;
> >
> > It should be !has_psr
> >
> > > +
> > > + for_each_encoder_on_crtc(display->drm, crtc,
> > > encoder)
> > > + if (encoder->type != INTEL_OUTPUT_EDP)
> > > + return false;
> > > + }
> > > +
> > > + return true;
> > > +}
> > > +
> > > static void hsw_activate_psr1(struct intel_dp *intel_dp) {
> > > struct intel_display *display =
> > > to_intel_display(intel_dp); @@
> > > -986,7
> > > +1059,15 @@ static void hsw_activate_psr2(struct intel_dp
> > > *intel_dp)
> > > u32 val = EDP_PSR2_ENABLE;
> > > u32 psr_val = 0;
> > >
> > > - val |=
> > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > > + /*
> > > + * Wa_22019444797
> > > + * TODO: Disable idle frames when vblank gets enabled
> > > while
> > > + * PSR2 is enabled
> > > + */
> > > + if (DISPLAY_VER(dev_priv) != 20 ||
> > > + !intel_dp->psr.is_dpkgc_configured ||
> >
> > Why ! for dpkgc, Here this can be enabled if dpkgc_configured right
> > ?
> >
>
> So we want idle frames to be written in these scenarios display ver
> !=20 if it is equal to 20
> Then we write idle frames if dpkgc is not configured and if dpkgc is
> confirgured then we write
> Idle frames if dc5 entry is possible
>
> > > + intel_dp->psr.is_dc5_entry_possible)
> > > + val |=
> > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > >
> > > if (DISPLAY_VER(display) < 14 &&
> > > !IS_ALDERLAKE_P(dev_priv))
> > > val |= EDP_SU_TRACK_ENABLE;
> > > @@ -2667,10 +2748,20 @@ void intel_psr_pre_plane_update(struct
> > > intel_atomic_state *state,
> > > const struct intel_crtc_state *new_crtc_state =
> > > intel_atomic_get_new_crtc_state(state, crtc);
> > > struct intel_encoder *encoder;
> > > + bool dpkgc_configured = false, dc5_entry_possible =
> > > false;
> > > + bool wa_delayed_vblank_limit = false;
> > >
> > > if (!HAS_PSR(display))
> > > return;
> > >
> > > + if (DISPLAY_VER(display) == 20) {
> > > + dpkgc_configured =
> > > intel_psr_is_dpkgc_configured(display,
> > > state);
> > > + dc5_entry_possible =
> > > + intel_psr_is_dc5_entry_possible(display,
> > > state);
> > > + wa_delayed_vblank_limit =
> > > +
> > intel_psr_check_wa_delayed_vblank(&new_crtc_state-
> > > > hw.adjusted_mode);
> > > + }
> > > +
> > > for_each_intel_encoder_mask_with_psr(state->base.dev,
> > > encoder,
> > > old_crtc_state-
> > > uapi.encoder_mask)
> > > {
> > > struct intel_dp *intel_dp =
> > > enc_to_intel_dp(encoder); @@ -
> > > 2679,6 +2770,12 @@ void intel_psr_pre_plane_update(struct
> > > intel_atomic_state *state,
> > >
> > > mutex_lock(&psr->lock);
> > >
> > > + if (DISPLAY_VER(i915) == 20) {
> > > + psr->is_dpkgc_configured =
> > > dpkgc_configured;
> > > + psr->is_dc5_entry_possible =
> > > dc5_entry_possible;
> > > + psr->is_wa_delayed_vblank_limit =
> > > wa_delayed_vblank_limit;
> >
> > We can drop the variables and directly assign this to psr->... and
> > use it
> > subsequently.
>
> So the reason I had assigned this to variables is I did not want to
> call the 3 functions
> Above inside the for_each_encoder loop since the functions themselves
> have loops inside them
> Which would just increase the cost hence the variables.
>
>
> > Also it would be good to have this done in compute and than just
> > use it
> > here.
>
> It was done in compute a few revisions ago @Hogander, Jouni suggested
> to move it to
> pre_plane_update.
It needs to be done in pre/post_planee update because only there you
know what will be the state of all crtcs. I.e. compute_config is done
for all crtcs and all encoders.
BR,
Jouni Högander
>
> >
> > > + }
> > > +
> > > /*
> > > * Reasons to disable:
> > > * - PSR disabled in new state
> > > @@ -2686,6 +2783,7 @@ void intel_psr_pre_plane_update(struct
> > > intel_atomic_state *state,
> > > * - Changing between PSR versions
> > > * - Region Early Transport changing
> > > * - Display WA #1136: skl, bxt
> > > + * - Display WA_22019444797
> > > */
> > > needs_to_disable |=
> > > intel_crtc_needs_modeset(new_crtc_state);
> > > needs_to_disable |= !new_crtc_state->has_psr; @@
> > > -2695,6
> > > +2793,10 @@ void intel_psr_pre_plane_update(struct
> > > intel_atomic_state
> > > +*state,
> > > psr->su_region_et_enabled;
> > > needs_to_disable |= DISPLAY_VER(i915) < 11 &&
> > > new_crtc_state->wm_level_disabled;
> > > + /* TODO: Disable PSR1 when vblank gets enabled
> > > while PSR1
> > is
> > > enabled */
> > > + needs_to_disable |= DISPLAY_VER(display) == 20 &&
> > > dpkgc_configured &&
> > > + (wa_delayed_vblank_limit ||
> > > dc5_entry_possible)
> > &&
> > > + !new_crtc_state->has_sel_update &&
> > > +!new_crtc_state->has_panel_replay;
> >
> > Good to move this to a small helper function which can be extended
> > if
> > required as well.
> > Also seems used in post_plane as well.
>
> Sure will move it into its own helper function
>
> Regards,
> Suraj Kandpal
>
> >
> > @Hogander, Jouni Can you also ack if this handling for PSR is ok.
> >
> > > if (psr->enabled && needs_to_disable)
> > > intel_psr_disable_locked(intel_dp);
> > > @@ -2735,6 +2837,14 @@ void intel_psr_post_plane_update(struct
> > > intel_atomic_state *state,
> > > keep_disabled |= DISPLAY_VER(display) < 11 &&
> > > crtc_state->wm_level_disabled;
> > >
> > > + /*
> > > + * Wa_22019444797
> > > + * TODO: Disable PSR1 when vblank gets enabled
> > > while PSR1
> > is
> > > enabled
> > > + */
> > > + keep_disabled |= DISPLAY_VER(display) == 20 &&
> > > psr-
> > > > is_dpkgc_configured &&
> > > + (psr->is_wa_delayed_vblank_limit || psr-
> > > > is_dc5_entry_possible) &&
> > > + !crtc_state->has_sel_update &&
> > > !crtc_state-
> > > > has_panel_replay;
> > > +
> > > if (!psr->enabled && !keep_disabled)
> > > intel_psr_enable_locked(intel_dp,
> > > crtc_state);
> > > else if (psr->enabled && !crtc_state-
> > > >wm_level_disabled)
> > > --
> > > 2.43.2
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-19 12:14 ` Shankar, Uma
2024-09-19 12:44 ` Kandpal, Suraj
@ 2024-09-20 5:36 ` Hogander, Jouni
2024-09-20 6:29 ` Kandpal, Suraj
1 sibling, 1 reply; 47+ messages in thread
From: Hogander, Jouni @ 2024-09-20 5:36 UTC (permalink / raw)
To: Shankar, Uma, Kandpal, Suraj, intel-gfx@lists.freedesktop.org; +Cc: Deak, Imre
On Thu, 2024-09-19 at 12:14 +0000, Shankar, Uma wrote:
>
>
> > -----Original Message-----
> > From: Kandpal, Suraj <suraj.kandpal@intel.com>
> > Sent: Monday, September 9, 2024 12:02 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Shankar, Uma <uma.shankar@intel.com>; Hogander, Jouni
> > <jouni.hogander@intel.com>; Deak, Imre <imre.deak@intel.com>;
> > Kandpal, Suraj
> > <suraj.kandpal@intel.com>
> > Subject: [PATCH] drm/i915/psr: Implment WA to help reach PC10
>
> Not: Typo in implement
>
> > To reach PC10 when PKG_C_LATENCY is configure we must do the
> > following
> > things
> > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> > entered
> > 2) Allow PSR2 deep sleep when DC5 can be entered
> > 3) DC5 can be entered when all transocoder have either PSR1, PSR2
> > or eDP 1.5 PR
> > ALPM enabled and VBI is disabled and flips and pushes are not
> > happening.
> >
> > --v2
> > -Switch condition and do an early return [Jani] -Do some checks in
> > compute_config [Jani] -Do not use register reads as a method of
> > checking states
> > for DPKGC or delayed vblank [Jani] -Use another way to see is
> > vblank interrupts
> > are disabled or not [Jani]
> >
> > --v3
> > -Use has_psr to check if psr can be enabled or not for dc5_entry
> > cond [Uma] -
> > Move the dc5 entry computation to psr_compute_config [Jouni] -No
> > need to
> > change sequence of enabled and activate, so dont make
> > hsw_psr1_activate
> > return anything [Jouni] -Use has_psr to stop psr1 activation
> > [Jouni] -Use lineage
> > no. in WA -Add the display ver restrictions for WA
> >
> > --v4
> > -use more appropriate name for check_vblank_limit() [Jouni] -Cover
> > the case for
> > idle frames when dpkgc is not configured [Jouni] -Check psr only
> > for edp [Jouni]
> >
> > --v5
> > -move psr1 handling to plane update [Jouni] -add todo for cases
> > when vblank is
> > enabled when psr enabled [Jouni] -use intel_display instead of
> > drm_i915_private
> >
> > --v6
> > -check target_dc_state [Jouni]
> > -fix condition in pre/post plane update [Jouni]
> >
> > WA: 22019444797
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > .../drm/i915/display/intel_display_types.h | 3 +
> > drivers/gpu/drm/i915/display/intel_psr.c | 112
> > +++++++++++++++++-
> > 2 files changed, 114 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 733de5edcfdb..59c81f0a3abd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1577,6 +1577,9 @@ struct intel_psr {
> > #define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
> >
> > u32 debug;
> > + bool is_dpkgc_configured;
> > + bool is_dc5_entry_possible;
> > + bool is_wa_delayed_vblank_limit;
> > bool sink_support;
> > bool source_support;
> > bool enabled;
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index b30fa067ce6e..e50b476494a0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -26,6 +26,7 @@
> > #include <drm/drm_atomic_helper.h>
> > #include <drm/drm_damage_helper.h>
> > #include <drm/drm_debugfs.h>
> > +#include <drm/drm_vblank.h>
> >
> > #include "i915_drv.h"
> > #include "i915_reg.h"
> > @@ -874,6 +875,78 @@ static u8 psr_compute_idle_frames(struct
> > intel_dp
> > *intel_dp)
> > return idle_frames;
> > }
> >
> > +static bool
> > +intel_psr_check_wa_delayed_vblank(const struct drm_display_mode
> > +*adjusted_mode) {
> > + return (adjusted_mode->crtc_vblank_start -
> > +adjusted_mode->crtc_vdisplay) >= 6; }
> > +
> > +/*
> > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> > + * VRR is not enabled
> > + */
> > +static bool intel_psr_is_dpkgc_configured(struct intel_display
> > *display,
> > + struct intel_atomic_state
> > *state) {
> > + struct intel_crtc *intel_crtc;
> > + struct intel_crtc_state *crtc_state;
> > + int i;
> > +
> > + if (DISPLAY_VER(display) < 20)
> > + return false;
> > +
> > + for_each_new_intel_crtc_in_state(state, intel_crtc,
> > crtc_state, i) {
> > + if (!intel_crtc->active)
> > + continue;
> > +
> > + if (crtc_state->vrr.enable)
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > +/*
> > + * DC5 entry is only possible if vblank interrupt is disabled
> > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> > + * enabled encoders.
> > + */
> > +static bool
> > +intel_psr_is_dc5_entry_possible(struct intel_display *display,
> > + struct intel_atomic_state *state)
> > +{
> > + struct intel_crtc *intel_crtc;
> > + struct intel_crtc_state *crtc_state;
> > + int i;
> > +
> > + if ((display->power.domains.target_dc_state &
> > + DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
> > + return false;
> > +
> > + for_each_new_intel_crtc_in_state(state, intel_crtc,
> > crtc_state, i) {
> > + struct drm_crtc *crtc = &intel_crtc->base;
> > + struct drm_vblank_crtc *vblank;
> > + struct intel_encoder *encoder;
> > +
> > + if (!intel_crtc->active)
> > + continue;
> > +
> > + vblank = drm_crtc_vblank_crtc(crtc);
> > +
> > + if (vblank->enabled)
> > + return false;
> > +
> > + if (crtc_state->has_psr)
> > + return false;
>
> It should be !has_psr
> > +
> > + for_each_encoder_on_crtc(display->drm, crtc,
> > encoder)
> > + if (encoder->type != INTEL_OUTPUT_EDP)
> > + return false;
I'm not sure if we need to care about dual eDP case. One PSR and
another non-PSR. That will return true from this function even thought
it's not possible. That can be solved by checking CAN_PSR(intel_dp)
here.
> > + }
> > +
> > + return true;
> > +}
> > +
> > static void hsw_activate_psr1(struct intel_dp *intel_dp) {
> > struct intel_display *display = to_intel_display(intel_dp);
> > @@ -986,7
> > +1059,15 @@ static void hsw_activate_psr2(struct intel_dp
> > *intel_dp)
> > u32 val = EDP_PSR2_ENABLE;
> > u32 psr_val = 0;
> >
> > - val |=
> > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > + /*
> > + * Wa_22019444797
> > + * TODO: Disable idle frames when vblank gets enabled while
> > + * PSR2 is enabled
> > + */
> > + if (DISPLAY_VER(dev_priv) != 20 ||
> > + !intel_dp->psr.is_dpkgc_configured ||
>
> Why ! for dpkgc, Here this can be enabled if dpkgc_configured right ?
>
> > + intel_dp->psr.is_dc5_entry_possible)
> > + val |=
> > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> >
> > if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
> > val |= EDP_SU_TRACK_ENABLE;
> > @@ -2667,10 +2748,20 @@ void intel_psr_pre_plane_update(struct
> > intel_atomic_state *state,
> > const struct intel_crtc_state *new_crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > struct intel_encoder *encoder;
> > + bool dpkgc_configured = false, dc5_entry_possible = false;
> > + bool wa_delayed_vblank_limit = false;
> >
> > if (!HAS_PSR(display))
> > return;
> >
> > + if (DISPLAY_VER(display) == 20) {
> > + dpkgc_configured =
> > intel_psr_is_dpkgc_configured(display,
> > state);
> > + dc5_entry_possible =
> > + intel_psr_is_dc5_entry_possible(display,
> > state);
> > + wa_delayed_vblank_limit =
> > + intel_psr_check_wa_delayed_vblank(&new_crtc
> > _state-
> > > hw.adjusted_mode);
> > + }
> > +
> > for_each_intel_encoder_mask_with_psr(state->base.dev,
> > encoder,
> > old_crtc_state-
> > >uapi.encoder_mask)
> > {
> > struct intel_dp *intel_dp =
> > enc_to_intel_dp(encoder); @@ -
> > 2679,6 +2770,12 @@ void intel_psr_pre_plane_update(struct
> > intel_atomic_state
> > *state,
> >
> > mutex_lock(&psr->lock);
> >
> > + if (DISPLAY_VER(i915) == 20) {
> > + psr->is_dpkgc_configured =
> > dpkgc_configured;
> > + psr->is_dc5_entry_possible =
> > dc5_entry_possible;
> > + psr->is_wa_delayed_vblank_limit =
> > wa_delayed_vblank_limit;
>
> We can drop the variables and directly assign this to psr->... and
> use it subsequently.
> Also it would be good to have this done in compute and than just use
> it here.
>
> > + }
> > +
> > /*
> > * Reasons to disable:
> > * - PSR disabled in new state
> > @@ -2686,6 +2783,7 @@ void intel_psr_pre_plane_update(struct
> > intel_atomic_state *state,
> > * - Changing between PSR versions
> > * - Region Early Transport changing
> > * - Display WA #1136: skl, bxt
> > + * - Display WA_22019444797
> > */
> > needs_to_disable |=
> > intel_crtc_needs_modeset(new_crtc_state);
> > needs_to_disable |= !new_crtc_state->has_psr; @@ -
> > 2695,6
> > +2793,10 @@ void intel_psr_pre_plane_update(struct
> > intel_atomic_state *state,
> > psr->su_region_et_enabled;
> > needs_to_disable |= DISPLAY_VER(i915) < 11 &&
> > new_crtc_state->wm_level_disabled;
> > + /* TODO: Disable PSR1 when vblank gets enabled
> > while PSR1 is
> > enabled */
> > + needs_to_disable |= DISPLAY_VER(display) == 20 &&
> > dpkgc_configured &&
> > + (wa_delayed_vblank_limit ||
> > dc5_entry_possible) &&
> > + !new_crtc_state->has_sel_update &&
> > +!new_crtc_state->has_panel_replay;
>
> Good to move this to a small helper function which can be extended if
> required as well.
> Also seems used in post_plane as well.
>
> @Hogander, Jouni Can you also ack if this handling for PSR is ok.
This need_to_disable/keep_disabled is ok. I think there is a bug in
check itself:
dc5_entry_possible should be !dc5_entry_possible
What do you think?
BR,
Jouni Högander
>
> > if (psr->enabled && needs_to_disable)
> > intel_psr_disable_locked(intel_dp);
> > @@ -2735,6 +2837,14 @@ void intel_psr_post_plane_update(struct
> > intel_atomic_state *state,
> > keep_disabled |= DISPLAY_VER(display) < 11 &&
> > crtc_state->wm_level_disabled;
> >
> > + /*
> > + * Wa_22019444797
> > + * TODO: Disable PSR1 when vblank gets enabled
> > while PSR1 is
> > enabled
> > + */
> > + keep_disabled |= DISPLAY_VER(display) == 20 && psr-
> > > is_dpkgc_configured &&
> > + (psr->is_wa_delayed_vblank_limit || psr-
> > > is_dc5_entry_possible) &&
> > + !crtc_state->has_sel_update && !crtc_state-
> > > has_panel_replay;
> > +
> > if (!psr->enabled && !keep_disabled)
> > intel_psr_enable_locked(intel_dp,
> > crtc_state);
> > else if (psr->enabled && !crtc_state-
> > >wm_level_disabled)
> > --
> > 2.43.2
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-20 5:36 ` Hogander, Jouni
@ 2024-09-20 6:29 ` Kandpal, Suraj
2024-09-20 6:41 ` Hogander, Jouni
0 siblings, 1 reply; 47+ messages in thread
From: Kandpal, Suraj @ 2024-09-20 6:29 UTC (permalink / raw)
To: Hogander, Jouni, Shankar, Uma, intel-gfx@lists.freedesktop.org; +Cc: Deak, Imre
> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Friday, September 20, 2024 11:06 AM
> To: Shankar, Uma <uma.shankar@intel.com>; Kandpal, Suraj
> <suraj.kandpal@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Deak, Imre <imre.deak@intel.com>
> Subject: Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
>
> On Thu, 2024-09-19 at 12:14 +0000, Shankar, Uma wrote:
> >
> >
> > > -----Original Message-----
> > > From: Kandpal, Suraj <suraj.kandpal@intel.com>
> > > Sent: Monday, September 9, 2024 12:02 PM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: Shankar, Uma <uma.shankar@intel.com>; Hogander, Jouni
> > > <jouni.hogander@intel.com>; Deak, Imre <imre.deak@intel.com>;
> > > Kandpal, Suraj <suraj.kandpal@intel.com>
> > > Subject: [PATCH] drm/i915/psr: Implment WA to help reach PC10
> >
> > Not: Typo in implement
> >
> > > To reach PC10 when PKG_C_LATENCY is configure we must do the
> > > following things
> > > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> > > entered
> > > 2) Allow PSR2 deep sleep when DC5 can be entered
> > > 3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
> > > eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
> > > not happening.
> > >
> > > --v2
> > > -Switch condition and do an early return [Jani] -Do some checks in
> > > compute_config [Jani] -Do not use register reads as a method of
> > > checking states for DPKGC or delayed vblank [Jani] -Use another way
> > > to see is vblank interrupts are disabled or not [Jani]
> > >
> > > --v3
> > > -Use has_psr to check if psr can be enabled or not for dc5_entry
> > > cond [Uma] - Move the dc5 entry computation to psr_compute_config
> > > [Jouni] -No need to change sequence of enabled and activate, so dont
> > > make hsw_psr1_activate return anything [Jouni] -Use has_psr to stop
> > > psr1 activation [Jouni] -Use lineage no. in WA -Add the display ver
> > > restrictions for WA
> > >
> > > --v4
> > > -use more appropriate name for check_vblank_limit() [Jouni] -Cover
> > > the case for idle frames when dpkgc is not configured [Jouni] -Check
> > > psr only for edp [Jouni]
> > >
> > > --v5
> > > -move psr1 handling to plane update [Jouni] -add todo for cases when
> > > vblank is enabled when psr enabled [Jouni] -use intel_display
> > > instead of drm_i915_private
> > >
> > > --v6
> > > -check target_dc_state [Jouni]
> > > -fix condition in pre/post plane update [Jouni]
> > >
> > > WA: 22019444797
> > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > ---
> > > .../drm/i915/display/intel_display_types.h | 3 +
> > > drivers/gpu/drm/i915/display/intel_psr.c | 112
> > > +++++++++++++++++-
> > > 2 files changed, 114 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 733de5edcfdb..59c81f0a3abd 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -1577,6 +1577,9 @@ struct intel_psr {
> > > #define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
> > >
> > > u32 debug;
> > > + bool is_dpkgc_configured;
> > > + bool is_dc5_entry_possible;
> > > + bool is_wa_delayed_vblank_limit;
> > > bool sink_support;
> > > bool source_support;
> > > bool enabled;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index b30fa067ce6e..e50b476494a0 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -26,6 +26,7 @@
> > > #include <drm/drm_atomic_helper.h>
> > > #include <drm/drm_damage_helper.h>
> > > #include <drm/drm_debugfs.h>
> > > +#include <drm/drm_vblank.h>
> > >
> > > #include "i915_drv.h"
> > > #include "i915_reg.h"
> > > @@ -874,6 +875,78 @@ static u8 psr_compute_idle_frames(struct
> > > intel_dp
> > > *intel_dp)
> > > return idle_frames;
> > > }
> > >
> > > +static bool
> > > +intel_psr_check_wa_delayed_vblank(const struct drm_display_mode
> > > +*adjusted_mode) {
> > > + return (adjusted_mode->crtc_vblank_start -
> > > +adjusted_mode->crtc_vdisplay) >= 6; }
> > > +
> > > +/*
> > > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> > > + * VRR is not enabled
> > > + */
> > > +static bool intel_psr_is_dpkgc_configured(struct intel_display
> > > *display,
> > > + struct intel_atomic_state
> > > *state) {
> > > + struct intel_crtc *intel_crtc;
> > > + struct intel_crtc_state *crtc_state;
> > > + int i;
> > > +
> > > + if (DISPLAY_VER(display) < 20)
> > > + return false;
> > > +
> > > + for_each_new_intel_crtc_in_state(state, intel_crtc,
> > > crtc_state, i) {
> > > + if (!intel_crtc->active)
> > > + continue;
> > > +
> > > + if (crtc_state->vrr.enable)
> > > + return false;
> > > + }
> > > +
> > > + return true;
> > > +}
> > > +
> > > +/*
> > > + * DC5 entry is only possible if vblank interrupt is disabled
> > > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> > > + * enabled encoders.
> > > + */
> > > +static bool
> > > +intel_psr_is_dc5_entry_possible(struct intel_display *display,
> > > + struct intel_atomic_state *state) {
> > > + struct intel_crtc *intel_crtc;
> > > + struct intel_crtc_state *crtc_state;
> > > + int i;
> > > +
> > > + if ((display->power.domains.target_dc_state &
> > > + DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
> > > + return false;
> > > +
> > > + for_each_new_intel_crtc_in_state(state, intel_crtc,
> > > crtc_state, i) {
> > > + struct drm_crtc *crtc = &intel_crtc->base;
> > > + struct drm_vblank_crtc *vblank;
> > > + struct intel_encoder *encoder;
> > > +
> > > + if (!intel_crtc->active)
> > > + continue;
> > > +
> > > + vblank = drm_crtc_vblank_crtc(crtc);
> > > +
> > > + if (vblank->enabled)
> > > + return false;
> > > +
> > > + if (crtc_state->has_psr)
> > > + return false;
> >
> > It should be !has_psr
> > > +
> > > + for_each_encoder_on_crtc(display->drm, crtc,
> > > encoder)
> > > + if (encoder->type != INTEL_OUTPUT_EDP)
> > > + return false;
>
> I'm not sure if we need to care about dual eDP case. One PSR and another non-
> PSR. That will return true from this function even thought it's not possible. That
> can be solved by checking CAN_PSR(intel_dp) here.
So ,
if (encoder->type != INTEL_OUTPUT_EDP && CAN_PSR(intel_dp))
return false;
>
> > > + }
> > > +
> > > + return true;
> > > +}
> > > +
> > > static void hsw_activate_psr1(struct intel_dp *intel_dp) {
> > > struct intel_display *display = to_intel_display(intel_dp);
> > > @@ -986,7
> > > +1059,15 @@ static void hsw_activate_psr2(struct intel_dp
> > > *intel_dp)
> > > u32 val = EDP_PSR2_ENABLE;
> > > u32 psr_val = 0;
> > >
> > > - val |=
> > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > > + /*
> > > + * Wa_22019444797
> > > + * TODO: Disable idle frames when vblank gets enabled while
> > > + * PSR2 is enabled
> > > + */
> > > + if (DISPLAY_VER(dev_priv) != 20 ||
> > > + !intel_dp->psr.is_dpkgc_configured ||
> >
> > Why ! for dpkgc, Here this can be enabled if dpkgc_configured right ?
> >
> > > + intel_dp->psr.is_dc5_entry_possible)
> > > + val |=
> > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > >
> > > if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
> > > val |= EDP_SU_TRACK_ENABLE; @@ -2667,10 +2748,20 @@
> > > void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> > > const struct intel_crtc_state *new_crtc_state =
> > > intel_atomic_get_new_crtc_state(state, crtc);
> > > struct intel_encoder *encoder;
> > > + bool dpkgc_configured = false, dc5_entry_possible = false;
> > > + bool wa_delayed_vblank_limit = false;
> > >
> > > if (!HAS_PSR(display))
> > > return;
> > >
> > > + if (DISPLAY_VER(display) == 20) {
> > > + dpkgc_configured =
> > > intel_psr_is_dpkgc_configured(display,
> > > state);
> > > + dc5_entry_possible =
> > > + intel_psr_is_dc5_entry_possible(display,
> > > state);
> > > + wa_delayed_vblank_limit =
> > > + intel_psr_check_wa_delayed_vblank(&new_crtc
> > > _state-
> > > > hw.adjusted_mode);
> > > + }
> > > +
> > > for_each_intel_encoder_mask_with_psr(state->base.dev,
> > > encoder,
> > > old_crtc_state-
> > > >uapi.encoder_mask)
> > > {
> > > struct intel_dp *intel_dp =
> > > enc_to_intel_dp(encoder); @@ -
> > > 2679,6 +2770,12 @@ void intel_psr_pre_plane_update(struct
> > > intel_atomic_state *state,
> > >
> > > mutex_lock(&psr->lock);
> > >
> > > + if (DISPLAY_VER(i915) == 20) {
> > > + psr->is_dpkgc_configured =
> > > dpkgc_configured;
> > > + psr->is_dc5_entry_possible =
> > > dc5_entry_possible;
> > > + psr->is_wa_delayed_vblank_limit =
> > > wa_delayed_vblank_limit;
> >
> > We can drop the variables and directly assign this to psr->... and use
> > it subsequently.
> > Also it would be good to have this done in compute and than just use
> > it here.
> >
> > > + }
> > > +
> > > /*
> > > * Reasons to disable:
> > > * - PSR disabled in new state @@ -2686,6 +2783,7 @@
> > > void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> > > * - Changing between PSR versions
> > > * - Region Early Transport changing
> > > * - Display WA #1136: skl, bxt
> > > + * - Display WA_22019444797
> > > */
> > > needs_to_disable |=
> > > intel_crtc_needs_modeset(new_crtc_state);
> > > needs_to_disable |= !new_crtc_state->has_psr; @@ -
> > > 2695,6
> > > +2793,10 @@ void intel_psr_pre_plane_update(struct
> > > intel_atomic_state *state,
> > > psr->su_region_et_enabled;
> > > needs_to_disable |= DISPLAY_VER(i915) < 11 &&
> > > new_crtc_state->wm_level_disabled;
> > > + /* TODO: Disable PSR1 when vblank gets enabled
> > > while PSR1 is
> > > enabled */
> > > + needs_to_disable |= DISPLAY_VER(display) == 20 &&
> > > dpkgc_configured &&
> > > + (wa_delayed_vblank_limit ||
> > > dc5_entry_possible) &&
> > > + !new_crtc_state->has_sel_update &&
> > > +!new_crtc_state->has_panel_replay;
> >
> > Good to move this to a small helper function which can be extended if
> > required as well.
> > Also seems used in post_plane as well.
> >
> > @Hogander, Jouni Can you also ack if this handling for PSR is ok.
>
> This need_to_disable/keep_disabled is ok. I think there is a bug in check itself:
>
> dc5_entry_possible should be !dc5_entry_possible
>
> What do you think?
>
Dc5_entry_possible returns true when we can enter dc5.
And the condition to disable ps1 is to have a delayed_vblank > 6 or
When dc5 can be entered so that check would be correct
Regards,
Suraj Kandpal
> BR,
>
> Jouni Högander
>
> >
> > > if (psr->enabled && needs_to_disable)
> > > intel_psr_disable_locked(intel_dp);
> > > @@ -2735,6 +2837,14 @@ void intel_psr_post_plane_update(struct
> > > intel_atomic_state *state,
> > > keep_disabled |= DISPLAY_VER(display) < 11 &&
> > > crtc_state->wm_level_disabled;
> > >
> > > + /*
> > > + * Wa_22019444797
> > > + * TODO: Disable PSR1 when vblank gets enabled
> > > while PSR1 is
> > > enabled
> > > + */
> > > + keep_disabled |= DISPLAY_VER(display) == 20 && psr-
> > > > is_dpkgc_configured &&
> > > + (psr->is_wa_delayed_vblank_limit || psr-
> > > > is_dc5_entry_possible) &&
> > > + !crtc_state->has_sel_update && !crtc_state-
> > > > has_panel_replay;
> > > +
> > > if (!psr->enabled && !keep_disabled)
> > > intel_psr_enable_locked(intel_dp,
> > > crtc_state);
> > > else if (psr->enabled && !crtc_state-
> > > >wm_level_disabled)
> > > --
> > > 2.43.2
> >
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-20 6:29 ` Kandpal, Suraj
@ 2024-09-20 6:41 ` Hogander, Jouni
2024-09-20 6:46 ` Kandpal, Suraj
0 siblings, 1 reply; 47+ messages in thread
From: Hogander, Jouni @ 2024-09-20 6:41 UTC (permalink / raw)
To: Kandpal, Suraj, Shankar, Uma, intel-gfx@lists.freedesktop.org; +Cc: Deak, Imre
On Fri, 2024-09-20 at 06:29 +0000, Kandpal, Suraj wrote:
>
>
> > -----Original Message-----
> > From: Hogander, Jouni <jouni.hogander@intel.com>
> > Sent: Friday, September 20, 2024 11:06 AM
> > To: Shankar, Uma <uma.shankar@intel.com>; Kandpal, Suraj
> > <suraj.kandpal@intel.com>; intel-gfx@lists.freedesktop.org
> > Cc: Deak, Imre <imre.deak@intel.com>
> > Subject: Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
> >
> > On Thu, 2024-09-19 at 12:14 +0000, Shankar, Uma wrote:
> > >
> > >
> > > > -----Original Message-----
> > > > From: Kandpal, Suraj <suraj.kandpal@intel.com>
> > > > Sent: Monday, September 9, 2024 12:02 PM
> > > > To: intel-gfx@lists.freedesktop.org
> > > > Cc: Shankar, Uma <uma.shankar@intel.com>; Hogander, Jouni
> > > > <jouni.hogander@intel.com>; Deak, Imre <imre.deak@intel.com>;
> > > > Kandpal, Suraj <suraj.kandpal@intel.com>
> > > > Subject: [PATCH] drm/i915/psr: Implment WA to help reach PC10
> > >
> > > Not: Typo in implement
> > >
> > > > To reach PC10 when PKG_C_LATENCY is configure we must do the
> > > > following things
> > > > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> > > > entered
> > > > 2) Allow PSR2 deep sleep when DC5 can be entered
> > > > 3) DC5 can be entered when all transocoder have either PSR1,
> > > > PSR2 or
> > > > eDP 1.5 PR ALPM enabled and VBI is disabled and flips and
> > > > pushes are
> > > > not happening.
> > > >
> > > > --v2
> > > > -Switch condition and do an early return [Jani] -Do some checks
> > > > in
> > > > compute_config [Jani] -Do not use register reads as a method of
> > > > checking states for DPKGC or delayed vblank [Jani] -Use another
> > > > way
> > > > to see is vblank interrupts are disabled or not [Jani]
> > > >
> > > > --v3
> > > > -Use has_psr to check if psr can be enabled or not for
> > > > dc5_entry
> > > > cond [Uma] - Move the dc5 entry computation to
> > > > psr_compute_config
> > > > [Jouni] -No need to change sequence of enabled and activate, so
> > > > dont
> > > > make hsw_psr1_activate return anything [Jouni] -Use has_psr to
> > > > stop
> > > > psr1 activation [Jouni] -Use lineage no. in WA -Add the display
> > > > ver
> > > > restrictions for WA
> > > >
> > > > --v4
> > > > -use more appropriate name for check_vblank_limit() [Jouni] -
> > > > Cover
> > > > the case for idle frames when dpkgc is not configured [Jouni] -
> > > > Check
> > > > psr only for edp [Jouni]
> > > >
> > > > --v5
> > > > -move psr1 handling to plane update [Jouni] -add todo for cases
> > > > when
> > > > vblank is enabled when psr enabled [Jouni] -use intel_display
> > > > instead of drm_i915_private
> > > >
> > > > --v6
> > > > -check target_dc_state [Jouni]
> > > > -fix condition in pre/post plane update [Jouni]
> > > >
> > > > WA: 22019444797
> > > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > > ---
> > > > .../drm/i915/display/intel_display_types.h | 3 +
> > > > drivers/gpu/drm/i915/display/intel_psr.c | 112
> > > > +++++++++++++++++-
> > > > 2 files changed, 114 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > index 733de5edcfdb..59c81f0a3abd 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > @@ -1577,6 +1577,9 @@ struct intel_psr {
> > > > #define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
> > > >
> > > > u32 debug;
> > > > + bool is_dpkgc_configured;
> > > > + bool is_dc5_entry_possible;
> > > > + bool is_wa_delayed_vblank_limit;
> > > > bool sink_support;
> > > > bool source_support;
> > > > bool enabled;
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index b30fa067ce6e..e50b476494a0 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -26,6 +26,7 @@
> > > > #include <drm/drm_atomic_helper.h>
> > > > #include <drm/drm_damage_helper.h>
> > > > #include <drm/drm_debugfs.h>
> > > > +#include <drm/drm_vblank.h>
> > > >
> > > > #include "i915_drv.h"
> > > > #include "i915_reg.h"
> > > > @@ -874,6 +875,78 @@ static u8 psr_compute_idle_frames(struct
> > > > intel_dp
> > > > *intel_dp)
> > > > return idle_frames;
> > > > }
> > > >
> > > > +static bool
> > > > +intel_psr_check_wa_delayed_vblank(const struct
> > > > drm_display_mode
> > > > +*adjusted_mode) {
> > > > + return (adjusted_mode->crtc_vblank_start -
> > > > +adjusted_mode->crtc_vdisplay) >= 6; }
> > > > +
> > > > +/*
> > > > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> > > > + * VRR is not enabled
> > > > + */
> > > > +static bool intel_psr_is_dpkgc_configured(struct intel_display
> > > > *display,
> > > > + struct
> > > > intel_atomic_state
> > > > *state) {
> > > > + struct intel_crtc *intel_crtc;
> > > > + struct intel_crtc_state *crtc_state;
> > > > + int i;
> > > > +
> > > > + if (DISPLAY_VER(display) < 20)
> > > > + return false;
> > > > +
> > > > + for_each_new_intel_crtc_in_state(state, intel_crtc,
> > > > crtc_state, i) {
> > > > + if (!intel_crtc->active)
> > > > + continue;
> > > > +
> > > > + if (crtc_state->vrr.enable)
> > > > + return false;
> > > > + }
> > > > +
> > > > + return true;
> > > > +}
> > > > +
> > > > +/*
> > > > + * DC5 entry is only possible if vblank interrupt is disabled
> > > > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> > > > + * enabled encoders.
> > > > + */
> > > > +static bool
> > > > +intel_psr_is_dc5_entry_possible(struct intel_display *display,
> > > > + struct intel_atomic_state
> > > > *state) {
> > > > + struct intel_crtc *intel_crtc;
> > > > + struct intel_crtc_state *crtc_state;
> > > > + int i;
> > > > +
> > > > + if ((display->power.domains.target_dc_state &
> > > > + DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
> > > > + return false;
> > > > +
> > > > + for_each_new_intel_crtc_in_state(state, intel_crtc,
> > > > crtc_state, i) {
> > > > + struct drm_crtc *crtc = &intel_crtc->base;
> > > > + struct drm_vblank_crtc *vblank;
> > > > + struct intel_encoder *encoder;
> > > > +
> > > > + if (!intel_crtc->active)
> > > > + continue;
> > > > +
> > > > + vblank = drm_crtc_vblank_crtc(crtc);
> > > > +
> > > > + if (vblank->enabled)
> > > > + return false;
> > > > +
> > > > + if (crtc_state->has_psr)
> > > > + return false;
> > >
> > > It should be !has_psr
> > > > +
> > > > + for_each_encoder_on_crtc(display->drm, crtc,
> > > > encoder)
> > > > + if (encoder->type != INTEL_OUTPUT_EDP)
> > > > + return false;
> >
> > I'm not sure if we need to care about dual eDP case. One PSR and
> > another non-
> > PSR. That will return true from this function even thought it's not
> > possible. That
> > can be solved by checking CAN_PSR(intel_dp) here.
>
> So ,
> if (encoder->type != INTEL_OUTPUT_EDP &&
> CAN_PSR(intel_dp))
> return false;
> >
> > > > + }
> > > > +
> > > > + return true;
> > > > +}
> > > > +
> > > > static void hsw_activate_psr1(struct intel_dp *intel_dp) {
> > > > struct intel_display *display =
> > > > to_intel_display(intel_dp);
> > > > @@ -986,7
> > > > +1059,15 @@ static void hsw_activate_psr2(struct intel_dp
> > > > *intel_dp)
> > > > u32 val = EDP_PSR2_ENABLE;
> > > > u32 psr_val = 0;
> > > >
> > > > - val |=
> > > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > > > + /*
> > > > + * Wa_22019444797
> > > > + * TODO: Disable idle frames when vblank gets enabled
> > > > while
> > > > + * PSR2 is enabled
> > > > + */
> > > > + if (DISPLAY_VER(dev_priv) != 20 ||
> > > > + !intel_dp->psr.is_dpkgc_configured ||
> > >
> > > Why ! for dpkgc, Here this can be enabled if dpkgc_configured
> > > right ?
> > >
> > > > + intel_dp->psr.is_dc5_entry_possible)
> > > > + val |=
> > > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > > >
> > > > if (DISPLAY_VER(display) < 14 &&
> > > > !IS_ALDERLAKE_P(dev_priv))
> > > > val |= EDP_SU_TRACK_ENABLE; @@ -2667,10
> > > > +2748,20 @@
> > > > void intel_psr_pre_plane_update(struct intel_atomic_state
> > > > *state,
> > > > const struct intel_crtc_state *new_crtc_state =
> > > > intel_atomic_get_new_crtc_state(state, crtc);
> > > > struct intel_encoder *encoder;
> > > > + bool dpkgc_configured = false, dc5_entry_possible =
> > > > false;
> > > > + bool wa_delayed_vblank_limit = false;
> > > >
> > > > if (!HAS_PSR(display))
> > > > return;
> > > >
> > > > + if (DISPLAY_VER(display) == 20) {
> > > > + dpkgc_configured =
> > > > intel_psr_is_dpkgc_configured(display,
> > > > state);
> > > > + dc5_entry_possible =
> > > > + intel_psr_is_dc5_entry_possible(display
> > > > ,
> > > > state);
> > > > + wa_delayed_vblank_limit =
> > > > + intel_psr_check_wa_delayed_vblank(&new_
> > > > crtc
> > > > _state-
> > > > > hw.adjusted_mode);
> > > > + }
> > > > +
> > > > for_each_intel_encoder_mask_with_psr(state->base.dev,
> > > > encoder,
> > > > old_crtc_state-
> > > > > uapi.encoder_mask)
> > > > {
> > > > struct intel_dp *intel_dp =
> > > > enc_to_intel_dp(encoder); @@ -
> > > > 2679,6 +2770,12 @@ void intel_psr_pre_plane_update(struct
> > > > intel_atomic_state *state,
> > > >
> > > > mutex_lock(&psr->lock);
> > > >
> > > > + if (DISPLAY_VER(i915) == 20) {
> > > > + psr->is_dpkgc_configured =
> > > > dpkgc_configured;
> > > > + psr->is_dc5_entry_possible =
> > > > dc5_entry_possible;
> > > > + psr->is_wa_delayed_vblank_limit =
> > > > wa_delayed_vblank_limit;
> > >
> > > We can drop the variables and directly assign this to psr->...
> > > and use
> > > it subsequently.
> > > Also it would be good to have this done in compute and than just
> > > use
> > > it here.
> > >
> > > > + }
> > > > +
> > > > /*
> > > > * Reasons to disable:
> > > > * - PSR disabled in new state @@ -2686,6
> > > > +2783,7 @@
> > > > void intel_psr_pre_plane_update(struct intel_atomic_state
> > > > *state,
> > > > * - Changing between PSR versions
> > > > * - Region Early Transport changing
> > > > * - Display WA #1136: skl, bxt
> > > > + * - Display WA_22019444797
> > > > */
> > > > needs_to_disable |=
> > > > intel_crtc_needs_modeset(new_crtc_state);
> > > > needs_to_disable |= !new_crtc_state->has_psr;
> > > > @@ -
> > > > 2695,6
> > > > +2793,10 @@ void intel_psr_pre_plane_update(struct
> > > > intel_atomic_state *state,
> > > > psr->su_region_et_enabled;
> > > > needs_to_disable |= DISPLAY_VER(i915) < 11 &&
> > > > new_crtc_state->wm_level_disabled;
> > > > + /* TODO: Disable PSR1 when vblank gets enabled
> > > > while PSR1 is
> > > > enabled */
> > > > + needs_to_disable |= DISPLAY_VER(display) == 20
> > > > &&
> > > > dpkgc_configured &&
> > > > + (wa_delayed_vblank_limit ||
> > > > dc5_entry_possible) &&
> > > > + !new_crtc_state->has_sel_update &&
> > > > +!new_crtc_state->has_panel_replay;
> > >
> > > Good to move this to a small helper function which can be
> > > extended if
> > > required as well.
> > > Also seems used in post_plane as well.
> > >
> > > @Hogander, Jouni Can you also ack if this handling for PSR is ok.
> >
> > This need_to_disable/keep_disabled is ok. I think there is a bug in
> > check itself:
> >
> > dc5_entry_possible should be !dc5_entry_possible
> >
> > What do you think?
> >
>
> Dc5_entry_possible returns true when we can enter dc5.
> And the condition to disable ps1 is to have a delayed_vblank > 6 or
> When dc5 can be entered so that check would be correct
"When PKG_C_LATENCY is configured (not all 1s), enable PSR1(SRD_CTL SRD
Enable == 1) only when the transcoder has Vblank delayed less than 6
lines OR DC5 can be entered. "
I think this emphasizes suggestion from Uma, move this as a helper.
Also add explanation there.
BR,
Jouni Högander
>
> Regards,
> Suraj Kandpal
>
> > BR,
> >
> > Jouni Högander
> >
> > >
> > > > if (psr->enabled && needs_to_disable)
> > > > intel_psr_disable_locked(intel_dp);
> > > > @@ -2735,6 +2837,14 @@ void intel_psr_post_plane_update(struct
> > > > intel_atomic_state *state,
> > > > keep_disabled |= DISPLAY_VER(display) < 11 &&
> > > > crtc_state->wm_level_disabled;
> > > >
> > > > + /*
> > > > + * Wa_22019444797
> > > > + * TODO: Disable PSR1 when vblank gets enabled
> > > > while PSR1 is
> > > > enabled
> > > > + */
> > > > + keep_disabled |= DISPLAY_VER(display) == 20 &&
> > > > psr-
> > > > > is_dpkgc_configured &&
> > > > + (psr->is_wa_delayed_vblank_limit ||
> > > > psr-
> > > > > is_dc5_entry_possible) &&
> > > > + !crtc_state->has_sel_update &&
> > > > !crtc_state-
> > > > > has_panel_replay;
> > > > +
> > > > if (!psr->enabled && !keep_disabled)
> > > > intel_psr_enable_locked(intel_dp,
> > > > crtc_state);
> > > > else if (psr->enabled && !crtc_state-
> > > > > wm_level_disabled)
> > > > --
> > > > 2.43.2
> > >
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
2024-09-20 6:41 ` Hogander, Jouni
@ 2024-09-20 6:46 ` Kandpal, Suraj
0 siblings, 0 replies; 47+ messages in thread
From: Kandpal, Suraj @ 2024-09-20 6:46 UTC (permalink / raw)
To: Hogander, Jouni, Shankar, Uma, intel-gfx@lists.freedesktop.org; +Cc: Deak, Imre
[-- Attachment #1: Type: text/plain, Size: 15364 bytes --]
________________________________
From: Hogander, Jouni <jouni.hogander@intel.com>
Sent: Friday, September 20, 2024 12:11:19 pm
To: Kandpal, Suraj <suraj.kandpal@intel.com>; Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org <intel-gfx@lists.freedesktop.org>
Cc: Deak, Imre <imre.deak@intel.com>
Subject: Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
On Fri, 2024-09-20 at 06:29 +0000, Kandpal, Suraj wrote:
>
>
> > -----Original Message-----
> > From: Hogander, Jouni <jouni.hogander@intel.com>
> > Sent: Friday, September 20, 2024 11:06 AM
> > To: Shankar, Uma <uma.shankar@intel.com>; Kandpal, Suraj
> > <suraj.kandpal@intel.com>; intel-gfx@lists.freedesktop.org
> > Cc: Deak, Imre <imre.deak@intel.com>
> > Subject: Re: [PATCH] drm/i915/psr: Implment WA to help reach PC10
> >
> > On Thu, 2024-09-19 at 12:14 +0000, Shankar, Uma wrote:
> > >
> > >
> > > > -----Original Message-----
> > > > From: Kandpal, Suraj <suraj.kandpal@intel.com>
> > > > Sent: Monday, September 9, 2024 12:02 PM
> > > > To: intel-gfx@lists.freedesktop.org
> > > > Cc: Shankar, Uma <uma.shankar@intel.com>; Hogander, Jouni
> > > > <jouni.hogander@intel.com>; Deak, Imre <imre.deak@intel.com>;
> > > > Kandpal, Suraj <suraj.kandpal@intel.com>
> > > > Subject: [PATCH] drm/i915/psr: Implment WA to help reach PC10
> > >
> > > Not: Typo in implement
> > >
> > > > To reach PC10 when PKG_C_LATENCY is configure we must do the
> > > > following things
> > > > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> > > > entered
> > > > 2) Allow PSR2 deep sleep when DC5 can be entered
> > > > 3) DC5 can be entered when all transocoder have either PSR1,
> > > > PSR2 or
> > > > eDP 1.5 PR ALPM enabled and VBI is disabled and flips and
> > > > pushes are
> > > > not happening.
> > > >
> > > > --v2
> > > > -Switch condition and do an early return [Jani] -Do some checks
> > > > in
> > > > compute_config [Jani] -Do not use register reads as a method of
> > > > checking states for DPKGC or delayed vblank [Jani] -Use another
> > > > way
> > > > to see is vblank interrupts are disabled or not [Jani]
> > > >
> > > > --v3
> > > > -Use has_psr to check if psr can be enabled or not for
> > > > dc5_entry
> > > > cond [Uma] - Move the dc5 entry computation to
> > > > psr_compute_config
> > > > [Jouni] -No need to change sequence of enabled and activate, so
> > > > dont
> > > > make hsw_psr1_activate return anything [Jouni] -Use has_psr to
> > > > stop
> > > > psr1 activation [Jouni] -Use lineage no. in WA -Add the display
> > > > ver
> > > > restrictions for WA
> > > >
> > > > --v4
> > > > -use more appropriate name for check_vblank_limit() [Jouni] -
> > > > Cover
> > > > the case for idle frames when dpkgc is not configured [Jouni] -
> > > > Check
> > > > psr only for edp [Jouni]
> > > >
> > > > --v5
> > > > -move psr1 handling to plane update [Jouni] -add todo for cases
> > > > when
> > > > vblank is enabled when psr enabled [Jouni] -use intel_display
> > > > instead of drm_i915_private
> > > >
> > > > --v6
> > > > -check target_dc_state [Jouni]
> > > > -fix condition in pre/post plane update [Jouni]
> > > >
> > > > WA: 22019444797
> > > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > > ---
> > > > .../drm/i915/display/intel_display_types.h | 3 +
> > > > drivers/gpu/drm/i915/display/intel_psr.c | 112
> > > > +++++++++++++++++-
> > > > 2 files changed, 114 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > index 733de5edcfdb..59c81f0a3abd 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > @@ -1577,6 +1577,9 @@ struct intel_psr {
> > > > #define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
> > > >
> > > > u32 debug;
> > > > + bool is_dpkgc_configured;
> > > > + bool is_dc5_entry_possible;
> > > > + bool is_wa_delayed_vblank_limit;
> > > > bool sink_support;
> > > > bool source_support;
> > > > bool enabled;
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index b30fa067ce6e..e50b476494a0 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -26,6 +26,7 @@
> > > > #include <drm/drm_atomic_helper.h>
> > > > #include <drm/drm_damage_helper.h>
> > > > #include <drm/drm_debugfs.h>
> > > > +#include <drm/drm_vblank.h>
> > > >
> > > > #include "i915_drv.h"
> > > > #include "i915_reg.h"
> > > > @@ -874,6 +875,78 @@ static u8 psr_compute_idle_frames(struct
> > > > intel_dp
> > > > *intel_dp)
> > > > return idle_frames;
> > > > }
> > > >
> > > > +static bool
> > > > +intel_psr_check_wa_delayed_vblank(const struct
> > > > drm_display_mode
> > > > +*adjusted_mode) {
> > > > + return (adjusted_mode->crtc_vblank_start -
> > > > +adjusted_mode->crtc_vdisplay) >= 6; }
> > > > +
> > > > +/*
> > > > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> > > > + * VRR is not enabled
> > > > + */
> > > > +static bool intel_psr_is_dpkgc_configured(struct intel_display
> > > > *display,
> > > > + struct
> > > > intel_atomic_state
> > > > *state) {
> > > > + struct intel_crtc *intel_crtc;
> > > > + struct intel_crtc_state *crtc_state;
> > > > + int i;
> > > > +
> > > > + if (DISPLAY_VER(display) < 20)
> > > > + return false;
> > > > +
> > > > + for_each_new_intel_crtc_in_state(state, intel_crtc,
> > > > crtc_state, i) {
> > > > + if (!intel_crtc->active)
> > > > + continue;
> > > > +
> > > > + if (crtc_state->vrr.enable)
> > > > + return false;
> > > > + }
> > > > +
> > > > + return true;
> > > > +}
> > > > +
> > > > +/*
> > > > + * DC5 entry is only possible if vblank interrupt is disabled
> > > > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> > > > + * enabled encoders.
> > > > + */
> > > > +static bool
> > > > +intel_psr_is_dc5_entry_possible(struct intel_display *display,
> > > > + struct intel_atomic_state
> > > > *state) {
> > > > + struct intel_crtc *intel_crtc;
> > > > + struct intel_crtc_state *crtc_state;
> > > > + int i;
> > > > +
> > > > + if ((display->power.domains.target_dc_state &
> > > > + DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
> > > > + return false;
> > > > +
> > > > + for_each_new_intel_crtc_in_state(state, intel_crtc,
> > > > crtc_state, i) {
> > > > + struct drm_crtc *crtc = &intel_crtc->base;
> > > > + struct drm_vblank_crtc *vblank;
> > > > + struct intel_encoder *encoder;
> > > > +
> > > > + if (!intel_crtc->active)
> > > > + continue;
> > > > +
> > > > + vblank = drm_crtc_vblank_crtc(crtc);
> > > > +
> > > > + if (vblank->enabled)
> > > > + return false;
> > > > +
> > > > + if (crtc_state->has_psr)
> > > > + return false;
> > >
> > > It should be !has_psr
> > > > +
> > > > + for_each_encoder_on_crtc(display->drm, crtc,
> > > > encoder)
> > > > + if (encoder->type != INTEL_OUTPUT_EDP)
> > > > + return false;
> >
> > I'm not sure if we need to care about dual eDP case. One PSR and
> > another non-
> > PSR. That will return true from this function even thought it's not
> > possible. That
> > can be solved by checking CAN_PSR(intel_dp) here.
>
> So ,
> if (encoder->type != INTEL_OUTPUT_EDP &&
> CAN_PSR(intel_dp))
> return false;
> >
> > > > + }
> > > > +
> > > > + return true;
> > > > +}
> > > > +
> > > > static void hsw_activate_psr1(struct intel_dp *intel_dp) {
> > > > struct intel_display *display =
> > > > to_intel_display(intel_dp);
> > > > @@ -986,7
> > > > +1059,15 @@ static void hsw_activate_psr2(struct intel_dp
> > > > *intel_dp)
> > > > u32 val = EDP_PSR2_ENABLE;
> > > > u32 psr_val = 0;
> > > >
> > > > - val |=
> > > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > > > + /*
> > > > + * Wa_22019444797
> > > > + * TODO: Disable idle frames when vblank gets enabled
> > > > while
> > > > + * PSR2 is enabled
> > > > + */
> > > > + if (DISPLAY_VER(dev_priv) != 20 ||
> > > > + !intel_dp->psr.is_dpkgc_configured ||
> > >
> > > Why ! for dpkgc, Here this can be enabled if dpkgc_configured
> > > right ?
> > >
> > > > + intel_dp->psr.is_dc5_entry_possible)
> > > > + val |=
> > > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > > >
> > > > if (DISPLAY_VER(display) < 14 &&
> > > > !IS_ALDERLAKE_P(dev_priv))
> > > > val |= EDP_SU_TRACK_ENABLE; @@ -2667,10
> > > > +2748,20 @@
> > > > void intel_psr_pre_plane_update(struct intel_atomic_state
> > > > *state,
> > > > const struct intel_crtc_state *new_crtc_state =
> > > > intel_atomic_get_new_crtc_state(state, crtc);
> > > > struct intel_encoder *encoder;
> > > > + bool dpkgc_configured = false, dc5_entry_possible =
> > > > false;
> > > > + bool wa_delayed_vblank_limit = false;
> > > >
> > > > if (!HAS_PSR(display))
> > > > return;
> > > >
> > > > + if (DISPLAY_VER(display) == 20) {
> > > > + dpkgc_configured =
> > > > intel_psr_is_dpkgc_configured(display,
> > > > state);
> > > > + dc5_entry_possible =
> > > > + intel_psr_is_dc5_entry_possible(display
> > > > ,
> > > > state);
> > > > + wa_delayed_vblank_limit =
> > > > + intel_psr_check_wa_delayed_vblank(&new_
> > > > crtc
> > > > _state-
> > > > > hw.adjusted_mode);
> > > > + }
> > > > +
> > > > for_each_intel_encoder_mask_with_psr(state->base.dev,
> > > > encoder,
> > > > old_crtc_state-
> > > > > uapi.encoder_mask)
> > > > {
> > > > struct intel_dp *intel_dp =
> > > > enc_to_intel_dp(encoder); @@ -
> > > > 2679,6 +2770,12 @@ void intel_psr_pre_plane_update(struct
> > > > intel_atomic_state *state,
> > > >
> > > > mutex_lock(&psr->lock);
> > > >
> > > > + if (DISPLAY_VER(i915) == 20) {
> > > > + psr->is_dpkgc_configured =
> > > > dpkgc_configured;
> > > > + psr->is_dc5_entry_possible =
> > > > dc5_entry_possible;
> > > > + psr->is_wa_delayed_vblank_limit =
> > > > wa_delayed_vblank_limit;
> > >
> > > We can drop the variables and directly assign this to psr->...
> > > and use
> > > it subsequently.
> > > Also it would be good to have this done in compute and than just
> > > use
> > > it here.
> > >
> > > > + }
> > > > +
> > > > /*
> > > > * Reasons to disable:
> > > > * - PSR disabled in new state @@ -2686,6
> > > > +2783,7 @@
> > > > void intel_psr_pre_plane_update(struct intel_atomic_state
> > > > *state,
> > > > * - Changing between PSR versions
> > > > * - Region Early Transport changing
> > > > * - Display WA #1136: skl, bxt
> > > > + * - Display WA_22019444797
> > > > */
> > > > needs_to_disable |=
> > > > intel_crtc_needs_modeset(new_crtc_state);
> > > > needs_to_disable |= !new_crtc_state->has_psr;
> > > > @@ -
> > > > 2695,6
> > > > +2793,10 @@ void intel_psr_pre_plane_update(struct
> > > > intel_atomic_state *state,
> > > > psr->su_region_et_enabled;
> > > > needs_to_disable |= DISPLAY_VER(i915) < 11 &&
> > > > new_crtc_state->wm_level_disabled;
> > > > + /* TODO: Disable PSR1 when vblank gets enabled
> > > > while PSR1 is
> > > > enabled */
> > > > + needs_to_disable |= DISPLAY_VER(display) == 20
> > > > &&
> > > > dpkgc_configured &&
> > > > + (wa_delayed_vblank_limit ||
> > > > dc5_entry_possible) &&
> > > > + !new_crtc_state->has_sel_update &&
> > > > +!new_crtc_state->has_panel_replay;
> > >
> > > Good to move this to a small helper function which can be
> > > extended if
> > > required as well.
> > > Also seems used in post_plane as well.
> > >
> > > @Hogander, Jouni Can you also ack if this handling for PSR is ok.
> >
> > This need_to_disable/keep_disabled is ok. I think there is a bug in
> > check itself:
> >
> > dc5_entry_possible should be !dc5_entry_possible
> >
> > What do you think?
> >
>
> Dc5_entry_possible returns true when we can enter dc5.
> And the condition to disable ps1 is to have a delayed_vblank > 6 or
> When dc5 can be entered so that check would be correct
"When PKG_C_LATENCY is configured (not all 1s), enable PSR1(SRD_CTL SRD
Enable == 1) only when the transcoder has Vblank delayed less than 6
lines OR DC5 can be entered. "
I think this emphasizes suggestion from Uma, move this as a helper.
Also add explanation there.
--------
I see what went wrong here it's should be !dc5_entry_possible will move this into its own helper too
Regards,
Suraj Kandpal
--------
BR,
Jouni Högander
>
> Regards,
> Suraj Kandpal
>
> > BR,
> >
> > Jouni Högander
> >
> > >
> > > > if (psr->enabled && needs_to_disable)
> > > > intel_psr_disable_locked(intel_dp);
> > > > @@ -2735,6 +2837,14 @@ void intel_psr_post_plane_update(struct
> > > > intel_atomic_state *state,
> > > > keep_disabled |= DISPLAY_VER(display) < 11 &&
> > > > crtc_state->wm_level_disabled;
> > > >
> > > > + /*
> > > > + * Wa_22019444797
> > > > + * TODO: Disable PSR1 when vblank gets enabled
> > > > while PSR1 is
> > > > enabled
> > > > + */
> > > > + keep_disabled |= DISPLAY_VER(display) == 20 &&
> > > > psr-
> > > > > is_dpkgc_configured &&
> > > > + (psr->is_wa_delayed_vblank_limit ||
> > > > psr-
> > > > > is_dc5_entry_possible) &&
> > > > + !crtc_state->has_sel_update &&
> > > > !crtc_state-
> > > > > has_panel_replay;
> > > > +
> > > > if (!psr->enabled && !keep_disabled)
> > > > intel_psr_enable_locked(intel_dp,
> > > > crtc_state);
> > > > else if (psr->enabled && !crtc_state-
> > > > > wm_level_disabled)
> > > > --
> > > > 2.43.2
> > >
>
[-- Attachment #2: Type: text/html, Size: 31099 bytes --]
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH] drm/i915/psr: Implement WA to help reach PC10
2024-09-09 6:32 ` Suraj Kandpal
2024-09-19 12:14 ` Shankar, Uma
@ 2024-09-20 9:12 ` Suraj Kandpal
2024-09-20 11:45 ` Hogander, Jouni
1 sibling, 1 reply; 47+ messages in thread
From: Suraj Kandpal @ 2024-09-20 9:12 UTC (permalink / raw)
To: intel-gfx; +Cc: uma.shankar, jouni.hogander, Suraj Kandpal
To reach PC10 when PKG_C_LATENCY is configure we must do the following
things
1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
2) Allow PSR2 deep sleep when DC5 can be entered
3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
not happening.
--v2
-Switch condition and do an early return [Jani]
-Do some checks in compute_config [Jani]
-Do not use register reads as a method of checking states for
DPKGC or delayed vblank [Jani]
-Use another way to see is vblank interrupts are disabled or not [Jani]
--v3
-Use has_psr to check if psr can be enabled or not for dc5_entry cond
[Uma]
-Move the dc5 entry computation to psr_compute_config [Jouni]
-No need to change sequence of enabled and activate,
so dont make hsw_psr1_activate return anything [Jouni]
-Use has_psr to stop psr1 activation [Jouni]
-Use lineage no. in WA
-Add the display ver restrictions for WA
--v4
-use more appropriate name for check_vblank_limit() [Jouni]
-Cover the case for idle frames when dpkgc is not configured [Jouni]
-Check psr only for edp [Jouni]
--v5
-move psr1 handling to plane update [Jouni]
-add todo for cases when vblank is enabled when psr enabled [Jouni]
-use intel_display instead of drm_i915_private
--v6
-check target_dc_state [Jouni]
-fix condition in pre/post plane update [Jouni]
--v7
-fix has_psr condition [Uma]
-fix typo in commit subject [Uma]
-put psr1_wa check in its own helper [Uma]
-fix the dc_entry check [Jouni]
-use HAS_PSR() to cover two edp one with psr and one nonpsr [Jouni]
WA: 22019444797
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/display/intel_psr.c | 119 +++++++++++++++++-
2 files changed, 121 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 3e694c1204db..2d790abee76e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1577,6 +1577,9 @@ struct intel_psr {
#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
u32 debug;
+ bool is_dpkgc_configured;
+ bool is_dc5_entry_possible;
+ bool is_wa_delayed_vblank_limit;
bool sink_support;
bool source_support;
bool enabled;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 5b355d0a3565..b882ff25fb92 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -26,6 +26,7 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_damage_helper.h>
#include <drm/drm_debugfs.h>
+#include <drm/drm_vblank.h>
#include "i915_drv.h"
#include "i915_reg.h"
@@ -895,6 +896,89 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
return idle_frames;
}
+static bool
+intel_psr_check_wa_delayed_vblank(const struct drm_display_mode *adjusted_mode)
+{
+ return (adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay) >= 6;
+}
+
+/*
+ * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
+ * VRR is not enabled
+ */
+static bool intel_psr_is_dpkgc_configured(struct intel_display *display,
+ struct intel_atomic_state *state)
+{
+ struct intel_crtc *intel_crtc;
+ struct intel_crtc_state *crtc_state;
+ int i;
+
+ if (DISPLAY_VER(display) < 20)
+ return false;
+
+ for_each_new_intel_crtc_in_state(state, intel_crtc, crtc_state, i) {
+ if (!intel_crtc->active)
+ continue;
+
+ if (crtc_state->vrr.enable)
+ return false;
+ }
+
+ return true;
+}
+
+static bool wa_22019444797_psr1_check(const struct intel_crtc_state *crtc_state,
+ struct intel_psr *psr)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ return DISPLAY_VER(display) == 20 && psr->is_dpkgc_configured &&
+ (psr->is_wa_delayed_vblank_limit || !psr->is_dc5_entry_possible) &&
+ !crtc_state->has_sel_update && !crtc_state->has_panel_replay;
+}
+
+/*
+ * DC5 entry is only possible if vblank interrupt is disabled
+ * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
+ * enabled encoders.
+ */
+static bool
+intel_psr_is_dc5_entry_possible(struct intel_display *display,
+ struct intel_atomic_state *state)
+{
+ struct intel_crtc *intel_crtc;
+ struct intel_crtc_state *crtc_state;
+ int i;
+
+ if ((display->power.domains.target_dc_state &
+ DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
+ return false;
+
+ for_each_new_intel_crtc_in_state(state, intel_crtc, crtc_state, i) {
+ struct drm_crtc *crtc = &intel_crtc->base;
+ struct drm_vblank_crtc *vblank;
+ struct intel_encoder *encoder;
+
+ if (!intel_crtc->active)
+ continue;
+
+ vblank = drm_crtc_vblank_crtc(crtc);
+
+ if (vblank->enabled)
+ return false;
+
+ if (!crtc_state->has_psr)
+ return false;
+
+ for_each_encoder_on_crtc(display->drm, crtc, encoder)
+ if (encoder->type != INTEL_OUTPUT_EDP ||
+ !CAN_PSR(enc_to_intel_dp(encoder)))
+ return false;
+ }
+
+ return true;
+}
+
static void hsw_activate_psr1(struct intel_dp *intel_dp)
{
struct intel_display *display = to_intel_display(intel_dp);
@@ -1007,7 +1091,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
u32 val = EDP_PSR2_ENABLE;
u32 psr_val = 0;
- val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ /*
+ * Wa_22019444797
+ * TODO: Disable idle frames when vblank gets enabled while
+ * PSR2 is enabled
+ */
+ if (DISPLAY_VER(dev_priv) != 20 ||
+ !intel_dp->psr.is_dpkgc_configured ||
+ intel_dp->psr.is_dc5_entry_possible)
+ val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
val |= EDP_SU_TRACK_ENABLE;
@@ -2692,10 +2784,20 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_encoder *encoder;
+ bool dpkgc_configured = false, dc5_entry_possible = false;
+ bool wa_delayed_vblank_limit = false;
if (!HAS_PSR(display))
return;
+ if (DISPLAY_VER(display) == 20) {
+ dpkgc_configured = intel_psr_is_dpkgc_configured(display, state);
+ dc5_entry_possible =
+ intel_psr_is_dc5_entry_possible(display, state);
+ wa_delayed_vblank_limit =
+ intel_psr_check_wa_delayed_vblank(&new_crtc_state->hw.adjusted_mode);
+ }
+
for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
old_crtc_state->uapi.encoder_mask) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2704,6 +2806,12 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
mutex_lock(&psr->lock);
+ if (DISPLAY_VER(i915) == 20) {
+ psr->is_dpkgc_configured = dpkgc_configured;
+ psr->is_dc5_entry_possible = dc5_entry_possible;
+ psr->is_wa_delayed_vblank_limit = wa_delayed_vblank_limit;
+ }
+
/*
* Reasons to disable:
* - PSR disabled in new state
@@ -2711,6 +2819,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
* - Changing between PSR versions
* - Region Early Transport changing
* - Display WA #1136: skl, bxt
+ * - Display WA_22019444797
*/
needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
needs_to_disable |= !new_crtc_state->has_psr;
@@ -2720,6 +2829,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
psr->su_region_et_enabled;
needs_to_disable |= DISPLAY_VER(i915) < 11 &&
new_crtc_state->wm_level_disabled;
+ /* TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled */
+ needs_to_disable |= wa_22019444797_psr1_check(new_crtc_state, psr);
if (psr->enabled && needs_to_disable)
intel_psr_disable_locked(intel_dp);
@@ -2760,6 +2871,12 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
keep_disabled |= DISPLAY_VER(display) < 11 &&
crtc_state->wm_level_disabled;
+ /*
+ * Wa_22019444797
+ * TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled
+ */
+ keep_disabled |= wa_22019444797_psr1_check(crtc_state, psr);
+
if (!psr->enabled && !keep_disabled)
intel_psr_enable_locked(intel_dp, crtc_state);
else if (psr->enabled && !crtc_state->wm_level_disabled)
--
2.43.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/psr: Implment WA to help reach PC10 (rev6)
2024-09-02 5:02 [PATCH] drm/i915/psr: Implment WA to help reach PC10 Suraj Kandpal
` (9 preceding siblings ...)
2024-09-10 17:15 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2024-09-20 10:57 ` Patchwork
2024-09-21 11:54 ` ✗ Fi.CI.IGT: failure " Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2024-09-20 10:57 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5287 bytes --]
== Series Details ==
Series: drm/i915/psr: Implment WA to help reach PC10 (rev6)
URL : https://patchwork.freedesktop.org/series/138065/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15441 -> Patchwork_138065v6
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/index.html
Participating hosts (38 -> 37)
------------------------------
Additional (2): fi-kbl-8809g fi-bsw-n3050
Missing (3): bat-dg2-11 fi-snb-2520m fi-elk-e7500
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_138065v6:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@guc_multi_lrc:
- {bat-arlh-3}: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/bat-arlh-3/igt@i915_selftest@live@guc_multi_lrc.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/bat-arlh-3/igt@i915_selftest@live@guc_multi_lrc.html
Known issues
------------
Here are the changes found in Patchwork_138065v6 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][3] ([i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-8809g: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/fi-kbl-8809g/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@random-engines:
- fi-bsw-n3050: NOTRUN -> [SKIP][5] +20 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/fi-bsw-n3050/igt@gem_lmem_swapping@random-engines.html
* igt@i915_selftest@live:
- bat-mtlp-8: [PASS][6] -> [ABORT][7] ([i915#12061]) +1 other test abort
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/bat-mtlp-8/igt@i915_selftest@live.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/bat-mtlp-8/igt@i915_selftest@live.html
- bat-twl-1: [PASS][8] -> [INCOMPLETE][9] ([i915#9413])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/bat-twl-1/igt@i915_selftest@live.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/bat-twl-1/igt@i915_selftest@live.html
* igt@i915_selftest@live@gt_lrc:
- bat-twl-1: [PASS][10] -> [INCOMPLETE][11] ([i915#10886] / [i915#9413])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/bat-twl-1/igt@i915_selftest@live@gt_lrc.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/bat-twl-1/igt@i915_selftest@live@gt_lrc.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-kbl-8809g: NOTRUN -> [SKIP][12] +30 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/fi-kbl-8809g/igt@kms_force_connector_basic@force-load-detect.html
#### Possible fixes ####
* igt@i915_selftest@live:
- bat-jsl-1: [DMESG-FAIL][13] ([i915#11984] / [i915#12010]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/bat-jsl-1/igt@i915_selftest@live.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/bat-jsl-1/igt@i915_selftest@live.html
* igt@i915_selftest@live@gt_pm:
- bat-jsl-1: [DMESG-FAIL][15] ([i915#11984]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/bat-jsl-1/igt@i915_selftest@live@gt_pm.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/bat-jsl-1/igt@i915_selftest@live@gt_pm.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10341]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10341
[i915#10886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10886
[i915#11984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11984
[i915#12010]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12010
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#12133]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12133
[i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#9413]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9413
Build changes
-------------
* Linux: CI_DRM_15441 -> Patchwork_138065v6
CI-20190529: 20190529
CI_DRM_15441: 128ccc5f71d7b9d84ce8f0651aa713ae490f4990 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8029: d22cd438e6356bd7c2ee55436553cdcadd55193a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_138065v6: 128ccc5f71d7b9d84ce8f0651aa713ae490f4990 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/index.html
[-- Attachment #2: Type: text/html, Size: 6118 bytes --]
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH] drm/i915/psr: Implement WA to help reach PC10
2024-09-20 9:12 ` [PATCH] drm/i915/psr: Implement " Suraj Kandpal
@ 2024-09-20 11:45 ` Hogander, Jouni
2024-09-23 2:54 ` Kandpal, Suraj
0 siblings, 1 reply; 47+ messages in thread
From: Hogander, Jouni @ 2024-09-20 11:45 UTC (permalink / raw)
To: Kandpal, Suraj, intel-gfx@lists.freedesktop.org; +Cc: Shankar, Uma
On Fri, 2024-09-20 at 14:42 +0530, Suraj Kandpal wrote:
> To reach PC10 when PKG_C_LATENCY is configure we must do the
> following
> things
> 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> entered
> 2) Allow PSR2 deep sleep when DC5 can be entered
> 3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
> eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
> not happening.
One comment below related to PantherLake. Otherwise patch looks ok to
me.
>
> --v2
> -Switch condition and do an early return [Jani]
> -Do some checks in compute_config [Jani]
> -Do not use register reads as a method of checking states for
> DPKGC or delayed vblank [Jani]
> -Use another way to see is vblank interrupts are disabled or not
> [Jani]
>
> --v3
> -Use has_psr to check if psr can be enabled or not for dc5_entry cond
> [Uma]
> -Move the dc5 entry computation to psr_compute_config [Jouni]
> -No need to change sequence of enabled and activate,
> so dont make hsw_psr1_activate return anything [Jouni]
> -Use has_psr to stop psr1 activation [Jouni]
> -Use lineage no. in WA
> -Add the display ver restrictions for WA
>
> --v4
> -use more appropriate name for check_vblank_limit() [Jouni]
> -Cover the case for idle frames when dpkgc is not configured [Jouni]
> -Check psr only for edp [Jouni]
>
> --v5
> -move psr1 handling to plane update [Jouni]
> -add todo for cases when vblank is enabled when psr enabled [Jouni]
> -use intel_display instead of drm_i915_private
>
> --v6
> -check target_dc_state [Jouni]
> -fix condition in pre/post plane update [Jouni]
>
> --v7
> -fix has_psr condition [Uma]
> -fix typo in commit subject [Uma]
> -put psr1_wa check in its own helper [Uma]
> -fix the dc_entry check [Jouni]
> -use HAS_PSR() to cover two edp one with psr and one nonpsr [Jouni]
>
> WA: 22019444797
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 3 +
> drivers/gpu/drm/i915/display/intel_psr.c | 119
> +++++++++++++++++-
> 2 files changed, 121 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 3e694c1204db..2d790abee76e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1577,6 +1577,9 @@ struct intel_psr {
> #define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
>
> u32 debug;
> + bool is_dpkgc_configured;
> + bool is_dc5_entry_possible;
> + bool is_wa_delayed_vblank_limit;
> bool sink_support;
> bool source_support;
> bool enabled;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 5b355d0a3565..b882ff25fb92 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -26,6 +26,7 @@
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_damage_helper.h>
> #include <drm/drm_debugfs.h>
> +#include <drm/drm_vblank.h>
>
> #include "i915_drv.h"
> #include "i915_reg.h"
> @@ -895,6 +896,89 @@ static u8 psr_compute_idle_frames(struct
> intel_dp *intel_dp)
> return idle_frames;
> }
>
> +static bool
> +intel_psr_check_wa_delayed_vblank(const struct drm_display_mode
> *adjusted_mode)
> +{
> + return (adjusted_mode->crtc_vblank_start - adjusted_mode-
> >crtc_vdisplay) >= 6;
> +}
> +
> +/*
> + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> + * VRR is not enabled
> + */
> +static bool intel_psr_is_dpkgc_configured(struct intel_display
> *display,
> + struct intel_atomic_state
> *state)
> +{
> + struct intel_crtc *intel_crtc;
> + struct intel_crtc_state *crtc_state;
> + int i;
> +
> + if (DISPLAY_VER(display) < 20)
> + return false;
> +
> + for_each_new_intel_crtc_in_state(state, intel_crtc,
> crtc_state, i) {
> + if (!intel_crtc->active)
> + continue;
> +
> + if (crtc_state->vrr.enable)
> + return false;
> + }
> +
> + return true;
> +}
> +
> +static bool wa_22019444797_psr1_check(const struct intel_crtc_state
> *crtc_state,
> + struct intel_psr *psr)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> +
> + return DISPLAY_VER(display) == 20 && psr->is_dpkgc_configured
> &&
> + (psr->is_wa_delayed_vblank_limit || !psr-
> >is_dc5_entry_possible) &&
> + !crtc_state->has_sel_update && !crtc_state-
> >has_panel_replay;
> +}
> +
> +/*
> + * DC5 entry is only possible if vblank interrupt is disabled
> + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> + * enabled encoders.
> + */
> +static bool
> +intel_psr_is_dc5_entry_possible(struct intel_display *display,
> + struct intel_atomic_state *state)
> +{
> + struct intel_crtc *intel_crtc;
> + struct intel_crtc_state *crtc_state;
> + int i;
> +
> + if ((display->power.domains.target_dc_state &
> + DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
> + return false;
> +
> + for_each_new_intel_crtc_in_state(state, intel_crtc,
> crtc_state, i) {
> + struct drm_crtc *crtc = &intel_crtc->base;
> + struct drm_vblank_crtc *vblank;
> + struct intel_encoder *encoder;
> +
> + if (!intel_crtc->active)
> + continue;
> +
> + vblank = drm_crtc_vblank_crtc(crtc);
> +
> + if (vblank->enabled)
> + return false;
> +
> + if (!crtc_state->has_psr)
> + return false;
> +
> + for_each_encoder_on_crtc(display->drm, crtc, encoder)
> + if (encoder->type != INTEL_OUTPUT_EDP ||
> + !CAN_PSR(enc_to_intel_dp(encoder)))
> + return false;
> + }
> +
> + return true;
> +}
> +
> static void hsw_activate_psr1(struct intel_dp *intel_dp)
> {
> struct intel_display *display = to_intel_display(intel_dp);
> @@ -1007,7 +1091,15 @@ static void hsw_activate_psr2(struct intel_dp
> *intel_dp)
> u32 val = EDP_PSR2_ENABLE;
> u32 psr_val = 0;
>
> - val |=
> EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> + /*
> + * Wa_22019444797
> + * TODO: Disable idle frames when vblank gets enabled while
> + * PSR2 is enabled
> + */
> + if (DISPLAY_VER(dev_priv) != 20 ||
I think same Workaround is needed by PantherLake but only if stepping
is A0. You could have this here:
(DISPLAY_VER(display) != 20 && !IS_DISPLAY_VER_STEP(display, IP_VER(30,
0), STEP_A0, STEP_B0))
BR,
Jouni Högander
> + !intel_dp->psr.is_dpkgc_configured ||
> + intel_dp->psr.is_dc5_entry_possible)
> + val |=
> EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
>
> if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
> val |= EDP_SU_TRACK_ENABLE;
> @@ -2692,10 +2784,20 @@ void intel_psr_pre_plane_update(struct
> intel_atomic_state *state,
> const struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> struct intel_encoder *encoder;
> + bool dpkgc_configured = false, dc5_entry_possible = false;
> + bool wa_delayed_vblank_limit = false;
>
> if (!HAS_PSR(display))
> return;
>
> + if (DISPLAY_VER(display) == 20) {
> + dpkgc_configured =
> intel_psr_is_dpkgc_configured(display, state);
> + dc5_entry_possible =
> + intel_psr_is_dc5_entry_possible(display,
> state);
> + wa_delayed_vblank_limit =
> + intel_psr_check_wa_delayed_vblank(&new_crtc_s
> tate->hw.adjusted_mode);
> + }
> +
> for_each_intel_encoder_mask_with_psr(state->base.dev,
> encoder,
> old_crtc_state-
> >uapi.encoder_mask) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> @@ -2704,6 +2806,12 @@ void intel_psr_pre_plane_update(struct
> intel_atomic_state *state,
>
> mutex_lock(&psr->lock);
>
> + if (DISPLAY_VER(i915) == 20) {
> + psr->is_dpkgc_configured = dpkgc_configured;
> + psr->is_dc5_entry_possible =
> dc5_entry_possible;
> + psr->is_wa_delayed_vblank_limit =
> wa_delayed_vblank_limit;
> + }
> +
> /*
> * Reasons to disable:
> * - PSR disabled in new state
> @@ -2711,6 +2819,7 @@ void intel_psr_pre_plane_update(struct
> intel_atomic_state *state,
> * - Changing between PSR versions
> * - Region Early Transport changing
> * - Display WA #1136: skl, bxt
> + * - Display WA_22019444797
> */
> needs_to_disable |=
> intel_crtc_needs_modeset(new_crtc_state);
> needs_to_disable |= !new_crtc_state->has_psr;
> @@ -2720,6 +2829,8 @@ void intel_psr_pre_plane_update(struct
> intel_atomic_state *state,
> psr->su_region_et_enabled;
> needs_to_disable |= DISPLAY_VER(i915) < 11 &&
> new_crtc_state->wm_level_disabled;
> + /* TODO: Disable PSR1 when vblank gets enabled while
> PSR1 is enabled */
> + needs_to_disable |=
> wa_22019444797_psr1_check(new_crtc_state, psr);
>
> if (psr->enabled && needs_to_disable)
> intel_psr_disable_locked(intel_dp);
> @@ -2760,6 +2871,12 @@ void intel_psr_post_plane_update(struct
> intel_atomic_state *state,
> keep_disabled |= DISPLAY_VER(display) < 11 &&
> crtc_state->wm_level_disabled;
>
> + /*
> + * Wa_22019444797
> + * TODO: Disable PSR1 when vblank gets enabled while
> PSR1 is enabled
> + */
> + keep_disabled |=
> wa_22019444797_psr1_check(crtc_state, psr);
> +
> if (!psr->enabled && !keep_disabled)
> intel_psr_enable_locked(intel_dp,
> crtc_state);
> else if (psr->enabled && !crtc_state-
> >wm_level_disabled)
^ permalink raw reply [flat|nested] 47+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915/psr: Implment WA to help reach PC10 (rev6)
2024-09-02 5:02 [PATCH] drm/i915/psr: Implment WA to help reach PC10 Suraj Kandpal
` (10 preceding siblings ...)
2024-09-20 10:57 ` ✓ Fi.CI.BAT: success for drm/i915/psr: Implment WA to help reach PC10 (rev6) Patchwork
@ 2024-09-21 11:54 ` Patchwork
2024-09-27 18:54 ` ✓ Fi.CI.IGT: success " Patchwork
2024-09-28 16:12 ` Patchwork
13 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2024-09-21 11:54 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 79180 bytes --]
== Series Details ==
Series: drm/i915/psr: Implment WA to help reach PC10 (rev6)
URL : https://patchwork.freedesktop.org/series/138065/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_15441_full -> Patchwork_138065v6_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_138065v6_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_138065v6_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_138065v6_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_legacy@torture-bo:
- shard-dg2: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-6/igt@kms_cursor_legacy@torture-bo.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-2/igt@kms_cursor_legacy@torture-bo.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c:
- shard-dg1: NOTRUN -> [INCOMPLETE][3] +3 other tests incomplete
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d:
- shard-dg2: NOTRUN -> [INCOMPLETE][4] +1 other test incomplete
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d.html
Known issues
------------
Here are the changes found in Patchwork_138065v6_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@object-reloc-purge-cache:
- shard-dg1: NOTRUN -> [SKIP][5] ([i915#8411])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@api_intel_bb@object-reloc-purge-cache.html
* igt@drm_fdinfo@busy-check-all@bcs0:
- shard-dg1: NOTRUN -> [SKIP][6] ([i915#8414]) +18 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@drm_fdinfo@busy-check-all@bcs0.html
* igt@drm_fdinfo@virtual-busy-all:
- shard-dg2: NOTRUN -> [SKIP][7] ([i915#8414])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@drm_fdinfo@virtual-busy-all.html
* igt@gem_busy@semaphore:
- shard-dg1: NOTRUN -> [SKIP][8] ([i915#3936])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_busy@semaphore.html
* igt@gem_caching@reads:
- shard-mtlp: NOTRUN -> [SKIP][9] ([i915#4873])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@gem_caching@reads.html
* igt@gem_ccs@block-copy-compressed:
- shard-mtlp: NOTRUN -> [SKIP][10] ([i915#3555] / [i915#9323])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_ccs@block-copy-compressed.html
* igt@gem_close_race@multigpu-basic-process:
- shard-rkl: NOTRUN -> [SKIP][11] ([i915#7697])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@gem_close_race@multigpu-basic-process.html
- shard-dg1: NOTRUN -> [SKIP][12] ([i915#7697])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_ctx_persistence@heartbeat-hostile:
- shard-dg1: NOTRUN -> [SKIP][13] ([i915#8555]) +1 other test skip
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_ctx_persistence@heartbeat-hostile.html
* igt@gem_ctx_persistence@heartbeat-many:
- shard-mtlp: NOTRUN -> [SKIP][14] ([i915#8555])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_ctx_persistence@heartbeat-many.html
* igt@gem_ctx_persistence@hostile:
- shard-dg2: NOTRUN -> [FAIL][15] ([i915#11980])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@gem_ctx_persistence@hostile.html
- shard-tglu: [PASS][16] -> [FAIL][17] ([i915#11980])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-tglu-6/igt@gem_ctx_persistence@hostile.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-tglu-5/igt@gem_ctx_persistence@hostile.html
* igt@gem_ctx_sseu@engines:
- shard-dg2: NOTRUN -> [SKIP][18] ([i915#280])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_ctx_sseu@engines.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-mtlp: NOTRUN -> [SKIP][19] ([i915#280])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_eio@hibernate:
- shard-rkl: NOTRUN -> [ABORT][20] ([i915#7975] / [i915#8213])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-3/igt@gem_eio@hibernate.html
* igt@gem_eio@kms:
- shard-dg2: [PASS][21] -> [FAIL][22] ([i915#5784])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-8/igt@gem_eio@kms.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-10/igt@gem_eio@kms.html
* igt@gem_exec_balancer@bonded-dual:
- shard-mtlp: NOTRUN -> [SKIP][23] ([i915#4771])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_exec_balancer@bonded-dual.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-rkl: NOTRUN -> [SKIP][24] ([i915#4525])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_capture@capture:
- shard-mtlp: NOTRUN -> [FAIL][25] ([i915#11965]) +1 other test fail
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_exec_capture@capture.html
* igt@gem_exec_fair@basic-deadline:
- shard-rkl: [PASS][26] -> [FAIL][27] ([i915#2846])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-3/igt@gem_exec_fair@basic-deadline.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-rkl: [PASS][28] -> [FAIL][29] ([i915#2842])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-2/igt@gem_exec_fair@basic-none@vecs0.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace:
- shard-dg2: NOTRUN -> [SKIP][30] ([i915#3539])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_exec_fair@basic-pace.html
* igt@gem_exec_fair@basic-sync:
- shard-dg1: NOTRUN -> [SKIP][31] ([i915#3539]) +1 other test skip
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_exec_fair@basic-sync.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-dg1: NOTRUN -> [SKIP][32] ([i915#3539] / [i915#4852]) +1 other test skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_flush@basic-wb-rw-before-default:
- shard-dg2: NOTRUN -> [SKIP][33] ([i915#3539] / [i915#4852])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_exec_flush@basic-wb-rw-before-default.html
* igt@gem_exec_reloc@basic-cpu-read:
- shard-rkl: NOTRUN -> [SKIP][34] ([i915#3281]) +4 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@gem_exec_reloc@basic-cpu-read.html
* igt@gem_exec_reloc@basic-gtt-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][35] ([i915#3281]) +6 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@gem_exec_reloc@basic-gtt-noreloc.html
* igt@gem_exec_reloc@basic-wc-cpu-noreloc:
- shard-dg1: NOTRUN -> [SKIP][36] ([i915#3281]) +10 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@gem_exec_reloc@basic-wc-cpu-noreloc.html
* igt@gem_exec_reloc@basic-write-wc-active:
- shard-dg2: NOTRUN -> [SKIP][37] ([i915#3281]) +5 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_exec_reloc@basic-write-wc-active.html
* igt@gem_exec_schedule@preempt-queue:
- shard-dg1: NOTRUN -> [SKIP][38] ([i915#4812]) +2 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_exec_schedule@preempt-queue.html
* igt@gem_exec_schedule@preempt-queue-chain:
- shard-dg2: NOTRUN -> [SKIP][39] ([i915#4537] / [i915#4812])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_exec_schedule@preempt-queue-chain.html
* igt@gem_fence_thrash@bo-write-verify-none:
- shard-dg1: NOTRUN -> [SKIP][40] ([i915#4860]) +1 other test skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_fence_thrash@bo-write-verify-none.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-rkl: NOTRUN -> [SKIP][41] ([i915#4613]) +3 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@massive-random:
- shard-mtlp: NOTRUN -> [SKIP][42] ([i915#4613])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_lmem_swapping@massive-random.html
* igt@gem_mmap_gtt@basic:
- shard-dg2: NOTRUN -> [SKIP][43] ([i915#4077]) +2 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@gem_mmap_gtt@basic.html
* igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
- shard-mtlp: NOTRUN -> [SKIP][44] ([i915#4077]) +4 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
* igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-dg1: NOTRUN -> [SKIP][45] ([i915#4077]) +13 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
* igt@gem_mmap_wc@fault-concurrent:
- shard-mtlp: NOTRUN -> [SKIP][46] ([i915#4083]) +1 other test skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_mmap_wc@fault-concurrent.html
* igt@gem_mmap_wc@write-prefaulted:
- shard-dg2: NOTRUN -> [SKIP][47] ([i915#4083]) +3 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@gem_mmap_wc@write-prefaulted.html
* igt@gem_mmap_wc@write-read:
- shard-dg1: NOTRUN -> [SKIP][48] ([i915#4083]) +4 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_mmap_wc@write-read.html
* igt@gem_pread@bench:
- shard-rkl: NOTRUN -> [SKIP][49] ([i915#3282])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@gem_pread@bench.html
- shard-dg1: NOTRUN -> [SKIP][50] ([i915#3282]) +1 other test skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_pread@bench.html
* igt@gem_pxp@create-regular-context-2:
- shard-rkl: NOTRUN -> [SKIP][51] ([i915#4270]) +2 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@gem_pxp@create-regular-context-2.html
* igt@gem_pxp@display-protected-crc:
- shard-dg2: NOTRUN -> [SKIP][52] ([i915#4270])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@gem_pxp@display-protected-crc.html
* igt@gem_pxp@reject-modify-context-protection-off-1:
- shard-mtlp: NOTRUN -> [SKIP][53] ([i915#4270])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_pxp@reject-modify-context-protection-off-1.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-dg1: NOTRUN -> [SKIP][54] ([i915#4270]) +4 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_readwrite@beyond-eob:
- shard-mtlp: NOTRUN -> [SKIP][55] ([i915#3282]) +2 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_readwrite@beyond-eob.html
* igt@gem_readwrite@write-bad-handle:
- shard-dg2: NOTRUN -> [SKIP][56] ([i915#3282]) +2 other tests skip
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_readwrite@write-bad-handle.html
* igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:
- shard-mtlp: NOTRUN -> [SKIP][57] ([i915#8428]) +2 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html
* igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled:
- shard-dg2: NOTRUN -> [SKIP][58] ([i915#5190] / [i915#8428]) +3 other tests skip
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled.html
* igt@gem_softpin@evict-snoop:
- shard-mtlp: NOTRUN -> [SKIP][59] ([i915#4885])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_softpin@evict-snoop.html
* igt@gem_softpin@evict-snoop-interruptible:
- shard-dg1: NOTRUN -> [SKIP][60] ([i915#4885])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_softpin@evict-snoop-interruptible.html
* igt@gem_tiled_pread_pwrite:
- shard-dg1: NOTRUN -> [SKIP][61] ([i915#4079])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@gem_tiled_pread_pwrite.html
* igt@gem_userptr_blits@coherency-unsync:
- shard-dg2: NOTRUN -> [SKIP][62] ([i915#3297])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_userptr_blits@coherency-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-dg2: NOTRUN -> [SKIP][63] ([i915#3297] / [i915#4880])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@readonly-pwrite-unsync:
- shard-mtlp: NOTRUN -> [SKIP][64] ([i915#3297]) +1 other test skip
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_userptr_blits@readonly-pwrite-unsync.html
* igt@gem_userptr_blits@relocations:
- shard-dg2: NOTRUN -> [SKIP][65] ([i915#3281] / [i915#3297])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_userptr_blits@relocations.html
* igt@gen9_exec_parse@allowed-single:
- shard-rkl: NOTRUN -> [SKIP][66] ([i915#2527]) +2 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@gen9_exec_parse@allowed-single.html
- shard-glk: NOTRUN -> [ABORT][67] ([i915#5566])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-glk7/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-dg1: NOTRUN -> [SKIP][68] ([i915#2527]) +5 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@gen9_exec_parse@bb-start-cmd.html
* igt@gen9_exec_parse@bb-start-far:
- shard-dg2: NOTRUN -> [SKIP][69] ([i915#2856]) +1 other test skip
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gen9_exec_parse@bb-start-far.html
* igt@gen9_exec_parse@valid-registers:
- shard-mtlp: NOTRUN -> [SKIP][70] ([i915#2856])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gen9_exec_parse@valid-registers.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg2: [PASS][71] -> [ABORT][72] ([i915#9820])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-2/igt@i915_module_load@reload-with-fault-injection.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-10/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pipe_stress@stress-xrgb8888-ytiled:
- shard-mtlp: NOTRUN -> [SKIP][73] ([i915#8436])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html
* igt@i915_pm_freq_mult@media-freq@gt0:
- shard-rkl: NOTRUN -> [SKIP][74] ([i915#6590]) +1 other test skip
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@i915_pm_freq_mult@media-freq@gt0.html
* igt@i915_pm_rps@basic-api:
- shard-dg2: NOTRUN -> [SKIP][75] ([i915#11681] / [i915#6621])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@i915_pm_rps@basic-api.html
* igt@i915_pm_rps@thresholds-idle:
- shard-dg1: NOTRUN -> [SKIP][76] ([i915#11681])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@i915_pm_rps@thresholds-idle.html
* igt@i915_pm_rps@thresholds-idle-park:
- shard-mtlp: NOTRUN -> [SKIP][77] ([i915#11681])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@i915_pm_rps@thresholds-idle-park.html
* igt@i915_query@hwconfig_table:
- shard-dg1: NOTRUN -> [SKIP][78] ([i915#6245])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@i915_query@hwconfig_table.html
* igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- shard-dg1: NOTRUN -> [SKIP][79] ([i915#4212])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc-ccs:
- shard-dg1: NOTRUN -> [SKIP][80] ([i915#8709]) +7 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc-ccs.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-mtlp: NOTRUN -> [SKIP][81] ([i915#3555])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-snb: [PASS][82] -> [FAIL][83] ([i915#5956]) +1 other test fail
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-snb4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-snb5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-0:
- shard-dg1: NOTRUN -> [SKIP][84] ([i915#4538] / [i915#5286]) +3 other tests skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-addfb:
- shard-dg1: NOTRUN -> [SKIP][85] ([i915#5286]) +2 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_big_fb@4-tiled-addfb.html
* igt@kms_big_fb@4-tiled-addfb-size-overflow:
- shard-rkl: NOTRUN -> [SKIP][86] ([i915#5286]) +2 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_big_fb@4-tiled-addfb-size-overflow.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][87] ([i915#4538] / [i915#5190]) +4 other tests skip
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][88] ([i915#3638]) +1 other test skip
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
- shard-dg1: NOTRUN -> [SKIP][89] ([i915#3638]) +3 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][90] +13 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-dg2: NOTRUN -> [SKIP][91] ([i915#5190])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0:
- shard-dg1: NOTRUN -> [SKIP][92] ([i915#4538]) +6 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-mtlp: NOTRUN -> [SKIP][93] +11 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][94] ([i915#10307] / [i915#10434] / [i915#6095]) +6 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-2/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][95] ([i915#6095]) +107 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-4.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][96] ([i915#6095]) +93 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][97] ([i915#10307] / [i915#6095]) +173 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
- shard-mtlp: NOTRUN -> [SKIP][98] ([i915#12042])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][99] ([i915#6095]) +19 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-edp-1.html
* igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
- shard-dg1: NOTRUN -> [SKIP][100] ([i915#12042])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-rkl: NOTRUN -> [SKIP][101] ([i915#3742])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_cdclk@mode-transition-all-outputs.html
- shard-dg1: NOTRUN -> [SKIP][102] ([i915#3742])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_chamelium_frames@hdmi-cmp-planar-formats:
- shard-dg2: NOTRUN -> [SKIP][103] ([i915#7828]) +4 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html
* igt@kms_chamelium_hpd@dp-hpd-for-each-pipe:
- shard-mtlp: NOTRUN -> [SKIP][104] ([i915#7828]) +3 other tests skip
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_chamelium_hpd@dp-hpd-for-each-pipe.html
* igt@kms_chamelium_hpd@vga-hpd-fast:
- shard-rkl: NOTRUN -> [SKIP][105] ([i915#7828]) +5 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_chamelium_hpd@vga-hpd-fast.html
- shard-dg1: NOTRUN -> [SKIP][106] ([i915#7828]) +10 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_chamelium_hpd@vga-hpd-fast.html
* igt@kms_content_protection@content-type-change:
- shard-dg1: NOTRUN -> [SKIP][107] ([i915#9424])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_content_protection@content-type-change.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-dg1: NOTRUN -> [SKIP][108] ([i915#3299]) +1 other test skip
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@legacy:
- shard-dg2: NOTRUN -> [SKIP][109] ([i915#7118] / [i915#9424])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@mei-interface:
- shard-mtlp: NOTRUN -> [SKIP][110] ([i915#8063] / [i915#9433])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@srm:
- shard-rkl: NOTRUN -> [SKIP][111] ([i915#7118])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_content_protection@srm.html
- shard-dg1: NOTRUN -> [SKIP][112] ([i915#7116])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_content_protection@srm.html
* igt@kms_content_protection@uevent@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [FAIL][113] ([i915#1339] / [i915#7173])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_content_protection@uevent@pipe-a-dp-4.html
* igt@kms_cursor_crc@cursor-offscreen-512x170:
- shard-mtlp: NOTRUN -> [SKIP][114] ([i915#3359])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_cursor_crc@cursor-offscreen-512x170.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-dg2: NOTRUN -> [SKIP][115] ([i915#11453])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-6/igt@kms_cursor_crc@cursor-onscreen-512x170.html
- shard-dg1: NOTRUN -> [SKIP][116] ([i915#11453]) +1 other test skip
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x10:
- shard-mtlp: NOTRUN -> [SKIP][117] ([i915#3555] / [i915#8814]) +2 other tests skip
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-rkl: NOTRUN -> [SKIP][118] ([i915#11453])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-mtlp: NOTRUN -> [SKIP][119] ([i915#4213])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-rkl: NOTRUN -> [SKIP][120] ([i915#4103])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
- shard-dg1: NOTRUN -> [SKIP][121] ([i915#4103] / [i915#4213])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
- shard-mtlp: NOTRUN -> [SKIP][122] ([i915#9809])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@torture-bo@pipe-a:
- shard-snb: [PASS][123] -> [DMESG-WARN][124] ([i915#10166]) +1 other test dmesg-warn
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-snb2/igt@kms_cursor_legacy@torture-bo@pipe-a.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-snb6/igt@kms_cursor_legacy@torture-bo@pipe-a.html
- shard-dg2: [PASS][125] -> [DMESG-WARN][126] ([i915#10166])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-6/igt@kms_cursor_legacy@torture-bo@pipe-a.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-2/igt@kms_cursor_legacy@torture-bo@pipe-a.html
* igt@kms_display_modes@extended-mode-basic:
- shard-mtlp: NOTRUN -> [SKIP][127] ([i915#3555] / [i915#8827])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_display_modes@mst-extended-mode-negative:
- shard-dg1: NOTRUN -> [SKIP][128] ([i915#8588])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_display_modes@mst-extended-mode-negative.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][129] ([i915#3804])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_dither@fb-8bpc-vs-panel-8bpc:
- shard-dg2: [PASS][130] -> [SKIP][131] ([i915#3555])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-11/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-1/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
* igt@kms_dp_aux_dev:
- shard-dg1: NOTRUN -> [SKIP][132] ([i915#1257])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@kms_dp_aux_dev.html
* igt@kms_draw_crc@draw-method-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][133] ([i915#8812])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_draw_crc@draw-method-mmap-gtt.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-dg2: NOTRUN -> [SKIP][134] ([i915#3840] / [i915#9688])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-fractional-bpp-with-bpc:
- shard-dg2: NOTRUN -> [SKIP][135] ([i915#3840])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-mtlp: NOTRUN -> [SKIP][136] ([i915#3555] / [i915#3840])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_feature_discovery@display-2x:
- shard-rkl: NOTRUN -> [SKIP][137] ([i915#1839])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_feature_discovery@display-2x.html
- shard-dg1: NOTRUN -> [SKIP][138] ([i915#1839])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_feature_discovery@display-2x.html
* igt@kms_fence_pin_leak:
- shard-dg1: NOTRUN -> [SKIP][139] ([i915#4881])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_fence_pin_leak.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-dg1: NOTRUN -> [SKIP][140] ([i915#8381])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@2x-flip-vs-panning-interruptible:
- shard-dg2: NOTRUN -> [SKIP][141] +6 other tests skip
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_flip@2x-flip-vs-panning-interruptible.html
* igt@kms_flip@2x-flip-vs-rmfb:
- shard-mtlp: NOTRUN -> [SKIP][142] ([i915#3637]) +5 other tests skip
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_flip@2x-flip-vs-rmfb.html
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
- shard-dg1: NOTRUN -> [SKIP][143] ([i915#9934]) +3 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-fences-interruptible:
- shard-dg2: NOTRUN -> [SKIP][144] ([i915#8381])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_flip@flip-vs-fences-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling:
- shard-mtlp: NOTRUN -> [SKIP][145] ([i915#2672] / [i915#3555] / [i915#8813]) +2 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][146] ([i915#2672]) +1 other test skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
- shard-dg1: NOTRUN -> [SKIP][147] ([i915#2587] / [i915#2672] / [i915#3555]) +2 other tests skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][148] ([i915#2672]) +1 other test skip
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
- shard-dg1: NOTRUN -> [SKIP][149] ([i915#2587] / [i915#2672]) +3 other tests skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
- shard-dg2: NOTRUN -> [SKIP][150] ([i915#2672] / [i915#3555] / [i915#5190])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
- shard-rkl: NOTRUN -> [SKIP][151] ([i915#2672] / [i915#3555]) +1 other test skip
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
- shard-dg1: NOTRUN -> [SKIP][152] ([i915#2672] / [i915#3555])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
- shard-dg2: NOTRUN -> [SKIP][153] ([i915#2672] / [i915#3555]) +1 other test skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][154] ([i915#2672]) +2 other tests skip
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][155] ([i915#2672] / [i915#3555])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][156] ([i915#8708]) +9 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt:
- shard-mtlp: NOTRUN -> [SKIP][157] ([i915#1825]) +13 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- shard-dg1: NOTRUN -> [SKIP][158] ([i915#5439])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][159] ([i915#1825]) +16 other tests skip
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff:
- shard-dg1: NOTRUN -> [SKIP][160] +53 other tests skip
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move:
- shard-dg2: NOTRUN -> [SKIP][161] ([i915#5354]) +18 other tests skip
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
- shard-dg1: NOTRUN -> [SKIP][162] ([i915#3458]) +15 other tests skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][163] ([i915#3023]) +13 other tests skip
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][164] ([i915#8708]) +29 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][165] ([i915#3458]) +3 other tests skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][166] ([i915#8708]) +3 other tests skip
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_hdr@static-swap:
- shard-dg2: [PASS][167] -> [SKIP][168] ([i915#3555] / [i915#8228])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-11/igt@kms_hdr@static-swap.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-3/igt@kms_hdr@static-swap.html
- shard-mtlp: NOTRUN -> [SKIP][169] ([i915#3555] / [i915#8228])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_hdr@static-swap.html
* igt@kms_hdr@static-toggle:
- shard-dg2: NOTRUN -> [SKIP][170] ([i915#3555] / [i915#8228]) +1 other test skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-6/igt@kms_hdr@static-toggle.html
- shard-dg1: NOTRUN -> [SKIP][171] ([i915#3555] / [i915#8228]) +2 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_hdr@static-toggle.html
* igt@kms_panel_fitting@legacy:
- shard-dg1: NOTRUN -> [SKIP][172] ([i915#6301])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_panel_fitting@legacy.html
* igt@kms_plane_lowres@tiling-y:
- shard-mtlp: NOTRUN -> [SKIP][173] ([i915#3555] / [i915#8821])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_plane_lowres@tiling-y.html
* igt@kms_plane_lowres@tiling-yf:
- shard-rkl: NOTRUN -> [SKIP][174] ([i915#3555]) +2 other tests skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_plane_lowres@tiling-yf.html
- shard-dg1: NOTRUN -> [SKIP][175] ([i915#3555]) +6 other tests skip
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [FAIL][176] ([i915#8292])
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25:
- shard-dg2: NOTRUN -> [SKIP][177] ([i915#6953] / [i915#9423]) +2 other tests skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_plane_scaling@planes-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d:
- shard-dg2: NOTRUN -> [SKIP][178] ([i915#12247]) +7 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25:
- shard-dg1: NOTRUN -> [SKIP][179] ([i915#6953])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b:
- shard-dg1: NOTRUN -> [SKIP][180] ([i915#12247]) +8 other tests skip
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b.html
* igt@kms_pm_dc@dc6-psr:
- shard-dg1: NOTRUN -> [SKIP][181] ([i915#9685])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-rkl: [PASS][182] -> [SKIP][183] ([i915#9340])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-4/igt@kms_pm_lpsp@kms-lpsp.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-6/igt@kms_pm_lpsp@kms-lpsp.html
- shard-dg1: NOTRUN -> [SKIP][184] ([i915#9340])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_lpsp@screens-disabled:
- shard-rkl: NOTRUN -> [SKIP][185] ([i915#8430])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_pm_lpsp@screens-disabled.html
- shard-dg1: NOTRUN -> [SKIP][186] ([i915#8430])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_pm_lpsp@screens-disabled.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-rkl: [PASS][187] -> [SKIP][188] ([i915#9519]) +2 other tests skip
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-dg2: [PASS][189] -> [SKIP][190] ([i915#9519])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-3/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_prime@basic-crc-hybrid:
- shard-dg1: NOTRUN -> [SKIP][191] ([i915#6524]) +2 other tests skip
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-dg2: NOTRUN -> [SKIP][192] ([i915#11520]) +2 other tests skip
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-overlay-plane-update-sf-dmg-area:
- shard-dg1: NOTRUN -> [SKIP][193] ([i915#11520]) +2 other tests skip
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_psr2_sf@fbc-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area@psr2-pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][194] ([i915#9808]) +2 other tests skip
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area@psr2-pipe-a-edp-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-rkl: NOTRUN -> [SKIP][195] ([i915#11520]) +2 other tests skip
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr2_su@page_flip-p010:
- shard-rkl: NOTRUN -> [SKIP][196] ([i915#9683])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_psr2_su@page_flip-p010.html
- shard-dg1: NOTRUN -> [SKIP][197] ([i915#9683])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-dg2: NOTRUN -> [SKIP][198] ([i915#9683])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-pr-primary-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][199] ([i915#1072] / [i915#9673] / [i915#9732]) +4 other tests skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_psr@fbc-pr-primary-mmap-gtt.html
* igt@kms_psr@fbc-psr2-sprite-plane-onoff:
- shard-mtlp: NOTRUN -> [SKIP][200] ([i915#9688]) +10 other tests skip
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_psr@fbc-psr2-sprite-plane-onoff.html
* igt@kms_psr@psr-sprite-plane-move:
- shard-rkl: NOTRUN -> [SKIP][201] ([i915#1072] / [i915#9732]) +12 other tests skip
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_psr@psr-sprite-plane-move.html
* igt@kms_psr@psr2-cursor-plane-move:
- shard-dg2: NOTRUN -> [SKIP][202] ([i915#1072] / [i915#9732]) +5 other tests skip
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_psr@psr2-cursor-plane-move.html
* igt@kms_psr@psr2-sprite-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][203] ([i915#1072] / [i915#9732]) +24 other tests skip
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_psr@psr2-sprite-mmap-gtt.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
- shard-dg1: NOTRUN -> [SKIP][204] ([i915#5289])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-dg2: NOTRUN -> [SKIP][205] ([i915#11131] / [i915#5190])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-rkl: NOTRUN -> [SKIP][206] ([i915#5289]) +1 other test skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-mtlp: NOTRUN -> [SKIP][207] ([i915#4235])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-dg2: NOTRUN -> [SKIP][208] ([i915#3555]) +1 other test skip
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_setmode@clone-exclusive-crtc.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-mtlp: NOTRUN -> [SKIP][209] ([i915#3555] / [i915#8809])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
* igt@kms_sysfs_edid_timing:
- shard-dg2: [PASS][210] -> [FAIL][211] ([IGT#2])
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-11/igt@kms_sysfs_edid_timing.html
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-1/igt@kms_sysfs_edid_timing.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-dg1: NOTRUN -> [SKIP][212] ([i915#8623])
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_vrr@max-min:
- shard-dg2: NOTRUN -> [SKIP][213] ([i915#9906])
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_vrr@max-min.html
* igt@kms_vrr@seamless-rr-switch-virtual:
- shard-rkl: NOTRUN -> [SKIP][214] ([i915#9906])
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_vrr@seamless-rr-switch-virtual.html
- shard-dg1: NOTRUN -> [SKIP][215] ([i915#9906])
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_vrr@seamless-rr-switch-virtual.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-dg1: NOTRUN -> [SKIP][216] ([i915#2437]) +1 other test skip
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_writeback@writeback-invalid-parameters.html
- shard-rkl: NOTRUN -> [SKIP][217] ([i915#2437])
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_writeback@writeback-invalid-parameters.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-mtlp: NOTRUN -> [SKIP][218] ([i915#2437] / [i915#9412])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@mi-rpc:
- shard-mtlp: NOTRUN -> [SKIP][219] ([i915#2434])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@perf@mi-rpc.html
* igt@perf@unprivileged-single-ctx-counters:
- shard-dg1: NOTRUN -> [SKIP][220] ([i915#2433])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@perf@unprivileged-single-ctx-counters.html
* igt@perf_pmu@rc6@other-idle-gt0:
- shard-rkl: NOTRUN -> [SKIP][221] ([i915#8516])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@perf_pmu@rc6@other-idle-gt0.html
- shard-dg1: NOTRUN -> [SKIP][222] ([i915#8516])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@perf_pmu@rc6@other-idle-gt0.html
* igt@prime_vgem@basic-read:
- shard-mtlp: NOTRUN -> [SKIP][223] ([i915#3708])
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-write:
- shard-dg1: NOTRUN -> [SKIP][224] ([i915#3708]) +1 other test skip
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@prime_vgem@basic-write.html
* igt@prime_vgem@fence-write-hang:
- shard-rkl: NOTRUN -> [SKIP][225] ([i915#3708])
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@prime_vgem@fence-write-hang.html
* igt@sriov_basic@bind-unbind-vf:
- shard-rkl: NOTRUN -> [SKIP][226] ([i915#9917]) +1 other test skip
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@sriov_basic@bind-unbind-vf.html
- shard-dg1: NOTRUN -> [SKIP][227] ([i915#9917]) +1 other test skip
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@sriov_basic@bind-unbind-vf.html
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-check-all:
- shard-rkl: [FAIL][228] ([i915#12179]) -> [PASS][229]
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-3/igt@drm_fdinfo@most-busy-check-all.html
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-2/igt@drm_fdinfo@most-busy-check-all.html
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [FAIL][230] ([i915#7742]) -> [PASS][231]
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-3/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-2/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@gem_ctx_engines@invalid-engines:
- shard-tglu: [FAIL][232] ([i915#12027]) -> [PASS][233]
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-tglu-5/igt@gem_ctx_engines@invalid-engines.html
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-tglu-6/igt@gem_ctx_engines@invalid-engines.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0:
- shard-dg1: [FAIL][234] ([i915#3591]) -> [PASS][235] +1 other test pass
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
* igt@kms_atomic_transition@modeset-transition:
- shard-glk: [FAIL][236] ([i915#12238]) -> [PASS][237]
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-glk8/igt@kms_atomic_transition@modeset-transition.html
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-glk5/igt@kms_atomic_transition@modeset-transition.html
* igt@kms_atomic_transition@modeset-transition@2x-outputs:
- shard-glk: [FAIL][238] ([i915#11859]) -> [PASS][239]
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-glk8/igt@kms_atomic_transition@modeset-transition@2x-outputs.html
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-glk5/igt@kms_atomic_transition@modeset-transition@2x-outputs.html
* igt@kms_cursor_legacy@torture-bo:
- shard-tglu: [DMESG-WARN][240] ([i915#10166] / [i915#1982]) -> [PASS][241]
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-tglu-9/igt@kms_cursor_legacy@torture-bo.html
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-tglu-8/igt@kms_cursor_legacy@torture-bo.html
* igt@kms_cursor_legacy@torture-bo@pipe-a:
- shard-tglu: [DMESG-WARN][242] ([i915#10166]) -> [PASS][243]
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-tglu-9/igt@kms_cursor_legacy@torture-bo@pipe-a.html
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-tglu-8/igt@kms_cursor_legacy@torture-bo@pipe-a.html
* igt@kms_dp_aux_dev:
- shard-dg2: [SKIP][244] ([i915#1257]) -> [PASS][245]
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-3/igt@kms_dp_aux_dev.html
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_dp_aux_dev.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt:
- shard-snb: [SKIP][246] -> [PASS][247]
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-snb4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-snb5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-dg2: [SKIP][248] ([i915#9340]) -> [PASS][249]
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-6/igt@kms_pm_lpsp@kms-lpsp.html
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-2/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-rkl: [SKIP][250] ([i915#9519]) -> [PASS][251] +1 other test pass
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-5/igt@kms_pm_rpm@dpms-lpsp.html
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-2/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-dg2: [SKIP][252] ([i915#9519]) -> [PASS][253]
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-10/igt@kms_pm_rpm@modeset-non-lpsp.html
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-3/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_vblank@ts-continuation-modeset-hang:
- shard-dg2: [INCOMPLETE][254] -> [PASS][255]
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-7/igt@kms_vblank@ts-continuation-modeset-hang.html
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-3/igt@kms_vblank@ts-continuation-modeset-hang.html
#### Warnings ####
* igt@gem_exec_fair@basic-pace-solo:
- shard-glk: [FAIL][256] -> [FAIL][257] ([i915#2842])
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-glk5/igt@gem_exec_fair@basic-pace-solo.html
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-glk6/igt@gem_exec_fair@basic-pace-solo.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-rkl: [FAIL][258] ([i915#2876]) -> [FAIL][259] ([i915#2842])
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-2/igt@gem_exec_fair@basic-pace@rcs0.html
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_lmem_swapping@smem-oom:
- shard-dg2: [DMESG-WARN][260] ([i915#5493]) -> [TIMEOUT][261] ([i915#5493])
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-1/igt@gem_lmem_swapping@smem-oom.html
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-6/igt@gem_lmem_swapping@smem-oom.html
- shard-dg1: [WARN][262] -> [TIMEOUT][263] ([i915#5493])
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg1-17/igt@gem_lmem_swapping@smem-oom.html
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@gem_lmem_swapping@smem-oom.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [CRASH][264] ([i915#5493]) -> [TIMEOUT][265] ([i915#5493])
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-1/igt@gem_lmem_swapping@smem-oom@lmem0.html
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-6/igt@gem_lmem_swapping@smem-oom@lmem0.html
- shard-dg1: [CRASH][266] ([i915#5493]) -> [TIMEOUT][267] ([i915#5493])
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg1-17/igt@gem_lmem_swapping@smem-oom@lmem0.html
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@i915_selftest@mock:
- shard-glk: [DMESG-WARN][268] ([i915#9311]) -> [DMESG-WARN][269] ([i915#1982] / [i915#9311])
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-glk1/igt@i915_selftest@mock.html
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-glk9/igt@i915_selftest@mock.html
- shard-dg1: [DMESG-WARN][270] ([i915#9311]) -> [DMESG-WARN][271] ([i915#1982] / [i915#9311])
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg1-16/igt@i915_selftest@mock.html
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@i915_selftest@mock.html
* igt@kms_content_protection@lic-type-0:
- shard-dg2: [TIMEOUT][272] ([i915#7173]) -> [SKIP][273] ([i915#9424])
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-11/igt@kms_content_protection@lic-type-0.html
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-1/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@uevent:
- shard-dg2: [SKIP][274] ([i915#7118] / [i915#9424]) -> [FAIL][275] ([i915#1339] / [i915#7173])
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-6/igt@kms_content_protection@uevent.html
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x170:
- shard-dg2: [SKIP][276] ([i915#11453]) -> [SKIP][277] ([i915#11453] / [i915#3359])
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-2/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-dg2: [SKIP][278] ([i915#11453] / [i915#3359]) -> [SKIP][279] ([i915#11453])
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-11/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-1/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][280] ([i915#4070] / [i915#4816]) -> [SKIP][281] ([i915#4816])
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pm_dc@dc9-dpms:
- shard-rkl: [SKIP][282] ([i915#3361]) -> [SKIP][283] ([i915#4281])
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-3/igt@kms_pm_dc@dc9-dpms.html
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_psr@fbc-psr-cursor-plane-move:
- shard-dg2: [SKIP][284] ([i915#1072] / [i915#9732]) -> [SKIP][285] ([i915#1072] / [i915#9673] / [i915#9732]) +15 other tests skip
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-2/igt@kms_psr@fbc-psr-cursor-plane-move.html
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_psr@fbc-psr-cursor-plane-move.html
* igt@kms_psr@fbc-psr-primary-page-flip:
- shard-dg2: [SKIP][286] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][287] ([i915#1072] / [i915#9732]) +9 other tests skip
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-11/igt@kms_psr@fbc-psr-primary-page-flip.html
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-1/igt@kms_psr@fbc-psr-primary-page-flip.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
- shard-dg2: [SKIP][288] ([i915#11131] / [i915#5190]) -> [SKIP][289] ([i915#11131] / [i915#4235] / [i915#5190])
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-2/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-dg2: [SKIP][290] ([i915#11131] / [i915#4235]) -> [SKIP][291] ([i915#11131])
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-11/igt@kms_rotation_crc@sprite-rotation-90.html
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-3/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: [FAIL][292] ([i915#7484]) -> [FAIL][293] ([i915#9100]) +1 other test fail
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-1/igt@perf@non-zero-reason@0-rcs0.html
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-2/igt@perf@non-zero-reason@0-rcs0.html
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[i915#10166]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10166
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#11131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11131
[i915#11453]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11453
[i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#11859]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11859
[i915#11965]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11965
[i915#11980]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11980
[i915#12027]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12027
[i915#12042]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12042
[i915#12179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12179
[i915#12238]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12238
[i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
[i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
[i915#1339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1339
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#2433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#2876]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2876
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
[i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#3936]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3936
[i915#4070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4873
[i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4881
[i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
[i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
[i915#5566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
[i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6245]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6245
[i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590
[i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
[i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
[i915#7484]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7484
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
[i915#8063]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8063
[i915#8213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8292]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8292
[i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
[i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
[i915#8436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8436
[i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
[i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
[i915#8588]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8588
[i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
[i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
[i915#8812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8812
[i915#8813]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8813
[i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
[i915#8821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8821
[i915#8827]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8827
[i915#9100]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9100
[i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9808
[i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
[i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_15441 -> Patchwork_138065v6
CI-20190529: 20190529
CI_DRM_15441: 128ccc5f71d7b9d84ce8f0651aa713ae490f4990 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8029: d22cd438e6356bd7c2ee55436553cdcadd55193a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_138065v6: 128ccc5f71d7b9d84ce8f0651aa713ae490f4990 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/index.html
[-- Attachment #2: Type: text/html, Size: 98421 bytes --]
^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [PATCH] drm/i915/psr: Implement WA to help reach PC10
2024-09-20 11:45 ` Hogander, Jouni
@ 2024-09-23 2:54 ` Kandpal, Suraj
2024-09-23 10:23 ` Shankar, Uma
0 siblings, 1 reply; 47+ messages in thread
From: Kandpal, Suraj @ 2024-09-23 2:54 UTC (permalink / raw)
To: Hogander, Jouni, intel-gfx@lists.freedesktop.org, Shankar, Uma
> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Friday, September 20, 2024 5:16 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [PATCH] drm/i915/psr: Implement WA to help reach PC10
>
> On Fri, 2024-09-20 at 14:42 +0530, Suraj Kandpal wrote:
> > To reach PC10 when PKG_C_LATENCY is configure we must do the
> following
> > things
> > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> > entered
> > 2) Allow PSR2 deep sleep when DC5 can be entered
> > 3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
> > eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
> > not happening.
>
> One comment below related to PantherLake. Otherwise patch looks ok to
> me.
>
>
> >
> > --v2
> > -Switch condition and do an early return [Jani] -Do some checks in
> > compute_config [Jani] -Do not use register reads as a method of
> > checking states for DPKGC or delayed vblank [Jani] -Use another way to
> > see is vblank interrupts are disabled or not [Jani]
> >
> > --v3
> > -Use has_psr to check if psr can be enabled or not for dc5_entry cond
> > [Uma] -Move the dc5 entry computation to psr_compute_config [Jouni]
> > -No need to change sequence of enabled and activate, so dont make
> > hsw_psr1_activate return anything [Jouni] -Use has_psr to stop psr1
> > activation [Jouni] -Use lineage no. in WA -Add the display ver
> > restrictions for WA
> >
> > --v4
> > -use more appropriate name for check_vblank_limit() [Jouni] -Cover the
> > case for idle frames when dpkgc is not configured [Jouni] -Check psr
> > only for edp [Jouni]
> >
> > --v5
> > -move psr1 handling to plane update [Jouni] -add todo for cases when
> > vblank is enabled when psr enabled [Jouni] -use intel_display instead
> > of drm_i915_private
> >
> > --v6
> > -check target_dc_state [Jouni]
> > -fix condition in pre/post plane update [Jouni]
> >
> > --v7
> > -fix has_psr condition [Uma]
> > -fix typo in commit subject [Uma]
> > -put psr1_wa check in its own helper [Uma] -fix the dc_entry check
> > [Jouni] -use HAS_PSR() to cover two edp one with psr and one nonpsr
> > [Jouni]
> >
> > WA: 22019444797
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > .../drm/i915/display/intel_display_types.h | 3 +
> > drivers/gpu/drm/i915/display/intel_psr.c | 119
> > +++++++++++++++++-
> > 2 files changed, 121 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 3e694c1204db..2d790abee76e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1577,6 +1577,9 @@ struct intel_psr {
> > #define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
> >
> > u32 debug;
> > + bool is_dpkgc_configured;
> > + bool is_dc5_entry_possible;
> > + bool is_wa_delayed_vblank_limit;
> > bool sink_support;
> > bool source_support;
> > bool enabled;
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 5b355d0a3565..b882ff25fb92 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -26,6 +26,7 @@
> > #include <drm/drm_atomic_helper.h>
> > #include <drm/drm_damage_helper.h>
> > #include <drm/drm_debugfs.h>
> > +#include <drm/drm_vblank.h>
> >
> > #include "i915_drv.h"
> > #include "i915_reg.h"
> > @@ -895,6 +896,89 @@ static u8 psr_compute_idle_frames(struct
> intel_dp
> > *intel_dp)
> > return idle_frames;
> > }
> >
> > +static bool
> > +intel_psr_check_wa_delayed_vblank(const struct drm_display_mode
> > *adjusted_mode)
> > +{
> > + return (adjusted_mode->crtc_vblank_start - adjusted_mode-
> > >crtc_vdisplay) >= 6;
> > +}
> > +
> > +/*
> > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> > + * VRR is not enabled
> > + */
> > +static bool intel_psr_is_dpkgc_configured(struct intel_display
> > *display,
> > + struct intel_atomic_state
> > *state)
> > +{
> > + struct intel_crtc *intel_crtc;
> > + struct intel_crtc_state *crtc_state;
> > + int i;
> > +
> > + if (DISPLAY_VER(display) < 20)
> > + return false;
> > +
> > + for_each_new_intel_crtc_in_state(state, intel_crtc,
> > crtc_state, i) {
> > + if (!intel_crtc->active)
> > + continue;
> > +
> > + if (crtc_state->vrr.enable)
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > +static bool wa_22019444797_psr1_check(const struct intel_crtc_state
> > *crtc_state,
> > + struct intel_psr *psr) {
> > + struct intel_display *display = to_intel_display(crtc_state);
> > +
> > + return DISPLAY_VER(display) == 20 && psr->is_dpkgc_configured
> > &&
> > + (psr->is_wa_delayed_vblank_limit || !psr-
> > >is_dc5_entry_possible) &&
> > + !crtc_state->has_sel_update && !crtc_state-
> > >has_panel_replay;
> > +}
> > +
> > +/*
> > + * DC5 entry is only possible if vblank interrupt is disabled
> > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> > + * enabled encoders.
> > + */
> > +static bool
> > +intel_psr_is_dc5_entry_possible(struct intel_display *display,
> > + struct intel_atomic_state *state) {
> > + struct intel_crtc *intel_crtc;
> > + struct intel_crtc_state *crtc_state;
> > + int i;
> > +
> > + if ((display->power.domains.target_dc_state &
> > + DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
> > + return false;
> > +
> > + for_each_new_intel_crtc_in_state(state, intel_crtc,
> > crtc_state, i) {
> > + struct drm_crtc *crtc = &intel_crtc->base;
> > + struct drm_vblank_crtc *vblank;
> > + struct intel_encoder *encoder;
> > +
> > + if (!intel_crtc->active)
> > + continue;
> > +
> > + vblank = drm_crtc_vblank_crtc(crtc);
> > +
> > + if (vblank->enabled)
> > + return false;
> > +
> > + if (!crtc_state->has_psr)
> > + return false;
> > +
> > + for_each_encoder_on_crtc(display->drm, crtc, encoder)
> > + if (encoder->type != INTEL_OUTPUT_EDP ||
> > + !CAN_PSR(enc_to_intel_dp(encoder)))
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > static void hsw_activate_psr1(struct intel_dp *intel_dp)
> > {
> > struct intel_display *display = to_intel_display(intel_dp); @@
> > -1007,7 +1091,15 @@ static void hsw_activate_psr2(struct intel_dp
> > *intel_dp)
> > u32 val = EDP_PSR2_ENABLE;
> > u32 psr_val = 0;
> >
> > - val |=
> > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > + /*
> > + * Wa_22019444797
> > + * TODO: Disable idle frames when vblank gets enabled while
> > + * PSR2 is enabled
> > + */
> > + if (DISPLAY_VER(dev_priv) != 20 ||
>
>
> I think same Workaround is needed by PantherLake but only if stepping is
> A0. You could have this here:
>
> (DISPLAY_VER(display) != 20 && !IS_DISPLAY_VER_STEP(display, IP_VER(30,
> 0), STEP_A0, STEP_B0))
>
I do see the WA mentioned in bspec 74219 but the I don’t see any individual HSD cloned for it.
Moreover it is for one stepping and a driver temp workaround not sure if I need to implement this
@Shankar, Uma what do you suggest should I float a version implementing this or do this later on requirement
Regards,
Suraj Kandpal
> BR,
>
> Jouni Högander
>
>
> > + !intel_dp->psr.is_dpkgc_configured ||
> > + intel_dp->psr.is_dc5_entry_possible)
> > + val |=
> > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> >
> > if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
> > val |= EDP_SU_TRACK_ENABLE; @@ -2692,10 +2784,20 @@
> > void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> > const struct intel_crtc_state *new_crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > struct intel_encoder *encoder;
> > + bool dpkgc_configured = false, dc5_entry_possible = false;
> > + bool wa_delayed_vblank_limit = false;
> >
> > if (!HAS_PSR(display))
> > return;
> >
> > + if (DISPLAY_VER(display) == 20) {
> > + dpkgc_configured =
> > intel_psr_is_dpkgc_configured(display, state);
> > + dc5_entry_possible =
> > + intel_psr_is_dc5_entry_possible(display,
> > state);
> > + wa_delayed_vblank_limit =
> > + intel_psr_check_wa_delayed_vblank(&new_crtc_s
> > tate->hw.adjusted_mode);
> > + }
> > +
> > for_each_intel_encoder_mask_with_psr(state->base.dev,
> > encoder,
> > old_crtc_state-
> > >uapi.encoder_mask) {
> > struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > @@ -2704,6 +2806,12 @@ void intel_psr_pre_plane_update(struct
> > intel_atomic_state *state,
> >
> > mutex_lock(&psr->lock);
> >
> > + if (DISPLAY_VER(i915) == 20) {
> > + psr->is_dpkgc_configured = dpkgc_configured;
> > + psr->is_dc5_entry_possible =
> > dc5_entry_possible;
> > + psr->is_wa_delayed_vblank_limit =
> > wa_delayed_vblank_limit;
> > + }
> > +
> > /*
> > * Reasons to disable:
> > * - PSR disabled in new state @@ -2711,6 +2819,7 @@
> > void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> > * - Changing between PSR versions
> > * - Region Early Transport changing
> > * - Display WA #1136: skl, bxt
> > + * - Display WA_22019444797
> > */
> > needs_to_disable |=
> > intel_crtc_needs_modeset(new_crtc_state);
> > needs_to_disable |= !new_crtc_state->has_psr; @@
> > -2720,6 +2829,8 @@ void intel_psr_pre_plane_update(struct
> > intel_atomic_state *state,
> > psr->su_region_et_enabled;
> > needs_to_disable |= DISPLAY_VER(i915) < 11 &&
> > new_crtc_state->wm_level_disabled;
> > + /* TODO: Disable PSR1 when vblank gets enabled while
> > PSR1 is enabled */
> > + needs_to_disable |=
> > wa_22019444797_psr1_check(new_crtc_state, psr);
> >
> > if (psr->enabled && needs_to_disable)
> > intel_psr_disable_locked(intel_dp);
> > @@ -2760,6 +2871,12 @@ void intel_psr_post_plane_update(struct
> > intel_atomic_state *state,
> > keep_disabled |= DISPLAY_VER(display) < 11 &&
> > crtc_state->wm_level_disabled;
> >
> > + /*
> > + * Wa_22019444797
> > + * TODO: Disable PSR1 when vblank gets enabled while
> > PSR1 is enabled
> > + */
> > + keep_disabled |=
> > wa_22019444797_psr1_check(crtc_state, psr);
> > +
> > if (!psr->enabled && !keep_disabled)
> > intel_psr_enable_locked(intel_dp, crtc_state);
> > else if (psr->enabled && !crtc_state-
> > >wm_level_disabled)
^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [PATCH] drm/i915/psr: Implement WA to help reach PC10
2024-09-23 2:54 ` Kandpal, Suraj
@ 2024-09-23 10:23 ` Shankar, Uma
0 siblings, 0 replies; 47+ messages in thread
From: Shankar, Uma @ 2024-09-23 10:23 UTC (permalink / raw)
To: Kandpal, Suraj, Hogander, Jouni, intel-gfx@lists.freedesktop.org
> > On Fri, 2024-09-20 at 14:42 +0530, Suraj Kandpal wrote:
> > > To reach PC10 when PKG_C_LATENCY is configure we must do the
> > following
> > > things
> > > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> > > entered
> > > 2) Allow PSR2 deep sleep when DC5 can be entered
> > > 3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
> > > eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
> > > not happening.
> >
> > One comment below related to PantherLake. Otherwise patch looks ok to
> > me.
> > > --v2
> > > -Switch condition and do an early return [Jani] -Do some checks in
> > > compute_config [Jani] -Do not use register reads as a method of
> > > checking states for DPKGC or delayed vblank [Jani] -Use another way
> > > to see is vblank interrupts are disabled or not [Jani]
> > >
> > > --v3
> > > -Use has_psr to check if psr can be enabled or not for dc5_entry
> > > cond [Uma] -Move the dc5 entry computation to psr_compute_config
> > > [Jouni] -No need to change sequence of enabled and activate, so dont
> > > make hsw_psr1_activate return anything [Jouni] -Use has_psr to stop
> > > psr1 activation [Jouni] -Use lineage no. in WA -Add the display ver
> > > restrictions for WA
> > >
> > > --v4
> > > -use more appropriate name for check_vblank_limit() [Jouni] -Cover
> > > the case for idle frames when dpkgc is not configured [Jouni] -Check
> > > psr only for edp [Jouni]
> > >
> > > --v5
> > > -move psr1 handling to plane update [Jouni] -add todo for cases when
> > > vblank is enabled when psr enabled [Jouni] -use intel_display
> > > instead of drm_i915_private
> > >
> > > --v6
> > > -check target_dc_state [Jouni]
> > > -fix condition in pre/post plane update [Jouni]
> > >
> > > --v7
> > > -fix has_psr condition [Uma]
> > > -fix typo in commit subject [Uma]
> > > -put psr1_wa check in its own helper [Uma] -fix the dc_entry check
> > > [Jouni] -use HAS_PSR() to cover two edp one with psr and one nonpsr
> > > [Jouni]
> > >
> > > WA: 22019444797
> > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > ---
> > > .../drm/i915/display/intel_display_types.h | 3 +
> > > drivers/gpu/drm/i915/display/intel_psr.c | 119
> > > +++++++++++++++++-
> > > 2 files changed, 121 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 3e694c1204db..2d790abee76e 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -1577,6 +1577,9 @@ struct intel_psr {
> > > #define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
> > >
> > > u32 debug;
> > > + bool is_dpkgc_configured;
> > > + bool is_dc5_entry_possible;
> > > + bool is_wa_delayed_vblank_limit;
> > > bool sink_support;
> > > bool source_support;
> > > bool enabled;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 5b355d0a3565..b882ff25fb92 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -26,6 +26,7 @@
> > > #include <drm/drm_atomic_helper.h>
> > > #include <drm/drm_damage_helper.h>
> > > #include <drm/drm_debugfs.h>
> > > +#include <drm/drm_vblank.h>
> > >
> > > #include "i915_drv.h"
> > > #include "i915_reg.h"
> > > @@ -895,6 +896,89 @@ static u8 psr_compute_idle_frames(struct
> > intel_dp
> > > *intel_dp)
> > > return idle_frames;
> > > }
> > >
> > > +static bool
> > > +intel_psr_check_wa_delayed_vblank(const struct drm_display_mode
> > > *adjusted_mode)
> > > +{
> > > + return (adjusted_mode->crtc_vblank_start - adjusted_mode-
> > > >crtc_vdisplay) >= 6;
> > > +}
> > > +
> > > +/*
> > > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> > > + * VRR is not enabled
> > > + */
> > > +static bool intel_psr_is_dpkgc_configured(struct intel_display
> > > *display,
> > > + struct intel_atomic_state
> > > *state)
> > > +{
> > > + struct intel_crtc *intel_crtc;
> > > + struct intel_crtc_state *crtc_state;
> > > + int i;
> > > +
> > > + if (DISPLAY_VER(display) < 20)
> > > + return false;
> > > +
> > > + for_each_new_intel_crtc_in_state(state, intel_crtc,
> > > crtc_state, i) {
> > > + if (!intel_crtc->active)
> > > + continue;
> > > +
> > > + if (crtc_state->vrr.enable)
> > > + return false;
> > > + }
> > > +
> > > + return true;
> > > +}
> > > +
> > > +static bool wa_22019444797_psr1_check(const struct intel_crtc_state
> > > *crtc_state,
> > > + struct intel_psr *psr) {
> > > + struct intel_display *display =
> > > +to_intel_display(crtc_state);
> > > +
> > > + return DISPLAY_VER(display) == 20 &&
> > > +psr->is_dpkgc_configured
> > > &&
> > > + (psr->is_wa_delayed_vblank_limit || !psr-
> > > >is_dc5_entry_possible) &&
> > > + !crtc_state->has_sel_update && !crtc_state-
> > > >has_panel_replay;
> > > +}
> > > +
> > > +/*
> > > + * DC5 entry is only possible if vblank interrupt is disabled
> > > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> > > + * enabled encoders.
> > > + */
> > > +static bool
> > > +intel_psr_is_dc5_entry_possible(struct intel_display *display,
> > > + struct intel_atomic_state *state) {
> > > + struct intel_crtc *intel_crtc;
> > > + struct intel_crtc_state *crtc_state;
> > > + int i;
> > > +
> > > + if ((display->power.domains.target_dc_state &
> > > + DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
> > > + return false;
> > > +
> > > + for_each_new_intel_crtc_in_state(state, intel_crtc,
> > > crtc_state, i) {
> > > + struct drm_crtc *crtc = &intel_crtc->base;
> > > + struct drm_vblank_crtc *vblank;
> > > + struct intel_encoder *encoder;
> > > +
> > > + if (!intel_crtc->active)
> > > + continue;
> > > +
> > > + vblank = drm_crtc_vblank_crtc(crtc);
> > > +
> > > + if (vblank->enabled)
> > > + return false;
> > > +
> > > + if (!crtc_state->has_psr)
> > > + return false;
> > > +
> > > + for_each_encoder_on_crtc(display->drm, crtc,
> > > +encoder)
> > > + if (encoder->type != INTEL_OUTPUT_EDP ||
> > > + !CAN_PSR(enc_to_intel_dp(encoder)))
> > > + return false;
> > > + }
> > > +
> > > + return true;
> > > +}
> > > +
> > > static void hsw_activate_psr1(struct intel_dp *intel_dp)
> > > {
> > > struct intel_display *display = to_intel_display(intel_dp);
> > > @@
> > > -1007,7 +1091,15 @@ static void hsw_activate_psr2(struct intel_dp
> > > *intel_dp)
> > > u32 val = EDP_PSR2_ENABLE;
> > > u32 psr_val = 0;
> > >
> > > - val |=
> > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > > + /*
> > > + * Wa_22019444797
> > > + * TODO: Disable idle frames when vblank gets enabled while
> > > + * PSR2 is enabled
> > > + */
> > > + if (DISPLAY_VER(dev_priv) != 20 ||
> >
> >
> > I think same Workaround is needed by PantherLake but only if stepping
> > is A0. You could have this here:
> >
> > (DISPLAY_VER(display) != 20 && !IS_DISPLAY_VER_STEP(display,
> > IP_VER(30, 0), STEP_A0, STEP_B0))
> >
>
> I do see the WA mentioned in bspec 74219 but the I don’t see any individual HSD
> cloned for it.
> Moreover it is for one stepping and a driver temp workaround not sure if I need to
> implement this @Shankar, Uma what do you suggest should I float a version
> implementing this or do this later on requirement
Yeah, its needed for PTL but gets fixed later in hardware. I would suggest we can limit
this to LNL for now and don't add a stepping check in upstream.
Overall patch looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Regards,
Uma Shankar
> Regards,
> Suraj Kandpal
>
> > BR,
> >
> > Jouni Högander
> >
> >
> > > + !intel_dp->psr.is_dpkgc_configured ||
> > > + intel_dp->psr.is_dc5_entry_possible)
> > > + val |=
> > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > >
> > > if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
> > > val |= EDP_SU_TRACK_ENABLE; @@ -2692,10 +2784,20 @@
> > > void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> > > const struct intel_crtc_state *new_crtc_state =
> > > intel_atomic_get_new_crtc_state(state, crtc);
> > > struct intel_encoder *encoder;
> > > + bool dpkgc_configured = false, dc5_entry_possible = false;
> > > + bool wa_delayed_vblank_limit = false;
> > >
> > > if (!HAS_PSR(display))
> > > return;
> > >
> > > + if (DISPLAY_VER(display) == 20) {
> > > + dpkgc_configured =
> > > intel_psr_is_dpkgc_configured(display, state);
> > > + dc5_entry_possible =
> > > + intel_psr_is_dc5_entry_possible(display,
> > > state);
> > > + wa_delayed_vblank_limit =
> > > +
> > > +intel_psr_check_wa_delayed_vblank(&new_crtc_s
> > > tate->hw.adjusted_mode);
> > > + }
> > > +
> > > for_each_intel_encoder_mask_with_psr(state->base.dev,
> > > encoder,
> > > old_crtc_state-
> > > >uapi.encoder_mask) {
> > > struct intel_dp *intel_dp =
> > > enc_to_intel_dp(encoder); @@ -2704,6 +2806,12 @@ void
> > > intel_psr_pre_plane_update(struct intel_atomic_state *state,
> > >
> > > mutex_lock(&psr->lock);
> > >
> > > + if (DISPLAY_VER(i915) == 20) {
> > > + psr->is_dpkgc_configured = dpkgc_configured;
> > > + psr->is_dc5_entry_possible =
> > > dc5_entry_possible;
> > > + psr->is_wa_delayed_vblank_limit =
> > > wa_delayed_vblank_limit;
> > > + }
> > > +
> > > /*
> > > * Reasons to disable:
> > > * - PSR disabled in new state @@ -2711,6 +2819,7 @@
> > > void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> > > * - Changing between PSR versions
> > > * - Region Early Transport changing
> > > * - Display WA #1136: skl, bxt
> > > + * - Display WA_22019444797
> > > */
> > > needs_to_disable |=
> > > intel_crtc_needs_modeset(new_crtc_state);
> > > needs_to_disable |= !new_crtc_state->has_psr; @@
> > > -2720,6 +2829,8 @@ void intel_psr_pre_plane_update(struct
> > > intel_atomic_state *state,
> > > psr->su_region_et_enabled;
> > > needs_to_disable |= DISPLAY_VER(i915) < 11 &&
> > > new_crtc_state->wm_level_disabled;
> > > + /* TODO: Disable PSR1 when vblank gets enabled while
> > > PSR1 is enabled */
> > > + needs_to_disable |=
> > > wa_22019444797_psr1_check(new_crtc_state, psr);
> > >
> > > if (psr->enabled && needs_to_disable)
> > > intel_psr_disable_locked(intel_dp);
> > > @@ -2760,6 +2871,12 @@ void intel_psr_post_plane_update(struct
> > > intel_atomic_state *state,
> > > keep_disabled |= DISPLAY_VER(display) < 11 &&
> > > crtc_state->wm_level_disabled;
> > >
> > > + /*
> > > + * Wa_22019444797
> > > + * TODO: Disable PSR1 when vblank gets enabled while
> > > PSR1 is enabled
> > > + */
> > > + keep_disabled |=
> > > wa_22019444797_psr1_check(crtc_state, psr);
> > > +
> > > if (!psr->enabled && !keep_disabled)
> > > intel_psr_enable_locked(intel_dp,
> > > crtc_state);
> > > else if (psr->enabled && !crtc_state-
> > > >wm_level_disabled)
^ permalink raw reply [flat|nested] 47+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/psr: Implment WA to help reach PC10 (rev6)
2024-09-02 5:02 [PATCH] drm/i915/psr: Implment WA to help reach PC10 Suraj Kandpal
` (11 preceding siblings ...)
2024-09-21 11:54 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2024-09-27 18:54 ` Patchwork
2024-09-28 16:12 ` Patchwork
13 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2024-09-27 18:54 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 79758 bytes --]
== Series Details ==
Series: drm/i915/psr: Implment WA to help reach PC10 (rev6)
URL : https://patchwork.freedesktop.org/series/138065/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15441_full -> Patchwork_138065v6_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
New tests
---------
New tests have been introduced between CI_DRM_15441_full and Patchwork_138065v6_full:
### New IGT tests (9) ###
* igt@kms_lease@lease-unleased-connector@pipe-a-hdmi-a-2:
- Statuses : 3 pass(s)
- Exec time: [0.06, 0.07] s
* igt@kms_lease@lease-unleased-connector@pipe-a-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [0.06] s
* igt@kms_lease@lease-unleased-connector@pipe-b-hdmi-a-2:
- Statuses : 3 pass(s)
- Exec time: [0.06, 0.07] s
* igt@kms_lease@lease-unleased-connector@pipe-b-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [0.06] s
* igt@kms_lease@lease-unleased-connector@pipe-c-hdmi-a-2:
- Statuses : 2 pass(s)
- Exec time: [0.06, 0.07] s
* igt@kms_lease@lease-unleased-connector@pipe-c-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [0.06] s
* igt@kms_lease@lease-unleased-connector@pipe-d-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.01] s
* igt@kms_lease@lease-unleased-connector@pipe-d-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [0.06] s
* igt@kms_lease@lease-unleased-connector@pipe-d-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [0.06] s
Known issues
------------
Here are the changes found in Patchwork_138065v6_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@object-reloc-purge-cache:
- shard-dg1: NOTRUN -> [SKIP][1] ([i915#8411])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@api_intel_bb@object-reloc-purge-cache.html
* igt@drm_fdinfo@busy-check-all@bcs0:
- shard-dg1: NOTRUN -> [SKIP][2] ([i915#8414]) +18 other tests skip
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@drm_fdinfo@busy-check-all@bcs0.html
* igt@drm_fdinfo@virtual-busy-all:
- shard-dg2: NOTRUN -> [SKIP][3] ([i915#8414])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@drm_fdinfo@virtual-busy-all.html
* igt@gem_busy@semaphore:
- shard-dg1: NOTRUN -> [SKIP][4] ([i915#3936])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_busy@semaphore.html
* igt@gem_caching@reads:
- shard-mtlp: NOTRUN -> [SKIP][5] ([i915#4873])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@gem_caching@reads.html
* igt@gem_ccs@block-copy-compressed:
- shard-mtlp: NOTRUN -> [SKIP][6] ([i915#3555] / [i915#9323])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_ccs@block-copy-compressed.html
* igt@gem_close_race@multigpu-basic-process:
- shard-rkl: NOTRUN -> [SKIP][7] ([i915#7697])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@gem_close_race@multigpu-basic-process.html
- shard-dg1: NOTRUN -> [SKIP][8] ([i915#7697])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_ctx_persistence@heartbeat-hostile:
- shard-dg1: NOTRUN -> [SKIP][9] ([i915#8555]) +1 other test skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_ctx_persistence@heartbeat-hostile.html
* igt@gem_ctx_persistence@heartbeat-many:
- shard-mtlp: NOTRUN -> [SKIP][10] ([i915#8555])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_ctx_persistence@heartbeat-many.html
* igt@gem_ctx_persistence@hostile:
- shard-dg2: NOTRUN -> [FAIL][11] ([i915#11980])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@gem_ctx_persistence@hostile.html
- shard-tglu: [PASS][12] -> [FAIL][13] ([i915#11980])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-tglu-6/igt@gem_ctx_persistence@hostile.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-tglu-5/igt@gem_ctx_persistence@hostile.html
* igt@gem_ctx_sseu@engines:
- shard-dg2: NOTRUN -> [SKIP][14] ([i915#280])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_ctx_sseu@engines.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-mtlp: NOTRUN -> [SKIP][15] ([i915#280])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_eio@hibernate:
- shard-rkl: NOTRUN -> [ABORT][16] ([i915#7975] / [i915#8213])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-3/igt@gem_eio@hibernate.html
* igt@gem_eio@kms:
- shard-dg2: [PASS][17] -> [FAIL][18] ([i915#5784])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-8/igt@gem_eio@kms.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-10/igt@gem_eio@kms.html
* igt@gem_exec_balancer@bonded-dual:
- shard-mtlp: NOTRUN -> [SKIP][19] ([i915#4771])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_exec_balancer@bonded-dual.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-rkl: NOTRUN -> [SKIP][20] ([i915#4525])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_capture@capture:
- shard-mtlp: NOTRUN -> [FAIL][21] ([i915#11965]) +1 other test fail
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_exec_capture@capture.html
* igt@gem_exec_fair@basic-deadline:
- shard-rkl: [PASS][22] -> [FAIL][23] ([i915#2846])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-3/igt@gem_exec_fair@basic-deadline.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-rkl: [PASS][24] -> [FAIL][25] ([i915#2842])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-2/igt@gem_exec_fair@basic-none@vecs0.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace:
- shard-dg2: NOTRUN -> [SKIP][26] ([i915#3539])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_exec_fair@basic-pace.html
* igt@gem_exec_fair@basic-sync:
- shard-dg1: NOTRUN -> [SKIP][27] ([i915#3539]) +1 other test skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_exec_fair@basic-sync.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-dg1: NOTRUN -> [SKIP][28] ([i915#3539] / [i915#4852]) +1 other test skip
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_flush@basic-wb-rw-before-default:
- shard-dg2: NOTRUN -> [SKIP][29] ([i915#3539] / [i915#4852])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_exec_flush@basic-wb-rw-before-default.html
* igt@gem_exec_reloc@basic-cpu-read:
- shard-rkl: NOTRUN -> [SKIP][30] ([i915#3281]) +4 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@gem_exec_reloc@basic-cpu-read.html
* igt@gem_exec_reloc@basic-gtt-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][31] ([i915#3281]) +6 other tests skip
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@gem_exec_reloc@basic-gtt-noreloc.html
* igt@gem_exec_reloc@basic-wc-cpu-noreloc:
- shard-dg1: NOTRUN -> [SKIP][32] ([i915#3281]) +10 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@gem_exec_reloc@basic-wc-cpu-noreloc.html
* igt@gem_exec_reloc@basic-write-wc-active:
- shard-dg2: NOTRUN -> [SKIP][33] ([i915#3281]) +5 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_exec_reloc@basic-write-wc-active.html
* igt@gem_exec_schedule@preempt-queue:
- shard-dg1: NOTRUN -> [SKIP][34] ([i915#4812]) +2 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_exec_schedule@preempt-queue.html
* igt@gem_exec_schedule@preempt-queue-chain:
- shard-dg2: NOTRUN -> [SKIP][35] ([i915#4537] / [i915#4812])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_exec_schedule@preempt-queue-chain.html
* igt@gem_fence_thrash@bo-write-verify-none:
- shard-dg1: NOTRUN -> [SKIP][36] ([i915#4860]) +1 other test skip
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_fence_thrash@bo-write-verify-none.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-rkl: NOTRUN -> [SKIP][37] ([i915#4613]) +3 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@massive-random:
- shard-mtlp: NOTRUN -> [SKIP][38] ([i915#4613])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_lmem_swapping@massive-random.html
* igt@gem_mmap_gtt@basic:
- shard-dg2: NOTRUN -> [SKIP][39] ([i915#4077]) +2 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@gem_mmap_gtt@basic.html
* igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
- shard-mtlp: NOTRUN -> [SKIP][40] ([i915#4077]) +4 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
* igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-dg1: NOTRUN -> [SKIP][41] ([i915#4077]) +13 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
* igt@gem_mmap_wc@fault-concurrent:
- shard-mtlp: NOTRUN -> [SKIP][42] ([i915#4083]) +1 other test skip
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_mmap_wc@fault-concurrent.html
* igt@gem_mmap_wc@write-prefaulted:
- shard-dg2: NOTRUN -> [SKIP][43] ([i915#4083]) +3 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@gem_mmap_wc@write-prefaulted.html
* igt@gem_mmap_wc@write-read:
- shard-dg1: NOTRUN -> [SKIP][44] ([i915#4083]) +4 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_mmap_wc@write-read.html
* igt@gem_pread@bench:
- shard-rkl: NOTRUN -> [SKIP][45] ([i915#3282])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@gem_pread@bench.html
- shard-dg1: NOTRUN -> [SKIP][46] ([i915#3282]) +1 other test skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_pread@bench.html
* igt@gem_pxp@create-regular-context-2:
- shard-rkl: NOTRUN -> [SKIP][47] ([i915#4270]) +2 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@gem_pxp@create-regular-context-2.html
* igt@gem_pxp@display-protected-crc:
- shard-dg2: NOTRUN -> [SKIP][48] ([i915#4270])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@gem_pxp@display-protected-crc.html
* igt@gem_pxp@reject-modify-context-protection-off-1:
- shard-mtlp: NOTRUN -> [SKIP][49] ([i915#4270])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_pxp@reject-modify-context-protection-off-1.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-dg1: NOTRUN -> [SKIP][50] ([i915#4270]) +4 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_readwrite@beyond-eob:
- shard-mtlp: NOTRUN -> [SKIP][51] ([i915#3282]) +2 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_readwrite@beyond-eob.html
* igt@gem_readwrite@write-bad-handle:
- shard-dg2: NOTRUN -> [SKIP][52] ([i915#3282]) +2 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_readwrite@write-bad-handle.html
* igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:
- shard-mtlp: NOTRUN -> [SKIP][53] ([i915#8428]) +2 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html
* igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled:
- shard-dg2: NOTRUN -> [SKIP][54] ([i915#5190] / [i915#8428]) +3 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled.html
* igt@gem_softpin@evict-snoop:
- shard-mtlp: NOTRUN -> [SKIP][55] ([i915#4885])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_softpin@evict-snoop.html
* igt@gem_softpin@evict-snoop-interruptible:
- shard-dg1: NOTRUN -> [SKIP][56] ([i915#4885])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_softpin@evict-snoop-interruptible.html
* igt@gem_tiled_pread_pwrite:
- shard-dg1: NOTRUN -> [SKIP][57] ([i915#4079])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@gem_tiled_pread_pwrite.html
* igt@gem_userptr_blits@coherency-unsync:
- shard-dg2: NOTRUN -> [SKIP][58] ([i915#3297])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_userptr_blits@coherency-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-dg2: NOTRUN -> [SKIP][59] ([i915#3297] / [i915#4880])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@readonly-pwrite-unsync:
- shard-mtlp: NOTRUN -> [SKIP][60] ([i915#3297]) +1 other test skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_userptr_blits@readonly-pwrite-unsync.html
* igt@gem_userptr_blits@relocations:
- shard-dg2: NOTRUN -> [SKIP][61] ([i915#3281] / [i915#3297])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_userptr_blits@relocations.html
* igt@gen9_exec_parse@allowed-single:
- shard-rkl: NOTRUN -> [SKIP][62] ([i915#2527]) +2 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@gen9_exec_parse@allowed-single.html
- shard-glk: NOTRUN -> [ABORT][63] ([i915#5566])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-glk7/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-dg1: NOTRUN -> [SKIP][64] ([i915#2527]) +5 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@gen9_exec_parse@bb-start-cmd.html
* igt@gen9_exec_parse@bb-start-far:
- shard-dg2: NOTRUN -> [SKIP][65] ([i915#2856]) +1 other test skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gen9_exec_parse@bb-start-far.html
* igt@gen9_exec_parse@valid-registers:
- shard-mtlp: NOTRUN -> [SKIP][66] ([i915#2856])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gen9_exec_parse@valid-registers.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg2: [PASS][67] -> [ABORT][68] ([i915#9820])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-2/igt@i915_module_load@reload-with-fault-injection.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-10/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pipe_stress@stress-xrgb8888-ytiled:
- shard-mtlp: NOTRUN -> [SKIP][69] ([i915#8436])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html
* igt@i915_pm_freq_mult@media-freq@gt0:
- shard-rkl: NOTRUN -> [SKIP][70] ([i915#6590]) +1 other test skip
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@i915_pm_freq_mult@media-freq@gt0.html
* igt@i915_pm_rps@basic-api:
- shard-dg2: NOTRUN -> [SKIP][71] ([i915#11681] / [i915#6621])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@i915_pm_rps@basic-api.html
* igt@i915_pm_rps@thresholds-idle:
- shard-dg1: NOTRUN -> [SKIP][72] ([i915#11681])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@i915_pm_rps@thresholds-idle.html
* igt@i915_pm_rps@thresholds-idle-park:
- shard-mtlp: NOTRUN -> [SKIP][73] ([i915#11681])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@i915_pm_rps@thresholds-idle-park.html
* igt@i915_query@hwconfig_table:
- shard-dg1: NOTRUN -> [SKIP][74] ([i915#6245])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@i915_query@hwconfig_table.html
* igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- shard-dg1: NOTRUN -> [SKIP][75] ([i915#4212])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc-ccs:
- shard-dg1: NOTRUN -> [SKIP][76] ([i915#8709]) +7 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc-ccs.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-mtlp: NOTRUN -> [SKIP][77] ([i915#3555])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-snb: [PASS][78] -> [FAIL][79] ([i915#5956]) +1 other test fail
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-snb4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-snb5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-0:
- shard-dg1: NOTRUN -> [SKIP][80] ([i915#4538] / [i915#5286]) +3 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-addfb:
- shard-dg1: NOTRUN -> [SKIP][81] ([i915#5286]) +2 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_big_fb@4-tiled-addfb.html
* igt@kms_big_fb@4-tiled-addfb-size-overflow:
- shard-rkl: NOTRUN -> [SKIP][82] ([i915#5286]) +2 other tests skip
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_big_fb@4-tiled-addfb-size-overflow.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][83] ([i915#4538] / [i915#5190]) +4 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][84] ([i915#3638]) +1 other test skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
- shard-dg1: NOTRUN -> [SKIP][85] ([i915#3638]) +3 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][86] +13 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-dg2: NOTRUN -> [SKIP][87] ([i915#5190])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0:
- shard-dg1: NOTRUN -> [SKIP][88] ([i915#4538]) +6 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-mtlp: NOTRUN -> [SKIP][89] +11 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][90] ([i915#10307] / [i915#10434] / [i915#6095]) +6 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-2/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][91] ([i915#6095]) +107 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-4.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][92] ([i915#6095]) +93 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][93] ([i915#10307] / [i915#6095]) +173 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
- shard-mtlp: NOTRUN -> [SKIP][94] ([i915#12042])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][95] ([i915#6095]) +19 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-edp-1.html
* igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
- shard-dg1: NOTRUN -> [SKIP][96] ([i915#12042])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-rkl: NOTRUN -> [SKIP][97] ([i915#3742])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_cdclk@mode-transition-all-outputs.html
- shard-dg1: NOTRUN -> [SKIP][98] ([i915#3742])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_chamelium_frames@hdmi-cmp-planar-formats:
- shard-dg2: NOTRUN -> [SKIP][99] ([i915#7828]) +4 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html
* igt@kms_chamelium_hpd@dp-hpd-for-each-pipe:
- shard-mtlp: NOTRUN -> [SKIP][100] ([i915#7828]) +3 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_chamelium_hpd@dp-hpd-for-each-pipe.html
* igt@kms_chamelium_hpd@vga-hpd-fast:
- shard-rkl: NOTRUN -> [SKIP][101] ([i915#7828]) +5 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_chamelium_hpd@vga-hpd-fast.html
- shard-dg1: NOTRUN -> [SKIP][102] ([i915#7828]) +10 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_chamelium_hpd@vga-hpd-fast.html
* igt@kms_content_protection@content-type-change:
- shard-dg1: NOTRUN -> [SKIP][103] ([i915#9424])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_content_protection@content-type-change.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-dg1: NOTRUN -> [SKIP][104] ([i915#3299]) +1 other test skip
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@legacy:
- shard-dg2: NOTRUN -> [SKIP][105] ([i915#7118] / [i915#9424])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@mei-interface:
- shard-mtlp: NOTRUN -> [SKIP][106] ([i915#8063] / [i915#9433])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@srm:
- shard-rkl: NOTRUN -> [SKIP][107] ([i915#7118])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_content_protection@srm.html
- shard-dg1: NOTRUN -> [SKIP][108] ([i915#7116])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_content_protection@srm.html
* igt@kms_content_protection@uevent@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [FAIL][109] ([i915#1339] / [i915#7173])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_content_protection@uevent@pipe-a-dp-4.html
* igt@kms_cursor_crc@cursor-offscreen-512x170:
- shard-mtlp: NOTRUN -> [SKIP][110] ([i915#3359])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_cursor_crc@cursor-offscreen-512x170.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-dg2: NOTRUN -> [SKIP][111] ([i915#11453])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-6/igt@kms_cursor_crc@cursor-onscreen-512x170.html
- shard-dg1: NOTRUN -> [SKIP][112] ([i915#11453]) +1 other test skip
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x10:
- shard-mtlp: NOTRUN -> [SKIP][113] ([i915#3555] / [i915#8814]) +2 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-rkl: NOTRUN -> [SKIP][114] ([i915#11453])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-mtlp: NOTRUN -> [SKIP][115] ([i915#4213])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-rkl: NOTRUN -> [SKIP][116] ([i915#4103])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
- shard-dg1: NOTRUN -> [SKIP][117] ([i915#4103] / [i915#4213])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
- shard-mtlp: NOTRUN -> [SKIP][118] ([i915#9809])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@torture-bo@pipe-a:
- shard-snb: [PASS][119] -> [DMESG-WARN][120] ([i915#10166]) +1 other test dmesg-warn
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-snb2/igt@kms_cursor_legacy@torture-bo@pipe-a.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-snb6/igt@kms_cursor_legacy@torture-bo@pipe-a.html
- shard-dg2: [PASS][121] -> [DMESG-WARN][122] ([i915#10166]) +1 other test dmesg-warn
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-6/igt@kms_cursor_legacy@torture-bo@pipe-a.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-2/igt@kms_cursor_legacy@torture-bo@pipe-a.html
* igt@kms_display_modes@extended-mode-basic:
- shard-mtlp: NOTRUN -> [SKIP][123] ([i915#3555] / [i915#8827])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_display_modes@mst-extended-mode-negative:
- shard-dg1: NOTRUN -> [SKIP][124] ([i915#8588])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_display_modes@mst-extended-mode-negative.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][125] ([i915#3804])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_dither@fb-8bpc-vs-panel-8bpc:
- shard-dg2: [PASS][126] -> [SKIP][127] ([i915#3555])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-11/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-1/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
* igt@kms_dp_aux_dev:
- shard-dg1: NOTRUN -> [SKIP][128] ([i915#1257])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@kms_dp_aux_dev.html
* igt@kms_draw_crc@draw-method-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][129] ([i915#8812])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_draw_crc@draw-method-mmap-gtt.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-dg2: NOTRUN -> [SKIP][130] ([i915#3840] / [i915#9688])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-fractional-bpp-with-bpc:
- shard-dg2: NOTRUN -> [SKIP][131] ([i915#3840])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-mtlp: NOTRUN -> [SKIP][132] ([i915#3555] / [i915#3840])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_feature_discovery@display-2x:
- shard-rkl: NOTRUN -> [SKIP][133] ([i915#1839])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_feature_discovery@display-2x.html
- shard-dg1: NOTRUN -> [SKIP][134] ([i915#1839])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_feature_discovery@display-2x.html
* igt@kms_fence_pin_leak:
- shard-dg1: NOTRUN -> [SKIP][135] ([i915#4881])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_fence_pin_leak.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-dg1: NOTRUN -> [SKIP][136] ([i915#8381])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@2x-flip-vs-panning-interruptible:
- shard-dg2: NOTRUN -> [SKIP][137] +6 other tests skip
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_flip@2x-flip-vs-panning-interruptible.html
* igt@kms_flip@2x-flip-vs-rmfb:
- shard-mtlp: NOTRUN -> [SKIP][138] ([i915#3637]) +5 other tests skip
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_flip@2x-flip-vs-rmfb.html
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
- shard-dg1: NOTRUN -> [SKIP][139] ([i915#9934]) +3 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-fences-interruptible:
- shard-dg2: NOTRUN -> [SKIP][140] ([i915#8381])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_flip@flip-vs-fences-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling:
- shard-mtlp: NOTRUN -> [SKIP][141] ([i915#2672] / [i915#3555] / [i915#8813]) +2 other tests skip
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][142] ([i915#2672]) +1 other test skip
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
- shard-dg1: NOTRUN -> [SKIP][143] ([i915#2587] / [i915#2672] / [i915#3555]) +2 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][144] ([i915#2672]) +1 other test skip
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
- shard-dg1: NOTRUN -> [SKIP][145] ([i915#2587] / [i915#2672]) +3 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
- shard-dg2: NOTRUN -> [SKIP][146] ([i915#2672] / [i915#3555] / [i915#5190])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
- shard-rkl: NOTRUN -> [SKIP][147] ([i915#2672] / [i915#3555]) +1 other test skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
- shard-dg1: NOTRUN -> [SKIP][148] ([i915#2672] / [i915#3555])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
- shard-dg2: NOTRUN -> [SKIP][149] ([i915#2672] / [i915#3555]) +1 other test skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][150] ([i915#2672]) +2 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][151] ([i915#2672] / [i915#3555])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][152] ([i915#8708]) +9 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt:
- shard-mtlp: NOTRUN -> [SKIP][153] ([i915#1825]) +13 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- shard-dg1: NOTRUN -> [SKIP][154] ([i915#5439])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][155] ([i915#1825]) +16 other tests skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff:
- shard-dg1: NOTRUN -> [SKIP][156] +53 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move:
- shard-dg2: NOTRUN -> [SKIP][157] ([i915#5354]) +18 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
- shard-dg1: NOTRUN -> [SKIP][158] ([i915#3458]) +15 other tests skip
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][159] ([i915#3023]) +13 other tests skip
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][160] ([i915#8708]) +29 other tests skip
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][161] ([i915#3458]) +3 other tests skip
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][162] ([i915#8708]) +3 other tests skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_hdr@static-swap:
- shard-dg2: [PASS][163] -> [SKIP][164] ([i915#3555] / [i915#8228])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-11/igt@kms_hdr@static-swap.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-3/igt@kms_hdr@static-swap.html
- shard-mtlp: NOTRUN -> [SKIP][165] ([i915#3555] / [i915#8228])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_hdr@static-swap.html
* igt@kms_hdr@static-toggle:
- shard-dg2: NOTRUN -> [SKIP][166] ([i915#3555] / [i915#8228]) +1 other test skip
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-6/igt@kms_hdr@static-toggle.html
- shard-dg1: NOTRUN -> [SKIP][167] ([i915#3555] / [i915#8228]) +2 other tests skip
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_hdr@static-toggle.html
* igt@kms_panel_fitting@legacy:
- shard-dg1: NOTRUN -> [SKIP][168] ([i915#6301])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_panel_fitting@legacy.html
* igt@kms_plane_lowres@tiling-y:
- shard-mtlp: NOTRUN -> [SKIP][169] ([i915#3555] / [i915#8821])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_plane_lowres@tiling-y.html
* igt@kms_plane_lowres@tiling-yf:
- shard-rkl: NOTRUN -> [SKIP][170] ([i915#3555]) +2 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_plane_lowres@tiling-yf.html
- shard-dg1: NOTRUN -> [SKIP][171] ([i915#3555]) +6 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [FAIL][172] ([i915#8292])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25:
- shard-dg2: NOTRUN -> [SKIP][173] ([i915#6953] / [i915#9423]) +2 other tests skip
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_plane_scaling@planes-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d:
- shard-dg2: NOTRUN -> [SKIP][174] ([i915#12247]) +7 other tests skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c:
- shard-dg1: NOTRUN -> [INCOMPLETE][175] ([i915#12291]) +1 other test incomplete
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d:
- shard-dg2: NOTRUN -> [INCOMPLETE][176] ([i915#12291]) +1 other test incomplete
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25:
- shard-dg1: NOTRUN -> [SKIP][177] ([i915#6953])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b:
- shard-dg1: NOTRUN -> [SKIP][178] ([i915#12247]) +8 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b.html
* igt@kms_pm_dc@dc6-psr:
- shard-dg1: NOTRUN -> [SKIP][179] ([i915#9685])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-rkl: [PASS][180] -> [SKIP][181] ([i915#9340])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-4/igt@kms_pm_lpsp@kms-lpsp.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-6/igt@kms_pm_lpsp@kms-lpsp.html
- shard-dg1: NOTRUN -> [SKIP][182] ([i915#9340])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_lpsp@screens-disabled:
- shard-rkl: NOTRUN -> [SKIP][183] ([i915#8430])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_pm_lpsp@screens-disabled.html
- shard-dg1: NOTRUN -> [SKIP][184] ([i915#8430])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_pm_lpsp@screens-disabled.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-rkl: [PASS][185] -> [SKIP][186] ([i915#9519]) +2 other tests skip
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-dg2: [PASS][187] -> [SKIP][188] ([i915#9519])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-3/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_prime@basic-crc-hybrid:
- shard-dg1: NOTRUN -> [SKIP][189] ([i915#6524]) +2 other tests skip
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-dg2: NOTRUN -> [SKIP][190] ([i915#11520]) +2 other tests skip
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-overlay-plane-update-sf-dmg-area:
- shard-dg1: NOTRUN -> [SKIP][191] ([i915#11520]) +2 other tests skip
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_psr2_sf@fbc-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area@psr2-pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][192] ([i915#9808]) +2 other tests skip
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area@psr2-pipe-a-edp-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-rkl: NOTRUN -> [SKIP][193] ([i915#11520]) +2 other tests skip
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr2_su@page_flip-p010:
- shard-rkl: NOTRUN -> [SKIP][194] ([i915#9683])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_psr2_su@page_flip-p010.html
- shard-dg1: NOTRUN -> [SKIP][195] ([i915#9683])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-dg2: NOTRUN -> [SKIP][196] ([i915#9683])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-pr-primary-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][197] ([i915#1072] / [i915#9673] / [i915#9732]) +4 other tests skip
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_psr@fbc-pr-primary-mmap-gtt.html
* igt@kms_psr@fbc-psr2-sprite-plane-onoff:
- shard-mtlp: NOTRUN -> [SKIP][198] ([i915#9688]) +10 other tests skip
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_psr@fbc-psr2-sprite-plane-onoff.html
* igt@kms_psr@psr-sprite-plane-move:
- shard-rkl: NOTRUN -> [SKIP][199] ([i915#1072] / [i915#9732]) +12 other tests skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_psr@psr-sprite-plane-move.html
* igt@kms_psr@psr2-cursor-plane-move:
- shard-dg2: NOTRUN -> [SKIP][200] ([i915#1072] / [i915#9732]) +5 other tests skip
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_psr@psr2-cursor-plane-move.html
* igt@kms_psr@psr2-sprite-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][201] ([i915#1072] / [i915#9732]) +24 other tests skip
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_psr@psr2-sprite-mmap-gtt.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
- shard-dg1: NOTRUN -> [SKIP][202] ([i915#5289])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-dg2: NOTRUN -> [SKIP][203] ([i915#11131] / [i915#5190])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-rkl: NOTRUN -> [SKIP][204] ([i915#5289]) +1 other test skip
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-mtlp: NOTRUN -> [SKIP][205] ([i915#4235])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-dg2: NOTRUN -> [SKIP][206] ([i915#3555]) +1 other test skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_setmode@clone-exclusive-crtc.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-mtlp: NOTRUN -> [SKIP][207] ([i915#3555] / [i915#8809])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
* igt@kms_sysfs_edid_timing:
- shard-dg2: [PASS][208] -> [FAIL][209] ([IGT#2])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-11/igt@kms_sysfs_edid_timing.html
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-1/igt@kms_sysfs_edid_timing.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-dg1: NOTRUN -> [SKIP][210] ([i915#8623])
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_vblank@ts-continuation-modeset-hang@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [INCOMPLETE][211] ([i915#12274]) +1 other test incomplete
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_vblank@ts-continuation-modeset-hang@pipe-a-hdmi-a-4.html
* igt@kms_vrr@max-min:
- shard-dg2: NOTRUN -> [SKIP][212] ([i915#9906])
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_vrr@max-min.html
* igt@kms_vrr@seamless-rr-switch-virtual:
- shard-rkl: NOTRUN -> [SKIP][213] ([i915#9906])
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_vrr@seamless-rr-switch-virtual.html
- shard-dg1: NOTRUN -> [SKIP][214] ([i915#9906])
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_vrr@seamless-rr-switch-virtual.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-dg1: NOTRUN -> [SKIP][215] ([i915#2437]) +1 other test skip
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_writeback@writeback-invalid-parameters.html
- shard-rkl: NOTRUN -> [SKIP][216] ([i915#2437])
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_writeback@writeback-invalid-parameters.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-mtlp: NOTRUN -> [SKIP][217] ([i915#2437] / [i915#9412])
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@mi-rpc:
- shard-mtlp: NOTRUN -> [SKIP][218] ([i915#2434])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@perf@mi-rpc.html
* igt@perf@unprivileged-single-ctx-counters:
- shard-dg1: NOTRUN -> [SKIP][219] ([i915#2433])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@perf@unprivileged-single-ctx-counters.html
* igt@perf_pmu@rc6@other-idle-gt0:
- shard-rkl: NOTRUN -> [SKIP][220] ([i915#8516])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@perf_pmu@rc6@other-idle-gt0.html
- shard-dg1: NOTRUN -> [SKIP][221] ([i915#8516])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@perf_pmu@rc6@other-idle-gt0.html
* igt@prime_vgem@basic-read:
- shard-mtlp: NOTRUN -> [SKIP][222] ([i915#3708])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-write:
- shard-dg1: NOTRUN -> [SKIP][223] ([i915#3708]) +1 other test skip
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@prime_vgem@basic-write.html
* igt@prime_vgem@fence-write-hang:
- shard-rkl: NOTRUN -> [SKIP][224] ([i915#3708])
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@prime_vgem@fence-write-hang.html
* igt@sriov_basic@bind-unbind-vf:
- shard-rkl: NOTRUN -> [SKIP][225] ([i915#9917]) +1 other test skip
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@sriov_basic@bind-unbind-vf.html
- shard-dg1: NOTRUN -> [SKIP][226] ([i915#9917]) +1 other test skip
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@sriov_basic@bind-unbind-vf.html
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-check-all:
- shard-rkl: [FAIL][227] ([i915#12179]) -> [PASS][228]
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-3/igt@drm_fdinfo@most-busy-check-all.html
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-2/igt@drm_fdinfo@most-busy-check-all.html
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [FAIL][229] ([i915#7742]) -> [PASS][230]
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-3/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-2/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@gem_ctx_engines@invalid-engines:
- shard-tglu: [FAIL][231] ([i915#12027]) -> [PASS][232]
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-tglu-5/igt@gem_ctx_engines@invalid-engines.html
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-tglu-6/igt@gem_ctx_engines@invalid-engines.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0:
- shard-dg1: [FAIL][233] ([i915#3591]) -> [PASS][234] +1 other test pass
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
* igt@kms_atomic_transition@modeset-transition:
- shard-glk: [FAIL][235] ([i915#12238]) -> [PASS][236]
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-glk8/igt@kms_atomic_transition@modeset-transition.html
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-glk5/igt@kms_atomic_transition@modeset-transition.html
* igt@kms_atomic_transition@modeset-transition@2x-outputs:
- shard-glk: [FAIL][237] ([i915#11859]) -> [PASS][238]
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-glk8/igt@kms_atomic_transition@modeset-transition@2x-outputs.html
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-glk5/igt@kms_atomic_transition@modeset-transition@2x-outputs.html
* igt@kms_cursor_legacy@torture-bo:
- shard-tglu: [DMESG-WARN][239] ([i915#10166] / [i915#1982]) -> [PASS][240]
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-tglu-9/igt@kms_cursor_legacy@torture-bo.html
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-tglu-8/igt@kms_cursor_legacy@torture-bo.html
* igt@kms_cursor_legacy@torture-bo@pipe-a:
- shard-tglu: [DMESG-WARN][241] ([i915#10166]) -> [PASS][242]
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-tglu-9/igt@kms_cursor_legacy@torture-bo@pipe-a.html
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-tglu-8/igt@kms_cursor_legacy@torture-bo@pipe-a.html
* igt@kms_dp_aux_dev:
- shard-dg2: [SKIP][243] ([i915#1257]) -> [PASS][244]
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-3/igt@kms_dp_aux_dev.html
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_dp_aux_dev.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt:
- shard-snb: [SKIP][245] -> [PASS][246]
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-snb4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-snb5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-dg2: [SKIP][247] ([i915#9340]) -> [PASS][248]
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-6/igt@kms_pm_lpsp@kms-lpsp.html
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-2/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-rkl: [SKIP][249] ([i915#9519]) -> [PASS][250] +1 other test pass
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-5/igt@kms_pm_rpm@dpms-lpsp.html
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-2/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-dg2: [SKIP][251] ([i915#9519]) -> [PASS][252]
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-10/igt@kms_pm_rpm@modeset-non-lpsp.html
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-3/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_vblank@ts-continuation-modeset-hang:
- shard-dg2: [INCOMPLETE][253] ([i915#12276]) -> [PASS][254]
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-7/igt@kms_vblank@ts-continuation-modeset-hang.html
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-3/igt@kms_vblank@ts-continuation-modeset-hang.html
#### Warnings ####
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-rkl: [FAIL][255] ([i915#2876]) -> [FAIL][256] ([i915#2842])
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-2/igt@gem_exec_fair@basic-pace@rcs0.html
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_lmem_swapping@smem-oom:
- shard-dg2: [DMESG-WARN][257] ([i915#5493]) -> [TIMEOUT][258] ([i915#5493])
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-1/igt@gem_lmem_swapping@smem-oom.html
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-6/igt@gem_lmem_swapping@smem-oom.html
- shard-dg1: [WARN][259] -> [TIMEOUT][260] ([i915#5493])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg1-17/igt@gem_lmem_swapping@smem-oom.html
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@gem_lmem_swapping@smem-oom.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [CRASH][261] ([i915#5493]) -> [TIMEOUT][262] ([i915#5493])
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-1/igt@gem_lmem_swapping@smem-oom@lmem0.html
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-6/igt@gem_lmem_swapping@smem-oom@lmem0.html
- shard-dg1: [CRASH][263] ([i915#5493]) -> [TIMEOUT][264] ([i915#5493])
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg1-17/igt@gem_lmem_swapping@smem-oom@lmem0.html
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@i915_selftest@mock:
- shard-glk: [DMESG-WARN][265] ([i915#9311]) -> [DMESG-WARN][266] ([i915#1982] / [i915#9311])
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-glk1/igt@i915_selftest@mock.html
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-glk9/igt@i915_selftest@mock.html
- shard-dg1: [DMESG-WARN][267] ([i915#9311]) -> [DMESG-WARN][268] ([i915#1982] / [i915#9311])
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg1-16/igt@i915_selftest@mock.html
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@i915_selftest@mock.html
* igt@kms_content_protection@lic-type-0:
- shard-dg2: [TIMEOUT][269] ([i915#7173]) -> [SKIP][270] ([i915#9424])
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-11/igt@kms_content_protection@lic-type-0.html
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-1/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@uevent:
- shard-dg2: [SKIP][271] ([i915#7118] / [i915#9424]) -> [FAIL][272] ([i915#1339] / [i915#7173])
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-6/igt@kms_content_protection@uevent.html
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x170:
- shard-dg2: [SKIP][273] ([i915#11453]) -> [SKIP][274] ([i915#11453] / [i915#3359])
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-2/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-dg2: [SKIP][275] ([i915#11453] / [i915#3359]) -> [SKIP][276] ([i915#11453])
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-11/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-1/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][277] ([i915#4070] / [i915#4816]) -> [SKIP][278] ([i915#4816])
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pm_dc@dc9-dpms:
- shard-rkl: [SKIP][279] ([i915#3361]) -> [SKIP][280] ([i915#4281])
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-3/igt@kms_pm_dc@dc9-dpms.html
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_psr@fbc-psr-cursor-plane-move:
- shard-dg2: [SKIP][281] ([i915#1072] / [i915#9732]) -> [SKIP][282] ([i915#1072] / [i915#9673] / [i915#9732]) +15 other tests skip
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-2/igt@kms_psr@fbc-psr-cursor-plane-move.html
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_psr@fbc-psr-cursor-plane-move.html
* igt@kms_psr@fbc-psr-primary-page-flip:
- shard-dg2: [SKIP][283] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][284] ([i915#1072] / [i915#9732]) +9 other tests skip
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-11/igt@kms_psr@fbc-psr-primary-page-flip.html
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-1/igt@kms_psr@fbc-psr-primary-page-flip.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
- shard-dg2: [SKIP][285] ([i915#11131] / [i915#5190]) -> [SKIP][286] ([i915#11131] / [i915#4235] / [i915#5190])
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-2/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-dg2: [SKIP][287] ([i915#11131] / [i915#4235]) -> [SKIP][288] ([i915#11131])
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-11/igt@kms_rotation_crc@sprite-rotation-90.html
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-3/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: [FAIL][289] ([i915#7484]) -> [FAIL][290] ([i915#9100]) +1 other test fail
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-1/igt@perf@non-zero-reason@0-rcs0.html
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-2/igt@perf@non-zero-reason@0-rcs0.html
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[i915#10166]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10166
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#11131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11131
[i915#11453]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11453
[i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#11859]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11859
[i915#11965]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11965
[i915#11980]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11980
[i915#12027]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12027
[i915#12042]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12042
[i915#12179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12179
[i915#12238]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12238
[i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
[i915#12274]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12274
[i915#12276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12276
[i915#12291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12291
[i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
[i915#1339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1339
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#2433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#2876]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2876
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
[i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#3936]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3936
[i915#4070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4873
[i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4881
[i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
[i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
[i915#5566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
[i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6245]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6245
[i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590
[i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
[i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
[i915#7484]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7484
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
[i915#8063]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8063
[i915#8213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8292]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8292
[i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
[i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
[i915#8436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8436
[i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
[i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
[i915#8588]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8588
[i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
[i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
[i915#8812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8812
[i915#8813]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8813
[i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
[i915#8821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8821
[i915#8827]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8827
[i915#9100]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9100
[i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9808
[i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
[i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_15441 -> Patchwork_138065v6
CI-20190529: 20190529
CI_DRM_15441: 128ccc5f71d7b9d84ce8f0651aa713ae490f4990 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8029: d22cd438e6356bd7c2ee55436553cdcadd55193a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_138065v6: 128ccc5f71d7b9d84ce8f0651aa713ae490f4990 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/index.html
[-- Attachment #2: Type: text/html, Size: 99228 bytes --]
^ permalink raw reply [flat|nested] 47+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/psr: Implment WA to help reach PC10 (rev6)
2024-09-02 5:02 [PATCH] drm/i915/psr: Implment WA to help reach PC10 Suraj Kandpal
` (12 preceding siblings ...)
2024-09-27 18:54 ` ✓ Fi.CI.IGT: success " Patchwork
@ 2024-09-28 16:12 ` Patchwork
13 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2024-09-28 16:12 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 79719 bytes --]
== Series Details ==
Series: drm/i915/psr: Implment WA to help reach PC10 (rev6)
URL : https://patchwork.freedesktop.org/series/138065/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_15441_full -> Patchwork_138065v6_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (9 -> 10)
------------------------------
Additional (1): shard-snb-0
New tests
---------
New tests have been introduced between CI_DRM_15441_full and Patchwork_138065v6_full:
### New IGT tests (9) ###
* igt@kms_lease@cursor-implicit-plane@pipe-a-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [0.34] s
* igt@kms_lease@cursor-implicit-plane@pipe-b-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [0.22] s
* igt@kms_lease@cursor-implicit-plane@pipe-c-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_lease@cursor-implicit-plane@pipe-d-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [0.20] s
* igt@kms_lease@lease-unleased-connector@pipe-d-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [0.06] s
* igt@kms_lease@setcrtc-implicit-plane@pipe-a-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [0.36] s
* igt@kms_lease@setcrtc-implicit-plane@pipe-b-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [0.26] s
* igt@kms_lease@setcrtc-implicit-plane@pipe-c-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [0.19] s
* igt@kms_lease@setcrtc-implicit-plane@pipe-d-hdmi-a-4:
- Statuses : 1 pass(s)
- Exec time: [0.23] s
Known issues
------------
Here are the changes found in Patchwork_138065v6_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@object-reloc-purge-cache:
- shard-dg1: NOTRUN -> [SKIP][1] ([i915#8411])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@api_intel_bb@object-reloc-purge-cache.html
* igt@drm_fdinfo@busy-check-all@bcs0:
- shard-dg1: NOTRUN -> [SKIP][2] ([i915#8414]) +18 other tests skip
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@drm_fdinfo@busy-check-all@bcs0.html
* igt@drm_fdinfo@virtual-busy-all:
- shard-dg2: NOTRUN -> [SKIP][3] ([i915#8414])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@drm_fdinfo@virtual-busy-all.html
* igt@gem_busy@semaphore:
- shard-dg1: NOTRUN -> [SKIP][4] ([i915#3936])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_busy@semaphore.html
* igt@gem_caching@reads:
- shard-mtlp: NOTRUN -> [SKIP][5] ([i915#4873])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@gem_caching@reads.html
* igt@gem_ccs@block-copy-compressed:
- shard-mtlp: NOTRUN -> [SKIP][6] ([i915#3555] / [i915#9323])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_ccs@block-copy-compressed.html
* igt@gem_close_race@multigpu-basic-process:
- shard-rkl: NOTRUN -> [SKIP][7] ([i915#7697])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@gem_close_race@multigpu-basic-process.html
- shard-dg1: NOTRUN -> [SKIP][8] ([i915#7697])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_ctx_persistence@heartbeat-hostile:
- shard-dg1: NOTRUN -> [SKIP][9] ([i915#8555]) +1 other test skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_ctx_persistence@heartbeat-hostile.html
* igt@gem_ctx_persistence@heartbeat-many:
- shard-mtlp: NOTRUN -> [SKIP][10] ([i915#8555])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_ctx_persistence@heartbeat-many.html
* igt@gem_ctx_persistence@hostile:
- shard-dg2: NOTRUN -> [FAIL][11] ([i915#11980])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@gem_ctx_persistence@hostile.html
- shard-tglu: [PASS][12] -> [FAIL][13] ([i915#11980])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-tglu-6/igt@gem_ctx_persistence@hostile.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-tglu-5/igt@gem_ctx_persistence@hostile.html
* igt@gem_ctx_sseu@engines:
- shard-dg2: NOTRUN -> [SKIP][14] ([i915#280])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_ctx_sseu@engines.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-mtlp: NOTRUN -> [SKIP][15] ([i915#280])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_eio@hibernate:
- shard-rkl: NOTRUN -> [ABORT][16] ([i915#7975] / [i915#8213])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-3/igt@gem_eio@hibernate.html
* igt@gem_eio@kms:
- shard-dg2: [PASS][17] -> [FAIL][18] ([i915#5784])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-8/igt@gem_eio@kms.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-10/igt@gem_eio@kms.html
* igt@gem_exec_balancer@bonded-dual:
- shard-mtlp: NOTRUN -> [SKIP][19] ([i915#4771])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_exec_balancer@bonded-dual.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-rkl: NOTRUN -> [SKIP][20] ([i915#4525])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_capture@capture:
- shard-mtlp: NOTRUN -> [FAIL][21] ([i915#11965]) +1 other test fail
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_exec_capture@capture.html
* igt@gem_exec_fair@basic-deadline:
- shard-rkl: [PASS][22] -> [FAIL][23] ([i915#2846])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-3/igt@gem_exec_fair@basic-deadline.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-rkl: [PASS][24] -> [FAIL][25] ([i915#2842])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-2/igt@gem_exec_fair@basic-none@vecs0.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace:
- shard-dg2: NOTRUN -> [SKIP][26] ([i915#3539])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_exec_fair@basic-pace.html
* igt@gem_exec_fair@basic-sync:
- shard-dg1: NOTRUN -> [SKIP][27] ([i915#3539]) +1 other test skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_exec_fair@basic-sync.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-dg1: NOTRUN -> [SKIP][28] ([i915#3539] / [i915#4852]) +1 other test skip
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_flush@basic-wb-rw-before-default:
- shard-dg2: NOTRUN -> [SKIP][29] ([i915#3539] / [i915#4852])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_exec_flush@basic-wb-rw-before-default.html
* igt@gem_exec_reloc@basic-cpu-read:
- shard-rkl: NOTRUN -> [SKIP][30] ([i915#3281]) +4 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@gem_exec_reloc@basic-cpu-read.html
* igt@gem_exec_reloc@basic-gtt-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][31] ([i915#3281]) +6 other tests skip
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@gem_exec_reloc@basic-gtt-noreloc.html
* igt@gem_exec_reloc@basic-wc-cpu-noreloc:
- shard-dg1: NOTRUN -> [SKIP][32] ([i915#3281]) +10 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@gem_exec_reloc@basic-wc-cpu-noreloc.html
* igt@gem_exec_reloc@basic-write-wc-active:
- shard-dg2: NOTRUN -> [SKIP][33] ([i915#3281]) +5 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_exec_reloc@basic-write-wc-active.html
* igt@gem_exec_schedule@preempt-queue:
- shard-dg1: NOTRUN -> [SKIP][34] ([i915#4812]) +2 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_exec_schedule@preempt-queue.html
* igt@gem_exec_schedule@preempt-queue-chain:
- shard-dg2: NOTRUN -> [SKIP][35] ([i915#4537] / [i915#4812])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_exec_schedule@preempt-queue-chain.html
* igt@gem_fence_thrash@bo-write-verify-none:
- shard-dg1: NOTRUN -> [SKIP][36] ([i915#4860]) +1 other test skip
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_fence_thrash@bo-write-verify-none.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-rkl: NOTRUN -> [SKIP][37] ([i915#4613]) +3 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@massive-random:
- shard-mtlp: NOTRUN -> [SKIP][38] ([i915#4613])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_lmem_swapping@massive-random.html
* igt@gem_mmap_gtt@basic:
- shard-dg2: NOTRUN -> [SKIP][39] ([i915#4077]) +2 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@gem_mmap_gtt@basic.html
* igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
- shard-mtlp: NOTRUN -> [SKIP][40] ([i915#4077]) +4 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
* igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-dg1: NOTRUN -> [SKIP][41] ([i915#4077]) +13 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
* igt@gem_mmap_wc@fault-concurrent:
- shard-mtlp: NOTRUN -> [SKIP][42] ([i915#4083]) +1 other test skip
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_mmap_wc@fault-concurrent.html
* igt@gem_mmap_wc@write-prefaulted:
- shard-dg2: NOTRUN -> [SKIP][43] ([i915#4083]) +3 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@gem_mmap_wc@write-prefaulted.html
* igt@gem_mmap_wc@write-read:
- shard-dg1: NOTRUN -> [SKIP][44] ([i915#4083]) +4 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_mmap_wc@write-read.html
* igt@gem_pread@bench:
- shard-rkl: NOTRUN -> [SKIP][45] ([i915#3282])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@gem_pread@bench.html
- shard-dg1: NOTRUN -> [SKIP][46] ([i915#3282]) +1 other test skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_pread@bench.html
* igt@gem_pxp@create-regular-context-2:
- shard-rkl: NOTRUN -> [SKIP][47] ([i915#4270]) +2 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@gem_pxp@create-regular-context-2.html
* igt@gem_pxp@display-protected-crc:
- shard-dg2: NOTRUN -> [SKIP][48] ([i915#4270])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@gem_pxp@display-protected-crc.html
* igt@gem_pxp@reject-modify-context-protection-off-1:
- shard-mtlp: NOTRUN -> [SKIP][49] ([i915#4270])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_pxp@reject-modify-context-protection-off-1.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-dg1: NOTRUN -> [SKIP][50] ([i915#4270]) +4 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_readwrite@beyond-eob:
- shard-mtlp: NOTRUN -> [SKIP][51] ([i915#3282]) +2 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_readwrite@beyond-eob.html
* igt@gem_readwrite@write-bad-handle:
- shard-dg2: NOTRUN -> [SKIP][52] ([i915#3282]) +2 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_readwrite@write-bad-handle.html
* igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:
- shard-mtlp: NOTRUN -> [SKIP][53] ([i915#8428]) +2 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html
* igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled:
- shard-dg2: NOTRUN -> [SKIP][54] ([i915#5190] / [i915#8428]) +3 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled.html
* igt@gem_softpin@evict-snoop:
- shard-mtlp: NOTRUN -> [SKIP][55] ([i915#4885])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_softpin@evict-snoop.html
* igt@gem_softpin@evict-snoop-interruptible:
- shard-dg1: NOTRUN -> [SKIP][56] ([i915#4885])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@gem_softpin@evict-snoop-interruptible.html
* igt@gem_tiled_pread_pwrite:
- shard-dg1: NOTRUN -> [SKIP][57] ([i915#4079])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@gem_tiled_pread_pwrite.html
* igt@gem_userptr_blits@coherency-unsync:
- shard-dg2: NOTRUN -> [SKIP][58] ([i915#3297])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_userptr_blits@coherency-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-dg2: NOTRUN -> [SKIP][59] ([i915#3297] / [i915#4880])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@readonly-pwrite-unsync:
- shard-mtlp: NOTRUN -> [SKIP][60] ([i915#3297]) +1 other test skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gem_userptr_blits@readonly-pwrite-unsync.html
* igt@gem_userptr_blits@relocations:
- shard-dg2: NOTRUN -> [SKIP][61] ([i915#3281] / [i915#3297])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gem_userptr_blits@relocations.html
* igt@gen9_exec_parse@allowed-single:
- shard-rkl: NOTRUN -> [SKIP][62] ([i915#2527]) +2 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@gen9_exec_parse@allowed-single.html
- shard-glk: NOTRUN -> [ABORT][63] ([i915#5566])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-glk7/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-dg1: NOTRUN -> [SKIP][64] ([i915#2527]) +5 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@gen9_exec_parse@bb-start-cmd.html
* igt@gen9_exec_parse@bb-start-far:
- shard-dg2: NOTRUN -> [SKIP][65] ([i915#2856]) +1 other test skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@gen9_exec_parse@bb-start-far.html
* igt@gen9_exec_parse@valid-registers:
- shard-mtlp: NOTRUN -> [SKIP][66] ([i915#2856])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@gen9_exec_parse@valid-registers.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg2: [PASS][67] -> [ABORT][68] ([i915#9820])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-2/igt@i915_module_load@reload-with-fault-injection.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-10/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pipe_stress@stress-xrgb8888-ytiled:
- shard-mtlp: NOTRUN -> [SKIP][69] ([i915#8436])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html
* igt@i915_pm_freq_mult@media-freq@gt0:
- shard-rkl: NOTRUN -> [SKIP][70] ([i915#6590]) +1 other test skip
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@i915_pm_freq_mult@media-freq@gt0.html
* igt@i915_pm_rps@basic-api:
- shard-dg2: NOTRUN -> [SKIP][71] ([i915#11681] / [i915#6621])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@i915_pm_rps@basic-api.html
* igt@i915_pm_rps@thresholds-idle:
- shard-dg1: NOTRUN -> [SKIP][72] ([i915#11681])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@i915_pm_rps@thresholds-idle.html
* igt@i915_pm_rps@thresholds-idle-park:
- shard-mtlp: NOTRUN -> [SKIP][73] ([i915#11681])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@i915_pm_rps@thresholds-idle-park.html
* igt@i915_query@hwconfig_table:
- shard-dg1: NOTRUN -> [SKIP][74] ([i915#6245])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@i915_query@hwconfig_table.html
* igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- shard-dg1: NOTRUN -> [SKIP][75] ([i915#4212])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc-ccs:
- shard-dg1: NOTRUN -> [SKIP][76] ([i915#8709]) +7 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc-ccs.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-mtlp: NOTRUN -> [SKIP][77] ([i915#3555])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-snb: [PASS][78] -> [FAIL][79] ([i915#5956]) +1 other test fail
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-snb4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-snb5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-0:
- shard-dg1: NOTRUN -> [SKIP][80] ([i915#4538] / [i915#5286]) +3 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-addfb:
- shard-dg1: NOTRUN -> [SKIP][81] ([i915#5286]) +2 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_big_fb@4-tiled-addfb.html
* igt@kms_big_fb@4-tiled-addfb-size-overflow:
- shard-rkl: NOTRUN -> [SKIP][82] ([i915#5286]) +2 other tests skip
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_big_fb@4-tiled-addfb-size-overflow.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][83] ([i915#4538] / [i915#5190]) +4 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][84] ([i915#3638]) +1 other test skip
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
- shard-dg1: NOTRUN -> [SKIP][85] ([i915#3638]) +3 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][86] +13 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-dg2: NOTRUN -> [SKIP][87] ([i915#5190])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0:
- shard-dg1: NOTRUN -> [SKIP][88] ([i915#4538]) +6 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-mtlp: NOTRUN -> [SKIP][89] +11 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][90] ([i915#10307] / [i915#10434] / [i915#6095]) +6 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-2/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][91] ([i915#6095]) +107 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-4.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][92] ([i915#6095]) +93 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][93] ([i915#10307] / [i915#6095]) +173 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
- shard-mtlp: NOTRUN -> [SKIP][94] ([i915#12042])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][95] ([i915#6095]) +19 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-edp-1.html
* igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
- shard-dg1: NOTRUN -> [SKIP][96] ([i915#12042])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-rkl: NOTRUN -> [SKIP][97] ([i915#3742])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_cdclk@mode-transition-all-outputs.html
- shard-dg1: NOTRUN -> [SKIP][98] ([i915#3742])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_chamelium_frames@hdmi-cmp-planar-formats:
- shard-dg2: NOTRUN -> [SKIP][99] ([i915#7828]) +4 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html
* igt@kms_chamelium_hpd@dp-hpd-for-each-pipe:
- shard-mtlp: NOTRUN -> [SKIP][100] ([i915#7828]) +3 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_chamelium_hpd@dp-hpd-for-each-pipe.html
* igt@kms_chamelium_hpd@vga-hpd-fast:
- shard-rkl: NOTRUN -> [SKIP][101] ([i915#7828]) +5 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_chamelium_hpd@vga-hpd-fast.html
- shard-dg1: NOTRUN -> [SKIP][102] ([i915#7828]) +10 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_chamelium_hpd@vga-hpd-fast.html
* igt@kms_content_protection@content-type-change:
- shard-dg1: NOTRUN -> [SKIP][103] ([i915#9424])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_content_protection@content-type-change.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-dg1: NOTRUN -> [SKIP][104] ([i915#3299]) +1 other test skip
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@legacy:
- shard-dg2: NOTRUN -> [SKIP][105] ([i915#7118] / [i915#9424])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@mei-interface:
- shard-mtlp: NOTRUN -> [SKIP][106] ([i915#8063] / [i915#9433])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@srm:
- shard-rkl: NOTRUN -> [SKIP][107] ([i915#7118])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_content_protection@srm.html
- shard-dg1: NOTRUN -> [SKIP][108] ([i915#7116])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_content_protection@srm.html
* igt@kms_content_protection@uevent@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [FAIL][109] ([i915#1339] / [i915#7173])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_content_protection@uevent@pipe-a-dp-4.html
* igt@kms_cursor_crc@cursor-offscreen-512x170:
- shard-mtlp: NOTRUN -> [SKIP][110] ([i915#3359])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_cursor_crc@cursor-offscreen-512x170.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-dg2: NOTRUN -> [SKIP][111] ([i915#11453])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-6/igt@kms_cursor_crc@cursor-onscreen-512x170.html
- shard-dg1: NOTRUN -> [SKIP][112] ([i915#11453]) +1 other test skip
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x10:
- shard-mtlp: NOTRUN -> [SKIP][113] ([i915#3555] / [i915#8814]) +2 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-rkl: NOTRUN -> [SKIP][114] ([i915#11453])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-mtlp: NOTRUN -> [SKIP][115] ([i915#4213])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-rkl: NOTRUN -> [SKIP][116] ([i915#4103])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
- shard-dg1: NOTRUN -> [SKIP][117] ([i915#4103] / [i915#4213])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
- shard-mtlp: NOTRUN -> [SKIP][118] ([i915#9809])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@torture-bo@pipe-a:
- shard-snb: [PASS][119] -> [DMESG-WARN][120] ([i915#10166]) +1 other test dmesg-warn
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-snb2/igt@kms_cursor_legacy@torture-bo@pipe-a.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-snb6/igt@kms_cursor_legacy@torture-bo@pipe-a.html
- shard-dg2: [PASS][121] -> [DMESG-WARN][122] ([i915#10166]) +1 other test dmesg-warn
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-6/igt@kms_cursor_legacy@torture-bo@pipe-a.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-2/igt@kms_cursor_legacy@torture-bo@pipe-a.html
* igt@kms_display_modes@extended-mode-basic:
- shard-mtlp: NOTRUN -> [SKIP][123] ([i915#3555] / [i915#8827])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_display_modes@mst-extended-mode-negative:
- shard-dg1: NOTRUN -> [SKIP][124] ([i915#8588])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_display_modes@mst-extended-mode-negative.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][125] ([i915#3804])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_dither@fb-8bpc-vs-panel-8bpc:
- shard-dg2: [PASS][126] -> [SKIP][127] ([i915#3555])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-11/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-1/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
* igt@kms_dp_aux_dev:
- shard-dg1: NOTRUN -> [SKIP][128] ([i915#1257])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@kms_dp_aux_dev.html
* igt@kms_draw_crc@draw-method-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][129] ([i915#8812])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_draw_crc@draw-method-mmap-gtt.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-dg2: NOTRUN -> [SKIP][130] ([i915#3840] / [i915#9688])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-fractional-bpp-with-bpc:
- shard-dg2: NOTRUN -> [SKIP][131] ([i915#3840])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-mtlp: NOTRUN -> [SKIP][132] ([i915#3555] / [i915#3840])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_feature_discovery@display-2x:
- shard-rkl: NOTRUN -> [SKIP][133] ([i915#1839])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_feature_discovery@display-2x.html
- shard-dg1: NOTRUN -> [SKIP][134] ([i915#1839])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_feature_discovery@display-2x.html
* igt@kms_fence_pin_leak:
- shard-dg1: NOTRUN -> [SKIP][135] ([i915#4881])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_fence_pin_leak.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-dg1: NOTRUN -> [SKIP][136] ([i915#8381])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@2x-flip-vs-panning-interruptible:
- shard-dg2: NOTRUN -> [SKIP][137] +6 other tests skip
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_flip@2x-flip-vs-panning-interruptible.html
* igt@kms_flip@2x-flip-vs-rmfb:
- shard-mtlp: NOTRUN -> [SKIP][138] ([i915#3637]) +5 other tests skip
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_flip@2x-flip-vs-rmfb.html
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
- shard-dg1: NOTRUN -> [SKIP][139] ([i915#9934]) +3 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-fences-interruptible:
- shard-dg2: NOTRUN -> [SKIP][140] ([i915#8381])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_flip@flip-vs-fences-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling:
- shard-mtlp: NOTRUN -> [SKIP][141] ([i915#2672] / [i915#3555] / [i915#8813]) +2 other tests skip
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][142] ([i915#2672]) +1 other test skip
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
- shard-dg1: NOTRUN -> [SKIP][143] ([i915#2587] / [i915#2672] / [i915#3555]) +2 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][144] ([i915#2672]) +1 other test skip
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
- shard-dg1: NOTRUN -> [SKIP][145] ([i915#2587] / [i915#2672]) +3 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
- shard-dg2: NOTRUN -> [SKIP][146] ([i915#2672] / [i915#3555] / [i915#5190])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
- shard-rkl: NOTRUN -> [SKIP][147] ([i915#2672] / [i915#3555]) +1 other test skip
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
- shard-dg1: NOTRUN -> [SKIP][148] ([i915#2672] / [i915#3555])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
- shard-dg2: NOTRUN -> [SKIP][149] ([i915#2672] / [i915#3555]) +1 other test skip
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][150] ([i915#2672]) +2 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][151] ([i915#2672] / [i915#3555])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][152] ([i915#8708]) +9 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt:
- shard-mtlp: NOTRUN -> [SKIP][153] ([i915#1825]) +13 other tests skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- shard-dg1: NOTRUN -> [SKIP][154] ([i915#5439])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][155] ([i915#1825]) +16 other tests skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff:
- shard-dg1: NOTRUN -> [SKIP][156] +53 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move:
- shard-dg2: NOTRUN -> [SKIP][157] ([i915#5354]) +18 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
- shard-dg1: NOTRUN -> [SKIP][158] ([i915#3458]) +15 other tests skip
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][159] ([i915#3023]) +13 other tests skip
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][160] ([i915#8708]) +29 other tests skip
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][161] ([i915#3458]) +3 other tests skip
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][162] ([i915#8708]) +3 other tests skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_hdr@static-swap:
- shard-dg2: [PASS][163] -> [SKIP][164] ([i915#3555] / [i915#8228])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-11/igt@kms_hdr@static-swap.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-3/igt@kms_hdr@static-swap.html
- shard-mtlp: NOTRUN -> [SKIP][165] ([i915#3555] / [i915#8228])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_hdr@static-swap.html
* igt@kms_hdr@static-toggle:
- shard-dg2: NOTRUN -> [SKIP][166] ([i915#3555] / [i915#8228]) +1 other test skip
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-6/igt@kms_hdr@static-toggle.html
- shard-dg1: NOTRUN -> [SKIP][167] ([i915#3555] / [i915#8228]) +2 other tests skip
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_hdr@static-toggle.html
* igt@kms_panel_fitting@legacy:
- shard-dg1: NOTRUN -> [SKIP][168] ([i915#6301])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_panel_fitting@legacy.html
* igt@kms_plane_lowres@tiling-y:
- shard-mtlp: NOTRUN -> [SKIP][169] ([i915#3555] / [i915#8821])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_plane_lowres@tiling-y.html
* igt@kms_plane_lowres@tiling-yf:
- shard-rkl: NOTRUN -> [SKIP][170] ([i915#3555]) +2 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_plane_lowres@tiling-yf.html
- shard-dg1: NOTRUN -> [SKIP][171] ([i915#3555]) +6 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [FAIL][172] ([i915#8292])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25:
- shard-dg2: NOTRUN -> [SKIP][173] ([i915#6953] / [i915#9423]) +2 other tests skip
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_plane_scaling@planes-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d:
- shard-dg2: NOTRUN -> [SKIP][174] ([i915#12247]) +7 other tests skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c:
- shard-dg1: NOTRUN -> [INCOMPLETE][175] ([i915#12291]) +1 other test incomplete
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d:
- shard-dg2: NOTRUN -> [INCOMPLETE][176] ([i915#12291]) +1 other test incomplete
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25:
- shard-dg1: NOTRUN -> [SKIP][177] ([i915#6953])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b:
- shard-dg1: NOTRUN -> [SKIP][178] ([i915#12247]) +8 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b.html
* igt@kms_pm_dc@dc6-psr:
- shard-dg1: NOTRUN -> [SKIP][179] ([i915#9685])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-rkl: [PASS][180] -> [SKIP][181] ([i915#9340])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-4/igt@kms_pm_lpsp@kms-lpsp.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-6/igt@kms_pm_lpsp@kms-lpsp.html
- shard-dg1: NOTRUN -> [SKIP][182] ([i915#9340])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_lpsp@screens-disabled:
- shard-rkl: NOTRUN -> [SKIP][183] ([i915#8430])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_pm_lpsp@screens-disabled.html
- shard-dg1: NOTRUN -> [SKIP][184] ([i915#8430])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_pm_lpsp@screens-disabled.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-rkl: [PASS][185] -> [SKIP][186] ([i915#9519]) +2 other tests skip
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-dg2: [PASS][187] -> [SKIP][188] ([i915#9519])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-3/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_prime@basic-crc-hybrid:
- shard-dg1: NOTRUN -> [SKIP][189] ([i915#6524]) +2 other tests skip
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-dg2: NOTRUN -> [SKIP][190] ([i915#11520]) +2 other tests skip
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@fbc-overlay-plane-update-sf-dmg-area:
- shard-dg1: NOTRUN -> [SKIP][191] ([i915#11520]) +2 other tests skip
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_psr2_sf@fbc-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area@psr2-pipe-a-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][192] ([i915#9808]) +2 other tests skip
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_psr2_sf@fbc-plane-move-sf-dmg-area@psr2-pipe-a-edp-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-rkl: NOTRUN -> [SKIP][193] ([i915#11520]) +2 other tests skip
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr2_su@page_flip-p010:
- shard-rkl: NOTRUN -> [SKIP][194] ([i915#9683])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_psr2_su@page_flip-p010.html
- shard-dg1: NOTRUN -> [SKIP][195] ([i915#9683])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-dg2: NOTRUN -> [SKIP][196] ([i915#9683])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-pr-primary-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][197] ([i915#1072] / [i915#9673] / [i915#9732]) +4 other tests skip
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_psr@fbc-pr-primary-mmap-gtt.html
* igt@kms_psr@fbc-psr2-sprite-plane-onoff:
- shard-mtlp: NOTRUN -> [SKIP][198] ([i915#9688]) +10 other tests skip
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_psr@fbc-psr2-sprite-plane-onoff.html
* igt@kms_psr@psr-sprite-plane-move:
- shard-rkl: NOTRUN -> [SKIP][199] ([i915#1072] / [i915#9732]) +12 other tests skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_psr@psr-sprite-plane-move.html
* igt@kms_psr@psr2-cursor-plane-move:
- shard-dg2: NOTRUN -> [SKIP][200] ([i915#1072] / [i915#9732]) +5 other tests skip
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_psr@psr2-cursor-plane-move.html
* igt@kms_psr@psr2-sprite-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][201] ([i915#1072] / [i915#9732]) +24 other tests skip
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_psr@psr2-sprite-mmap-gtt.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
- shard-dg1: NOTRUN -> [SKIP][202] ([i915#5289])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-dg2: NOTRUN -> [SKIP][203] ([i915#11131] / [i915#5190])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-rkl: NOTRUN -> [SKIP][204] ([i915#5289]) +1 other test skip
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-mtlp: NOTRUN -> [SKIP][205] ([i915#4235])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-dg2: NOTRUN -> [SKIP][206] ([i915#3555]) +1 other test skip
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_setmode@clone-exclusive-crtc.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-mtlp: NOTRUN -> [SKIP][207] ([i915#3555] / [i915#8809])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
* igt@kms_sysfs_edid_timing:
- shard-dg2: [PASS][208] -> [FAIL][209] ([IGT#2])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-11/igt@kms_sysfs_edid_timing.html
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-1/igt@kms_sysfs_edid_timing.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-dg1: NOTRUN -> [SKIP][210] ([i915#8623])
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_vblank@ts-continuation-modeset-hang@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [INCOMPLETE][211] ([i915#12274]) +1 other test incomplete
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_vblank@ts-continuation-modeset-hang@pipe-a-hdmi-a-4.html
* igt@kms_vrr@max-min:
- shard-dg2: NOTRUN -> [SKIP][212] ([i915#9906])
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-8/igt@kms_vrr@max-min.html
* igt@kms_vrr@seamless-rr-switch-virtual:
- shard-rkl: NOTRUN -> [SKIP][213] ([i915#9906])
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@kms_vrr@seamless-rr-switch-virtual.html
- shard-dg1: NOTRUN -> [SKIP][214] ([i915#9906])
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@kms_vrr@seamless-rr-switch-virtual.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-dg1: NOTRUN -> [SKIP][215] ([i915#2437]) +1 other test skip
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@kms_writeback@writeback-invalid-parameters.html
- shard-rkl: NOTRUN -> [SKIP][216] ([i915#2437])
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_writeback@writeback-invalid-parameters.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-mtlp: NOTRUN -> [SKIP][217] ([i915#2437] / [i915#9412])
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@mi-rpc:
- shard-mtlp: NOTRUN -> [SKIP][218] ([i915#2434])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-4/igt@perf@mi-rpc.html
* igt@perf@unprivileged-single-ctx-counters:
- shard-dg1: NOTRUN -> [SKIP][219] ([i915#2433])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@perf@unprivileged-single-ctx-counters.html
* igt@perf_pmu@rc6@other-idle-gt0:
- shard-rkl: NOTRUN -> [SKIP][220] ([i915#8516])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@perf_pmu@rc6@other-idle-gt0.html
- shard-dg1: NOTRUN -> [SKIP][221] ([i915#8516])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-15/igt@perf_pmu@rc6@other-idle-gt0.html
* igt@prime_vgem@basic-read:
- shard-mtlp: NOTRUN -> [SKIP][222] ([i915#3708])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-mtlp-6/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-write:
- shard-dg1: NOTRUN -> [SKIP][223] ([i915#3708]) +1 other test skip
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@prime_vgem@basic-write.html
* igt@prime_vgem@fence-write-hang:
- shard-rkl: NOTRUN -> [SKIP][224] ([i915#3708])
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@prime_vgem@fence-write-hang.html
* igt@sriov_basic@bind-unbind-vf:
- shard-rkl: NOTRUN -> [SKIP][225] ([i915#9917]) +1 other test skip
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@sriov_basic@bind-unbind-vf.html
- shard-dg1: NOTRUN -> [SKIP][226] ([i915#9917]) +1 other test skip
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-17/igt@sriov_basic@bind-unbind-vf.html
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-check-all:
- shard-rkl: [FAIL][227] ([i915#12179]) -> [PASS][228]
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-3/igt@drm_fdinfo@most-busy-check-all.html
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-2/igt@drm_fdinfo@most-busy-check-all.html
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [FAIL][229] ([i915#7742]) -> [PASS][230]
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-3/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-2/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@gem_ctx_engines@invalid-engines:
- shard-tglu: [FAIL][231] ([i915#12027]) -> [PASS][232]
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-tglu-5/igt@gem_ctx_engines@invalid-engines.html
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-tglu-6/igt@gem_ctx_engines@invalid-engines.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0:
- shard-dg1: [FAIL][233] ([i915#3591]) -> [PASS][234] +1 other test pass
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
* igt@kms_atomic_transition@modeset-transition:
- shard-glk: [FAIL][235] ([i915#12238]) -> [PASS][236]
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-glk8/igt@kms_atomic_transition@modeset-transition.html
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-glk5/igt@kms_atomic_transition@modeset-transition.html
* igt@kms_atomic_transition@modeset-transition@2x-outputs:
- shard-glk: [FAIL][237] ([i915#11859]) -> [PASS][238]
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-glk8/igt@kms_atomic_transition@modeset-transition@2x-outputs.html
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-glk5/igt@kms_atomic_transition@modeset-transition@2x-outputs.html
* igt@kms_cursor_legacy@torture-bo:
- shard-tglu: [DMESG-WARN][239] ([i915#10166] / [i915#1982]) -> [PASS][240]
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-tglu-9/igt@kms_cursor_legacy@torture-bo.html
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-tglu-8/igt@kms_cursor_legacy@torture-bo.html
* igt@kms_cursor_legacy@torture-bo@pipe-a:
- shard-tglu: [DMESG-WARN][241] ([i915#10166]) -> [PASS][242]
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-tglu-9/igt@kms_cursor_legacy@torture-bo@pipe-a.html
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-tglu-8/igt@kms_cursor_legacy@torture-bo@pipe-a.html
* igt@kms_dp_aux_dev:
- shard-dg2: [SKIP][243] ([i915#1257]) -> [PASS][244]
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-3/igt@kms_dp_aux_dev.html
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_dp_aux_dev.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt:
- shard-snb: [SKIP][245] -> [PASS][246]
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-snb4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-snb5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-dg2: [SKIP][247] ([i915#9340]) -> [PASS][248]
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-6/igt@kms_pm_lpsp@kms-lpsp.html
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-2/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-rkl: [SKIP][249] ([i915#9519]) -> [PASS][250] +1 other test pass
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-5/igt@kms_pm_rpm@dpms-lpsp.html
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-2/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-dg2: [SKIP][251] ([i915#9519]) -> [PASS][252]
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-10/igt@kms_pm_rpm@modeset-non-lpsp.html
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-3/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_vblank@ts-continuation-modeset-hang:
- shard-dg2: [INCOMPLETE][253] ([i915#12276]) -> [PASS][254]
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-7/igt@kms_vblank@ts-continuation-modeset-hang.html
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-3/igt@kms_vblank@ts-continuation-modeset-hang.html
#### Warnings ####
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-rkl: [FAIL][255] ([i915#2876]) -> [FAIL][256] ([i915#2842])
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-2/igt@gem_exec_fair@basic-pace@rcs0.html
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-1/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_lmem_swapping@smem-oom:
- shard-dg2: [DMESG-WARN][257] ([i915#5493]) -> [TIMEOUT][258] ([i915#5493])
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-1/igt@gem_lmem_swapping@smem-oom.html
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-6/igt@gem_lmem_swapping@smem-oom.html
- shard-dg1: [WARN][259] -> [TIMEOUT][260] ([i915#5493])
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg1-17/igt@gem_lmem_swapping@smem-oom.html
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@gem_lmem_swapping@smem-oom.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [CRASH][261] ([i915#5493]) -> [TIMEOUT][262] ([i915#5493])
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-1/igt@gem_lmem_swapping@smem-oom@lmem0.html
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-6/igt@gem_lmem_swapping@smem-oom@lmem0.html
- shard-dg1: [CRASH][263] ([i915#5493]) -> [TIMEOUT][264] ([i915#5493])
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg1-17/igt@gem_lmem_swapping@smem-oom@lmem0.html
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@i915_selftest@mock:
- shard-glk: [DMESG-WARN][265] ([i915#9311]) -> [DMESG-WARN][266] ([i915#1982] / [i915#9311])
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-glk1/igt@i915_selftest@mock.html
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-glk9/igt@i915_selftest@mock.html
- shard-dg1: [DMESG-WARN][267] ([i915#9311]) -> [DMESG-WARN][268] ([i915#1982] / [i915#9311])
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg1-16/igt@i915_selftest@mock.html
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg1-13/igt@i915_selftest@mock.html
* igt@kms_content_protection@lic-type-0:
- shard-dg2: [TIMEOUT][269] ([i915#7173]) -> [SKIP][270] ([i915#9424])
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-11/igt@kms_content_protection@lic-type-0.html
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-1/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@uevent:
- shard-dg2: [SKIP][271] ([i915#7118] / [i915#9424]) -> [FAIL][272] ([i915#1339] / [i915#7173])
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-6/igt@kms_content_protection@uevent.html
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x170:
- shard-dg2: [SKIP][273] ([i915#11453]) -> [SKIP][274] ([i915#11453] / [i915#3359])
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-2/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-dg2: [SKIP][275] ([i915#11453] / [i915#3359]) -> [SKIP][276] ([i915#11453])
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-11/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-1/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][277] ([i915#4070] / [i915#4816]) -> [SKIP][278] ([i915#4816])
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pm_dc@dc9-dpms:
- shard-rkl: [SKIP][279] ([i915#3361]) -> [SKIP][280] ([i915#4281])
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-rkl-3/igt@kms_pm_dc@dc9-dpms.html
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-rkl-5/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_psr@fbc-psr-cursor-plane-move:
- shard-dg2: [SKIP][281] ([i915#1072] / [i915#9732]) -> [SKIP][282] ([i915#1072] / [i915#9673] / [i915#9732]) +15 other tests skip
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-2/igt@kms_psr@fbc-psr-cursor-plane-move.html
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_psr@fbc-psr-cursor-plane-move.html
* igt@kms_psr@fbc-psr-primary-page-flip:
- shard-dg2: [SKIP][283] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][284] ([i915#1072] / [i915#9732]) +9 other tests skip
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-11/igt@kms_psr@fbc-psr-primary-page-flip.html
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-1/igt@kms_psr@fbc-psr-primary-page-flip.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
- shard-dg2: [SKIP][285] ([i915#11131] / [i915#5190]) -> [SKIP][286] ([i915#11131] / [i915#4235] / [i915#5190])
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-2/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-11/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-dg2: [SKIP][287] ([i915#11131] / [i915#4235]) -> [SKIP][288] ([i915#11131])
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-11/igt@kms_rotation_crc@sprite-rotation-90.html
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-3/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: [FAIL][289] ([i915#7484]) -> [FAIL][290] ([i915#9100]) +1 other test fail
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_15441/shard-dg2-1/igt@perf@non-zero-reason@0-rcs0.html
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/shard-dg2-2/igt@perf@non-zero-reason@0-rcs0.html
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[i915#10166]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10166
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#11131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11131
[i915#11453]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11453
[i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
[i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
[i915#11859]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11859
[i915#11965]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11965
[i915#11980]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11980
[i915#12027]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12027
[i915#12042]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12042
[i915#12179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12179
[i915#12238]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12238
[i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
[i915#12274]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12274
[i915#12276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12276
[i915#12291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12291
[i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
[i915#1339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1339
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#2433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#2876]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2876
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
[i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#3936]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3936
[i915#4070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4873
[i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4881
[i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
[i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
[i915#5566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
[i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6245]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6245
[i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590
[i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
[i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
[i915#7484]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7484
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
[i915#8063]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8063
[i915#8213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8292]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8292
[i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
[i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
[i915#8436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8436
[i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
[i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
[i915#8588]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8588
[i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
[i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
[i915#8812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8812
[i915#8813]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8813
[i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
[i915#8821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8821
[i915#8827]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8827
[i915#9100]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9100
[i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9808
[i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
[i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_15441 -> Patchwork_138065v6
CI-20190529: 20190529
CI_DRM_15441: 128ccc5f71d7b9d84ce8f0651aa713ae490f4990 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8029: d22cd438e6356bd7c2ee55436553cdcadd55193a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_138065v6: 128ccc5f71d7b9d84ce8f0651aa713ae490f4990 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_138065v6/index.html
[-- Attachment #2: Type: text/html, Size: 99189 bytes --]
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH] drm/i915/psr: Implement WA to help reach PC10
@ 2024-10-03 14:53 Suraj Kandpal
2024-10-06 16:53 ` Suraj Kandpal
2024-10-17 7:54 ` Suraj Kandpal
0 siblings, 2 replies; 47+ messages in thread
From: Suraj Kandpal @ 2024-10-03 14:53 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: uma.shankar, jouni.hogander, Suraj Kandpal
To reach PC10 when PKG_C_LATENCY is configure we must do the following
things
1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
2) Allow PSR2 deep sleep when DC5 can be entered
3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
not happening.
WA: 22019444797
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/display/intel_psr.c | 108 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_psr.h | 2 +
4 files changed, 115 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index fe1ded6707f9..cbd71c136c8d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4368,6 +4368,9 @@ static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
}
+ if (intel_encoder_is_dp(encoder))
+ intel_psr_compute_config_late(encoder, crtc_state);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 17fc21f6ae36..7fb3eeb0e0f2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1576,6 +1576,9 @@ struct intel_psr {
#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
u32 debug;
+ bool is_dpkgc_configured;
+ bool is_dc5_entry_possible;
+ bool is_wa_delayed_vblank_limit;
bool sink_support;
bool source_support;
bool enabled;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 8e9f068b9b2b..2136737429b4 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -26,6 +26,7 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_damage_helper.h>
#include <drm/drm_debugfs.h>
+#include <drm/drm_vblank.h>
#include "i915_drv.h"
#include "i915_reg.h"
@@ -896,6 +897,76 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
return idle_frames;
}
+static bool
+intel_psr_check_wa_delayed_vblank(const struct drm_display_mode *adjusted_mode)
+{
+ return (adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay) >= 6;
+}
+
+/*
+ * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
+ * VRR is not enabled
+ */
+static bool intel_psr_is_dpkgc_configured(struct intel_display *display,
+ struct intel_crtc_state *crtc_state)
+{
+ if (DISPLAY_VER(display) < 20 || crtc_state->vrr.enable)
+ return false;
+
+ return true;
+}
+
+static bool wa_22019444797_psr1_check(const struct intel_crtc_state *crtc_state,
+ struct intel_psr *psr)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ return DISPLAY_VER(display) == 20 && psr->is_dpkgc_configured &&
+ (psr->is_wa_delayed_vblank_limit || !psr->is_dc5_entry_possible) &&
+ !crtc_state->has_sel_update && !crtc_state->has_panel_replay;
+}
+
+/*
+ * DC5 entry is only possible if vblank interrupt is disabled
+ * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
+ * enabled encoders.
+ */
+static bool
+intel_psr_is_dc5_entry_possible(struct intel_display *display,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *intel_crtc;
+
+ if ((display->power.domains.target_dc_state &
+ DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
+ return false;
+
+ if (!crtc_state->has_psr && !crtc_state->has_sel_update &&
+ !crtc_state->has_panel_replay)
+ return false;
+
+ for_each_intel_crtc(display->drm, intel_crtc) {
+ struct drm_crtc *crtc = &intel_crtc->base;
+ struct drm_vblank_crtc *vblank;
+ struct intel_encoder *encoder;
+
+ if (!intel_crtc->active)
+ continue;
+
+ vblank = drm_crtc_vblank_crtc(crtc);
+
+ if (vblank->enabled)
+ return false;
+
+ for_each_encoder_on_crtc(display->drm, crtc, encoder)
+ if (encoder->type != INTEL_OUTPUT_EDP ||
+ !CAN_PSR(enc_to_intel_dp(encoder)))
+ return false;
+ }
+
+ return true;
+}
+
static void hsw_activate_psr1(struct intel_dp *intel_dp)
{
struct intel_display *display = to_intel_display(intel_dp);
@@ -1008,7 +1079,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
u32 val = EDP_PSR2_ENABLE;
u32 psr_val = 0;
- val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ /*
+ * Wa_22019444797
+ * TODO: Disable idle frames when vblank gets enabled while
+ * PSR2 is enabled
+ */
+ if (DISPLAY_VER(dev_priv) != 20 ||
+ !intel_dp->psr.is_dpkgc_configured ||
+ intel_dp->psr.is_dc5_entry_possible)
+ val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
val |= EDP_SU_TRACK_ENABLE;
@@ -1686,6 +1765,24 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
}
+void intel_psr_compute_config_late(struct intel_encoder *intel_encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(intel_encoder);
+ struct intel_dp *dp = enc_to_intel_dp(intel_encoder);
+
+ if (DISPLAY_VER(display) == 20) {
+ mutex_lock(&dp->psr.lock);
+ dp->psr.is_dpkgc_configured =
+ intel_psr_is_dpkgc_configured(display, crtc_state);
+ dp->psr.is_dc5_entry_possible =
+ intel_psr_is_dc5_entry_possible(display, crtc_state);
+ dp->psr.is_wa_delayed_vblank_limit =
+ intel_psr_check_wa_delayed_vblank(&crtc_state->hw.adjusted_mode);
+ mutex_unlock(&dp->psr.lock);
+ }
+}
+
void intel_psr_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
@@ -2742,6 +2839,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
* - Changing between PSR versions
* - Region Early Transport changing
* - Display WA #1136: skl, bxt
+ * - Display WA_22019444797
*/
needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
needs_to_disable |= !new_crtc_state->has_psr;
@@ -2751,6 +2849,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
psr->su_region_et_enabled;
needs_to_disable |= DISPLAY_VER(i915) < 11 &&
new_crtc_state->wm_level_disabled;
+ /* TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled */
+ needs_to_disable |= wa_22019444797_psr1_check(new_crtc_state, psr);
if (psr->enabled && needs_to_disable)
intel_psr_disable_locked(intel_dp);
@@ -2791,6 +2891,12 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
keep_disabled |= DISPLAY_VER(display) < 11 &&
crtc_state->wm_level_disabled;
+ /*
+ * Wa_22019444797
+ * TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled
+ */
+ keep_disabled |= wa_22019444797_psr1_check(crtc_state, psr);
+
if (!psr->enabled && !keep_disabled)
intel_psr_enable_locked(intel_dp, crtc_state);
else if (psr->enabled && !crtc_state->wm_level_disabled)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 5f26f61f82aa..e0fa04952393 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -47,6 +47,8 @@ void intel_psr_init(struct intel_dp *intel_dp);
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state);
+void intel_psr_compute_config_late(struct intel_encoder *intel_encoder,
+ struct intel_crtc_state *crtc_state);
void intel_psr_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
--
2.43.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/i915/psr: Implement WA to help reach PC10
2024-10-03 14:53 [PATCH] drm/i915/psr: Implement WA to help reach PC10 Suraj Kandpal
@ 2024-10-06 16:53 ` Suraj Kandpal
2024-10-17 7:54 ` Suraj Kandpal
1 sibling, 0 replies; 47+ messages in thread
From: Suraj Kandpal @ 2024-10-06 16:53 UTC (permalink / raw)
To: intel-gfx; +Cc: Suraj Kandpal
To reach PC10 when PKG_C_LATENCY is configure we must do the following
things
1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
2) Allow PSR2 deep sleep when DC5 can be entered
3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
not happening.
--v2
-Add debug prints
WA: 22019444797
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/display/intel_psr.c | 117 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_psr.h | 2 +
4 files changed, 124 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index fe1ded6707f9..cbd71c136c8d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4368,6 +4368,9 @@ static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
}
+ if (intel_encoder_is_dp(encoder))
+ intel_psr_compute_config_late(encoder, crtc_state);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 17fc21f6ae36..7fb3eeb0e0f2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1576,6 +1576,9 @@ struct intel_psr {
#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
u32 debug;
+ bool is_dpkgc_configured;
+ bool is_dc5_entry_possible;
+ bool is_wa_delayed_vblank_limit;
bool sink_support;
bool source_support;
bool enabled;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 8e9f068b9b2b..9b77045df228 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -26,6 +26,7 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_damage_helper.h>
#include <drm/drm_debugfs.h>
+#include <drm/drm_vblank.h>
#include "i915_drv.h"
#include "i915_reg.h"
@@ -896,6 +897,82 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
return idle_frames;
}
+static bool
+intel_psr_check_wa_delayed_vblank(const struct drm_display_mode *adjusted_mode)
+{
+ return (adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay) >= 6;
+}
+
+/*
+ * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
+ * VRR is not enabled
+ */
+static bool intel_psr_is_dpkgc_configured(struct intel_display *display,
+ struct intel_crtc_state *crtc_state)
+{
+ if (DISPLAY_VER(display) < 20 || crtc_state->vrr.enable)
+ return false;
+
+ return true;
+}
+
+static bool wa_22019444797_psr1_check(const struct intel_crtc_state *crtc_state,
+ struct intel_psr *psr)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ if (DISPLAY_VER(display) == 20 && psr->is_dpkgc_configured &&
+ (psr->is_wa_delayed_vblank_limit || !psr->is_dc5_entry_possible) &&
+ !crtc_state->has_sel_update && !crtc_state->has_panel_replay) {
+ drm_dbg_kms(display->drm,
+ "Wa 22019444797 requirement met PSR1 disabled\n");
+ return true;
+ } else {
+ return false;
+ }
+}
+
+/*
+ * DC5 entry is only possible if vblank interrupt is disabled
+ * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
+ * enabled encoders.
+ */
+static bool
+intel_psr_is_dc5_entry_possible(struct intel_display *display,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *intel_crtc;
+
+ if ((display->power.domains.target_dc_state &
+ DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
+ return false;
+
+ if (!crtc_state->has_psr && !crtc_state->has_sel_update &&
+ !crtc_state->has_panel_replay)
+ return false;
+
+ for_each_intel_crtc(display->drm, intel_crtc) {
+ struct drm_crtc *crtc = &intel_crtc->base;
+ struct drm_vblank_crtc *vblank;
+ struct intel_encoder *encoder;
+
+ if (!intel_crtc->active)
+ continue;
+
+ vblank = drm_crtc_vblank_crtc(crtc);
+
+ if (vblank->enabled)
+ return false;
+
+ for_each_encoder_on_crtc(display->drm, crtc, encoder)
+ if (encoder->type != INTEL_OUTPUT_EDP ||
+ !CAN_PSR(enc_to_intel_dp(encoder)))
+ return false;
+ }
+
+ return true;
+}
+
static void hsw_activate_psr1(struct intel_dp *intel_dp)
{
struct intel_display *display = to_intel_display(intel_dp);
@@ -1008,7 +1085,18 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
u32 val = EDP_PSR2_ENABLE;
u32 psr_val = 0;
- val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ /*
+ * Wa_22019444797
+ * TODO: Disable idle frames when vblank gets enabled while
+ * PSR2 is enabled
+ */
+ if (DISPLAY_VER(dev_priv) != 20 ||
+ !intel_dp->psr.is_dpkgc_configured ||
+ intel_dp->psr.is_dc5_entry_possible)
+ val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ else
+ drm_dbg_kms(display->drm,
+ "Wa 22019444797 requirement met PSR2 deep sleep disabled\n");
if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
val |= EDP_SU_TRACK_ENABLE;
@@ -1686,6 +1774,24 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
}
+void intel_psr_compute_config_late(struct intel_encoder *intel_encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(intel_encoder);
+ struct intel_dp *dp = enc_to_intel_dp(intel_encoder);
+
+ if (DISPLAY_VER(display) == 20) {
+ mutex_lock(&dp->psr.lock);
+ dp->psr.is_dpkgc_configured =
+ intel_psr_is_dpkgc_configured(display, crtc_state);
+ dp->psr.is_dc5_entry_possible =
+ intel_psr_is_dc5_entry_possible(display, crtc_state);
+ dp->psr.is_wa_delayed_vblank_limit =
+ intel_psr_check_wa_delayed_vblank(&crtc_state->hw.adjusted_mode);
+ mutex_unlock(&dp->psr.lock);
+ }
+}
+
void intel_psr_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
@@ -2742,6 +2848,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
* - Changing between PSR versions
* - Region Early Transport changing
* - Display WA #1136: skl, bxt
+ * - Display WA_22019444797
*/
needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
needs_to_disable |= !new_crtc_state->has_psr;
@@ -2751,6 +2858,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
psr->su_region_et_enabled;
needs_to_disable |= DISPLAY_VER(i915) < 11 &&
new_crtc_state->wm_level_disabled;
+ /* TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled */
+ needs_to_disable |= wa_22019444797_psr1_check(new_crtc_state, psr);
if (psr->enabled && needs_to_disable)
intel_psr_disable_locked(intel_dp);
@@ -2791,6 +2900,12 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
keep_disabled |= DISPLAY_VER(display) < 11 &&
crtc_state->wm_level_disabled;
+ /*
+ * Wa_22019444797
+ * TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled
+ */
+ keep_disabled |= wa_22019444797_psr1_check(crtc_state, psr);
+
if (!psr->enabled && !keep_disabled)
intel_psr_enable_locked(intel_dp, crtc_state);
else if (psr->enabled && !crtc_state->wm_level_disabled)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 5f26f61f82aa..e0fa04952393 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -47,6 +47,8 @@ void intel_psr_init(struct intel_dp *intel_dp);
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state);
+void intel_psr_compute_config_late(struct intel_encoder *intel_encoder,
+ struct intel_crtc_state *crtc_state);
void intel_psr_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
--
2.43.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/i915/psr: Implement WA to help reach PC10
2024-10-03 14:53 [PATCH] drm/i915/psr: Implement WA to help reach PC10 Suraj Kandpal
2024-10-06 16:53 ` Suraj Kandpal
@ 2024-10-17 7:54 ` Suraj Kandpal
1 sibling, 0 replies; 47+ messages in thread
From: Suraj Kandpal @ 2024-10-17 7:54 UTC (permalink / raw)
To: intel-gfx; +Cc: uma.shankar, jouni.hogander, jani.nikula, Suraj Kandpal
To reach PC10 when PKG_C_LATENCY is configure we must do the following
things
1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
2) Allow PSR2 deep sleep when DC5 can be entered
3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
not happening.
--v2
-Add debug prints
--v3
-use crtc as variable name for intel_crtc [Jani]
-use encoder as variable name for intel_encoder [Jani]
-No changes in intel_dp in compute_config_late [Jani]
WA: 22019444797
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
.../drm/i915/display/intel_display_types.h | 6 +
drivers/gpu/drm/i915/display/intel_psr.c | 131 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_psr.h | 2 +
4 files changed, 141 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index fe1ded6707f9..cbd71c136c8d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4368,6 +4368,9 @@ static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
}
+ if (intel_encoder_is_dp(encoder))
+ intel_psr_compute_config_late(encoder, crtc_state);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 2bb1fa64da2f..c980f21a192d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1089,6 +1089,9 @@ struct intel_crtc_state {
bool req_psr2_sdp_prior_scanline;
bool has_panel_replay;
bool wm_level_disabled;
+ bool is_wa_delayed_vblank_limit;
+ bool is_dpkgc_configured;
+ bool is_dc5_entry_possible;
u32 dc3co_exitline;
u16 su_y_granularity;
@@ -1587,6 +1590,9 @@ struct intel_psr {
#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
u32 debug;
+ bool is_dpkgc_configured;
+ bool is_dc5_entry_possible;
+ bool is_wa_delayed_vblank_limit;
bool sink_support;
bool source_support;
bool enabled;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 3b20325b3f6a..9f6dcac64dc9 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -26,6 +26,7 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_damage_helper.h>
#include <drm/drm_debugfs.h>
+#include <drm/drm_vblank.h>
#include "i915_drv.h"
#include "i915_reg.h"
@@ -896,6 +897,81 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
return idle_frames;
}
+static bool
+intel_psr_check_wa_delayed_vblank(const struct drm_display_mode *adjusted_mode)
+{
+ return (adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay) >= 6;
+}
+
+/*
+ * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
+ * VRR is not enabled
+ */
+static bool intel_psr_is_dpkgc_configured(struct intel_display *display,
+ struct intel_crtc_state *crtc_state)
+{
+ if (DISPLAY_VER(display) < 20 || crtc_state->vrr.enable)
+ return false;
+
+ return true;
+}
+
+static bool wa_22019444797_psr1_check(const struct intel_crtc_state *crtc_state,
+ struct intel_psr *psr)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ if (DISPLAY_VER(display) == 20 && psr->is_dpkgc_configured &&
+ (psr->is_wa_delayed_vblank_limit || !psr->is_dc5_entry_possible) &&
+ !crtc_state->has_sel_update && !crtc_state->has_panel_replay) {
+ drm_dbg_kms(display->drm,
+ "Wa 22019444797 requirement met PSR1 disabled\n");
+ return true;
+ } else {
+ return false;
+ }
+}
+
+/*
+ * DC5 entry is only possible if vblank interrupt is disabled
+ * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
+ * enabled encoders.
+ */
+static bool
+intel_psr_is_dc5_entry_possible(struct intel_display *display,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc;
+
+ if ((display->power.domains.target_dc_state &
+ DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
+ return false;
+
+ if (!crtc_state->has_psr && !crtc_state->has_sel_update &&
+ !crtc_state->has_panel_replay)
+ return false;
+
+ for_each_intel_crtc(display->drm, crtc) {
+ struct drm_vblank_crtc *vblank;
+ struct intel_encoder *encoder;
+
+ if (!crtc->active)
+ continue;
+
+ vblank = drm_crtc_vblank_crtc(&crtc->base);
+
+ if (vblank->enabled)
+ return false;
+
+ for_each_encoder_on_crtc(display->drm, &crtc->base, encoder)
+ if (encoder->type != INTEL_OUTPUT_EDP ||
+ !CAN_PSR(enc_to_intel_dp(encoder)))
+ return false;
+ }
+
+ return true;
+}
+
static void hsw_activate_psr1(struct intel_dp *intel_dp)
{
struct intel_display *display = to_intel_display(intel_dp);
@@ -1008,7 +1084,18 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
u32 val = EDP_PSR2_ENABLE;
u32 psr_val = 0;
- val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ /*
+ * Wa_22019444797
+ * TODO: Disable idle frames when vblank gets enabled while
+ * PSR2 is enabled
+ */
+ if (DISPLAY_VER(dev_priv) != 20 ||
+ !intel_dp->psr.is_dpkgc_configured ||
+ intel_dp->psr.is_dc5_entry_possible)
+ val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ else
+ drm_dbg_kms(display->drm,
+ "Wa 22019444797 requirement met PSR2 deep sleep disabled\n");
if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
val |= EDP_SU_TRACK_ENABLE;
@@ -1686,6 +1773,21 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
}
+void intel_psr_compute_config_late(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(encoder);
+
+ if (DISPLAY_VER(display) == 20) {
+ crtc_state->is_dpkgc_configured =
+ intel_psr_is_dpkgc_configured(display, crtc_state);
+ crtc_state->is_dc5_entry_possible =
+ intel_psr_is_dc5_entry_possible(display, crtc_state);
+ crtc_state->is_wa_delayed_vblank_limit =
+ intel_psr_check_wa_delayed_vblank(&crtc_state->hw.adjusted_mode);
+ }
+}
+
void intel_psr_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
@@ -2757,6 +2859,22 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
return 0;
}
+static void
+wa_22019444797_fill_psr_params(const struct intel_crtc_state *crtc_state,
+ struct intel_psr *psr)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ if (DISPLAY_VER(display) == 20) {
+ psr->is_dpkgc_configured =
+ crtc_state->is_dpkgc_configured;
+ psr->is_dc5_entry_possible =
+ crtc_state->is_dc5_entry_possible;
+ psr->is_wa_delayed_vblank_limit =
+ crtc_state->is_wa_delayed_vblank_limit;
+ }
+}
+
void intel_psr_pre_plane_update(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -2779,6 +2897,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
mutex_lock(&psr->lock);
+ wa_22019444797_fill_psr_params(new_crtc_state, psr);
+
/*
* Reasons to disable:
* - PSR disabled in new state
@@ -2786,6 +2906,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
* - Changing between PSR versions
* - Region Early Transport changing
* - Display WA #1136: skl, bxt
+ * - Display WA_22019444797
*/
needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
needs_to_disable |= !new_crtc_state->has_psr;
@@ -2795,6 +2916,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
psr->su_region_et_enabled;
needs_to_disable |= DISPLAY_VER(i915) < 11 &&
new_crtc_state->wm_level_disabled;
+ /* TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled */
+ needs_to_disable |= wa_22019444797_psr1_check(new_crtc_state, psr);
if (psr->enabled && needs_to_disable)
intel_psr_disable_locked(intel_dp);
@@ -2835,6 +2958,12 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
keep_disabled |= DISPLAY_VER(display) < 11 &&
crtc_state->wm_level_disabled;
+ /*
+ * Wa_22019444797
+ * TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled
+ */
+ keep_disabled |= wa_22019444797_psr1_check(crtc_state, psr);
+
if (!psr->enabled && !keep_disabled)
intel_psr_enable_locked(intel_dp, crtc_state);
else if (psr->enabled && !crtc_state->wm_level_disabled)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 5f26f61f82aa..e0fa04952393 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -47,6 +47,8 @@ void intel_psr_init(struct intel_dp *intel_dp);
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state);
+void intel_psr_compute_config_late(struct intel_encoder *intel_encoder,
+ struct intel_crtc_state *crtc_state);
void intel_psr_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
--
2.47.0
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH] drm/i915/psr: Implement WA to help reach PC10
@ 2024-11-04 9:12 Suraj Kandpal
2024-11-04 14:18 ` Jani Nikula
0 siblings, 1 reply; 47+ messages in thread
From: Suraj Kandpal @ 2024-11-04 9:12 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: jouni.hogander, Suraj Kandpal
To reach PC10 when PKG_C_LATENCY is configure we must do the following
things
1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
2) Allow PSR2 deep sleep when DC5 can be entered
3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
not happening.
--v2
-Add debug prints
--v3
-use crtc as variable name for intel_crtc [Jani]
-use encoder as variable name for intel_encoder [Jani]
-No changes in intel_dp in compute_config_late [Jani]
--v4
-Remove "check" from naming [Jani]
-Remove intel_encoder variable which is not necessary in
compute_config_late
WA: 22019444797
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
.../drm/i915/display/intel_display_types.h | 6 +
drivers/gpu/drm/i915/display/intel_psr.c | 130 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_psr.h | 1 +
4 files changed, 139 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 0535daed6a9f..8e0fb6bd6211 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4403,6 +4403,9 @@ static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
}
+ if (intel_encoder_is_dp(encoder))
+ intel_psr_compute_config_late(crtc_state);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ff6eb93337e0..dd5f3ea90e5b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1089,6 +1089,9 @@ struct intel_crtc_state {
bool req_psr2_sdp_prior_scanline;
bool has_panel_replay;
bool wm_level_disabled;
+ bool is_wa_delayed_vblank_limit;
+ bool is_dpkgc_configured;
+ bool is_dc5_entry_possible;
u32 dc3co_exitline;
u16 su_y_granularity;
@@ -1587,6 +1590,9 @@ struct intel_psr {
#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
u32 debug;
+ bool is_dpkgc_configured;
+ bool is_dc5_entry_possible;
+ bool is_wa_delayed_vblank_limit;
bool sink_support;
bool source_support;
bool enabled;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index a784c0b81556..b93358a82aa3 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -26,6 +26,7 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_damage_helper.h>
#include <drm/drm_debugfs.h>
+#include <drm/drm_vblank.h>
#include "i915_drv.h"
#include "i915_reg.h"
@@ -898,6 +899,81 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
return idle_frames;
}
+static bool
+intel_psr_wa_delayed_vblank(const struct drm_display_mode *adjusted_mode)
+{
+ return (adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay) >= 6;
+}
+
+/*
+ * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
+ * VRR is not enabled
+ */
+static bool intel_psr_is_dpkgc_configured(struct intel_display *display,
+ struct intel_crtc_state *crtc_state)
+{
+ if (DISPLAY_VER(display) < 20 || crtc_state->vrr.enable)
+ return false;
+
+ return true;
+}
+
+static bool wa_22019444797_psr1(const struct intel_crtc_state *crtc_state,
+ struct intel_psr *psr)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ if (DISPLAY_VER(display) == 20 && psr->is_dpkgc_configured &&
+ (psr->is_wa_delayed_vblank_limit || !psr->is_dc5_entry_possible) &&
+ !crtc_state->has_sel_update && !crtc_state->has_panel_replay) {
+ drm_dbg_kms(display->drm,
+ "Wa 22019444797 requirement met PSR1 disabled\n");
+ return true;
+ } else {
+ return false;
+ }
+}
+
+/*
+ * DC5 entry is only possible if vblank interrupt is disabled
+ * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
+ * enabled encoders.
+ */
+static bool
+intel_psr_is_dc5_entry_possible(struct intel_display *display,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc;
+
+ if ((display->power.domains.target_dc_state &
+ DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
+ return false;
+
+ if (!crtc_state->has_psr && !crtc_state->has_sel_update &&
+ !crtc_state->has_panel_replay)
+ return false;
+
+ for_each_intel_crtc(display->drm, crtc) {
+ struct drm_vblank_crtc *vblank;
+ struct intel_encoder *encoder;
+
+ if (!crtc->active)
+ continue;
+
+ vblank = drm_crtc_vblank_crtc(&crtc->base);
+
+ if (vblank->enabled)
+ return false;
+
+ for_each_encoder_on_crtc(display->drm, &crtc->base, encoder)
+ if (encoder->type != INTEL_OUTPUT_EDP ||
+ !CAN_PSR(enc_to_intel_dp(encoder)))
+ return false;
+ }
+
+ return true;
+}
+
static void hsw_activate_psr1(struct intel_dp *intel_dp)
{
struct intel_display *display = to_intel_display(intel_dp);
@@ -1010,7 +1086,18 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
u32 val = EDP_PSR2_ENABLE;
u32 psr_val = 0;
- val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ /*
+ * Wa_22019444797
+ * TODO: Disable idle frames when vblank gets enabled while
+ * PSR2 is enabled
+ */
+ if (DISPLAY_VER(dev_priv) != 20 ||
+ !intel_dp->psr.is_dpkgc_configured ||
+ intel_dp->psr.is_dc5_entry_possible)
+ val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ else
+ drm_dbg_kms(display->drm,
+ "Wa 22019444797 requirement met PSR2 deep sleep disabled\n");
if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
val |= EDP_SU_TRACK_ENABLE;
@@ -1692,6 +1779,20 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
}
+void intel_psr_compute_config_late(struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ if (DISPLAY_VER(display) == 20) {
+ crtc_state->is_dpkgc_configured =
+ intel_psr_is_dpkgc_configured(display, crtc_state);
+ crtc_state->is_dc5_entry_possible =
+ intel_psr_is_dc5_entry_possible(display, crtc_state);
+ crtc_state->is_wa_delayed_vblank_limit =
+ intel_psr_wa_delayed_vblank(&crtc_state->hw.adjusted_mode);
+ }
+}
+
void intel_psr_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
@@ -2774,6 +2875,22 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
return 0;
}
+static void
+wa_22019444797_fill_psr_params(const struct intel_crtc_state *crtc_state,
+ struct intel_psr *psr)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ if (DISPLAY_VER(display) == 20) {
+ psr->is_dpkgc_configured =
+ crtc_state->is_dpkgc_configured;
+ psr->is_dc5_entry_possible =
+ crtc_state->is_dc5_entry_possible;
+ psr->is_wa_delayed_vblank_limit =
+ crtc_state->is_wa_delayed_vblank_limit;
+ }
+}
+
void intel_psr_pre_plane_update(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
@@ -2796,6 +2913,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
mutex_lock(&psr->lock);
+ wa_22019444797_fill_psr_params(new_crtc_state, psr);
+
/*
* Reasons to disable:
* - PSR disabled in new state
@@ -2803,6 +2922,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
* - Changing between PSR versions
* - Region Early Transport changing
* - Display WA #1136: skl, bxt
+ * - Display WA_22019444797
*/
needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
needs_to_disable |= !new_crtc_state->has_psr;
@@ -2812,6 +2932,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
psr->su_region_et_enabled;
needs_to_disable |= DISPLAY_VER(i915) < 11 &&
new_crtc_state->wm_level_disabled;
+ /* TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled */
+ needs_to_disable |= wa_22019444797_psr1(new_crtc_state, psr);
if (psr->enabled && needs_to_disable)
intel_psr_disable_locked(intel_dp);
@@ -2852,6 +2974,12 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
keep_disabled |= DISPLAY_VER(display) < 11 &&
crtc_state->wm_level_disabled;
+ /*
+ * Wa_22019444797
+ * TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled
+ */
+ keep_disabled |= wa_22019444797_psr1(crtc_state, psr);
+
if (!psr->enabled && !keep_disabled)
intel_psr_enable_locked(intel_dp, crtc_state);
else if (psr->enabled && !crtc_state->wm_level_disabled)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 956be263c09e..0923a2f74901 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -47,6 +47,7 @@ void intel_psr_init(struct intel_dp *intel_dp);
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state);
+void intel_psr_compute_config_late(struct intel_crtc_state *crtc_state);
void intel_psr_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
--
2.34.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH] drm/i915/psr: Implement WA to help reach PC10
2024-11-04 9:12 Suraj Kandpal
@ 2024-11-04 14:18 ` Jani Nikula
2024-11-06 8:18 ` Kandpal, Suraj
0 siblings, 1 reply; 47+ messages in thread
From: Jani Nikula @ 2024-11-04 14:18 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx; +Cc: jouni.hogander, Suraj Kandpal
On Mon, 04 Nov 2024, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> To reach PC10 when PKG_C_LATENCY is configure we must do the following
> things
> 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
> 2) Allow PSR2 deep sleep when DC5 can be entered
> 3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
> eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
> not happening.
>
> --v2
> -Add debug prints
>
> --v3
> -use crtc as variable name for intel_crtc [Jani]
> -use encoder as variable name for intel_encoder [Jani]
> -No changes in intel_dp in compute_config_late [Jani]
>
> --v4
> -Remove "check" from naming [Jani]
> -Remove intel_encoder variable which is not necessary in
> compute_config_late
>
> WA: 22019444797
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
> .../drm/i915/display/intel_display_types.h | 6 +
> drivers/gpu/drm/i915/display/intel_psr.c | 130 +++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_psr.h | 1 +
> 4 files changed, 139 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 0535daed6a9f..8e0fb6bd6211 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4403,6 +4403,9 @@ static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
> port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
> }
>
> + if (intel_encoder_is_dp(encoder))
> + intel_psr_compute_config_late(crtc_state);
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index ff6eb93337e0..dd5f3ea90e5b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1089,6 +1089,9 @@ struct intel_crtc_state {
> bool req_psr2_sdp_prior_scanline;
> bool has_panel_replay;
> bool wm_level_disabled;
> + bool is_wa_delayed_vblank_limit;
> + bool is_dpkgc_configured;
> + bool is_dc5_entry_possible;
> u32 dc3co_exitline;
> u16 su_y_granularity;
>
> @@ -1587,6 +1590,9 @@ struct intel_psr {
> #define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
>
> u32 debug;
> + bool is_dpkgc_configured;
> + bool is_dc5_entry_possible;
> + bool is_wa_delayed_vblank_limit;
I don't understand why all of these need to be duplicated in struct
intel_psr.
I get that you don't necessarily have access to the crtc state in all
circumstances. But doesn't the workaround basically boil down to using 0
idle frames in hsw_activate_psr2()?
> bool sink_support;
> bool source_support;
> bool enabled;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index a784c0b81556..b93358a82aa3 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -26,6 +26,7 @@
> #include <drm/drm_atomic_helper.h>
> #include <drm/drm_damage_helper.h>
> #include <drm/drm_debugfs.h>
> +#include <drm/drm_vblank.h>
>
> #include "i915_drv.h"
> #include "i915_reg.h"
> @@ -898,6 +899,81 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
> return idle_frames;
> }
>
> +static bool
> +intel_psr_wa_delayed_vblank(const struct drm_display_mode *adjusted_mode)
> +{
> + return (adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay) >= 6;
> +}
> +
> +/*
> + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> + * VRR is not enabled
> + */
> +static bool intel_psr_is_dpkgc_configured(struct intel_display *display,
> + struct intel_crtc_state *crtc_state)
> +{
> + if (DISPLAY_VER(display) < 20 || crtc_state->vrr.enable)
> + return false;
> +
> + return true;
IOW,
return DISPLAY_VER(display) >= 20 && !crtc_state->vrr.enable;
> +}
> +
> +static bool wa_22019444797_psr1(const struct intel_crtc_state *crtc_state,
> + struct intel_psr *psr)
I really dislike function names like this. It doesn't say *anything* to
the reader. It's hard to pronounce. It's hard to talk about. I don't
know what it means.
Something like psr1_needs_wa_22019444797() is already much better, even
if it still contains the wa number. It tells what it's about, and the
reader doesn't have to try to guess.
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> +
> + if (DISPLAY_VER(display) == 20 && psr->is_dpkgc_configured &&
> + (psr->is_wa_delayed_vblank_limit || !psr->is_dc5_entry_possible) &&
> + !crtc_state->has_sel_update && !crtc_state->has_panel_replay) {
> + drm_dbg_kms(display->drm,
> + "Wa 22019444797 requirement met PSR1 disabled\n");
That debug log message is not a sentence. Maybe something like,
"Disabling PSR1 due to wa 22019444797\n".
> + return true;
> + } else {
> + return false;
> + }
> +}
Why is this function looking at struct intel_psr to make decisions?
Shouldn't it use old and new crtc state, and nothing else?
> +
> +/*
> + * DC5 entry is only possible if vblank interrupt is disabled
> + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> + * enabled encoders.
> + */
> +static bool
> +intel_psr_is_dc5_entry_possible(struct intel_display *display,
> + struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc;
> +
> + if ((display->power.domains.target_dc_state &
> + DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
> + return false;
> +
> + if (!crtc_state->has_psr && !crtc_state->has_sel_update &&
> + !crtc_state->has_panel_replay)
> + return false;
> +
> + for_each_intel_crtc(display->drm, crtc) {
> + struct drm_vblank_crtc *vblank;
> + struct intel_encoder *encoder;
> +
> + if (!crtc->active)
> + continue;
> +
> + vblank = drm_crtc_vblank_crtc(&crtc->base);
> +
> + if (vblank->enabled)
> + return false;
> +
> + for_each_encoder_on_crtc(display->drm, &crtc->base, encoder)
> + if (encoder->type != INTEL_OUTPUT_EDP ||
> + !CAN_PSR(enc_to_intel_dp(encoder)))
> + return false;
> + }
> +
> + return true;
> +}
> +
> static void hsw_activate_psr1(struct intel_dp *intel_dp)
> {
> struct intel_display *display = to_intel_display(intel_dp);
> @@ -1010,7 +1086,18 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> u32 val = EDP_PSR2_ENABLE;
> u32 psr_val = 0;
>
> - val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> + /*
> + * Wa_22019444797
> + * TODO: Disable idle frames when vblank gets enabled while
> + * PSR2 is enabled
> + */
> + if (DISPLAY_VER(dev_priv) != 20 ||
> + !intel_dp->psr.is_dpkgc_configured ||
> + intel_dp->psr.is_dc5_entry_possible)
> + val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> + else
> + drm_dbg_kms(display->drm,
> + "Wa 22019444797 requirement met PSR2 deep sleep disabled\n");
What if this was just something like,
if (!intel_dp->psr.disable_idle_frames)
val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
And that was set where needed, and everything else was based on old/new
crtc state.
I'm just feeling really dumb because it's hard for me to follow what's
going on here in this patch. Is it really this complicated?
>
> if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
> val |= EDP_SU_TRACK_ENABLE;
> @@ -1692,6 +1779,20 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
> }
>
> +void intel_psr_compute_config_late(struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> +
> + if (DISPLAY_VER(display) == 20) {
> + crtc_state->is_dpkgc_configured =
> + intel_psr_is_dpkgc_configured(display, crtc_state);
> + crtc_state->is_dc5_entry_possible =
> + intel_psr_is_dc5_entry_possible(display, crtc_state);
> + crtc_state->is_wa_delayed_vblank_limit =
> + intel_psr_wa_delayed_vblank(&crtc_state->hw.adjusted_mode);
> + }
> +}
> +
> void intel_psr_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> @@ -2774,6 +2875,22 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> return 0;
> }
>
> +static void
> +wa_22019444797_fill_psr_params(const struct intel_crtc_state *crtc_state,
> + struct intel_psr *psr)
Again, that's a horrible function name. This doesn't have to include the
workaround number in any way.
The rule of thumb: Say the function name aloud, as if you were
discussing the code with someone. If it's difficult to talk about, it's
probably not a good name.
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> +
> + if (DISPLAY_VER(display) == 20) {
I think this part is independent of display version.
> + psr->is_dpkgc_configured =
> + crtc_state->is_dpkgc_configured;
> + psr->is_dc5_entry_possible =
> + crtc_state->is_dc5_entry_possible;
> + psr->is_wa_delayed_vblank_limit =
> + crtc_state->is_wa_delayed_vblank_limit;
> + }
> +}
Again, why do we need all of this duplicated? I think it only boils down
to just one thing in struct intel_psr, unless I'm mistaken.
> +
> void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> @@ -2796,6 +2913,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
>
> mutex_lock(&psr->lock);
>
> + wa_22019444797_fill_psr_params(new_crtc_state, psr);
> +
So you're filling stuff from new_crtc_state into psr.
> /*
> * Reasons to disable:
> * - PSR disabled in new state
> @@ -2803,6 +2922,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> * - Changing between PSR versions
> * - Region Early Transport changing
> * - Display WA #1136: skl, bxt
> + * - Display WA_22019444797
> */
> needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
> needs_to_disable |= !new_crtc_state->has_psr;
> @@ -2812,6 +2932,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> psr->su_region_et_enabled;
> needs_to_disable |= DISPLAY_VER(i915) < 11 &&
> new_crtc_state->wm_level_disabled;
> + /* TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled */
> + needs_to_disable |= wa_22019444797_psr1(new_crtc_state, psr);
And then use it here. I don't get it.
>
> if (psr->enabled && needs_to_disable)
> intel_psr_disable_locked(intel_dp);
> @@ -2852,6 +2974,12 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
> keep_disabled |= DISPLAY_VER(display) < 11 &&
> crtc_state->wm_level_disabled;
>
> + /*
> + * Wa_22019444797
> + * TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled
> + */
> + keep_disabled |= wa_22019444797_psr1(crtc_state, psr);
So this carries it over from pre plane update new crtc state via
psr... but it's all very confusing.
BR,
Jani.
> +
> if (!psr->enabled && !keep_disabled)
> intel_psr_enable_locked(intel_dp, crtc_state);
> else if (psr->enabled && !crtc_state->wm_level_disabled)
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index 956be263c09e..0923a2f74901 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -47,6 +47,7 @@ void intel_psr_init(struct intel_dp *intel_dp);
> void intel_psr_compute_config(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state,
> struct drm_connector_state *conn_state);
> +void intel_psr_compute_config_late(struct intel_crtc_state *crtc_state);
> void intel_psr_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config);
> void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 47+ messages in thread
* RE: [PATCH] drm/i915/psr: Implement WA to help reach PC10
2024-11-04 14:18 ` Jani Nikula
@ 2024-11-06 8:18 ` Kandpal, Suraj
0 siblings, 0 replies; 47+ messages in thread
From: Kandpal, Suraj @ 2024-11-06 8:18 UTC (permalink / raw)
To: Jani Nikula, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: Hogander, Jouni
> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Monday, November 4, 2024 7:48 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-xe@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org
> Cc: Hogander, Jouni <jouni.hogander@intel.com>; Kandpal, Suraj
> <suraj.kandpal@intel.com>
> Subject: Re: [PATCH] drm/i915/psr: Implement WA to help reach PC10
>
> On Mon, 04 Nov 2024, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > To reach PC10 when PKG_C_LATENCY is configure we must do the following
> > things
> > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be
> > entered
> > 2) Allow PSR2 deep sleep when DC5 can be entered
> > 3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
> > eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
> > not happening.
> >
> > --v2
> > -Add debug prints
> >
> > --v3
> > -use crtc as variable name for intel_crtc [Jani] -use encoder as
> > variable name for intel_encoder [Jani] -No changes in intel_dp in
> > compute_config_late [Jani]
> >
> > --v4
> > -Remove "check" from naming [Jani]
> > -Remove intel_encoder variable which is not necessary in
> > compute_config_late
> >
> > WA: 22019444797
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
> > .../drm/i915/display/intel_display_types.h | 6 +
> > drivers/gpu/drm/i915/display/intel_psr.c | 130 +++++++++++++++++-
> > drivers/gpu/drm/i915/display/intel_psr.h | 1 +
> > 4 files changed, 139 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 0535daed6a9f..8e0fb6bd6211 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4403,6 +4403,9 @@ static int intel_ddi_compute_config_late(struct
> intel_encoder *encoder,
> > port_sync_transcoders & ~BIT(crtc_state-
> >cpu_transcoder);
> > }
> >
> > + if (intel_encoder_is_dp(encoder))
> > + intel_psr_compute_config_late(crtc_state);
> > +
> > return 0;
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index ff6eb93337e0..dd5f3ea90e5b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1089,6 +1089,9 @@ struct intel_crtc_state {
> > bool req_psr2_sdp_prior_scanline;
> > bool has_panel_replay;
> > bool wm_level_disabled;
> > + bool is_wa_delayed_vblank_limit;
> > + bool is_dpkgc_configured;
> > + bool is_dc5_entry_possible;
> > u32 dc3co_exitline;
> > u16 su_y_granularity;
> >
> > @@ -1587,6 +1590,9 @@ struct intel_psr {
> > #define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
> >
> > u32 debug;
> > + bool is_dpkgc_configured;
> > + bool is_dc5_entry_possible;
> > + bool is_wa_delayed_vblank_limit;
>
> I don't understand why all of these need to be duplicated in struct intel_psr.
>
> I get that you don't necessarily have access to the crtc state in all
> circumstances. But doesn't the workaround basically boil down to using 0 idle
> frames in hsw_activate_psr2()?
>
> > bool sink_support;
> > bool source_support;
> > bool enabled;
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index a784c0b81556..b93358a82aa3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -26,6 +26,7 @@
> > #include <drm/drm_atomic_helper.h>
> > #include <drm/drm_damage_helper.h>
> > #include <drm/drm_debugfs.h>
> > +#include <drm/drm_vblank.h>
> >
> > #include "i915_drv.h"
> > #include "i915_reg.h"
> > @@ -898,6 +899,81 @@ static u8 psr_compute_idle_frames(struct intel_dp
> *intel_dp)
> > return idle_frames;
> > }
> >
> > +static bool
> > +intel_psr_wa_delayed_vblank(const struct drm_display_mode
> > +*adjusted_mode) {
> > + return (adjusted_mode->crtc_vblank_start -
> > +adjusted_mode->crtc_vdisplay) >= 6; }
> > +
> > +/*
> > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
> > + * VRR is not enabled
> > + */
> > +static bool intel_psr_is_dpkgc_configured(struct intel_display *display,
> > + struct intel_crtc_state *crtc_state) {
> > + if (DISPLAY_VER(display) < 20 || crtc_state->vrr.enable)
> > + return false;
> > +
> > + return true;
>
> IOW,
>
> return DISPLAY_VER(display) >= 20 && !crtc_state->vrr.enable;
>
> > +}
> > +
> > +static bool wa_22019444797_psr1(const struct intel_crtc_state *crtc_state,
> > + struct intel_psr *psr)
>
> I really dislike function names like this. It doesn't say *anything* to the reader.
> It's hard to pronounce. It's hard to talk about. I don't know what it means.
>
> Something like psr1_needs_wa_22019444797() is already much better, even if
> it still contains the wa number. It tells what it's about, and the reader doesn't
> have to try to guess.
Sure will fix the name here Jani
>
> > +{
> > + struct intel_display *display = to_intel_display(crtc_state);
> > +
> > + if (DISPLAY_VER(display) == 20 && psr->is_dpkgc_configured &&
> > + (psr->is_wa_delayed_vblank_limit || !psr->is_dc5_entry_possible)
> &&
> > + !crtc_state->has_sel_update && !crtc_state->has_panel_replay) {
> > + drm_dbg_kms(display->drm,
> > + "Wa 22019444797 requirement met PSR1
> disabled\n");
>
> That debug log message is not a sentence. Maybe something like, "Disabling
> PSR1 due to wa 22019444797\n".
Got it will update the debug message to state the above message
>
> > + return true;
> > + } else {
> > + return false;
> > + }
> > +}
>
> Why is this function looking at struct intel_psr to make decisions?
> Shouldn't it use old and new crtc state, and nothing else?
>
> > +
> > +/*
> > + * DC5 entry is only possible if vblank interrupt is disabled
> > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
> > + * enabled encoders.
> > + */
> > +static bool
> > +intel_psr_is_dc5_entry_possible(struct intel_display *display,
> > + struct intel_crtc_state *crtc_state) {
> > + struct intel_crtc *crtc;
> > +
> > + if ((display->power.domains.target_dc_state &
> > + DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
> > + return false;
> > +
> > + if (!crtc_state->has_psr && !crtc_state->has_sel_update &&
> > + !crtc_state->has_panel_replay)
> > + return false;
> > +
> > + for_each_intel_crtc(display->drm, crtc) {
> > + struct drm_vblank_crtc *vblank;
> > + struct intel_encoder *encoder;
> > +
> > + if (!crtc->active)
> > + continue;
> > +
> > + vblank = drm_crtc_vblank_crtc(&crtc->base);
> > +
> > + if (vblank->enabled)
> > + return false;
> > +
> > + for_each_encoder_on_crtc(display->drm, &crtc->base,
> encoder)
> > + if (encoder->type != INTEL_OUTPUT_EDP ||
> > + !CAN_PSR(enc_to_intel_dp(encoder)))
> > + return false;
> > + }
> > +
> > + return true;
> > +}
> > +
> > static void hsw_activate_psr1(struct intel_dp *intel_dp) {
> > struct intel_display *display = to_intel_display(intel_dp); @@
> > -1010,7 +1086,18 @@ static void hsw_activate_psr2(struct intel_dp
> *intel_dp)
> > u32 val = EDP_PSR2_ENABLE;
> > u32 psr_val = 0;
> >
> > - val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > + /*
> > + * Wa_22019444797
> > + * TODO: Disable idle frames when vblank gets enabled while
> > + * PSR2 is enabled
> > + */
> > + if (DISPLAY_VER(dev_priv) != 20 ||
> > + !intel_dp->psr.is_dpkgc_configured ||
> > + intel_dp->psr.is_dc5_entry_possible)
> > + val |=
> EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
> > + else
> > + drm_dbg_kms(display->drm,
> > + "Wa 22019444797 requirement met PSR2 deep
> sleep disabled\n");
>
> What if this was just something like,
>
> if (!intel_dp->psr.disable_idle_frames)
> val |=
> EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
>
> And that was set where needed, and everything else was based on old/new
> crtc state.
Sure I can work on that.
>
> I'm just feeling really dumb because it's hard for me to follow what's going on
> here in this patch. Is it really this complicated?
It actually became complicated due the multiple conditions each asking us to do different actions for both
Psr1 and psr2 and each of those conditions having its own conditions for example dc5_entry_possible has its
own list of condition to end up being true
>
> >
> > if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
> > val |= EDP_SU_TRACK_ENABLE;
> > @@ -1692,6 +1779,20 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
> > crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp,
> > crtc_state); }
> >
> > +void intel_psr_compute_config_late(struct intel_crtc_state
> > +*crtc_state) {
> > + struct intel_display *display = to_intel_display(crtc_state);
> > +
> > + if (DISPLAY_VER(display) == 20) {
> > + crtc_state->is_dpkgc_configured =
> > + intel_psr_is_dpkgc_configured(display, crtc_state);
> > + crtc_state->is_dc5_entry_possible =
> > + intel_psr_is_dc5_entry_possible(display, crtc_state);
> > + crtc_state->is_wa_delayed_vblank_limit =
> > + intel_psr_wa_delayed_vblank(&crtc_state-
> >hw.adjusted_mode);
> > + }
> > +}
> > +
> > void intel_psr_get_config(struct intel_encoder *encoder,
> > struct intel_crtc_state *pipe_config) { @@ -2774,6
> +2875,22 @@
> > int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > return 0;
> > }
> >
> > +static void
> > +wa_22019444797_fill_psr_params(const struct intel_crtc_state *crtc_state,
> > + struct intel_psr *psr)
>
> Again, that's a horrible function name. This doesn't have to include the
> workaround number in any way.
>
> The rule of thumb: Say the function name aloud, as if you were discussing the
> code with someone. If it's difficult to talk about, it's probably not a good
> name.
Sure will update it and from what I can see from the comments above and below this may
altogether not be needed since we will only have one variable we need to fill and the rest can be
taken care by crtc_state itself.
>
> > +{
> > + struct intel_display *display = to_intel_display(crtc_state);
> > +
> > + if (DISPLAY_VER(display) == 20) {
>
> I think this part is independent of display version.
Okay got it.
>
> > + psr->is_dpkgc_configured =
> > + crtc_state->is_dpkgc_configured;
> > + psr->is_dc5_entry_possible =
> > + crtc_state->is_dc5_entry_possible;
> > + psr->is_wa_delayed_vblank_limit =
> > + crtc_state->is_wa_delayed_vblank_limit;
> > + }
> > +}
>
> Again, why do we need all of this duplicated? I think it only boils down to just
> one thing in struct intel_psr, unless I'm mistaken.
I think as you suggested above having one variable should suffice and that can be set here and later
On used in hsw_psr2_activate
>
> > +
> > void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> > struct intel_crtc *crtc)
> > {
> > @@ -2796,6 +2913,8 @@ void intel_psr_pre_plane_update(struct
> > intel_atomic_state *state,
> >
> > mutex_lock(&psr->lock);
> >
> > + wa_22019444797_fill_psr_params(new_crtc_state, psr);
> > +
>
> So you're filling stuff from new_crtc_state into psr.
>
> > /*
> > * Reasons to disable:
> > * - PSR disabled in new state
> > @@ -2803,6 +2922,7 @@ void intel_psr_pre_plane_update(struct
> intel_atomic_state *state,
> > * - Changing between PSR versions
> > * - Region Early Transport changing
> > * - Display WA #1136: skl, bxt
> > + * - Display WA_22019444797
> > */
> > needs_to_disable |=
> intel_crtc_needs_modeset(new_crtc_state);
> > needs_to_disable |= !new_crtc_state->has_psr; @@ -2812,6
> +2932,8 @@
> > void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> > psr->su_region_et_enabled;
> > needs_to_disable |= DISPLAY_VER(i915) < 11 &&
> > new_crtc_state->wm_level_disabled;
> > + /* TODO: Disable PSR1 when vblank gets enabled while PSR1
> is enabled */
> > + needs_to_disable |= wa_22019444797_psr1(new_crtc_state,
> psr);
>
> And then use it here. I don't get it.
>
> >
> > if (psr->enabled && needs_to_disable)
> > intel_psr_disable_locked(intel_dp);
> > @@ -2852,6 +2974,12 @@ void intel_psr_post_plane_update(struct
> intel_atomic_state *state,
> > keep_disabled |= DISPLAY_VER(display) < 11 &&
> > crtc_state->wm_level_disabled;
> >
> > + /*
> > + * Wa_22019444797
> > + * TODO: Disable PSR1 when vblank gets enabled while PSR1
> is enabled
> > + */
> > + keep_disabled |= wa_22019444797_psr1(crtc_state, psr);
>
> So this carries it over from pre plane update new crtc state via psr... but it's all
> very confusing.
I think this will be solved with the suggestion you made above in the next revision
Regards,
Suraj Kandpal
>
> BR,
> Jani.
>
> > +
> > if (!psr->enabled && !keep_disabled)
> > intel_psr_enable_locked(intel_dp, crtc_state);
> > else if (psr->enabled && !crtc_state->wm_level_disabled) diff
> --git
> > a/drivers/gpu/drm/i915/display/intel_psr.h
> > b/drivers/gpu/drm/i915/display/intel_psr.h
> > index 956be263c09e..0923a2f74901 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > @@ -47,6 +47,7 @@ void intel_psr_init(struct intel_dp *intel_dp);
> > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > struct intel_crtc_state *crtc_state,
> > struct drm_connector_state *conn_state);
> > +void intel_psr_compute_config_late(struct intel_crtc_state
> > +*crtc_state);
> > void intel_psr_get_config(struct intel_encoder *encoder,
> > struct intel_crtc_state *pipe_config); void
> > intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH] drm/i915/psr: Implement WA to help reach PC10
@ 2024-11-06 9:00 Suraj Kandpal
0 siblings, 0 replies; 47+ messages in thread
From: Suraj Kandpal @ 2024-11-06 9:00 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: jouni.hogander, jani.nikula, Suraj Kandpal
To reach PC10 when PKG_C_LATENCY is configure we must do the following
things
1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
2) Allow PSR2 deep sleep when DC5 can be entered
3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
not happening.
--v2
-Add debug prints
--v3
-use crtc as variable name for intel_crtc [Jani]
-use encoder as variable name for intel_encoder [Jani]
-No changes in intel_dp in compute_config_late [Jani]
--v4
-Remove "check" from naming [Jani]
-Remove intel_encoder variable which is not necessary in
compute_config_late
--v5
-Make readable function names [Jani]
-No need to duplicate all variables into intel_psr [Jani]
-Optimize dpkgc_configured function [Jani]
-Use crtc_state only to decide if wa is needed for PSR1 [Jani]
WA: 22019444797
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
.../drm/i915/display/intel_display_types.h | 4 +
drivers/gpu/drm/i915/display/intel_psr.c | 111 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_psr.h | 1 +
4 files changed, 118 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 49b5cc01ce40..61b7dd6a9dc4 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4414,6 +4414,9 @@ static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
}
+ if (intel_encoder_is_dp(encoder))
+ intel_psr_compute_config_late(crtc_state);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ff6eb93337e0..24b95268f42d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1089,6 +1089,9 @@ struct intel_crtc_state {
bool req_psr2_sdp_prior_scanline;
bool has_panel_replay;
bool wm_level_disabled;
+ bool is_dpkgc_configured;
+ bool is_dc5_entry_possible;
+ bool is_wa_delayed_vblank_limit;
u32 dc3co_exitline;
u16 su_y_granularity;
@@ -1587,6 +1590,7 @@ struct intel_psr {
#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
u32 debug;
+ bool disable_idle_frames;
bool sink_support;
bool source_support;
bool enabled;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index a784c0b81556..3cb267437324 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -26,6 +26,7 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_damage_helper.h>
#include <drm/drm_debugfs.h>
+#include <drm/drm_vblank.h>
#include "i915_drv.h"
#include "i915_reg.h"
@@ -898,6 +899,78 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
return idle_frames;
}
+static bool
+intel_psr_wa_delayed_vblank(const struct drm_display_mode *adjusted_mode)
+{
+ return (adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay) >= 6;
+}
+
+/*
+ * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and
+ * VRR is not enabled
+ */
+static bool intel_psr_is_dpkgc_configured(struct intel_display *display,
+ struct intel_crtc_state *crtc_state)
+{
+ return DISPLAY_VER(display) >= 20 && !crtc_state->vrr.enable;
+}
+
+static bool
+psr1_needs_wa_22019444797(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ if (DISPLAY_VER(display) == 20 && crtc_state->is_dpkgc_configured &&
+ (crtc_state->is_wa_delayed_vblank_limit || !crtc_state->is_dc5_entry_possible) &&
+ !crtc_state->has_sel_update && !crtc_state->has_panel_replay) {
+ drm_dbg_kms(display->drm,
+ "Disabling PSR1 due to wa 22019444797\n");
+ return true;
+ } else {
+ return false;
+ }
+}
+
+/*
+ * DC5 entry is only possible if vblank interrupt is disabled
+ * and either psr1, psr2, edp 1.5 pr alpm is enabled on all
+ * enabled encoders.
+ */
+static bool
+intel_psr_is_dc5_entry_possible(struct intel_display *display,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc;
+
+ if ((display->power.domains.target_dc_state &
+ DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0)
+ return false;
+
+ if (!crtc_state->has_psr && !crtc_state->has_sel_update &&
+ !crtc_state->has_panel_replay)
+ return false;
+
+ for_each_intel_crtc(display->drm, crtc) {
+ struct drm_vblank_crtc *vblank;
+ struct intel_encoder *encoder;
+
+ if (!crtc->active)
+ continue;
+
+ vblank = drm_crtc_vblank_crtc(&crtc->base);
+
+ if (vblank->enabled)
+ return false;
+
+ for_each_encoder_on_crtc(display->drm, &crtc->base, encoder)
+ if (encoder->type != INTEL_OUTPUT_EDP ||
+ !CAN_PSR(enc_to_intel_dp(encoder)))
+ return false;
+ }
+
+ return true;
+}
+
static void hsw_activate_psr1(struct intel_dp *intel_dp)
{
struct intel_display *display = to_intel_display(intel_dp);
@@ -1010,7 +1083,16 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
u32 val = EDP_PSR2_ENABLE;
u32 psr_val = 0;
- val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ /*
+ * Wa_22019444797
+ * TODO: Disable idle frames when vblank gets enabled while
+ * PSR2 is enabled
+ */
+ if (!intel_dp->psr.disable_idle_frames)
+ val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp));
+ else
+ drm_dbg_kms(display->drm,
+ "Wa 22019444797 requirement met PSR2 deep sleep disabled\n");
if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv))
val |= EDP_SU_TRACK_ENABLE;
@@ -1692,6 +1774,20 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state);
}
+void intel_psr_compute_config_late(struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ if (DISPLAY_VER(display) == 20) {
+ crtc_state->is_dpkgc_configured =
+ intel_psr_is_dpkgc_configured(display, crtc_state);
+ crtc_state->is_dc5_entry_possible =
+ intel_psr_is_dc5_entry_possible(display, crtc_state);
+ crtc_state->is_wa_delayed_vblank_limit =
+ intel_psr_wa_delayed_vblank(&crtc_state->hw.adjusted_mode);
+ }
+}
+
void intel_psr_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
{
@@ -2796,6 +2892,10 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
mutex_lock(&psr->lock);
+ psr->disable_idle_frames = DISPLAY_VER(display) != 20 ||
+ !new_crtc_state->is_dpkgc_configured ||
+ new_crtc_state->is_dc5_entry_possible;
+
/*
* Reasons to disable:
* - PSR disabled in new state
@@ -2803,6 +2903,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
* - Changing between PSR versions
* - Region Early Transport changing
* - Display WA #1136: skl, bxt
+ * - Display WA_22019444797
*/
needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
needs_to_disable |= !new_crtc_state->has_psr;
@@ -2812,6 +2913,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
psr->su_region_et_enabled;
needs_to_disable |= DISPLAY_VER(i915) < 11 &&
new_crtc_state->wm_level_disabled;
+ /* TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled */
+ needs_to_disable |= psr1_needs_wa_22019444797(new_crtc_state);
if (psr->enabled && needs_to_disable)
intel_psr_disable_locked(intel_dp);
@@ -2852,6 +2955,12 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
keep_disabled |= DISPLAY_VER(display) < 11 &&
crtc_state->wm_level_disabled;
+ /*
+ * Wa_22019444797
+ * TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled
+ */
+ keep_disabled |= psr1_needs_wa_22019444797(crtc_state);
+
if (!psr->enabled && !keep_disabled)
intel_psr_enable_locked(intel_dp, crtc_state);
else if (psr->enabled && !crtc_state->wm_level_disabled)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 956be263c09e..0923a2f74901 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -47,6 +47,7 @@ void intel_psr_init(struct intel_dp *intel_dp);
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state);
+void intel_psr_compute_config_late(struct intel_crtc_state *crtc_state);
void intel_psr_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config);
void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
--
2.34.1
^ permalink raw reply related [flat|nested] 47+ messages in thread
end of thread, other threads:[~2024-11-06 9:02 UTC | newest]
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2024-09-02 5:02 [PATCH] drm/i915/psr: Implment WA to help reach PC10 Suraj Kandpal
2024-09-02 6:13 ` ✗ Fi.CI.BAT: failure for " Patchwork
2024-09-02 9:37 ` [PATCH] " Hogander, Jouni
2024-09-02 10:01 ` Kandpal, Suraj
2024-09-03 7:42 ` Hogander, Jouni
2024-09-03 7:46 ` Kandpal, Suraj
2024-09-02 10:02 ` Hogander, Jouni
2024-09-02 10:14 ` Kandpal, Suraj
2024-09-02 11:02 ` Hogander, Jouni
2024-09-02 11:07 ` Kandpal, Suraj
2024-09-02 11:13 ` Hogander, Jouni
2024-09-02 11:16 ` Kandpal, Suraj
2024-09-03 8:24 ` Suraj Kandpal
2024-09-05 4:41 ` Suraj Kandpal
2024-09-09 4:54 ` Suraj Kandpal
2024-09-09 6:32 ` Suraj Kandpal
2024-09-19 12:14 ` Shankar, Uma
2024-09-19 12:44 ` Kandpal, Suraj
2024-09-19 12:55 ` Hogander, Jouni
2024-09-20 5:36 ` Hogander, Jouni
2024-09-20 6:29 ` Kandpal, Suraj
2024-09-20 6:41 ` Hogander, Jouni
2024-09-20 6:46 ` Kandpal, Suraj
2024-09-20 9:12 ` [PATCH] drm/i915/psr: Implement " Suraj Kandpal
2024-09-20 11:45 ` Hogander, Jouni
2024-09-23 2:54 ` Kandpal, Suraj
2024-09-23 10:23 ` Shankar, Uma
2024-09-09 14:12 ` [PATCH] drm/i915/psr: Implment " Ville Syrjälä
2024-09-10 4:15 ` Kandpal, Suraj
2024-09-03 10:25 ` ✓ Fi.CI.BAT: success for drm/i915/psr: Implment WA to help reach PC10 (rev2) Patchwork
2024-09-04 13:03 ` ✓ Fi.CI.IGT: " Patchwork
2024-09-05 5:18 ` ✓ Fi.CI.BAT: success for drm/i915/psr: Implment WA to help reach PC10 (rev3) Patchwork
2024-09-06 15:26 ` ✓ Fi.CI.IGT: " Patchwork
2024-09-09 5:26 ` ✗ Fi.CI.BUILD: failure for drm/i915/psr: Implment WA to help reach PC10 (rev4) Patchwork
2024-09-09 7:28 ` ✓ Fi.CI.BAT: success for drm/i915/psr: Implment WA to help reach PC10 (rev5) Patchwork
2024-09-10 17:15 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-09-20 10:57 ` ✓ Fi.CI.BAT: success for drm/i915/psr: Implment WA to help reach PC10 (rev6) Patchwork
2024-09-21 11:54 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-09-27 18:54 ` ✓ Fi.CI.IGT: success " Patchwork
2024-09-28 16:12 ` Patchwork
-- strict thread matches above, loose matches on Subject: below --
2024-10-03 14:53 [PATCH] drm/i915/psr: Implement WA to help reach PC10 Suraj Kandpal
2024-10-06 16:53 ` Suraj Kandpal
2024-10-17 7:54 ` Suraj Kandpal
2024-11-04 9:12 Suraj Kandpal
2024-11-04 14:18 ` Jani Nikula
2024-11-06 8:18 ` Kandpal, Suraj
2024-11-06 9:00 Suraj Kandpal
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