* [Intel-gfx] [PATCH 01/20] drm/i915/mtl: Initial DDI port setup
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
@ 2022-10-14 12:47 ` Mika Kahola
2022-11-29 0:23 ` Sripada, Radhakrishna
2022-10-14 12:47 ` [Intel-gfx] [PATCH 02/20] drm/i915/mtl: Add DP rates Mika Kahola
` (24 subsequent siblings)
25 siblings, 1 reply; 36+ messages in thread
From: Mika Kahola @ 2022-10-14 12:47 UTC (permalink / raw)
To: intel-gfx
From: Clint Taylor <clinton.a.taylor@intel.com>
Initialize c10 combo phy ports. TODO Type-C ports.
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c52da2a21896..6a8937a7d2d9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7900,7 +7900,11 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_DG2(dev_priv)) {
+ if (IS_METEORLAKE(dev_priv)) {
+ /* TODO: initialize TC ports as well */
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ } else if (IS_DG2(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [Intel-gfx] [PATCH 01/20] drm/i915/mtl: Initial DDI port setup
2022-10-14 12:47 ` [Intel-gfx] [PATCH 01/20] drm/i915/mtl: Initial DDI port setup Mika Kahola
@ 2022-11-29 0:23 ` Sripada, Radhakrishna
0 siblings, 0 replies; 36+ messages in thread
From: Sripada, Radhakrishna @ 2022-11-29 0:23 UTC (permalink / raw)
To: Kahola, Mika, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Kahola, Mika <mika.kahola@intel.com>
> Sent: Friday, October 14, 2022 5:47 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>; Taylor, Clinton A
> <clinton.a.taylor@intel.com>; Sripada, Radhakrishna
> <radhakrishna.sripada@intel.com>
> Subject: [PATCH 01/20] drm/i915/mtl: Initial DDI port setup
>
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> Initialize c10 combo phy ports. TODO Type-C ports.
>
> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>
Shouldn't this be moved after C10 phy patches. Apart from that.
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index c52da2a21896..6a8937a7d2d9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7900,7 +7900,11 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv))
> return;
>
> - if (IS_DG2(dev_priv)) {
> + if (IS_METEORLAKE(dev_priv)) {
> + /* TODO: initialize TC ports as well */
> + intel_ddi_init(dev_priv, PORT_A);
> + intel_ddi_init(dev_priv, PORT_B);
> + } else if (IS_DG2(dev_priv)) {
> intel_ddi_init(dev_priv, PORT_A);
> intel_ddi_init(dev_priv, PORT_B);
> intel_ddi_init(dev_priv, PORT_C);
> --
> 2.34.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH 02/20] drm/i915/mtl: Add DP rates
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 01/20] drm/i915/mtl: Initial DDI port setup Mika Kahola
@ 2022-10-14 12:47 ` Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 03/20] drm/i915/mtl: Create separate reg file for PICA registers Mika Kahola
` (23 subsequent siblings)
25 siblings, 0 replies; 36+ messages in thread
From: Mika Kahola @ 2022-10-14 12:47 UTC (permalink / raw)
To: intel-gfx
Add DP rates for Meteorlake.
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a060903891b2..0c96444776c4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -420,6 +420,11 @@ static int ehl_max_source_rate(struct intel_dp *intel_dp)
return 810000;
}
+static int mtl_max_source_rate(struct intel_dp *intel_dp)
+{
+ return intel_dp_is_edp(intel_dp) ? 675000 : 810000;
+}
+
static int vbt_max_link_rate(struct intel_dp *intel_dp)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
@@ -444,6 +449,10 @@ static void
intel_dp_set_source_rates(struct intel_dp *intel_dp)
{
/* The values must be in increasing order */
+ static const int mtl_rates[] = {
+ 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
+ 810000,
+ };
static const int icl_rates[] = {
162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
1000000, 1350000,
@@ -469,7 +478,11 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
drm_WARN_ON(&dev_priv->drm,
intel_dp->source_rates || intel_dp->num_source_rates);
- if (DISPLAY_VER(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ source_rates = mtl_rates;
+ size = ARRAY_SIZE(mtl_rates);
+ max_rate = mtl_max_source_rate(intel_dp);
+ } else if (DISPLAY_VER(dev_priv) >= 11) {
source_rates = icl_rates;
size = ARRAY_SIZE(icl_rates);
if (IS_DG2(dev_priv))
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 03/20] drm/i915/mtl: Create separate reg file for PICA registers
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 01/20] drm/i915/mtl: Initial DDI port setup Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 02/20] drm/i915/mtl: Add DP rates Mika Kahola
@ 2022-10-14 12:47 ` Mika Kahola
2022-11-02 16:54 ` Jani Nikula
2022-10-14 12:47 ` [Intel-gfx] [PATCH 04/20] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming Mika Kahola
` (22 subsequent siblings)
25 siblings, 1 reply; 36+ messages in thread
From: Mika Kahola @ 2022-10-14 12:47 UTC (permalink / raw)
To: intel-gfx
Create a separate file to store registers for PICA chips
C10 and C20.
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
.../gpu/drm/i915/display/intel_cx0_reg_defs.h | 136 ++++++++++++++++++
1 file changed, 136 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
new file mode 100644
index 000000000000..dfe156141d73
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_CX0_REG_DEFS_H__
+#define __INTEL_CX0_REG_DEFS_H__
+
+#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A 0x64040
+#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B 0x64140
+#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1 0x16F240
+#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2 0x16F440
+#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC3 0x16F640
+#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC4 0x16F840
+#define _XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) (_PICK(port, \
+ [PORT_A] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
+ [PORT_B] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
+ [PORT_TC1] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
+ [PORT_TC2] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2, \
+ [PORT_TC3] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC3, \
+ [PORT_TC4] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC4) + ((lane) * 4))
+
+#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_XELPDP_PORT_M2P_MSGBUS_CTL(port, lane))
+#define XELPDP_PORT_M2P_TRANSACTION_PENDING REG_BIT(31)
+#define XELPDP_PORT_M2P_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
+#define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1)
+#define XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2)
+#define XELPDP_PORT_M2P_COMMAND_READ REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3)
+#define XELPDP_PORT_M2P_DATA_MASK REG_GENMASK(23, 16)
+#define XELPDP_PORT_M2P_DATA(val) REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val)
+#define XELPDP_PORT_M2P_TRANSACTION_RESET REG_BIT(15)
+#define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0)
+#define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
+
+#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) + 8)
+#define XELPDP_PORT_P2M_RESPONSE_READY REG_BIT(31)
+#define XELPDP_PORT_P2M_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
+#define XELPDP_PORT_P2M_COMMAND_READ_ACK 0x4
+#define XELPDP_PORT_P2M_COMMAND_WRITE_ACK 0x5
+#define XELPDP_PORT_P2M_DATA_MASK REG_GENMASK(23, 16)
+#define XELPDP_PORT_P2M_DATA(val) REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val)
+#define XELPDP_PORT_P2M_ERROR_SET REG_BIT(15)
+
+#define XELPDP_MSGBUS_TIMEOUT_SLOW 1
+#define XELPDP_MSGBUS_TIMEOUT_FAST_US 2
+#define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US 3200
+#define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US 20
+#define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100
+#define XELPDP_PORT_RESET_START_TIMEOUT_US 5
+#define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US 100
+#define XELPDP_PORT_RESET_END_TIMEOUT 15
+#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 1
+
+#define _XELPDP_PORT_BUF_CTL1_LN0_A 0x64004
+#define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104
+#define _XELPDP_PORT_BUF_CTL1_LN0_USBC1 0x16F200
+#define _XELPDP_PORT_BUF_CTL1_LN0_USBC2 0x16F400
+#define _XELPDP_PORT_BUF_CTL1_LN0_USBC3 0x16F600
+#define _XELPDP_PORT_BUF_CTL1_LN0_USBC4 0x16F800
+#define _XELPDP_PORT_BUF_CTL1(port) (_PICK(port, \
+ [PORT_A] = _XELPDP_PORT_BUF_CTL1_LN0_A, \
+ [PORT_B] = _XELPDP_PORT_BUF_CTL1_LN0_B, \
+ [PORT_TC1] = _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
+ [PORT_TC2] = _XELPDP_PORT_BUF_CTL1_LN0_USBC2, \
+ [PORT_TC3] = _XELPDP_PORT_BUF_CTL1_LN0_USBC3, \
+ [PORT_TC4] = _XELPDP_PORT_BUF_CTL1_LN0_USBC4))
+
+#define XELPDP_PORT_BUF_CTL1(port) _MMIO(_XELPDP_PORT_BUF_CTL1(port))
+#define XELPDP_PORT_BUF_SOC_PHY_READY REG_BIT(24)
+#define XELPDP_PORT_REVERSAL REG_BIT(16)
+
+#define XELPDP_TC_PHY_OWNERSHIP REG_BIT(6)
+#define XELPDP_TCSS_POWER_REQUEST REG_BIT(5)
+#define XELPDP_TCSS_POWER_STATE REG_BIT(4)
+#define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1)
+#define XELPDP_PORT_WIDTH(val) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val)
+
+#define XELPDP_PORT_BUF_CTL2(port) _MMIO(_XELPDP_PORT_BUF_CTL1(port) + 4)
+#define XELPDP_LANE0_PIPE_RESET REG_BIT(31)
+#define XELPDP_LANE1_PIPE_RESET REG_BIT(30)
+#define XELPDP_LANE0_PHY_CURRENT_STATUS REG_BIT(29)
+#define XELPDP_LANE1_PHY_CURRENT_STATUS REG_BIT(28)
+#define XELPDP_LANE0_POWERDOWN_UPDATE REG_BIT(25)
+#define XELPDP_LANE1_POWERDOWN_UPDATE REG_BIT(24)
+#define XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK REG_GENMASK(23, 20)
+#define XELPDP_LANE0_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK, val)
+#define XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK REG_GENMASK(19, 16)
+#define XELPDP_LANE1_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK, val)
+#define XELPDP_POWER_STATE_READY_MASK REG_GENMASK(7, 4)
+#define XELPDP_POWER_STATE_READY(val) REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
+
+#define XELPDP_PORT_BUF_CTL3(port) _MMIO(_XELPDP_PORT_BUF_CTL1(port) + 8)
+#define XELPDP_PLL_LANE_STAGGERING_DELAY_MASK REG_GENMASK(15, 8)
+#define XELPDP_PLL_LANE_STAGGERING_DELAY(val) REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val)
+#define XELPDP_POWER_STATE_ACTIVE_MASK REG_GENMASK(3, 0)
+#define XELPDP_POWER_STATE_ACTIVE(val) REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val)
+
+#define _XELPDP_PORT_CLOCK_CTL_A 0x640E0
+#define _XELPDP_PORT_CLOCK_CTL_B 0x641E0
+#define _XELPDP_PORT_CLOCK_CTL_USBC1 0x16F260
+#define _XELPDP_PORT_CLOCK_CTL_USBC2 0x16F460
+#define _XELPDP_PORT_CLOCK_CTL_USBC3 0x16F660
+#define _XELPDP_PORT_CLOCK_CTL_USBC4 0x16F860
+#define XELPDP_PORT_CLOCK_CTL(port) _MMIO(_PICK(port, \
+ [PORT_A] = _XELPDP_PORT_CLOCK_CTL_A, \
+ [PORT_B] = _XELPDP_PORT_CLOCK_CTL_B, \
+ [PORT_TC1] = _XELPDP_PORT_CLOCK_CTL_USBC1, \
+ [PORT_TC2] = _XELPDP_PORT_CLOCK_CTL_USBC2, \
+ [PORT_TC3] = _XELPDP_PORT_CLOCK_CTL_USBC3, \
+ [PORT_TC4] = _XELPDP_PORT_CLOCK_CTL_USBC4))
+
+#define XELPDP_LANE0_PCLK_PLL_REQUEST REG_BIT(31)
+#define XELPDP_LANE0_PCLK_PLL_ACK REG_BIT(30)
+#define XELPDP_LANE0_PCLK_REFCLK_REQUEST REG_BIT(29)
+#define XELPDP_LANE0_PCLK_REFCLK_ACK REG_BIT(28)
+#define XELPDP_LANE1_PCLK_PLL_REQUEST REG_BIT(27)
+#define XELPDP_LANE1_PCLK_PLL_ACK REG_BIT(26)
+#define XELPDP_LANE1_PCLK_REFCLK_REQUEST REG_BIT(25)
+#define XELPDP_LANE1_PCLK_REFCLK_ACK REG_BIT(24)
+#define XELPDP_TBT_CLOCK_REQUEST REG_BIT(19)
+#define XELPDP_TBT_CLOCK_ACK REG_BIT(18)
+#define XELPDP_DDI_CLOCK_SELECT_MASK REG_GENMASK(15, 12)
+#define XELPDP_DDI_CLOCK_SELECT(val) REG_FIELD_PREP(XELPDP_DDI_CLOCK_SELECT_MASK, val)
+#define XELPDP_DDI_CLOCK_SELECT_NONE 0x0
+#define XELPDP_DDI_CLOCK_SELECT_MAXPCLK 0x8
+#define XELPDP_DDI_CLOCK_SELECT_DIV18CLK 0x9
+#define XELPDP_DDI_CLOCK_SELECT_TBT_162 0xc
+#define XELPDP_DDI_CLOCK_SELECT_TBT_270 0xd
+#define XELPDP_DDI_CLOCK_SELECT_TBT_540 0xe
+#define XELPDP_DDI_CLOCK_SELECT_TBT_810 0xf
+#define XELPDP_FORWARD_CLOCK_UNGATE REG_BIT(10)
+#define XELPDP_LANE1_PHY_CLOCK_SELECT REG_BIT(8)
+#define XELPDP_SSC_ENABLE_PLLA REG_BIT(1)
+#define XELPDP_SSC_ENABLE_PLLB REG_BIT(0)
+
+#endif /* __INTEL_CX0_REG_DEFS_H__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [Intel-gfx] [PATCH 03/20] drm/i915/mtl: Create separate reg file for PICA registers
2022-10-14 12:47 ` [Intel-gfx] [PATCH 03/20] drm/i915/mtl: Create separate reg file for PICA registers Mika Kahola
@ 2022-11-02 16:54 ` Jani Nikula
2022-11-02 16:59 ` Jani Nikula
0 siblings, 1 reply; 36+ messages in thread
From: Jani Nikula @ 2022-11-02 16:54 UTC (permalink / raw)
To: Mika Kahola, intel-gfx
On Fri, 14 Oct 2022, Mika Kahola <mika.kahola@intel.com> wrote:
> Create a separate file to store registers for PICA chips
> C10 and C20.
>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> .../gpu/drm/i915/display/intel_cx0_reg_defs.h | 136 ++++++++++++++++++
> 1 file changed, 136 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
> new file mode 100644
> index 000000000000..dfe156141d73
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
intel_cx0_regs.h not intel_cx0_reg_defs.h
See
$ find drivers/gpu/drm/i915/ -name "*_regs.h"
> @@ -0,0 +1,136 @@
> +// SPDX-License-Identifier: MIT
Wrap it in /* ... */ for .h files.
It's a bit confusing, but .h and .c have different requirements.
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef __INTEL_CX0_REG_DEFS_H__
> +#define __INTEL_CX0_REG_DEFS_H__
> +
> +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A 0x64040
> +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B 0x64140
> +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1 0x16F240
> +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2 0x16F440
> +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC3 0x16F640
> +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC4 0x16F840
> +#define _XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) (_PICK(port, \
> + [PORT_A] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
> + [PORT_B] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
> + [PORT_TC1] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
> + [PORT_TC2] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2, \
> + [PORT_TC3] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC3, \
> + [PORT_TC4] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC4) + ((lane) * 4))
> +
> +#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_XELPDP_PORT_M2P_MSGBUS_CTL(port, lane))
> +#define XELPDP_PORT_M2P_TRANSACTION_PENDING REG_BIT(31)
> +#define XELPDP_PORT_M2P_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
> +#define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1)
> +#define XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2)
> +#define XELPDP_PORT_M2P_COMMAND_READ REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3)
> +#define XELPDP_PORT_M2P_DATA_MASK REG_GENMASK(23, 16)
> +#define XELPDP_PORT_M2P_DATA(val) REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val)
> +#define XELPDP_PORT_M2P_TRANSACTION_RESET REG_BIT(15)
> +#define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0)
> +#define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
> +
> +#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) + 8)
> +#define XELPDP_PORT_P2M_RESPONSE_READY REG_BIT(31)
> +#define XELPDP_PORT_P2M_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
> +#define XELPDP_PORT_P2M_COMMAND_READ_ACK 0x4
> +#define XELPDP_PORT_P2M_COMMAND_WRITE_ACK 0x5
> +#define XELPDP_PORT_P2M_DATA_MASK REG_GENMASK(23, 16)
> +#define XELPDP_PORT_P2M_DATA(val) REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val)
> +#define XELPDP_PORT_P2M_ERROR_SET REG_BIT(15)
> +
> +#define XELPDP_MSGBUS_TIMEOUT_SLOW 1
> +#define XELPDP_MSGBUS_TIMEOUT_FAST_US 2
> +#define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US 3200
> +#define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US 20
> +#define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100
> +#define XELPDP_PORT_RESET_START_TIMEOUT_US 5
> +#define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US 100
> +#define XELPDP_PORT_RESET_END_TIMEOUT 15
> +#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 1
> +
> +#define _XELPDP_PORT_BUF_CTL1_LN0_A 0x64004
> +#define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104
> +#define _XELPDP_PORT_BUF_CTL1_LN0_USBC1 0x16F200
> +#define _XELPDP_PORT_BUF_CTL1_LN0_USBC2 0x16F400
> +#define _XELPDP_PORT_BUF_CTL1_LN0_USBC3 0x16F600
> +#define _XELPDP_PORT_BUF_CTL1_LN0_USBC4 0x16F800
> +#define _XELPDP_PORT_BUF_CTL1(port) (_PICK(port, \
> + [PORT_A] = _XELPDP_PORT_BUF_CTL1_LN0_A, \
> + [PORT_B] = _XELPDP_PORT_BUF_CTL1_LN0_B, \
> + [PORT_TC1] = _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> + [PORT_TC2] = _XELPDP_PORT_BUF_CTL1_LN0_USBC2, \
> + [PORT_TC3] = _XELPDP_PORT_BUF_CTL1_LN0_USBC3, \
> + [PORT_TC4] = _XELPDP_PORT_BUF_CTL1_LN0_USBC4))
> +
> +#define XELPDP_PORT_BUF_CTL1(port) _MMIO(_XELPDP_PORT_BUF_CTL1(port))
> +#define XELPDP_PORT_BUF_SOC_PHY_READY REG_BIT(24)
> +#define XELPDP_PORT_REVERSAL REG_BIT(16)
> +
> +#define XELPDP_TC_PHY_OWNERSHIP REG_BIT(6)
> +#define XELPDP_TCSS_POWER_REQUEST REG_BIT(5)
> +#define XELPDP_TCSS_POWER_STATE REG_BIT(4)
> +#define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1)
> +#define XELPDP_PORT_WIDTH(val) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val)
> +
> +#define XELPDP_PORT_BUF_CTL2(port) _MMIO(_XELPDP_PORT_BUF_CTL1(port) + 4)
> +#define XELPDP_LANE0_PIPE_RESET REG_BIT(31)
> +#define XELPDP_LANE1_PIPE_RESET REG_BIT(30)
> +#define XELPDP_LANE0_PHY_CURRENT_STATUS REG_BIT(29)
> +#define XELPDP_LANE1_PHY_CURRENT_STATUS REG_BIT(28)
> +#define XELPDP_LANE0_POWERDOWN_UPDATE REG_BIT(25)
> +#define XELPDP_LANE1_POWERDOWN_UPDATE REG_BIT(24)
> +#define XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK REG_GENMASK(23, 20)
> +#define XELPDP_LANE0_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK, val)
> +#define XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK REG_GENMASK(19, 16)
> +#define XELPDP_LANE1_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK, val)
> +#define XELPDP_POWER_STATE_READY_MASK REG_GENMASK(7, 4)
> +#define XELPDP_POWER_STATE_READY(val) REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
> +
> +#define XELPDP_PORT_BUF_CTL3(port) _MMIO(_XELPDP_PORT_BUF_CTL1(port) + 8)
> +#define XELPDP_PLL_LANE_STAGGERING_DELAY_MASK REG_GENMASK(15, 8)
> +#define XELPDP_PLL_LANE_STAGGERING_DELAY(val) REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val)
> +#define XELPDP_POWER_STATE_ACTIVE_MASK REG_GENMASK(3, 0)
> +#define XELPDP_POWER_STATE_ACTIVE(val) REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val)
> +
> +#define _XELPDP_PORT_CLOCK_CTL_A 0x640E0
> +#define _XELPDP_PORT_CLOCK_CTL_B 0x641E0
> +#define _XELPDP_PORT_CLOCK_CTL_USBC1 0x16F260
> +#define _XELPDP_PORT_CLOCK_CTL_USBC2 0x16F460
> +#define _XELPDP_PORT_CLOCK_CTL_USBC3 0x16F660
> +#define _XELPDP_PORT_CLOCK_CTL_USBC4 0x16F860
> +#define XELPDP_PORT_CLOCK_CTL(port) _MMIO(_PICK(port, \
> + [PORT_A] = _XELPDP_PORT_CLOCK_CTL_A, \
> + [PORT_B] = _XELPDP_PORT_CLOCK_CTL_B, \
> + [PORT_TC1] = _XELPDP_PORT_CLOCK_CTL_USBC1, \
> + [PORT_TC2] = _XELPDP_PORT_CLOCK_CTL_USBC2, \
> + [PORT_TC3] = _XELPDP_PORT_CLOCK_CTL_USBC3, \
> + [PORT_TC4] = _XELPDP_PORT_CLOCK_CTL_USBC4))
> +
> +#define XELPDP_LANE0_PCLK_PLL_REQUEST REG_BIT(31)
> +#define XELPDP_LANE0_PCLK_PLL_ACK REG_BIT(30)
> +#define XELPDP_LANE0_PCLK_REFCLK_REQUEST REG_BIT(29)
> +#define XELPDP_LANE0_PCLK_REFCLK_ACK REG_BIT(28)
> +#define XELPDP_LANE1_PCLK_PLL_REQUEST REG_BIT(27)
> +#define XELPDP_LANE1_PCLK_PLL_ACK REG_BIT(26)
> +#define XELPDP_LANE1_PCLK_REFCLK_REQUEST REG_BIT(25)
> +#define XELPDP_LANE1_PCLK_REFCLK_ACK REG_BIT(24)
> +#define XELPDP_TBT_CLOCK_REQUEST REG_BIT(19)
> +#define XELPDP_TBT_CLOCK_ACK REG_BIT(18)
> +#define XELPDP_DDI_CLOCK_SELECT_MASK REG_GENMASK(15, 12)
> +#define XELPDP_DDI_CLOCK_SELECT(val) REG_FIELD_PREP(XELPDP_DDI_CLOCK_SELECT_MASK, val)
> +#define XELPDP_DDI_CLOCK_SELECT_NONE 0x0
> +#define XELPDP_DDI_CLOCK_SELECT_MAXPCLK 0x8
> +#define XELPDP_DDI_CLOCK_SELECT_DIV18CLK 0x9
> +#define XELPDP_DDI_CLOCK_SELECT_TBT_162 0xc
> +#define XELPDP_DDI_CLOCK_SELECT_TBT_270 0xd
> +#define XELPDP_DDI_CLOCK_SELECT_TBT_540 0xe
> +#define XELPDP_DDI_CLOCK_SELECT_TBT_810 0xf
> +#define XELPDP_FORWARD_CLOCK_UNGATE REG_BIT(10)
> +#define XELPDP_LANE1_PHY_CLOCK_SELECT REG_BIT(8)
> +#define XELPDP_SSC_ENABLE_PLLA REG_BIT(1)
> +#define XELPDP_SSC_ENABLE_PLLB REG_BIT(0)
> +
> +#endif /* __INTEL_CX0_REG_DEFS_H__ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH 03/20] drm/i915/mtl: Create separate reg file for PICA registers
2022-11-02 16:54 ` Jani Nikula
@ 2022-11-02 16:59 ` Jani Nikula
0 siblings, 0 replies; 36+ messages in thread
From: Jani Nikula @ 2022-11-02 16:59 UTC (permalink / raw)
To: Mika Kahola, intel-gfx
On Wed, 02 Nov 2022, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Fri, 14 Oct 2022, Mika Kahola <mika.kahola@intel.com> wrote:
>> Create a separate file to store registers for PICA chips
>> C10 and C20.
>>
>> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
>> ---
>> .../gpu/drm/i915/display/intel_cx0_reg_defs.h | 136 ++++++++++++++++++
>> 1 file changed, 136 insertions(+)
>> create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
>> new file mode 100644
>> index 000000000000..dfe156141d73
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
>
> intel_cx0_regs.h not intel_cx0_reg_defs.h
I guess intel_cx0_phy_regs.h since you're adding intel_cx0_phy.c where
this is used.
But I'm confused as the next patch adds that. What's the difference
between the two?! And you're actually adding same stuff to both?
>
> See
>
> $ find drivers/gpu/drm/i915/ -name "*_regs.h"
>
>> @@ -0,0 +1,136 @@
>> +// SPDX-License-Identifier: MIT
>
> Wrap it in /* ... */ for .h files.
>
> It's a bit confusing, but .h and .c have different requirements.
>
>> +/*
>> + * Copyright © 2022 Intel Corporation
>> + */
>> +
>> +#ifndef __INTEL_CX0_REG_DEFS_H__
>> +#define __INTEL_CX0_REG_DEFS_H__
>> +
>> +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A 0x64040
>> +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B 0x64140
>> +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1 0x16F240
>> +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2 0x16F440
>> +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC3 0x16F640
>> +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC4 0x16F840
>> +#define _XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) (_PICK(port, \
>> + [PORT_A] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
>> + [PORT_B] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
>> + [PORT_TC1] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
>> + [PORT_TC2] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2, \
>> + [PORT_TC3] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC3, \
>> + [PORT_TC4] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC4) + ((lane) * 4))
>> +
>> +#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_XELPDP_PORT_M2P_MSGBUS_CTL(port, lane))
>> +#define XELPDP_PORT_M2P_TRANSACTION_PENDING REG_BIT(31)
>> +#define XELPDP_PORT_M2P_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
>> +#define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1)
>> +#define XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2)
>> +#define XELPDP_PORT_M2P_COMMAND_READ REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3)
>> +#define XELPDP_PORT_M2P_DATA_MASK REG_GENMASK(23, 16)
>> +#define XELPDP_PORT_M2P_DATA(val) REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val)
>> +#define XELPDP_PORT_M2P_TRANSACTION_RESET REG_BIT(15)
>> +#define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0)
>> +#define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
>> +
>> +#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) + 8)
>> +#define XELPDP_PORT_P2M_RESPONSE_READY REG_BIT(31)
>> +#define XELPDP_PORT_P2M_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
>> +#define XELPDP_PORT_P2M_COMMAND_READ_ACK 0x4
>> +#define XELPDP_PORT_P2M_COMMAND_WRITE_ACK 0x5
>> +#define XELPDP_PORT_P2M_DATA_MASK REG_GENMASK(23, 16)
>> +#define XELPDP_PORT_P2M_DATA(val) REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val)
>> +#define XELPDP_PORT_P2M_ERROR_SET REG_BIT(15)
>> +
>> +#define XELPDP_MSGBUS_TIMEOUT_SLOW 1
>> +#define XELPDP_MSGBUS_TIMEOUT_FAST_US 2
>> +#define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US 3200
>> +#define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US 20
>> +#define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100
>> +#define XELPDP_PORT_RESET_START_TIMEOUT_US 5
>> +#define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US 100
>> +#define XELPDP_PORT_RESET_END_TIMEOUT 15
>> +#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 1
>> +
>> +#define _XELPDP_PORT_BUF_CTL1_LN0_A 0x64004
>> +#define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104
>> +#define _XELPDP_PORT_BUF_CTL1_LN0_USBC1 0x16F200
>> +#define _XELPDP_PORT_BUF_CTL1_LN0_USBC2 0x16F400
>> +#define _XELPDP_PORT_BUF_CTL1_LN0_USBC3 0x16F600
>> +#define _XELPDP_PORT_BUF_CTL1_LN0_USBC4 0x16F800
>> +#define _XELPDP_PORT_BUF_CTL1(port) (_PICK(port, \
>> + [PORT_A] = _XELPDP_PORT_BUF_CTL1_LN0_A, \
>> + [PORT_B] = _XELPDP_PORT_BUF_CTL1_LN0_B, \
>> + [PORT_TC1] = _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
>> + [PORT_TC2] = _XELPDP_PORT_BUF_CTL1_LN0_USBC2, \
>> + [PORT_TC3] = _XELPDP_PORT_BUF_CTL1_LN0_USBC3, \
>> + [PORT_TC4] = _XELPDP_PORT_BUF_CTL1_LN0_USBC4))
>> +
>> +#define XELPDP_PORT_BUF_CTL1(port) _MMIO(_XELPDP_PORT_BUF_CTL1(port))
>> +#define XELPDP_PORT_BUF_SOC_PHY_READY REG_BIT(24)
>> +#define XELPDP_PORT_REVERSAL REG_BIT(16)
>> +
>> +#define XELPDP_TC_PHY_OWNERSHIP REG_BIT(6)
>> +#define XELPDP_TCSS_POWER_REQUEST REG_BIT(5)
>> +#define XELPDP_TCSS_POWER_STATE REG_BIT(4)
>> +#define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1)
>> +#define XELPDP_PORT_WIDTH(val) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val)
>> +
>> +#define XELPDP_PORT_BUF_CTL2(port) _MMIO(_XELPDP_PORT_BUF_CTL1(port) + 4)
>> +#define XELPDP_LANE0_PIPE_RESET REG_BIT(31)
>> +#define XELPDP_LANE1_PIPE_RESET REG_BIT(30)
>> +#define XELPDP_LANE0_PHY_CURRENT_STATUS REG_BIT(29)
>> +#define XELPDP_LANE1_PHY_CURRENT_STATUS REG_BIT(28)
>> +#define XELPDP_LANE0_POWERDOWN_UPDATE REG_BIT(25)
>> +#define XELPDP_LANE1_POWERDOWN_UPDATE REG_BIT(24)
>> +#define XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK REG_GENMASK(23, 20)
>> +#define XELPDP_LANE0_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK, val)
>> +#define XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK REG_GENMASK(19, 16)
>> +#define XELPDP_LANE1_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK, val)
>> +#define XELPDP_POWER_STATE_READY_MASK REG_GENMASK(7, 4)
>> +#define XELPDP_POWER_STATE_READY(val) REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
>> +
>> +#define XELPDP_PORT_BUF_CTL3(port) _MMIO(_XELPDP_PORT_BUF_CTL1(port) + 8)
>> +#define XELPDP_PLL_LANE_STAGGERING_DELAY_MASK REG_GENMASK(15, 8)
>> +#define XELPDP_PLL_LANE_STAGGERING_DELAY(val) REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val)
>> +#define XELPDP_POWER_STATE_ACTIVE_MASK REG_GENMASK(3, 0)
>> +#define XELPDP_POWER_STATE_ACTIVE(val) REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val)
>> +
>> +#define _XELPDP_PORT_CLOCK_CTL_A 0x640E0
>> +#define _XELPDP_PORT_CLOCK_CTL_B 0x641E0
>> +#define _XELPDP_PORT_CLOCK_CTL_USBC1 0x16F260
>> +#define _XELPDP_PORT_CLOCK_CTL_USBC2 0x16F460
>> +#define _XELPDP_PORT_CLOCK_CTL_USBC3 0x16F660
>> +#define _XELPDP_PORT_CLOCK_CTL_USBC4 0x16F860
>> +#define XELPDP_PORT_CLOCK_CTL(port) _MMIO(_PICK(port, \
>> + [PORT_A] = _XELPDP_PORT_CLOCK_CTL_A, \
>> + [PORT_B] = _XELPDP_PORT_CLOCK_CTL_B, \
>> + [PORT_TC1] = _XELPDP_PORT_CLOCK_CTL_USBC1, \
>> + [PORT_TC2] = _XELPDP_PORT_CLOCK_CTL_USBC2, \
>> + [PORT_TC3] = _XELPDP_PORT_CLOCK_CTL_USBC3, \
>> + [PORT_TC4] = _XELPDP_PORT_CLOCK_CTL_USBC4))
>> +
>> +#define XELPDP_LANE0_PCLK_PLL_REQUEST REG_BIT(31)
>> +#define XELPDP_LANE0_PCLK_PLL_ACK REG_BIT(30)
>> +#define XELPDP_LANE0_PCLK_REFCLK_REQUEST REG_BIT(29)
>> +#define XELPDP_LANE0_PCLK_REFCLK_ACK REG_BIT(28)
>> +#define XELPDP_LANE1_PCLK_PLL_REQUEST REG_BIT(27)
>> +#define XELPDP_LANE1_PCLK_PLL_ACK REG_BIT(26)
>> +#define XELPDP_LANE1_PCLK_REFCLK_REQUEST REG_BIT(25)
>> +#define XELPDP_LANE1_PCLK_REFCLK_ACK REG_BIT(24)
>> +#define XELPDP_TBT_CLOCK_REQUEST REG_BIT(19)
>> +#define XELPDP_TBT_CLOCK_ACK REG_BIT(18)
>> +#define XELPDP_DDI_CLOCK_SELECT_MASK REG_GENMASK(15, 12)
>> +#define XELPDP_DDI_CLOCK_SELECT(val) REG_FIELD_PREP(XELPDP_DDI_CLOCK_SELECT_MASK, val)
>> +#define XELPDP_DDI_CLOCK_SELECT_NONE 0x0
>> +#define XELPDP_DDI_CLOCK_SELECT_MAXPCLK 0x8
>> +#define XELPDP_DDI_CLOCK_SELECT_DIV18CLK 0x9
>> +#define XELPDP_DDI_CLOCK_SELECT_TBT_162 0xc
>> +#define XELPDP_DDI_CLOCK_SELECT_TBT_270 0xd
>> +#define XELPDP_DDI_CLOCK_SELECT_TBT_540 0xe
>> +#define XELPDP_DDI_CLOCK_SELECT_TBT_810 0xf
>> +#define XELPDP_FORWARD_CLOCK_UNGATE REG_BIT(10)
>> +#define XELPDP_LANE1_PHY_CLOCK_SELECT REG_BIT(8)
>> +#define XELPDP_SSC_ENABLE_PLLA REG_BIT(1)
>> +#define XELPDP_SSC_ENABLE_PLLB REG_BIT(0)
>> +
>> +#endif /* __INTEL_CX0_REG_DEFS_H__ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH 04/20] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (2 preceding siblings ...)
2022-10-14 12:47 ` [Intel-gfx] [PATCH 03/20] drm/i915/mtl: Create separate reg file for PICA registers Mika Kahola
@ 2022-10-14 12:47 ` Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 05/20] drm/i915/mtl: Add C10 phy programming for HDMI Mika Kahola
` (21 subsequent siblings)
25 siblings, 0 replies; 36+ messages in thread
From: Mika Kahola @ 2022-10-14 12:47 UTC (permalink / raw)
To: intel-gfx
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
has a dedicated PIPE 5.2 Message bus for configuration. This message
bus is used to configure the phy internal registers.
XELPDP has C10 phys to drive output to the EDP and the native output
from the display engine. Add structures, programming hardware state
readout logic. Port clock calculations are similar to DG2. Use the DG2
formulae to calculate the port clock but use the relevant pll signals.
Note: PHY lane 0 is always used for PLL programming.
Add sequences for C10 phy enable/disable phy lane reset,
powerdown change sequence and phy lane programming.
Bspec: 64539, 64568, 64599, 65100, 65101, 65450, 65451, 67610, 67636
v2: Squash patches related to C10 phy message bus and pll
programming support (Jani)
Move register definitions to a new file i.e. intel_cx0_reg_defs.h (Jani)
Move macro definitions (Jani)
DP rates as separate patch (Jani)
Spin out xelpdp register definitions into a separate file (Jani)
Replace macro to select registers based on phy lane with
function calls (Jani)
Fix styling issues (Jani)
Call XELPDP_PORT_P2M_MSGBUS_STATUS() with port instead of phy (Lucas)
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 1090 +++++++++++++++++
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 43 +
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 26 +
.../gpu/drm/i915/display/intel_cx0_reg_defs.h | 30 +
drivers/gpu/drm/i915/display/intel_ddi.c | 22 +-
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915/display/intel_display_power.c | 3 +-
.../i915/display/intel_display_power_well.c | 2 +-
.../drm/i915/display/intel_display_types.h | 6 +
drivers/gpu/drm/i915/display/intel_dpll.c | 22 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
.../drm/i915/display/intel_modeset_verify.c | 2 +
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/i915_reg_defs.h | 57 +
15 files changed, 1307 insertions(+), 5 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.c
create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.h
create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index f8cc1eb52626..8089920b2fa8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -279,6 +279,7 @@ i915-y += \
display/icl_dsi.o \
display/intel_backlight.o \
display/intel_crt.o \
+ display/intel_cx0_phy.o \
display/intel_ddi.o \
display/intel_ddi_buf_trans.o \
display/intel_display_trace.o \
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
new file mode 100644
index 000000000000..d0e8ddd0a905
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -0,0 +1,1090 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include "i915_reg_defs.h"
+#include "intel_cx0_phy.h"
+#include "intel_cx0_reg_defs.h"
+#include "intel_de.h"
+#include "intel_display_types.h"
+#include "intel_dp.h"
+#include "intel_panel.h"
+
+bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy)
+{
+ if (IS_METEORLAKE(dev_priv) && (phy < PHY_C))
+ return true;
+
+ return false;
+}
+
+static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, int lane)
+{
+ enum phy phy = intel_port_to_phy(i915, port);
+
+ /* Bring the phy to idle. */
+ intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ XELPDP_PORT_M2P_TRANSACTION_RESET);
+
+ /* Wait for Idle Clear. */
+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ XELPDP_PORT_M2P_TRANSACTION_RESET,
+ XELPDP_MSGBUS_TIMEOUT_SLOW)) {
+ drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy));
+ return;
+ }
+
+ intel_de_write(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane), ~0);
+}
+
+static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port port, int lane, u32 *val)
+{
+ enum phy phy = intel_port_to_phy(i915, port);
+
+ if (__intel_wait_for_register(&i915->uncore,
+ XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane),
+ XELPDP_PORT_P2M_RESPONSE_READY,
+ XELPDP_PORT_P2M_RESPONSE_READY,
+ XELPDP_MSGBUS_TIMEOUT_FAST_US,
+ XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
+ drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n", phy_name(phy), *val);
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int __intel_cx0_read(struct drm_i915_private *i915, enum port port,
+ int lane, u16 addr, u32 *val)
+{
+ enum phy phy = intel_port_to_phy(i915, port);
+ int ack;
+
+ /* Wait for pending transactions.*/
+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ XELPDP_PORT_M2P_TRANSACTION_PENDING,
+ XELPDP_MSGBUS_TIMEOUT_SLOW)) {
+ drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
+ intel_cx0_bus_reset(i915, port, lane);
+ return -ETIMEDOUT;
+ }
+
+ /* Issue the read command. */
+ intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ XELPDP_PORT_M2P_TRANSACTION_PENDING |
+ XELPDP_PORT_M2P_COMMAND_READ |
+ XELPDP_PORT_M2P_ADDRESS(addr));
+
+ /* Wait for response ready. And read response.*/
+ ack = intel_cx0_wait_for_ack(i915, port, lane, val);
+ if (ack < 0) {
+ intel_cx0_bus_reset(i915, port, lane);
+ return ack;
+ }
+
+ /* Check for error. */
+ if (*val & XELPDP_PORT_P2M_ERROR_SET) {
+ drm_dbg_kms(&i915->drm, "PHY %c Error occurred during read command. Status: 0x%x\n", phy_name(phy), *val);
+ intel_cx0_bus_reset(i915, port, lane);
+ return -EINVAL;
+ }
+
+ /* Check for Read Ack. */
+ if (REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, *val) !=
+ XELPDP_PORT_P2M_COMMAND_READ_ACK) {
+ drm_dbg_kms(&i915->drm, "PHY %c Not a Read response. MSGBUS Status: 0x%x.\n", phy_name(phy), *val);
+ intel_cx0_bus_reset(i915, port, lane);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static u8 intel_cx0_read(struct drm_i915_private *i915, enum port port,
+ int lane, u16 addr)
+{
+ enum phy phy = intel_port_to_phy(i915, port);
+ int i, status;
+ u32 val;
+
+ for (i = 0; i < 3; i++) {
+ status = __intel_cx0_read(i915, port, lane, addr, &val);
+
+ if (status == 0)
+ break;
+ }
+
+ if (i == 3) {
+ drm_err_once(&i915->drm, "PHY %c Read %04x failed after %d retries.\n", phy_name(phy), addr, i);
+ return 0;
+ }
+
+ /* Clear Response Ready flag.*/
+ intel_de_write(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane), ~0);
+
+ return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val);
+}
+
+static int intel_cx0_wait_cwrite_ack(struct drm_i915_private *i915,
+ enum port port, int lane)
+{
+ enum phy phy = intel_port_to_phy(i915, port);
+ int ack;
+ u32 val = 0;
+
+ /* Check for write ack. */
+ ack = intel_cx0_wait_for_ack(i915, port, lane, &val);
+ if (ack < 0)
+ return ack;
+
+ if ((REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, val) !=
+ XELPDP_PORT_P2M_COMMAND_WRITE_ACK) || val & XELPDP_PORT_P2M_ERROR_SET) {
+ drm_dbg_kms(&i915->drm, "PHY %c Unexpected ACK received. MSGBUS STATUS: 0x%x.\n", phy_name(phy), val);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
+ int lane, u16 addr, u8 data, bool committed)
+{
+ enum phy phy = intel_port_to_phy(i915, port);
+
+ /* Wait for pending transactions.*/
+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ XELPDP_PORT_M2P_TRANSACTION_PENDING,
+ XELPDP_MSGBUS_TIMEOUT_SLOW)) {
+ drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
+ intel_cx0_bus_reset(i915, port, lane);
+ return -ETIMEDOUT;
+ }
+
+ /* Issue the write command. */
+ intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ XELPDP_PORT_M2P_TRANSACTION_PENDING |
+ (committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
+ XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) |
+ XELPDP_PORT_M2P_DATA(data) |
+ XELPDP_PORT_M2P_ADDRESS(addr));
+
+ /* Check for error. */
+ if (committed) {
+ if (intel_cx0_wait_cwrite_ack(i915, port, lane) < 0) {
+ intel_cx0_bus_reset(i915, port, lane);
+ return -EINVAL;
+ }
+ } else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)) &
+ XELPDP_PORT_P2M_ERROR_SET)) {
+ drm_dbg_kms(&i915->drm, "PHY %c Error occurred during write command.\n", phy_name(phy));
+ intel_cx0_bus_reset(i915, port, lane);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void __intel_cx0_write(struct drm_i915_private *i915, enum port port,
+ int lane, u16 addr, u8 data, bool committed)
+{
+ enum phy phy = intel_port_to_phy(i915, port);
+ int i, status;
+
+ for (i = 0; i < 3; i++) {
+ status = __intel_cx0_write_once(i915, port, lane, addr, data, committed);
+
+ if (status == 0)
+ break;
+ }
+
+ if (i == 3) {
+ drm_err_once(&i915->drm, "PHY %c Write %04x failed after %d retries.\n", phy_name(phy), addr, i);
+ return;
+ }
+
+ intel_de_write(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane), ~0);
+}
+
+static void intel_cx0_write(struct drm_i915_private *i915, enum port port,
+ int lane, u16 addr, u8 data, bool committed)
+{
+ if (lane == INTEL_CX0_BOTH_LANES) {
+ __intel_cx0_write(i915, port, INTEL_CX0_LANE0, addr, data, committed);
+ __intel_cx0_write(i915, port, INTEL_CX0_LANE1, addr, data, committed);
+ } else {
+ __intel_cx0_write(i915, port, lane, addr, data, committed);
+ }
+}
+
+static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
+ int lane, u16 addr, u8 clear, u8 set, bool committed)
+{
+ u8 old, val;
+
+ old = intel_cx0_read(i915, port, lane, addr);
+ val = (old & ~clear) | set;
+
+ if (val != old)
+ intel_cx0_write(i915, port, lane, addr, val, committed);
+}
+
+static void intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
+ int lane, u16 addr, u8 clear, u8 set, bool committed)
+{
+ if (lane == INTEL_CX0_BOTH_LANES) {
+ __intel_cx0_rmw(i915, port, INTEL_CX0_LANE0, addr, clear, set, committed);
+ __intel_cx0_rmw(i915, port, INTEL_CX0_LANE1, addr, clear, set, committed);
+ } else {
+ __intel_cx0_rmw(i915, port, lane, addr, clear, set, committed);
+ }
+}
+
+/*
+ * Basic DP link rates with 38.4 MHz reference clock.
+ * Note: The tables below are with SSC. In non-ssc
+ * registers 0xC04 to 0xC08(pll[4] to pll[8]) will be
+ * programmed 0.
+ */
+
+static const struct intel_c10mpllb_state mtl_c10_dp_rbr = {
+ .clock = 162000,
+ .pll[0] = 0xB4,
+ .pll[1] = 0,
+ .pll[2] = 0x30,
+ .pll[3] = 0x1,
+ .pll[4] = 0x26,
+ .pll[5] = 0x0C,
+ .pll[6] = 0x98,
+ .pll[7] = 0x46,
+ .pll[8] = 0x1,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0xC0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0x2,
+ .pll[16] = 0x84,
+ .pll[17] = 0x4F,
+ .pll[18] = 0xE5,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_edp_r216 = {
+ .clock = 216000,
+ .pll[0] = 0x4,
+ .pll[1] = 0,
+ .pll[2] = 0xA2,
+ .pll[3] = 0x1,
+ .pll[4] = 0x33,
+ .pll[5] = 0x10,
+ .pll[6] = 0x75,
+ .pll[7] = 0xB3,
+ .pll[8] = 0x1,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0x2,
+ .pll[16] = 0x85,
+ .pll[17] = 0x0F,
+ .pll[18] = 0xE6,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_edp_r243 = {
+ .clock = 243000,
+ .pll[0] = 0x34,
+ .pll[1] = 0,
+ .pll[2] = 0xDA,
+ .pll[3] = 0x1,
+ .pll[4] = 0x39,
+ .pll[5] = 0x12,
+ .pll[6] = 0xE3,
+ .pll[7] = 0xE9,
+ .pll[8] = 0x1,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x20,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0x2,
+ .pll[16] = 0x85,
+ .pll[17] = 0x8F,
+ .pll[18] = 0xE6,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_dp_hbr1 = {
+ .clock = 270000,
+ .pll[0] = 0xF4,
+ .pll[1] = 0,
+ .pll[2] = 0xF8,
+ .pll[3] = 0x0,
+ .pll[4] = 0x20,
+ .pll[5] = 0x0A,
+ .pll[6] = 0x29,
+ .pll[7] = 0x10,
+ .pll[8] = 0x1, /* Verify */
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0xA0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0x1,
+ .pll[16] = 0x84,
+ .pll[17] = 0x4F,
+ .pll[18] = 0xE5,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_edp_r324 = {
+ .clock = 324000,
+ .pll[0] = 0xB4,
+ .pll[1] = 0,
+ .pll[2] = 0x30,
+ .pll[3] = 0x1,
+ .pll[4] = 0x26,
+ .pll[5] = 0x0C,
+ .pll[6] = 0x98,
+ .pll[7] = 0x46,
+ .pll[8] = 0x1,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0xC0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0x1,
+ .pll[16] = 0x85,
+ .pll[17] = 0x4F,
+ .pll[18] = 0xE6,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_edp_r432 = {
+ .clock = 432000,
+ .pll[0] = 0x4,
+ .pll[1] = 0,
+ .pll[2] = 0xA2,
+ .pll[3] = 0x1,
+ .pll[4] = 0x33,
+ .pll[5] = 0x10,
+ .pll[6] = 0x75,
+ .pll[7] = 0xB3,
+ .pll[8] = 0x1,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0x1,
+ .pll[16] = 0x85,
+ .pll[17] = 0x0F,
+ .pll[18] = 0xE6,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_dp_hbr2 = {
+ .clock = 540000,
+ .pll[0] = 0xF4,
+ .pll[1] = 0,
+ .pll[2] = 0xF8,
+ .pll[3] = 0,
+ .pll[4] = 0x20,
+ .pll[5] = 0x0A,
+ .pll[6] = 0x29,
+ .pll[7] = 0x10,
+ .pll[8] = 0x1,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0xA0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0,
+ .pll[16] = 0x84,
+ .pll[17] = 0x4F,
+ .pll[18] = 0xE5,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_edp_r675 = {
+ .clock = 675000,
+ .pll[0] = 0xB4,
+ .pll[1] = 0,
+ .pll[2] = 0x3E,
+ .pll[3] = 0x1,
+ .pll[4] = 0xA8,
+ .pll[5] = 0x0C,
+ .pll[6] = 0x33,
+ .pll[7] = 0x54,
+ .pll[8] = 0x1,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0xC8,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0,
+ .pll[16] = 0x85,
+ .pll[17] = 0x8F,
+ .pll[18] = 0xE6,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_dp_hbr3 = {
+ .clock = 810000,
+ .pll[0] = 0x34,
+ .pll[1] = 0,
+ .pll[2] = 0x84,
+ .pll[3] = 0x1,
+ .pll[4] = 0x30,
+ .pll[5] = 0x0F,
+ .pll[6] = 0x3D,
+ .pll[7] = 0x98,
+ .pll[8] = 0x1,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0xF0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0,
+ .pll[16] = 0x84,
+ .pll[17] = 0x0F,
+ .pll[18] = 0xE5,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state * const mtl_c10_dp_tables[] = {
+ &mtl_c10_dp_rbr,
+ &mtl_c10_dp_hbr1,
+ &mtl_c10_dp_hbr2,
+ &mtl_c10_dp_hbr3,
+ NULL,
+};
+
+static const struct intel_c10mpllb_state * const mtl_c10_edp_tables[] = {
+ &mtl_c10_dp_rbr,
+ &mtl_c10_edp_r216,
+ &mtl_c10_edp_r243,
+ &mtl_c10_dp_hbr1,
+ &mtl_c10_edp_r324,
+ &mtl_c10_edp_r432,
+ &mtl_c10_dp_hbr2,
+ &mtl_c10_edp_r675,
+ &mtl_c10_dp_hbr3,
+ NULL,
+};
+
+static const struct intel_c10mpllb_state * const *
+intel_c10_mpllb_tables_get(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
+{
+ if (intel_crtc_has_dp_encoder(crtc_state)) {
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+ return mtl_c10_edp_tables;
+ else
+ return mtl_c10_dp_tables;
+ }
+
+ /* TODO: Add HDMI Support */
+ MISSING_CASE(encoder->type);
+ return NULL;
+}
+
+static int intel_c10mpllb_calc_state(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
+{
+ const struct intel_c10mpllb_state * const *tables;
+ int i;
+
+ tables = intel_c10_mpllb_tables_get(crtc_state, encoder);
+ if (!tables)
+ return -EINVAL;
+
+ for (i = 0; tables[i]; i++) {
+ if (crtc_state->port_clock <= tables[i]->clock) {
+ crtc_state->c10mpllb_state = *tables[i];
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+int intel_cx0mpllb_calc_state(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
+
+ return intel_c10mpllb_calc_state(crtc_state, encoder);
+}
+
+void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
+ struct intel_c10mpllb_state *pll_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+ bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
+ u8 lane = lane_reversal ? INTEL_CX0_LANE1 :
+ INTEL_CX0_LANE0;
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+ int i;
+ u8 cmn, tx0;
+
+ /*
+ * According to C10 VDR Register programming Sequence we need
+ * to do this to read PHY internal registers from MsgBus.
+ */
+ intel_cx0_rmw(i915, encoder->port, lane, PHY_C10_VDR_CONTROL(1), 0,
+ C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
+
+ for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
+ pll_state->pll[i] = intel_cx0_read(i915, encoder->port, lane,
+ PHY_C10_VDR_PLL(i));
+
+ cmn = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_CMN(0));
+ tx0 = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_TX(0));
+
+ if (tx0 != C10_TX0_VAL || cmn != C10_CMN0_DP_VAL)
+ drm_warn(&i915->drm, "Unexpected tx: %x or cmn: %x for phy: %c.\n",
+ tx0, cmn, phy_name(phy));
+}
+
+static void intel_c10_pll_program(struct drm_i915_private *i915,
+ const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
+{
+ const struct intel_c10mpllb_state *pll_state = &crtc_state->c10mpllb_state;
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+ bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
+ u8 master_lane = lane_reversal ? INTEL_CX0_LANE1 :
+ INTEL_CX0_LANE0;
+ u8 follower_lane = lane_reversal ? INTEL_CX0_LANE0 :
+ INTEL_CX0_LANE1;
+
+ int i;
+ struct intel_dp *intel_dp;
+ bool use_ssc = false;
+ u8 cmn0 = 0;
+
+ if (intel_crtc_has_dp_encoder(crtc_state)) {
+ intel_dp = enc_to_intel_dp(encoder);
+ use_ssc = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
+ DP_MAX_DOWNSPREAD_0_5);
+
+ if (intel_dp_is_edp(intel_dp) && !intel_panel_use_ssc(i915))
+ use_ssc = false;
+
+ cmn0 = C10_CMN0_DP_VAL;
+ }
+
+ intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
+ /* Custom width needs to be programmed to 0 for both the phy lanes */
+ intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
+ PHY_C10_VDR_CUSTOM_WIDTH, 0x3, 0, MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, encoder->port, follower_lane, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MASTER_LANE, C10_VDR_CTRL_UPDATE_CFG,
+ MB_WRITE_COMMITTED);
+
+ /* Program the pll values only for the master lane */
+ for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
+ /* If not using ssc pll[4] through pll[8] must be 0*/
+ intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_PLL(i),
+ (!use_ssc && (i > 3 && i < 9)) ? 0 : pll_state->pll[i],
+ (i % 4) ? MB_WRITE_UNCOMMITTED : MB_WRITE_COMMITTED);
+
+ intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CMN(0), cmn0, MB_WRITE_COMMITTED);
+ intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_TX(0), C10_TX0_VAL, MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, encoder->port, master_lane, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS, C10_VDR_CTRL_MASTER_LANE |
+ C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
+}
+
+void intel_c10mpllb_dump_hw_state(struct drm_i915_private *dev_priv,
+ const struct intel_c10mpllb_state *hw_state)
+{
+ bool fracen;
+ int i;
+ unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
+ unsigned int multiplier, tx_clk_div;
+
+ fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
+ drm_dbg_kms(&dev_priv->drm, "c10pll_hw_state: fracen: %s, ",
+ str_yes_no(fracen));
+
+ if (fracen) {
+ frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];
+ frac_rem = hw_state->pll[14] << 8 | hw_state->pll[13];
+ frac_den = hw_state->pll[10] << 8 | hw_state->pll[9];
+ drm_dbg_kms(&dev_priv->drm, "quot: %u, rem: %u, den: %u,\n",
+ frac_quot, frac_rem, frac_den);
+ }
+
+ multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 |
+ hw_state->pll[2]) / 2 + 16;
+ tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]);
+ drm_dbg_kms(&dev_priv->drm,
+ "multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div);
+
+ drm_dbg_kms(&dev_priv->drm, "c10pll_rawhw_state:");
+
+ for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4)
+ drm_dbg_kms(&dev_priv->drm, "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n",
+ i, hw_state->pll[i], i + 1, hw_state->pll[i + 1],
+ i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
+}
+
+int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
+ const struct intel_c10mpllb_state *pll_state)
+{
+ unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
+ unsigned int multiplier, tx_clk_div, refclk = 38400;
+
+ if (pll_state->pll[0] & C10_PLL0_FRACEN) {
+ frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
+ frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13];
+ frac_den = pll_state->pll[10] << 8 | pll_state->pll[9];
+ }
+
+ multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 |
+ pll_state->pll[2]) / 2 + 16;
+
+ tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]);
+
+ return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
+ DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
+ 10 << (tx_clk_div + 16));
+}
+
+static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ bool lane_reversal)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_dp *intel_dp;
+ bool ssc_enabled;
+ u32 val = 0;
+
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port), XELPDP_PORT_REVERSAL,
+ lane_reversal ? XELPDP_PORT_REVERSAL : 0);
+
+ if (lane_reversal)
+ val |= XELPDP_LANE1_PHY_CLOCK_SELECT;
+
+ val |= XELPDP_FORWARD_CLOCK_UNGATE;
+ val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
+
+ if (intel_crtc_has_dp_encoder(crtc_state)) {
+ intel_dp = enc_to_intel_dp(encoder);
+ ssc_enabled = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
+ DP_MAX_DOWNSPREAD_0_5;
+
+ /* TODO: DP2.0 10G and 20G rates enable MPLLA*/
+ val |= ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
+ }
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ XELPDP_LANE1_PHY_CLOCK_SELECT |
+ XELPDP_FORWARD_CLOCK_UNGATE |
+ XELPDP_DDI_CLOCK_SELECT_MASK |
+ XELPDP_SSC_ENABLE_PLLB, val);
+}
+
+static u32 intel_cx0_get_powerdown_update(u8 lane)
+{
+ if (lane & INTEL_CX0_LANE0)
+ return XELPDP_LANE0_POWERDOWN_UPDATE;
+ else if (lane & INTEL_CX0_LANE1)
+ return XELPDP_LANE1_POWERDOWN_UPDATE;
+ else
+ return XELPDP_LANE0_POWERDOWN_UPDATE |
+ XELPDP_LANE1_POWERDOWN_UPDATE;
+}
+
+static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
+ enum port port,
+ u8 lane, u8 state)
+{
+ enum phy phy = intel_port_to_phy(i915, port);
+
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+ XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK | XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK,
+ XELPDP_LANE0_POWERDOWN_NEW_STATE(state) | XELPDP_LANE1_POWERDOWN_NEW_STATE(state));
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+ XELPDP_LANE0_POWERDOWN_UPDATE | XELPDP_LANE1_POWERDOWN_UPDATE,
+ intel_cx0_get_powerdown_update(lane));
+
+ /* Update Timeout Value */
+ if (__intel_wait_for_register(&i915->uncore, XELPDP_PORT_BUF_CTL2(port),
+ intel_cx0_get_powerdown_update(lane), 0,
+ XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
+ drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
+ phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
+}
+
+static void intel_cx0_setup_powerdown(struct drm_i915_private *i915, enum port port)
+{
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+ XELPDP_POWER_STATE_READY_MASK,
+ XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY));
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(port),
+ XELPDP_POWER_STATE_ACTIVE_MASK |
+ XELPDP_PLL_LANE_STAGGERING_DELAY_MASK,
+ XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) |
+ XELPDP_PLL_LANE_STAGGERING_DELAY(0));
+}
+
+static u32 intel_cx0_get_pclk_refclk_request(u8 lane)
+{
+ if (lane & INTEL_CX0_LANE0)
+ return XELPDP_LANE0_PCLK_REFCLK_REQUEST;
+ else if (lane & INTEL_CX0_LANE1)
+ return XELPDP_LANE1_PCLK_REFCLK_REQUEST;
+ else
+ return XELPDP_LANE0_PCLK_REFCLK_REQUEST |
+ XELPDP_LANE1_PCLK_REFCLK_REQUEST;
+}
+
+static u32 intel_cx0_get_pclk_refclk_ack(u8 lane)
+{
+ if (lane & INTEL_CX0_LANE0)
+ return XELPDP_LANE0_PCLK_REFCLK_ACK;
+ else if (lane & INTEL_CX0_LANE1)
+ return XELPDP_LANE1_PCLK_REFCLK_ACK;
+ else
+ return XELPDP_LANE0_PCLK_REFCLK_ACK |
+ XELPDP_LANE1_PCLK_REFCLK_ACK;
+}
+
+/* FIXME: Some Type-C cases need not reset both the lanes. Handle those cases. */
+static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, enum port port,
+ bool lane_reversal)
+{
+ enum phy phy = intel_port_to_phy(i915, port);
+ u8 lane = lane_reversal ? INTEL_CX0_LANE1 :
+ INTEL_CX0_LANE0;
+
+ if (__intel_wait_for_register(&i915->uncore, XELPDP_PORT_BUF_CTL1(port),
+ XELPDP_PORT_BUF_SOC_PHY_READY,
+ XELPDP_PORT_BUF_SOC_PHY_READY,
+ XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
+ drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n",
+ phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US);
+
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+ XELPDP_LANE0_PIPE_RESET | XELPDP_LANE1_PIPE_RESET,
+ XELPDP_LANE0_PIPE_RESET | XELPDP_LANE1_PIPE_RESET);
+
+ if (__intel_wait_for_register(&i915->uncore, XELPDP_PORT_BUF_CTL2(port),
+ XELPDP_LANE0_PHY_CURRENT_STATUS | XELPDP_LANE1_PHY_CURRENT_STATUS,
+ XELPDP_LANE0_PHY_CURRENT_STATUS | XELPDP_LANE1_PHY_CURRENT_STATUS,
+ XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))
+ drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
+ phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
+
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port),
+ intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES),
+ intel_cx0_get_pclk_refclk_request(lane));
+
+ if (__intel_wait_for_register(&i915->uncore, XELPDP_PORT_CLOCK_CTL(port),
+ intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES),
+ intel_cx0_get_pclk_refclk_ack(lane),
+ XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
+ drm_warn(&i915->drm, "PHY %c failed to request refclk after %dus.\n",
+ phy_name(phy), XELPDP_REFCLK_ENABLE_TIMEOUT_US);
+
+ intel_cx0_powerdown_change_sequence(i915, port, INTEL_CX0_BOTH_LANES,
+ CX0_P2_STATE_RESET);
+ intel_cx0_setup_powerdown(i915, port);
+
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+ XELPDP_LANE0_PIPE_RESET | XELPDP_LANE1_PIPE_RESET, 0);
+
+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(port),
+ XELPDP_LANE0_PHY_CURRENT_STATUS |
+ XELPDP_LANE1_PHY_CURRENT_STATUS,
+ XELPDP_PORT_RESET_END_TIMEOUT))
+ drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n",
+ phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
+}
+
+static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
+ enum port port, int lane_count,
+ bool lane_reversal)
+{
+ u8 l0t1, l0t2, l1t1, l1t2;
+
+ intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS, C10_VDR_CTRL_MSGBUS_ACCESS,
+ MB_WRITE_COMMITTED);
+
+ l0t1 = intel_cx0_read(i915, port, 0, PHY_CX0_TX_CONTROL(1, 2));
+ l0t2 = intel_cx0_read(i915, port, 0, PHY_CX0_TX_CONTROL(2, 2));
+ l1t1 = intel_cx0_read(i915, port, 1, PHY_CX0_TX_CONTROL(1, 2));
+ l1t2 = intel_cx0_read(i915, port, 1, PHY_CX0_TX_CONTROL(2, 2));
+
+ if (lane_reversal) {
+ switch (lane_count) {
+ case 1:
+ /* Disable MLs 1(lane0), 2(lane0), 3(lane1) */
+ intel_cx0_write(i915, port, 1, PHY_CX0_TX_CONTROL(1, 2),
+ l1t1 | CONTROL2_DISABLE_SINGLE_TX,
+ MB_WRITE_COMMITTED);
+ fallthrough;
+ case 2:
+ /* Disable MLs 1(lane0), 2(lane0) */
+ intel_cx0_write(i915, port, 0, PHY_CX0_TX_CONTROL(2, 2),
+ l0t2 | CONTROL2_DISABLE_SINGLE_TX,
+ MB_WRITE_COMMITTED);
+ fallthrough;
+ case 3:
+ /* Disable MLs 1(lane0) */
+ intel_cx0_write(i915, port, 0, PHY_CX0_TX_CONTROL(1, 2),
+ l0t1 | CONTROL2_DISABLE_SINGLE_TX,
+ MB_WRITE_COMMITTED);
+ break;
+ }
+ } else {
+ switch (lane_count) {
+ case 1:
+ /* Disable MLs 2(lane0), 3(lane1), 4(lane1) */
+ intel_cx0_write(i915, port, 0, PHY_CX0_TX_CONTROL(2, 2),
+ l0t2 | CONTROL2_DISABLE_SINGLE_TX,
+ MB_WRITE_COMMITTED);
+ fallthrough;
+ case 2:
+ /* Disable MLs 3(lane1), 4(lane1) */
+ intel_cx0_write(i915, port, 1, PHY_CX0_TX_CONTROL(1, 2),
+ l1t1 | CONTROL2_DISABLE_SINGLE_TX,
+ MB_WRITE_COMMITTED);
+ fallthrough;
+ case 3:
+ /* Disable MLs 4(lane1) */
+ intel_cx0_write(i915, port, 1, PHY_CX0_TX_CONTROL(2, 2),
+ l1t2 | CONTROL2_DISABLE_SINGLE_TX,
+ MB_WRITE_COMMITTED);
+ break;
+ }
+ }
+
+ intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_UPDATE_CFG, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
+}
+
+static u32 intel_cx0_get_pclk_pll_request(u8 lane)
+{
+ if (lane & INTEL_CX0_LANE0)
+ return XELPDP_LANE0_PCLK_REFCLK_REQUEST;
+ else if (lane & INTEL_CX0_LANE1)
+ return XELPDP_LANE1_PCLK_REFCLK_REQUEST;
+ else
+ return XELPDP_LANE0_PCLK_REFCLK_REQUEST |
+ XELPDP_LANE1_PCLK_REFCLK_REQUEST;
+}
+
+static u32 intel_cx0_get_pclk_pll_ack(u8 lane)
+{
+ if (lane & INTEL_CX0_LANE0)
+ return XELPDP_LANE0_PCLK_REFCLK_REQUEST;
+ else if (lane & INTEL_CX0_LANE1)
+ return XELPDP_LANE1_PCLK_REFCLK_REQUEST;
+ else
+ return XELPDP_LANE0_PCLK_REFCLK_REQUEST |
+ XELPDP_LANE1_PCLK_REFCLK_REQUEST;
+}
+
+static void intel_c10pll_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+ bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
+ u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 :
+ INTEL_CX0_LANE0;
+
+ /*
+ * 1. Program PORT_CLOCK_CTL REGISTER to configure
+ * clock muxes, gating and SSC
+ */
+ intel_program_port_clock_ctl(encoder, crtc_state, lane_reversal);
+
+ /* 2. Bring PHY out of reset. */
+ intel_cx0_phy_lane_reset(i915, encoder->port, lane_reversal);
+
+ /*
+ * 3. Change Phy power state to Ready.
+ * TODO: For DP alt mode use only one lane.
+ */
+ intel_cx0_powerdown_change_sequence(i915, encoder->port, INTEL_CX0_BOTH_LANES,
+ CX0_P2_STATE_READY);
+
+ /* 4. Program PHY internal PLL internal registers. */
+ intel_c10_pll_program(i915, crtc_state, encoder);
+
+ /*
+ * 5. Program the enabled and disabled owned PHY lane
+ * transmitters over message bus
+ */
+ intel_c10_program_phy_lane(i915, encoder->port, crtc_state->lane_count, lane_reversal);
+
+ /*
+ * 6. Follow the Display Voltage Frequency Switching - Sequence
+ * Before Frequency Change. We handle this step in bxt_set_cdclk().
+ */
+
+ /*
+ * 7. Program DDI_CLK_VALFREQ to match intended DDI
+ * clock frequency.
+ */
+ intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
+ crtc_state->port_clock);
+ /*
+ * 8. Set PORT_CLOCK_CTL register PCLK PLL Request
+ * LN<Lane for maxPCLK> to "1" to enable PLL.
+ */
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
+ intel_cx0_get_pclk_pll_request(maxpclk_lane));
+
+ /* 9. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
+ if (__intel_wait_for_register(&i915->uncore, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
+ intel_cx0_get_pclk_pll_ack(maxpclk_lane),
+ XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL))
+ drm_warn(&i915->drm, "Port %c PLL not locked after %dus.\n",
+ phy_name(phy), XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US);
+
+ /*
+ * 10. Follow the Display Voltage Frequency Switching Sequence After
+ * Frequency Change. We handle this step in bxt_set_cdclk().
+ */
+}
+
+void intel_cx0pll_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
+ intel_c10pll_enable(encoder, crtc_state);
+}
+
+static void intel_c10pll_disable(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ /* 1. Change owned PHY lane power to Disable state. */
+ intel_cx0_powerdown_change_sequence(i915, encoder->port, INTEL_CX0_BOTH_LANES,
+ CX0_P2PG_STATE_DISABLE);
+
+ /*
+ * 2. Follow the Display Voltage Frequency Switching Sequence Before
+ * Frequency Change. We handle this step in bxt_set_cdclk().
+ */
+
+ /*
+ * 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK>
+ * to "0" to disable PLL.
+ */
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) |
+ intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0);
+
+ /* 4. Program DDI_CLK_VALFREQ to 0. */
+ intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0);
+
+ /*
+ * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".
+ */
+ if (__intel_wait_for_register(&i915->uncore, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
+ intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
+ XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL))
+ drm_warn(&i915->drm, "Port %c PLL not unlocked after %dus.\n",
+ phy_name(phy), XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US);
+
+ /*
+ * 6. Follow the Display Voltage Frequency Switching Sequence After
+ * Frequency Change. We handle this step in bxt_set_cdclk().
+ */
+
+ /* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ XELPDP_DDI_CLOCK_SELECT_MASK |
+ XELPDP_FORWARD_CLOCK_UNGATE, 0);
+}
+
+void intel_cx0pll_disable(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
+ intel_c10pll_disable(encoder);
+}
+
+void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
+ struct intel_crtc_state *new_crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_c10mpllb_state mpllb_hw_state = { 0 };
+ struct intel_c10mpllb_state *mpllb_sw_state = &new_crtc_state->c10mpllb_state;
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ struct intel_encoder *encoder;
+ struct intel_dp *intel_dp;
+ enum phy phy;
+ int i;
+ bool use_ssc = false;
+
+ if (DISPLAY_VER(i915) < 14)
+ return;
+
+ if (!new_crtc_state->hw.active)
+ return;
+
+ encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
+ phy = intel_port_to_phy(i915, encoder->port);
+
+ if (intel_crtc_has_dp_encoder(new_crtc_state)) {
+ intel_dp = enc_to_intel_dp(encoder);
+ use_ssc = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
+ DP_MAX_DOWNSPREAD_0_5);
+
+ if (intel_dp_is_edp(intel_dp) && !intel_panel_use_ssc(i915))
+ use_ssc = false;
+ }
+
+ if (!intel_is_c10phy(i915, phy))
+ return;
+
+ intel_c10mpllb_readout_hw_state(encoder, &mpllb_hw_state);
+
+ for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) {
+ u8 expected;
+
+ if (!use_ssc && i > 3 && i < 9)
+ expected = 0;
+ else
+ expected = mpllb_sw_state->pll[i];
+
+ I915_STATE_WARN(mpllb_hw_state.pll[i] != expected,
+ "[CRTC:%d:%s] mismatch in C10MPLLB: Register[%d] (expected 0x%02x, found 0x%02x)",
+ crtc->base.base.id, crtc->base.name,
+ i, expected, mpllb_hw_state.pll[i]);
+ }
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
new file mode 100644
index 000000000000..8cf340509097
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef __INTEL_CX0_PHY_H__
+#define __INTEL_CX0_PHY_H__
+
+#include <linux/types.h>
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+
+#include "i915_drv.h"
+#include "intel_display_types.h"
+
+struct drm_i915_private;
+struct intel_encoder;
+struct intel_crtc_state;
+enum phy;
+
+#define INTEL_CX0_LANE0 0x1
+#define INTEL_CX0_LANE1 0x2
+#define INTEL_CX0_BOTH_LANES 0x3
+
+#define MB_WRITE_COMMITTED 1
+#define MB_WRITE_UNCOMMITTED 0
+
+bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy);
+void intel_cx0pll_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
+void intel_cx0pll_disable(struct intel_encoder *encoder);
+void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
+ struct intel_c10mpllb_state *pll_state);
+int intel_cx0mpllb_calc_state(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder);
+void intel_c10mpllb_dump_hw_state(struct drm_i915_private *dev_priv,
+ const struct intel_c10mpllb_state *hw_state);
+int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
+ const struct intel_c10mpllb_state *pll_state);
+void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
+ struct intel_crtc_state *new_crtc_state);
+
+#endif /* __INTEL_CX0_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
new file mode 100644
index 000000000000..2820b432941a
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_CX0_REG_DEFS_H__
+#define __INTEL_CX0_REG_DEFS_H__
+
+/* C10 Vendor Registers */
+#define PHY_C10_VDR_PLL(idx) (0xC00 + (idx))
+#define C10_PLL0_FRACEN REG_BIT8(4)
+#define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0)
+#define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0)
+#define PHY_C10_VDR_CMN(idx) (0xC20 + (idx))
+#define C10_CMN0_DP_VAL 0x21
+#define C10_CMN3_TXVBOOST_MASK REG_GENMASK8(7, 5)
+#define C10_CMN3_TXVBOOST(val) REG_FIELD_PREP8(C10_CMN3_TXVBOOST_MASK, val)
+#define PHY_C10_VDR_TX(idx) (0xC30 + (idx))
+#define C10_TX0_VAL 0x10
+#define PHY_C10_VDR_CONTROL(idx) (0xC70 + (idx) - 1)
+#define C10_VDR_CTRL_MSGBUS_ACCESS REG_BIT8(2)
+#define C10_VDR_CTRL_MASTER_LANE REG_BIT8(1)
+#define C10_VDR_CTRL_UPDATE_CFG REG_BIT8(0)
+#define PHY_C10_VDR_CUSTOM_WIDTH 0xD02
+
+#endif /* __INTEL_CX0_REG_DEFS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
index dfe156141d73..f91f8824febb 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
@@ -133,4 +133,34 @@
#define XELPDP_SSC_ENABLE_PLLA REG_BIT(1)
#define XELPDP_SSC_ENABLE_PLLB REG_BIT(0)
+/* C10 Vendor Registers */
+#define PHY_C10_VDR_PLL(idx) (0xC00 + (idx))
+#define C10_PLL0_FRACEN REG_BIT8(4)
+#define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0)
+#define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0)
+#define PHY_C10_VDR_CMN(idx) (0xC20 + (idx))
+#define C10_CMN0_DP_VAL 0x21
+#define C10_CMN3_TXVBOOST_MASK REG_GENMASK8(7, 5)
+#define C10_CMN3_TXVBOOST(val) REG_FIELD_PREP8(C10_CMN3_TXVBOOST_MASK, val)
+#define PHY_C10_VDR_TX(idx) (0xC30 + (idx))
+#define C10_TX0_VAL 0x10
+#define PHY_C10_VDR_CONTROL(idx) (0xC70 + (idx) - 1)
+#define C10_VDR_CTRL_MSGBUS_ACCESS REG_BIT8(2)
+#define C10_VDR_CTRL_MASTER_LANE REG_BIT8(1)
+#define C10_VDR_CTRL_UPDATE_CFG REG_BIT8(0)
+#define PHY_C10_VDR_CUSTOM_WIDTH 0xD02
+
+#define CX0_P0_STATE_ACTIVE 0x0
+#define CX0_P2_STATE_READY 0x2
+#define CX0_P2PG_STATE_DISABLE 0x9
+#define CX0_P4PG_STATE_DISABLE 0xC
+#define CX0_P2_STATE_RESET 0x2
+
+/* PHY_C10_VDR_PLL0 */
+#define PLL_C10_MPLL_SSC_EN REG_BIT8(0)
+
+/* PIPE SPEC Defined Registers */
+#define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 + (control))
+#define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6)
+
#endif /* __INTEL_CX0_REG_DEFS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 971356237eca..639ec604babf 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -38,6 +38,7 @@
#include "intel_combo_phy_regs.h"
#include "intel_connector.h"
#include "intel_crtc.h"
+#include "intel_cx0_phy.h"
#include "intel_ddi.h"
#include "intel_ddi_buf_trans.h"
#include "intel_de.h"
@@ -3487,6 +3488,21 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
&crtc_state->dpll_hw_state);
}
+static void mtl_ddi_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
+
+ intel_c10mpllb_readout_hw_state(encoder, &crtc_state->c10mpllb_state);
+ intel_c10mpllb_dump_hw_state(i915, &crtc_state->c10mpllb_state);
+ crtc_state->port_clock = intel_c10mpllb_calc_port_clock(encoder, &crtc_state->c10mpllb_state);
+
+ intel_ddi_get_config(encoder, crtc_state);
+}
+
static void dg2_ddi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
@@ -4367,7 +4383,11 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->cloneable = 0;
encoder->pipe_mask = ~0;
- if (IS_DG2(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ encoder->enable_clock = intel_cx0pll_enable;
+ encoder->disable_clock = intel_cx0pll_disable;
+ encoder->get_config = mtl_ddi_get_config;
+ } else if (IS_DG2(dev_priv)) {
encoder->enable_clock = intel_mpllb_enable;
encoder->disable_clock = intel_mpllb_disable;
encoder->get_config = dg2_ddi_get_config;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6a8937a7d2d9..0a8749753e6e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -47,6 +47,7 @@
#include "display/intel_audio.h"
#include "display/intel_crt.h"
+#include "display/intel_cx0_phy.h"
#include "display/intel_ddi.h"
#include "display/intel_display_debugfs.h"
#include "display/intel_display_power.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 4c1de91e56ff..4f6d1463cc99 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1625,7 +1625,8 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
return;
/* 2. Initialize all combo phys */
- intel_combo_phy_init(dev_priv);
+ if (DISPLAY_VER(dev_priv) < 14)
+ intel_combo_phy_init(dev_priv);
/*
* 3. Enable Power Well 1 (PG1).
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index df7ee4969ef1..84e7f9d44ff9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -980,7 +980,7 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
bxt_verify_ddi_phy_power_wells(dev_priv);
- if (DISPLAY_VER(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11 && DISPLAY_VER(dev_priv) < 14)
/*
* DMC retains HW context only for port A, the other combo
* PHY's HW context for port B is lost after DC transitions,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e2b853e9e51d..be6ff6cdfb0b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -969,6 +969,11 @@ struct intel_mpllb_state {
u32 mpllb_sscstep;
};
+struct intel_c10mpllb_state {
+ u32 clock; /* in KHz */
+ u8 pll[20];
+};
+
struct intel_crtc_state {
/*
* uapi (drm) state. This is the software state shown to userspace.
@@ -1108,6 +1113,7 @@ struct intel_crtc_state {
union {
struct intel_dpll_hw_state dpll_hw_state;
struct intel_mpllb_state mpllb_state;
+ struct intel_c10mpllb_state c10mpllb_state;
};
/*
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index b15ba78d64d6..d6fcdf4eba0e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -7,6 +7,7 @@
#include <linux/string_helpers.h>
#include "intel_crtc.h"
+#include "intel_cx0_phy.h"
#include "intel_de.h"
#include "intel_display.h"
#include "intel_display_types.h"
@@ -993,6 +994,17 @@ static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
return 0;
}
+static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ struct intel_encoder *encoder =
+ intel_get_crtc_new_encoder(state, crtc_state);
+
+ return intel_cx0mpllb_calc_state(crtc_state, encoder);
+}
+
static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
{
return dpll->m < factor * dpll->n;
@@ -1421,6 +1433,10 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
return 0;
}
+static const struct intel_dpll_funcs mtl_dpll_funcs = {
+ .crtc_compute_clock = mtl_crtc_compute_clock,
+};
+
static const struct intel_dpll_funcs dg2_dpll_funcs = {
.crtc_compute_clock = dg2_crtc_compute_clock,
};
@@ -1515,7 +1531,11 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
void
intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
{
- if (IS_DG2(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 14)
+ dev_priv->display.funcs.dpll = &mtl_dpll_funcs;
+ else if (DISPLAY_VER(dev_priv) >= 14)
+ dev_priv->display.funcs.dpll = &mtl_dpll_funcs;
+ else if (IS_DG2(dev_priv))
dev_priv->display.funcs.dpll = &dg2_dpll_funcs;
else if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
dev_priv->display.funcs.dpll = &hsw_dpll_funcs;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index b63600d8ebeb..a3d015f44eed 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4173,7 +4173,7 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
mutex_init(&dev_priv->display.dpll.lock);
- if (IS_DG2(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv))
/* No shared DPLLs on DG2; port PLLs are part of the PHY */
dpll_mgr = NULL;
else if (IS_ALDERLAKE_P(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index 0fdcf2e6d57f..dfd9a0108b0f 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -11,6 +11,7 @@
#include "intel_atomic.h"
#include "intel_crtc.h"
#include "intel_crtc_state_dump.h"
+#include "intel_cx0_phy.h"
#include "intel_display.h"
#include "intel_display_types.h"
#include "intel_fdi.h"
@@ -235,6 +236,7 @@ void intel_modeset_verify_crtc(struct intel_crtc *crtc,
verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
intel_shared_dpll_state_verify(crtc, old_crtc_state, new_crtc_state);
intel_mpllb_state_verify(state, new_crtc_state);
+ intel_c10mpllb_state_verify(state, new_crtc_state);
}
void intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3edfbe92c6dd..41f9bc4c8266 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2121,6 +2121,11 @@
#define TRANS_PUSH_EN REG_BIT(31)
#define TRANS_PUSH_SEND REG_BIT(30)
+/* DDI Buffer Control */
+#define _DDI_CLK_VALFREQ_A 0x64030
+#define _DDI_CLK_VALFREQ_B 0x64130
+#define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B)
+
/*
* HSW+ eDP PSR registers
*
diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
index 8f486f77609f..8c9c13e81c82 100644
--- a/drivers/gpu/drm/i915/i915_reg_defs.h
+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
@@ -22,6 +22,19 @@
BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
((__n) < 0 || (__n) > 31))))
+/**
+ * REG_BIT8() - Prepare a u8 bit value
+ * @__n: 0-based bit number
+ *
+ * Local wrapper for BIT() to force u8, with compile time checks.
+ *
+ * @return: Value with bit @__n set.
+ */
+#define REG_BIT8(__n) \
+ ((u8)(BIT(__n) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
+ ((__n) < 0 || (__n) > 7))))
+
/**
* REG_GENMASK() - Prepare a continuous u32 bitmask
* @__high: 0-based high bit
@@ -52,6 +65,21 @@
__is_constexpr(__low) && \
((__low) < 0 || (__high) > 63 || (__low) > (__high)))))
+/**
+ * REG_GENMASK8() - Prepare a continuous u8 bitmask
+ * @__high: 0-based high bit
+ * @__low: 0-based low bit
+ *
+ * Local wrapper for GENMASK() to force u8, with compile time checks.
+ *
+ * @return: Continuous bitmask from @__high to @__low, inclusive.
+ */
+#define REG_GENMASK8(__high, __low) \
+ ((u8)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || (__high) > 7 || (__low) > (__high)))))
+
/*
* Local integer constant expression version of is_power_of_2().
*/
@@ -74,6 +102,23 @@
BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
+/**
+ * REG_FIELD_PREP8() - Prepare a u8 bitfield value
+ * @__mask: shifted mask defining the field's length and position
+ * @__val: value to put in the field
+ *
+ * Local copy of FIELD_PREP8() to generate an integer constant expression, force
+ * u8 and for consistency with REG_FIELD_GET8(), REG_BIT8() and REG_GENMASK8().
+ *
+ * @return: @__val masked and shifted into the field defined by @__mask.
+ */
+#define REG_FIELD_PREP8(__mask, __val) \
+ ((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) + \
+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
+
/**
* REG_FIELD_GET() - Extract a u32 bitfield value
* @__mask: shifted mask defining the field's length and position
@@ -98,6 +143,18 @@
*/
#define REG_FIELD_GET64(__mask, __val) ((u64)FIELD_GET(__mask, __val))
+/**
+ * REG_FIELD_GET8() - Extract a u8 bitfield value
+ * @__mask: shifted mask defining the field's length and position
+ * @__val: value to extract the bitfield value from
+ *
+ * Local wrapper for FIELD_GET() to force u8 and for consistency with
+ * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
+ *
+ * @return: Masked and shifted value of the field defined by @__mask in @__val.
+ */
+#define REG_FIELD_GET8(__mask, __val) ((u8)FIELD_GET(__mask, __val))
+
typedef struct {
u32 reg;
} i915_reg_t;
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 05/20] drm/i915/mtl: Add C10 phy programming for HDMI
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (3 preceding siblings ...)
2022-10-14 12:47 ` [Intel-gfx] [PATCH 04/20] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming Mika Kahola
@ 2022-10-14 12:47 ` Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 06/20] drm/i915/mtl: Add vswing programming for C10 phys Mika Kahola
` (20 subsequent siblings)
25 siblings, 0 replies; 36+ messages in thread
From: Mika Kahola @ 2022-10-14 12:47 UTC (permalink / raw)
To: intel-gfx
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Like DG2, we still don't have a proper algorithm that can be used
for calculating PHY settings, but we do have tables of register
values for a handful of the more common link rates. Some support is
better than none, so let's go ahead and add/use these tables when we
can, and also add some logic to hdmi_port_clock_valid() to filter the
modelist to just the modes we can actually support with these link
rates.
Hopefully we'll have a proper / non-encumbered algorithm to calculate
these registers by the time we upstream and we'll be able to replace
this patch with something more general purpose.
Bspec: 64568
Cc: Imre Deak <imre.deak@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 168 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 +
.../gpu/drm/i915/display/intel_cx0_reg_defs.h | 31 ++--
drivers/gpu/drm/i915/display/intel_hdmi.c | 5 +-
4 files changed, 185 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index d0e8ddd0a905..dc033174c9c0 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -484,6 +484,152 @@ static const struct intel_c10mpllb_state * const mtl_c10_edp_tables[] = {
NULL,
};
+/*
+ * HDMI link rates with 38.4 MHz reference clock.
+ */
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_25_175 = {
+ .clock = 25175,
+ .pll[0] = 0x4,
+ .pll[1] = 0,
+ .pll[2] = 0xB2,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0xD,
+ .pll[16] = 0x6,
+ .pll[17] = 0x8F,
+ .pll[18] = 0x84,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_27_0 = {
+ .clock = 27000,
+ .pll[0] = 0x34,
+ .pll[1] = 0,
+ .pll[2] = 0xC0,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x80,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0xD,
+ .pll[16] = 0x6,
+ .pll[17] = 0xCF,
+ .pll[18] = 0x84,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_74_25 = {
+ .clock = 74250,
+ .pll[0] = 0xF4,
+ .pll[1] = 0,
+ .pll[2] = 0x7A,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x58,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0xB,
+ .pll[16] = 0x6,
+ .pll[17] = 0xF,
+ .pll[18] = 0x85,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_148_5 = {
+ .clock = 148500,
+ .pll[0] = 0xF4,
+ .pll[1] = 0,
+ .pll[2] = 0x7A,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x58,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0xA,
+ .pll[16] = 0x6,
+ .pll[17] = 0xF,
+ .pll[18] = 0x85,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_594 = {
+ .clock = 594000,
+ .pll[0] = 0xF4,
+ .pll[1] = 0,
+ .pll[2] = 0x7A,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x58,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0x8,
+ .pll[16] = 0x6,
+ .pll[17] = 0xF,
+ .pll[18] = 0x85,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state * const mtl_c10_hdmi_tables[] = {
+ &mtl_c10_hdmi_25_175,
+ &mtl_c10_hdmi_27_0,
+ &mtl_c10_hdmi_74_25,
+ &mtl_c10_hdmi_148_5,
+ &mtl_c10_hdmi_594,
+ NULL,
+};
+
+int intel_c10_phy_check_hdmi_link_rate(int clock)
+{
+ const struct intel_c10mpllb_state * const *tables = mtl_c10_hdmi_tables;
+ int i;
+
+ for (i = 0; tables[i]; i++) {
+ if (clock == tables[i]->clock)
+ return MODE_OK;
+ }
+
+ return MODE_CLOCK_RANGE;
+}
+
static const struct intel_c10mpllb_state * const *
intel_c10_mpllb_tables_get(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
@@ -493,9 +639,10 @@ intel_c10_mpllb_tables_get(struct intel_crtc_state *crtc_state,
return mtl_c10_edp_tables;
else
return mtl_c10_dp_tables;
+ } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+ return mtl_c10_hdmi_tables;
}
- /* TODO: Add HDMI Support */
MISSING_CASE(encoder->type);
return NULL;
}
@@ -503,9 +650,20 @@ intel_c10_mpllb_tables_get(struct intel_crtc_state *crtc_state,
static int intel_c10mpllb_calc_state(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
const struct intel_c10mpllb_state * const *tables;
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
int i;
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+ if (intel_c10_phy_check_hdmi_link_rate(crtc_state->port_clock)
+ != MODE_OK) {
+ drm_dbg_kms(&i915->drm, "Can't support HDMI link rate %d on phy %c.\n",
+ crtc_state->port_clock, phy_name(phy));
+ return -EINVAL;
+ }
+ }
+
tables = intel_c10_mpllb_tables_get(crtc_state, encoder);
if (!tables)
return -EINVAL;
@@ -557,7 +715,8 @@ void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
cmn = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_CMN(0));
tx0 = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_TX(0));
- if (tx0 != C10_TX0_VAL || cmn != C10_CMN0_DP_VAL)
+ if (tx0 != C10_TX0_VAL || cmn != (intel_encoder_is_dp(encoder) ?
+ C10_CMN0_DP_VAL : C10_CMN0_HDMI_VAL))
drm_warn(&i915->drm, "Unexpected tx: %x or cmn: %x for phy: %c.\n",
tx0, cmn, phy_name(phy));
}
@@ -573,11 +732,10 @@ static void intel_c10_pll_program(struct drm_i915_private *i915,
INTEL_CX0_LANE0;
u8 follower_lane = lane_reversal ? INTEL_CX0_LANE0 :
INTEL_CX0_LANE1;
-
int i;
struct intel_dp *intel_dp;
bool use_ssc = false;
- u8 cmn0 = 0;
+ u8 cmn0;
if (intel_crtc_has_dp_encoder(crtc_state)) {
intel_dp = enc_to_intel_dp(encoder);
@@ -588,6 +746,8 @@ static void intel_c10_pll_program(struct drm_i915_private *i915,
use_ssc = false;
cmn0 = C10_CMN0_DP_VAL;
+ } else {
+ cmn0 = C10_CMN0_HDMI_VAL;
}
intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 8cf340509097..f8023f240727 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -39,5 +39,6 @@ int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
const struct intel_c10mpllb_state *pll_state);
void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
struct intel_crtc_state *new_crtc_state);
+int intel_c10_phy_check_hdmi_link_rate(int clock);
#endif /* __INTEL_CX0_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
index f91f8824febb..b394f5c23acb 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
@@ -134,21 +134,22 @@
#define XELPDP_SSC_ENABLE_PLLB REG_BIT(0)
/* C10 Vendor Registers */
-#define PHY_C10_VDR_PLL(idx) (0xC00 + (idx))
-#define C10_PLL0_FRACEN REG_BIT8(4)
-#define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0)
-#define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0)
-#define PHY_C10_VDR_CMN(idx) (0xC20 + (idx))
-#define C10_CMN0_DP_VAL 0x21
-#define C10_CMN3_TXVBOOST_MASK REG_GENMASK8(7, 5)
-#define C10_CMN3_TXVBOOST(val) REG_FIELD_PREP8(C10_CMN3_TXVBOOST_MASK, val)
-#define PHY_C10_VDR_TX(idx) (0xC30 + (idx))
-#define C10_TX0_VAL 0x10
-#define PHY_C10_VDR_CONTROL(idx) (0xC70 + (idx) - 1)
-#define C10_VDR_CTRL_MSGBUS_ACCESS REG_BIT8(2)
-#define C10_VDR_CTRL_MASTER_LANE REG_BIT8(1)
-#define C10_VDR_CTRL_UPDATE_CFG REG_BIT8(0)
-#define PHY_C10_VDR_CUSTOM_WIDTH 0xD02
+#define PHY_C10_VDR_PLL(idx) (0xC00 + (idx))
+#define C10_PLL0_FRACEN REG_BIT8(4)
+#define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0)
+#define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0)
+#define PHY_C10_VDR_CMN(idx) (0xC20 + (idx))
+#define C10_CMN0_DP_VAL 0x21
+#define C10_CMN0_HDMI_VAL 0x1
+#define C10_CMN3_TXVBOOST_MASK REG_GENMASK8(7, 5)
+#define C10_CMN3_TXVBOOST(val) REG_FIELD_PREP8(C10_CMN3_TXVBOOST_MASK, val)
+#define PHY_C10_VDR_TX(idx) (0xC30 + (idx))
+#define C10_TX0_VAL 0x10
+#define PHY_C10_VDR_CONTROL(idx) (0xC70 + (idx) - 1)
+#define C10_VDR_CTRL_MSGBUS_ACCESS REG_BIT8(2)
+#define C10_VDR_CTRL_MASTER_LANE REG_BIT8(1)
+#define C10_VDR_CTRL_UPDATE_CFG REG_BIT8(0)
+#define PHY_C10_VDR_CUSTOM_WIDTH 0xD02
#define CX0_P0_STATE_ACTIVE 0x0
#define CX0_P2_STATE_READY 0x2
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 93519fb23d9d..c274098f2196 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -44,6 +44,7 @@
#include "i915_drv.h"
#include "intel_atomic.h"
#include "intel_connector.h"
+#include "intel_cx0_phy.h"
#include "intel_ddi.h"
#include "intel_de.h"
#include "intel_display_types.h"
@@ -1875,7 +1876,9 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
* FIXME: We will hopefully get an algorithmic way of programming
* the MPLLB for HDMI in the future.
*/
- if (IS_DG2(dev_priv))
+ if (IS_METEORLAKE(dev_priv))
+ return intel_c10_phy_check_hdmi_link_rate(clock);
+ else if (IS_DG2(dev_priv))
return intel_snps_phy_check_hdmi_link_rate(clock);
return MODE_OK;
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 06/20] drm/i915/mtl: Add vswing programming for C10 phys
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (4 preceding siblings ...)
2022-10-14 12:47 ` [Intel-gfx] [PATCH 05/20] drm/i915/mtl: Add C10 phy programming for HDMI Mika Kahola
@ 2022-10-14 12:47 ` Mika Kahola
2022-10-31 20:29 ` Taylor, Clinton A
2022-10-14 12:47 ` [Intel-gfx] [PATCH 07/20] drm/i915/mtl: Add support for PM DEMAND Mika Kahola
` (19 subsequent siblings)
25 siblings, 1 reply; 36+ messages in thread
From: Mika Kahola @ 2022-10-14 12:47 UTC (permalink / raw)
To: intel-gfx
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
C10 phys uses direct mapping internally for voltage and pre-emphasis levels.
Program the levels directly to the fields in the VDR Registers.
Bspec: 65449
Cc: Imre Deak <imre.deak@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 143 ++++++++++++++++--
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
.../gpu/drm/i915/display/intel_cx0_reg_defs.h | 6 +
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
.../drm/i915/display/intel_ddi_buf_trans.c | 36 ++++-
.../drm/i915/display/intel_ddi_buf_trans.h | 6 +
.../i915/display/intel_display_power_map.c | 1 +
7 files changed, 185 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index dc033174c9c0..ef874986940d 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -6,10 +6,14 @@
#include "i915_reg_defs.h"
#include "intel_cx0_phy.h"
#include "intel_cx0_reg_defs.h"
+#include "intel_ddi.h"
+#include "intel_ddi_buf_trans.h"
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_panel.h"
+#include "intel_psr.h"
+#include "intel_uncore.h"
bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy)
{
@@ -19,6 +23,15 @@ bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy)
return false;
}
+static void
+assert_dc_off(struct drm_i915_private *i915)
+{
+ bool enabled;
+
+ enabled = intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF);
+ drm_WARN_ON(&i915->drm, !enabled);
+}
+
static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, int lane)
{
enum phy phy = intel_port_to_phy(i915, port);
@@ -108,6 +121,8 @@ static u8 intel_cx0_read(struct drm_i915_private *i915, enum port port,
int i, status;
u32 val;
+ assert_dc_off(i915);
+
for (i = 0; i < 3; i++) {
status = __intel_cx0_read(i915, port, lane, addr, &val);
@@ -191,6 +206,8 @@ static void __intel_cx0_write(struct drm_i915_private *i915, enum port port,
enum phy phy = intel_port_to_phy(i915, port);
int i, status;
+ assert_dc_off(i915);
+
for (i = 0; i < 3; i++) {
status = __intel_cx0_write_once(i915, port, lane, addr, data, committed);
@@ -240,6 +257,84 @@ static void intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
}
}
+/*
+ * Prepare HW for CX0 phy transactions.
+ *
+ * It is required that PSR and DC5/6 are disabled before any CX0 message
+ * bus transaction is executed.
+ */
+static intel_wakeref_t intel_cx0_phy_transaction_begin(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ intel_psr_pause(intel_dp);
+ return intel_display_power_get(i915, POWER_DOMAIN_DC_OFF);
+}
+
+static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_wakeref_t wakeref)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ intel_psr_resume(intel_dp);
+ intel_display_power_put(i915, POWER_DOMAIN_DC_OFF, wakeref);
+}
+
+void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+ bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
+ u8 master_lane = lane_reversal ? INTEL_CX0_LANE1 :
+ INTEL_CX0_LANE0;
+ const struct intel_ddi_buf_trans *trans;
+ intel_wakeref_t wakeref;
+ int n_entries, ln;
+
+ wakeref = intel_cx0_phy_transaction_begin(encoder);
+
+ trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
+ if (drm_WARN_ON_ONCE(&i915->drm, !trans))
+ return;
+
+ intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
+ 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
+
+ for (ln = 0; ln < 4; ln++) {
+ int level = intel_ddi_level(encoder, crtc_state, ln);
+ int lane, tx;
+
+ lane = ln / 2;
+ tx = ln % 2 + 1;
+
+ intel_cx0_rmw(i915, encoder->port, lane, PHY_CX0_TX_CONTROL(tx, 2),
+ C10_PHY_VSWING_PREEMPH_MASK,
+ C10_PHY_VSWING_PREEMPH(trans->entries[level].direct.preemph),
+ MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, encoder->port, lane, PHY_CX0_TX_CONTROL(tx, 8),
+ C10_PHY_VSWING_LEVEL_MASK,
+ C10_PHY_VSWING_LEVEL(trans->entries[level].direct.level),
+ MB_WRITE_COMMITTED);
+ }
+
+ intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG,
+ MB_WRITE_COMMITTED);
+#if 0
+ /*
+ * FIXME: Revisit this code to see why we can't update
+ * config on Lane 1
+ */
+ intel_cx0_rmw(i915, encoder->port, !master_lane, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_UPDATE_CFG, C10_VDR_CTRL_UPDATE_CFG,
+ MB_WRITE_COMMITTED);
+#endif
+
+ intel_cx0_phy_transaction_end(encoder, wakeref);
+}
+
/*
* Basic DP link rates with 38.4 MHz reference clock.
* Note: The tables below are with SSC. In non-ssc
@@ -698,9 +793,12 @@ void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
u8 lane = lane_reversal ? INTEL_CX0_LANE1 :
INTEL_CX0_LANE0;
enum phy phy = intel_port_to_phy(i915, encoder->port);
+ intel_wakeref_t wakeref;
int i;
u8 cmn, tx0;
+ wakeref = intel_cx0_phy_transaction_begin(encoder);
+
/*
* According to C10 VDR Register programming Sequence we need
* to do this to read PHY internal registers from MsgBus.
@@ -719,6 +817,8 @@ void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
C10_CMN0_DP_VAL : C10_CMN0_HDMI_VAL))
drm_warn(&i915->drm, "Unexpected tx: %x or cmn: %x for phy: %c.\n",
tx0, cmn, phy_name(phy));
+
+ intel_cx0_phy_transaction_end(encoder, wakeref);
}
static void intel_c10_pll_program(struct drm_i915_private *i915,
@@ -849,17 +949,20 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
if (intel_crtc_has_dp_encoder(crtc_state)) {
intel_dp = enc_to_intel_dp(encoder);
- ssc_enabled = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
- DP_MAX_DOWNSPREAD_0_5;
+ ssc_enabled = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
+ DP_MAX_DOWNSPREAD_0_5);
+
+ if (intel_dp_is_edp(intel_dp) && !intel_panel_use_ssc(i915))
+ ssc_enabled = false;
/* TODO: DP2.0 10G and 20G rates enable MPLLA*/
val |= ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
}
+
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
- XELPDP_LANE1_PHY_CLOCK_SELECT |
- XELPDP_FORWARD_CLOCK_UNGATE |
+ XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
XELPDP_DDI_CLOCK_SELECT_MASK |
- XELPDP_SSC_ENABLE_PLLB, val);
+ XELPDP_SSC_ENABLE_PLLA | XELPDP_SSC_ENABLE_PLLB, val);
}
static u32 intel_cx0_get_powerdown_update(u8 lane)
@@ -986,9 +1089,12 @@ static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
{
u8 l0t1, l0t2, l1t1, l1t2;
- intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
- C10_VDR_CTRL_MSGBUS_ACCESS, C10_VDR_CTRL_MSGBUS_ACCESS,
- MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, port, 1, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_UPDATE_CFG,
+ C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, port, 0, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_UPDATE_CFG,
+ C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
l0t1 = intel_cx0_read(i915, port, 0, PHY_CX0_TX_CONTROL(1, 2));
l0t2 = intel_cx0_read(i915, port, 0, PHY_CX0_TX_CONTROL(2, 2));
@@ -1039,8 +1145,12 @@ static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
}
}
- intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
- C10_VDR_CTRL_UPDATE_CFG, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, port, 1, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_UPDATE_CFG | C10_VDR_CTRL_MSGBUS_ACCESS,
+ C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, port, 0, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_UPDATE_CFG | C10_VDR_CTRL_MSGBUS_ACCESS,
+ C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
}
static u32 intel_cx0_get_pclk_pll_request(u8 lane)
@@ -1138,9 +1248,14 @@ void intel_cx0pll_enable(struct intel_encoder *encoder,
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
+ intel_wakeref_t wakeref;
+
+ wakeref = intel_cx0_phy_transaction_begin(encoder);
drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
intel_c10pll_enable(encoder, crtc_state);
+
+ intel_cx0_phy_transaction_end(encoder, wakeref);
}
static void intel_c10pll_disable(struct intel_encoder *encoder)
@@ -1185,7 +1300,8 @@ static void intel_c10pll_disable(struct intel_encoder *encoder)
/* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
- XELPDP_DDI_CLOCK_SELECT_MASK |
+ XELPDP_DDI_CLOCK_SELECT_MASK, 0);
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
XELPDP_FORWARD_CLOCK_UNGATE, 0);
}
@@ -1193,9 +1309,14 @@ void intel_cx0pll_disable(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
+ intel_wakeref_t wakeref;
+
+ wakeref = intel_cx0_phy_transaction_begin(encoder);
drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
intel_c10pll_disable(encoder);
+
+ intel_cx0_phy_transaction_end(encoder, wakeref);
}
void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index f8023f240727..952c7deeffaa 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -40,5 +40,7 @@ int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
struct intel_crtc_state *new_crtc_state);
int intel_c10_phy_check_hdmi_link_rate(int clock);
+void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_CX0_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
index b394f5c23acb..fad6308bbf77 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
@@ -164,4 +164,10 @@
#define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 + (control))
#define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6)
+/* C10 Phy VSWING Masks */
+#define C10_PHY_VSWING_LEVEL_MASK REG_GENMASK8(2, 0)
+#define C10_PHY_VSWING_LEVEL(val) REG_FIELD_PREP8(C10_PHY_VSWING_LEVEL_MASK, val)
+#define C10_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(1, 0)
+#define C10_PHY_VSWING_PREEMPH(val) REG_FIELD_PREP8(C10_PHY_VSWING_PREEMPH_MASK, val)
+
#endif /* __INTEL_CX0_REG_DEFS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 639ec604babf..1380ed2221ad 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4445,7 +4445,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->get_config = hsw_ddi_get_config;
}
- if (IS_DG2(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ encoder->set_signal_levels = intel_cx0_phy_set_signal_levels;
+ } else if (IS_DG2(dev_priv)) {
encoder->set_signal_levels = intel_snps_phy_set_signal_levels;
} else if (DISPLAY_VER(dev_priv) >= 12) {
if (intel_phy_is_combo(dev_priv, phy))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 006a2e979000..49f8a0a6593b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1035,6 +1035,30 @@ static const struct intel_ddi_buf_trans dg2_snps_trans_uhbr = {
.num_entries = ARRAY_SIZE(_dg2_snps_trans_uhbr),
};
+/*
+ * Some platforms don't need a mapping table and only expect us to
+ * to program the vswing + preemphasis levels directly since the
+ * hardware will do its own mapping to tuning values internally.
+ */
+static const union intel_ddi_buf_trans_entry direct_map_trans[] = {
+ { .direct = { .level = 0, .preemph = 0 } },
+ { .direct = { .level = 0, .preemph = 1 } },
+ { .direct = { .level = 0, .preemph = 2 } },
+ { .direct = { .level = 0, .preemph = 3 } },
+ { .direct = { .level = 1, .preemph = 0 } },
+ { .direct = { .level = 1, .preemph = 0 } },
+ { .direct = { .level = 1, .preemph = 2 } },
+ { .direct = { .level = 2, .preemph = 0 } },
+ { .direct = { .level = 2, .preemph = 1 } },
+ { .direct = { .level = 3, .preemph = 0 } },
+};
+
+static const struct intel_ddi_buf_trans mtl_cx0c10_trans = {
+ .entries = direct_map_trans,
+ .num_entries = ARRAY_SIZE(direct_map_trans),
+ .hdmi_default_entry = ARRAY_SIZE(direct_map_trans) - 1,
+};
+
bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
{
return table == &tgl_combo_phy_trans_edp_hbr2_hobl;
@@ -1606,12 +1630,22 @@ dg2_get_snps_buf_trans(struct intel_encoder *encoder,
return intel_get_buf_trans(&dg2_snps_trans, n_entries);
}
+static const struct intel_ddi_buf_trans *
+mtl_get_cx0_buf_trans(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int *n_entries)
+{
+ return intel_get_buf_trans(&mtl_cx0c10_trans, n_entries);
+}
+
void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
- if (IS_DG2(i915)) {
+ if (DISPLAY_VER(i915) >= 14) {
+ encoder->get_buf_trans = mtl_get_cx0_buf_trans;
+ } else if (IS_DG2(i915)) {
encoder->get_buf_trans = dg2_get_snps_buf_trans;
} else if (IS_ALDERLAKE_P(i915)) {
if (intel_phy_is_combo(i915, phy))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
index 2133984a572b..e4a857b9829d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
@@ -51,6 +51,11 @@ struct dg2_snps_phy_buf_trans {
u8 post_cursor;
};
+struct direct_phy_buf_trans {
+ u8 level;
+ u8 preemph;
+};
+
union intel_ddi_buf_trans_entry {
struct hsw_ddi_buf_trans hsw;
struct bxt_ddi_buf_trans bxt;
@@ -58,6 +63,7 @@ union intel_ddi_buf_trans_entry {
struct icl_mg_phy_ddi_buf_trans mg;
struct tgl_dkl_phy_ddi_buf_trans dkl;
struct dg2_snps_phy_buf_trans snps;
+ struct direct_phy_buf_trans direct;
};
struct intel_ddi_buf_trans {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index dc04afc6cc8f..45c3ab4e2f28 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1374,6 +1374,7 @@ I915_DECL_PW_DOMAINS(xelpdp_pwdoms_dc_off,
XELPDP_PW_2_POWER_DOMAINS,
POWER_DOMAIN_AUDIO_MMIO,
POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_DC_OFF,
POWER_DOMAIN_AUX_A,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_INIT);
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [Intel-gfx] [PATCH 06/20] drm/i915/mtl: Add vswing programming for C10 phys
2022-10-14 12:47 ` [Intel-gfx] [PATCH 06/20] drm/i915/mtl: Add vswing programming for C10 phys Mika Kahola
@ 2022-10-31 20:29 ` Taylor, Clinton A
2022-11-01 7:31 ` Kahola, Mika
0 siblings, 1 reply; 36+ messages in thread
From: Taylor, Clinton A @ 2022-10-31 20:29 UTC (permalink / raw)
To: Kahola, Mika, intel-gfx@lists.freedesktop.org
[-- Attachment #1: Type: text/plain, Size: 20216 bytes --]
to fix the FIXME in intel_cx0_phy_set_signal_levels() we need the following patch snipet to be incorporated into this patch.
@@ -331,18 +331,14 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
}
}
- intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CONTROL(1),
- C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG,
+ intel_cx0_write(i915, encoder->port, !master_lane, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_UPDATE_CFG,
MB_WRITE_COMMITTED);
-#if 0
- /*
- * FIXME: Revisit this code to see why we can't update
- * config on Lane 1
- */
- intel_cx0_rmw(i915, encoder->port, !master_lane, PHY_C10_VDR_CONTROL(1),
- C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_UPDATE_CFG, C10_VDR_CTRL_UPDATE_CFG,
+
+ intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG,
MB_WRITE_COMMITTED);
-#endif
+
intel_cx0_phy_transaction_end(encoder, wakeref);
}
Sorry for the top post - webmail
-Clint
________________________________
From: Kahola, Mika <mika.kahola@intel.com>
Sent: Friday, October 14, 2022 5:47 AM
To: intel-gfx@lists.freedesktop.org <intel-gfx@lists.freedesktop.org>
Cc: Kahola, Mika <mika.kahola@intel.com>; Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; Deak, Imre <imre.deak@intel.com>; Shankar, Uma <uma.shankar@intel.com>; Taylor, Clinton A <clinton.a.taylor@intel.com>
Subject: [PATCH 06/20] drm/i915/mtl: Add vswing programming for C10 phys
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
C10 phys uses direct mapping internally for voltage and pre-emphasis levels.
Program the levels directly to the fields in the VDR Registers.
Bspec: 65449
Cc: Imre Deak <imre.deak@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 143 ++++++++++++++++--
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
.../gpu/drm/i915/display/intel_cx0_reg_defs.h | 6 +
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
.../drm/i915/display/intel_ddi_buf_trans.c | 36 ++++-
.../drm/i915/display/intel_ddi_buf_trans.h | 6 +
.../i915/display/intel_display_power_map.c | 1 +
7 files changed, 185 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index dc033174c9c0..ef874986940d 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -6,10 +6,14 @@
#include "i915_reg_defs.h"
#include "intel_cx0_phy.h"
#include "intel_cx0_reg_defs.h"
+#include "intel_ddi.h"
+#include "intel_ddi_buf_trans.h"
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_panel.h"
+#include "intel_psr.h"
+#include "intel_uncore.h"
bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy)
{
@@ -19,6 +23,15 @@ bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy)
return false;
}
+static void
+assert_dc_off(struct drm_i915_private *i915)
+{
+ bool enabled;
+
+ enabled = intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF);
+ drm_WARN_ON(&i915->drm, !enabled);
+}
+
static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, int lane)
{
enum phy phy = intel_port_to_phy(i915, port);
@@ -108,6 +121,8 @@ static u8 intel_cx0_read(struct drm_i915_private *i915, enum port port,
int i, status;
u32 val;
+ assert_dc_off(i915);
+
for (i = 0; i < 3; i++) {
status = __intel_cx0_read(i915, port, lane, addr, &val);
@@ -191,6 +206,8 @@ static void __intel_cx0_write(struct drm_i915_private *i915, enum port port,
enum phy phy = intel_port_to_phy(i915, port);
int i, status;
+ assert_dc_off(i915);
+
for (i = 0; i < 3; i++) {
status = __intel_cx0_write_once(i915, port, lane, addr, data, committed);
@@ -240,6 +257,84 @@ static void intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
}
}
+/*
+ * Prepare HW for CX0 phy transactions.
+ *
+ * It is required that PSR and DC5/6 are disabled before any CX0 message
+ * bus transaction is executed.
+ */
+static intel_wakeref_t intel_cx0_phy_transaction_begin(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ intel_psr_pause(intel_dp);
+ return intel_display_power_get(i915, POWER_DOMAIN_DC_OFF);
+}
+
+static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_wakeref_t wakeref)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ intel_psr_resume(intel_dp);
+ intel_display_power_put(i915, POWER_DOMAIN_DC_OFF, wakeref);
+}
+
+void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+ bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
+ u8 master_lane = lane_reversal ? INTEL_CX0_LANE1 :
+ INTEL_CX0_LANE0;
+ const struct intel_ddi_buf_trans *trans;
+ intel_wakeref_t wakeref;
+ int n_entries, ln;
+
+ wakeref = intel_cx0_phy_transaction_begin(encoder);
+
+ trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
+ if (drm_WARN_ON_ONCE(&i915->drm, !trans))
+ return;
+
+ intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
+ 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
+
+ for (ln = 0; ln < 4; ln++) {
+ int level = intel_ddi_level(encoder, crtc_state, ln);
+ int lane, tx;
+
+ lane = ln / 2;
+ tx = ln % 2 + 1;
+
+ intel_cx0_rmw(i915, encoder->port, lane, PHY_CX0_TX_CONTROL(tx, 2),
+ C10_PHY_VSWING_PREEMPH_MASK,
+ C10_PHY_VSWING_PREEMPH(trans->entries[level].direct.preemph),
+ MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, encoder->port, lane, PHY_CX0_TX_CONTROL(tx, 8),
+ C10_PHY_VSWING_LEVEL_MASK,
+ C10_PHY_VSWING_LEVEL(trans->entries[level].direct.level),
+ MB_WRITE_COMMITTED);
+ }
+
+ intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG,
+ MB_WRITE_COMMITTED);
+#if 0
+ /*
+ * FIXME: Revisit this code to see why we can't update
+ * config on Lane 1
+ */
+ intel_cx0_rmw(i915, encoder->port, !master_lane, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_UPDATE_CFG, C10_VDR_CTRL_UPDATE_CFG,
+ MB_WRITE_COMMITTED);
+#endif
+
+ intel_cx0_phy_transaction_end(encoder, wakeref);
+}
+
/*
* Basic DP link rates with 38.4 MHz reference clock.
* Note: The tables below are with SSC. In non-ssc
@@ -698,9 +793,12 @@ void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
u8 lane = lane_reversal ? INTEL_CX0_LANE1 :
INTEL_CX0_LANE0;
enum phy phy = intel_port_to_phy(i915, encoder->port);
+ intel_wakeref_t wakeref;
int i;
u8 cmn, tx0;
+ wakeref = intel_cx0_phy_transaction_begin(encoder);
+
/*
* According to C10 VDR Register programming Sequence we need
* to do this to read PHY internal registers from MsgBus.
@@ -719,6 +817,8 @@ void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
C10_CMN0_DP_VAL : C10_CMN0_HDMI_VAL))
drm_warn(&i915->drm, "Unexpected tx: %x or cmn: %x for phy: %c.\n",
tx0, cmn, phy_name(phy));
+
+ intel_cx0_phy_transaction_end(encoder, wakeref);
}
static void intel_c10_pll_program(struct drm_i915_private *i915,
@@ -849,17 +949,20 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
if (intel_crtc_has_dp_encoder(crtc_state)) {
intel_dp = enc_to_intel_dp(encoder);
- ssc_enabled = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
- DP_MAX_DOWNSPREAD_0_5;
+ ssc_enabled = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
+ DP_MAX_DOWNSPREAD_0_5);
+
+ if (intel_dp_is_edp(intel_dp) && !intel_panel_use_ssc(i915))
+ ssc_enabled = false;
/* TODO: DP2.0 10G and 20G rates enable MPLLA*/
val |= ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
}
+
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
- XELPDP_LANE1_PHY_CLOCK_SELECT |
- XELPDP_FORWARD_CLOCK_UNGATE |
+ XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
XELPDP_DDI_CLOCK_SELECT_MASK |
- XELPDP_SSC_ENABLE_PLLB, val);
+ XELPDP_SSC_ENABLE_PLLA | XELPDP_SSC_ENABLE_PLLB, val);
}
static u32 intel_cx0_get_powerdown_update(u8 lane)
@@ -986,9 +1089,12 @@ static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
{
u8 l0t1, l0t2, l1t1, l1t2;
- intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
- C10_VDR_CTRL_MSGBUS_ACCESS, C10_VDR_CTRL_MSGBUS_ACCESS,
- MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, port, 1, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_UPDATE_CFG,
+ C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, port, 0, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_UPDATE_CFG,
+ C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
l0t1 = intel_cx0_read(i915, port, 0, PHY_CX0_TX_CONTROL(1, 2));
l0t2 = intel_cx0_read(i915, port, 0, PHY_CX0_TX_CONTROL(2, 2));
@@ -1039,8 +1145,12 @@ static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
}
}
- intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
- C10_VDR_CTRL_UPDATE_CFG, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, port, 1, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_UPDATE_CFG | C10_VDR_CTRL_MSGBUS_ACCESS,
+ C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, port, 0, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_UPDATE_CFG | C10_VDR_CTRL_MSGBUS_ACCESS,
+ C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
}
static u32 intel_cx0_get_pclk_pll_request(u8 lane)
@@ -1138,9 +1248,14 @@ void intel_cx0pll_enable(struct intel_encoder *encoder,
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
+ intel_wakeref_t wakeref;
+
+ wakeref = intel_cx0_phy_transaction_begin(encoder);
drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
intel_c10pll_enable(encoder, crtc_state);
+
+ intel_cx0_phy_transaction_end(encoder, wakeref);
}
static void intel_c10pll_disable(struct intel_encoder *encoder)
@@ -1185,7 +1300,8 @@ static void intel_c10pll_disable(struct intel_encoder *encoder)
/* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
- XELPDP_DDI_CLOCK_SELECT_MASK |
+ XELPDP_DDI_CLOCK_SELECT_MASK, 0);
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
XELPDP_FORWARD_CLOCK_UNGATE, 0);
}
@@ -1193,9 +1309,14 @@ void intel_cx0pll_disable(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
+ intel_wakeref_t wakeref;
+
+ wakeref = intel_cx0_phy_transaction_begin(encoder);
drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
intel_c10pll_disable(encoder);
+
+ intel_cx0_phy_transaction_end(encoder, wakeref);
}
void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index f8023f240727..952c7deeffaa 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -40,5 +40,7 @@ int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
struct intel_crtc_state *new_crtc_state);
int intel_c10_phy_check_hdmi_link_rate(int clock);
+void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_CX0_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
index b394f5c23acb..fad6308bbf77 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
@@ -164,4 +164,10 @@
#define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 + (control))
#define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6)
+/* C10 Phy VSWING Masks */
+#define C10_PHY_VSWING_LEVEL_MASK REG_GENMASK8(2, 0)
+#define C10_PHY_VSWING_LEVEL(val) REG_FIELD_PREP8(C10_PHY_VSWING_LEVEL_MASK, val)
+#define C10_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(1, 0)
+#define C10_PHY_VSWING_PREEMPH(val) REG_FIELD_PREP8(C10_PHY_VSWING_PREEMPH_MASK, val)
+
#endif /* __INTEL_CX0_REG_DEFS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 639ec604babf..1380ed2221ad 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4445,7 +4445,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->get_config = hsw_ddi_get_config;
}
- if (IS_DG2(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ encoder->set_signal_levels = intel_cx0_phy_set_signal_levels;
+ } else if (IS_DG2(dev_priv)) {
encoder->set_signal_levels = intel_snps_phy_set_signal_levels;
} else if (DISPLAY_VER(dev_priv) >= 12) {
if (intel_phy_is_combo(dev_priv, phy))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 006a2e979000..49f8a0a6593b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1035,6 +1035,30 @@ static const struct intel_ddi_buf_trans dg2_snps_trans_uhbr = {
.num_entries = ARRAY_SIZE(_dg2_snps_trans_uhbr),
};
+/*
+ * Some platforms don't need a mapping table and only expect us to
+ * to program the vswing + preemphasis levels directly since the
+ * hardware will do its own mapping to tuning values internally.
+ */
+static const union intel_ddi_buf_trans_entry direct_map_trans[] = {
+ { .direct = { .level = 0, .preemph = 0 } },
+ { .direct = { .level = 0, .preemph = 1 } },
+ { .direct = { .level = 0, .preemph = 2 } },
+ { .direct = { .level = 0, .preemph = 3 } },
+ { .direct = { .level = 1, .preemph = 0 } },
+ { .direct = { .level = 1, .preemph = 0 } },
+ { .direct = { .level = 1, .preemph = 2 } },
+ { .direct = { .level = 2, .preemph = 0 } },
+ { .direct = { .level = 2, .preemph = 1 } },
+ { .direct = { .level = 3, .preemph = 0 } },
+};
+
+static const struct intel_ddi_buf_trans mtl_cx0c10_trans = {
+ .entries = direct_map_trans,
+ .num_entries = ARRAY_SIZE(direct_map_trans),
+ .hdmi_default_entry = ARRAY_SIZE(direct_map_trans) - 1,
+};
+
bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
{
return table == &tgl_combo_phy_trans_edp_hbr2_hobl;
@@ -1606,12 +1630,22 @@ dg2_get_snps_buf_trans(struct intel_encoder *encoder,
return intel_get_buf_trans(&dg2_snps_trans, n_entries);
}
+static const struct intel_ddi_buf_trans *
+mtl_get_cx0_buf_trans(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int *n_entries)
+{
+ return intel_get_buf_trans(&mtl_cx0c10_trans, n_entries);
+}
+
void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
- if (IS_DG2(i915)) {
+ if (DISPLAY_VER(i915) >= 14) {
+ encoder->get_buf_trans = mtl_get_cx0_buf_trans;
+ } else if (IS_DG2(i915)) {
encoder->get_buf_trans = dg2_get_snps_buf_trans;
} else if (IS_ALDERLAKE_P(i915)) {
if (intel_phy_is_combo(i915, phy))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
index 2133984a572b..e4a857b9829d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
@@ -51,6 +51,11 @@ struct dg2_snps_phy_buf_trans {
u8 post_cursor;
};
+struct direct_phy_buf_trans {
+ u8 level;
+ u8 preemph;
+};
+
union intel_ddi_buf_trans_entry {
struct hsw_ddi_buf_trans hsw;
struct bxt_ddi_buf_trans bxt;
@@ -58,6 +63,7 @@ union intel_ddi_buf_trans_entry {
struct icl_mg_phy_ddi_buf_trans mg;
struct tgl_dkl_phy_ddi_buf_trans dkl;
struct dg2_snps_phy_buf_trans snps;
+ struct direct_phy_buf_trans direct;
};
struct intel_ddi_buf_trans {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index dc04afc6cc8f..45c3ab4e2f28 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1374,6 +1374,7 @@ I915_DECL_PW_DOMAINS(xelpdp_pwdoms_dc_off,
XELPDP_PW_2_POWER_DOMAINS,
POWER_DOMAIN_AUDIO_MMIO,
POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_DC_OFF,
POWER_DOMAIN_AUX_A,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_INIT);
--
2.34.1
[-- Attachment #2: Type: text/html, Size: 37806 bytes --]
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [Intel-gfx] [PATCH 06/20] drm/i915/mtl: Add vswing programming for C10 phys
2022-10-31 20:29 ` Taylor, Clinton A
@ 2022-11-01 7:31 ` Kahola, Mika
0 siblings, 0 replies; 36+ messages in thread
From: Kahola, Mika @ 2022-11-01 7:31 UTC (permalink / raw)
To: Taylor, Clinton A, intel-gfx@lists.freedesktop.org
[-- Attachment #1: Type: text/plain, Size: 21176 bytes --]
From: Taylor, Clinton A <clinton.a.taylor@intel.com>
Sent: Monday, October 31, 2022 10:29 PM
To: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org
Cc: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; Deak, Imre <imre.deak@intel.com>; Shankar, Uma <uma.shankar@intel.com>
Subject: Re: [PATCH 06/20] drm/i915/mtl: Add vswing programming for C10 phys
to fix the FIXME in intel_cx0_phy_set_signal_levels() we need the following patch snipet to be incorporated into this patch.
@@ -331,18 +331,14 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
}
}
- intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CONTROL(1),
- C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG,
+ intel_cx0_write(i915, encoder->port, !master_lane, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_UPDATE_CFG,
MB_WRITE_COMMITTED);
-#if 0
- /*
- * FIXME: Revisit this code to see why we can't update
- * config on Lane 1
- */
- intel_cx0_rmw(i915, encoder->port, !master_lane, PHY_C10_VDR_CONTROL(1),
- C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_UPDATE_CFG, C10_VDR_CTRL_UPDATE_CFG,
+
+ intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG,
MB_WRITE_COMMITTED);
-#endif
+
intel_cx0_phy_transaction_end(encoder, wakeref);
}
Sorry for the top post - webmail
-Clint
Thanks Clint! I will add this snippet into v2 version of the C10/C20/TBT patch series.
Cheers,
Mika
________________________________
From: Kahola, Mika <mika.kahola@intel.com<mailto:mika.kahola@intel.com>>
Sent: Friday, October 14, 2022 5:47 AM
To: intel-gfx@lists.freedesktop.org<mailto:intel-gfx@lists.freedesktop.org> <intel-gfx@lists.freedesktop.org<mailto:intel-gfx@lists.freedesktop.org>>
Cc: Kahola, Mika <mika.kahola@intel.com<mailto:mika.kahola@intel.com>>; Sripada, Radhakrishna <radhakrishna.sripada@intel.com<mailto:radhakrishna.sripada@intel.com>>; Deak, Imre <imre.deak@intel.com<mailto:imre.deak@intel.com>>; Shankar, Uma <uma.shankar@intel.com<mailto:uma.shankar@intel.com>>; Taylor, Clinton A <clinton.a.taylor@intel.com<mailto:clinton.a.taylor@intel.com>>
Subject: [PATCH 06/20] drm/i915/mtl: Add vswing programming for C10 phys
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com<mailto:radhakrishna.sripada@intel.com>>
C10 phys uses direct mapping internally for voltage and pre-emphasis levels.
Program the levels directly to the fields in the VDR Registers.
Bspec: 65449
Cc: Imre Deak <imre.deak@intel.com<mailto:imre.deak@intel.com>>
Cc: Uma Shankar <uma.shankar@intel.com<mailto:uma.shankar@intel.com>>
Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com<mailto:Clinton.A.Taylor@intel.com>>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com<mailto:radhakrishna.sripada@intel.com>>
Signed-off-by: Mika Kahola <mika.kahola@intel.com<mailto:mika.kahola@intel.com>>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 143 ++++++++++++++++--
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
.../gpu/drm/i915/display/intel_cx0_reg_defs.h | 6 +
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
.../drm/i915/display/intel_ddi_buf_trans.c | 36 ++++-
.../drm/i915/display/intel_ddi_buf_trans.h | 6 +
.../i915/display/intel_display_power_map.c | 1 +
7 files changed, 185 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index dc033174c9c0..ef874986940d 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -6,10 +6,14 @@
#include "i915_reg_defs.h"
#include "intel_cx0_phy.h"
#include "intel_cx0_reg_defs.h"
+#include "intel_ddi.h"
+#include "intel_ddi_buf_trans.h"
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_panel.h"
+#include "intel_psr.h"
+#include "intel_uncore.h"
bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy)
{
@@ -19,6 +23,15 @@ bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy)
return false;
}
+static void
+assert_dc_off(struct drm_i915_private *i915)
+{
+ bool enabled;
+
+ enabled = intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF);
+ drm_WARN_ON(&i915->drm, !enabled);
+}
+
static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, int lane)
{
enum phy phy = intel_port_to_phy(i915, port);
@@ -108,6 +121,8 @@ static u8 intel_cx0_read(struct drm_i915_private *i915, enum port port,
int i, status;
u32 val;
+ assert_dc_off(i915);
+
for (i = 0; i < 3; i++) {
status = __intel_cx0_read(i915, port, lane, addr, &val);
@@ -191,6 +206,8 @@ static void __intel_cx0_write(struct drm_i915_private *i915, enum port port,
enum phy phy = intel_port_to_phy(i915, port);
int i, status;
+ assert_dc_off(i915);
+
for (i = 0; i < 3; i++) {
status = __intel_cx0_write_once(i915, port, lane, addr, data, committed);
@@ -240,6 +257,84 @@ static void intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
}
}
+/*
+ * Prepare HW for CX0 phy transactions.
+ *
+ * It is required that PSR and DC5/6 are disabled before any CX0 message
+ * bus transaction is executed.
+ */
+static intel_wakeref_t intel_cx0_phy_transaction_begin(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ intel_psr_pause(intel_dp);
+ return intel_display_power_get(i915, POWER_DOMAIN_DC_OFF);
+}
+
+static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_wakeref_t wakeref)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ intel_psr_resume(intel_dp);
+ intel_display_power_put(i915, POWER_DOMAIN_DC_OFF, wakeref);
+}
+
+void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+ bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
+ u8 master_lane = lane_reversal ? INTEL_CX0_LANE1 :
+ INTEL_CX0_LANE0;
+ const struct intel_ddi_buf_trans *trans;
+ intel_wakeref_t wakeref;
+ int n_entries, ln;
+
+ wakeref = intel_cx0_phy_transaction_begin(encoder);
+
+ trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
+ if (drm_WARN_ON_ONCE(&i915->drm, !trans))
+ return;
+
+ intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
+ 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
+
+ for (ln = 0; ln < 4; ln++) {
+ int level = intel_ddi_level(encoder, crtc_state, ln);
+ int lane, tx;
+
+ lane = ln / 2;
+ tx = ln % 2 + 1;
+
+ intel_cx0_rmw(i915, encoder->port, lane, PHY_CX0_TX_CONTROL(tx, 2),
+ C10_PHY_VSWING_PREEMPH_MASK,
+ C10_PHY_VSWING_PREEMPH(trans->entries[level].direct.preemph),
+ MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, encoder->port, lane, PHY_CX0_TX_CONTROL(tx, 8),
+ C10_PHY_VSWING_LEVEL_MASK,
+ C10_PHY_VSWING_LEVEL(trans->entries[level].direct.level),
+ MB_WRITE_COMMITTED);
+ }
+
+ intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG,
+ MB_WRITE_COMMITTED);
+#if 0
+ /*
+ * FIXME: Revisit this code to see why we can't update
+ * config on Lane 1
+ */
+ intel_cx0_rmw(i915, encoder->port, !master_lane, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_UPDATE_CFG, C10_VDR_CTRL_UPDATE_CFG,
+ MB_WRITE_COMMITTED);
+#endif
+
+ intel_cx0_phy_transaction_end(encoder, wakeref);
+}
+
/*
* Basic DP link rates with 38.4 MHz reference clock.
* Note: The tables below are with SSC. In non-ssc
@@ -698,9 +793,12 @@ void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
u8 lane = lane_reversal ? INTEL_CX0_LANE1 :
INTEL_CX0_LANE0;
enum phy phy = intel_port_to_phy(i915, encoder->port);
+ intel_wakeref_t wakeref;
int i;
u8 cmn, tx0;
+ wakeref = intel_cx0_phy_transaction_begin(encoder);
+
/*
* According to C10 VDR Register programming Sequence we need
* to do this to read PHY internal registers from MsgBus.
@@ -719,6 +817,8 @@ void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
C10_CMN0_DP_VAL : C10_CMN0_HDMI_VAL))
drm_warn(&i915->drm, "Unexpected tx: %x or cmn: %x for phy: %c.\n",
tx0, cmn, phy_name(phy));
+
+ intel_cx0_phy_transaction_end(encoder, wakeref);
}
static void intel_c10_pll_program(struct drm_i915_private *i915,
@@ -849,17 +949,20 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
if (intel_crtc_has_dp_encoder(crtc_state)) {
intel_dp = enc_to_intel_dp(encoder);
- ssc_enabled = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
- DP_MAX_DOWNSPREAD_0_5;
+ ssc_enabled = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
+ DP_MAX_DOWNSPREAD_0_5);
+
+ if (intel_dp_is_edp(intel_dp) && !intel_panel_use_ssc(i915))
+ ssc_enabled = false;
/* TODO: DP2.0 10G and 20G rates enable MPLLA*/
val |= ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
}
+
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
- XELPDP_LANE1_PHY_CLOCK_SELECT |
- XELPDP_FORWARD_CLOCK_UNGATE |
+ XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
XELPDP_DDI_CLOCK_SELECT_MASK |
- XELPDP_SSC_ENABLE_PLLB, val);
+ XELPDP_SSC_ENABLE_PLLA | XELPDP_SSC_ENABLE_PLLB, val);
}
static u32 intel_cx0_get_powerdown_update(u8 lane)
@@ -986,9 +1089,12 @@ static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
{
u8 l0t1, l0t2, l1t1, l1t2;
- intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
- C10_VDR_CTRL_MSGBUS_ACCESS, C10_VDR_CTRL_MSGBUS_ACCESS,
- MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, port, 1, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_UPDATE_CFG,
+ C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, port, 0, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_UPDATE_CFG,
+ C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
l0t1 = intel_cx0_read(i915, port, 0, PHY_CX0_TX_CONTROL(1, 2));
l0t2 = intel_cx0_read(i915, port, 0, PHY_CX0_TX_CONTROL(2, 2));
@@ -1039,8 +1145,12 @@ static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
}
}
- intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
- C10_VDR_CTRL_UPDATE_CFG, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, port, 1, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_UPDATE_CFG | C10_VDR_CTRL_MSGBUS_ACCESS,
+ C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, port, 0, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_UPDATE_CFG | C10_VDR_CTRL_MSGBUS_ACCESS,
+ C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
}
static u32 intel_cx0_get_pclk_pll_request(u8 lane)
@@ -1138,9 +1248,14 @@ void intel_cx0pll_enable(struct intel_encoder *encoder,
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
+ intel_wakeref_t wakeref;
+
+ wakeref = intel_cx0_phy_transaction_begin(encoder);
drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
intel_c10pll_enable(encoder, crtc_state);
+
+ intel_cx0_phy_transaction_end(encoder, wakeref);
}
static void intel_c10pll_disable(struct intel_encoder *encoder)
@@ -1185,7 +1300,8 @@ static void intel_c10pll_disable(struct intel_encoder *encoder)
/* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
- XELPDP_DDI_CLOCK_SELECT_MASK |
+ XELPDP_DDI_CLOCK_SELECT_MASK, 0);
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
XELPDP_FORWARD_CLOCK_UNGATE, 0);
}
@@ -1193,9 +1309,14 @@ void intel_cx0pll_disable(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
+ intel_wakeref_t wakeref;
+
+ wakeref = intel_cx0_phy_transaction_begin(encoder);
drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
intel_c10pll_disable(encoder);
+
+ intel_cx0_phy_transaction_end(encoder, wakeref);
}
void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index f8023f240727..952c7deeffaa 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -40,5 +40,7 @@ int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
struct intel_crtc_state *new_crtc_state);
int intel_c10_phy_check_hdmi_link_rate(int clock);
+void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_CX0_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
index b394f5c23acb..fad6308bbf77 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
@@ -164,4 +164,10 @@
#define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 + (control))
#define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6)
+/* C10 Phy VSWING Masks */
+#define C10_PHY_VSWING_LEVEL_MASK REG_GENMASK8(2, 0)
+#define C10_PHY_VSWING_LEVEL(val) REG_FIELD_PREP8(C10_PHY_VSWING_LEVEL_MASK, val)
+#define C10_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(1, 0)
+#define C10_PHY_VSWING_PREEMPH(val) REG_FIELD_PREP8(C10_PHY_VSWING_PREEMPH_MASK, val)
+
#endif /* __INTEL_CX0_REG_DEFS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 639ec604babf..1380ed2221ad 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4445,7 +4445,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->get_config = hsw_ddi_get_config;
}
- if (IS_DG2(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ encoder->set_signal_levels = intel_cx0_phy_set_signal_levels;
+ } else if (IS_DG2(dev_priv)) {
encoder->set_signal_levels = intel_snps_phy_set_signal_levels;
} else if (DISPLAY_VER(dev_priv) >= 12) {
if (intel_phy_is_combo(dev_priv, phy))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 006a2e979000..49f8a0a6593b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1035,6 +1035,30 @@ static const struct intel_ddi_buf_trans dg2_snps_trans_uhbr = {
.num_entries = ARRAY_SIZE(_dg2_snps_trans_uhbr),
};
+/*
+ * Some platforms don't need a mapping table and only expect us to
+ * to program the vswing + preemphasis levels directly since the
+ * hardware will do its own mapping to tuning values internally.
+ */
+static const union intel_ddi_buf_trans_entry direct_map_trans[] = {
+ { .direct = { .level = 0, .preemph = 0 } },
+ { .direct = { .level = 0, .preemph = 1 } },
+ { .direct = { .level = 0, .preemph = 2 } },
+ { .direct = { .level = 0, .preemph = 3 } },
+ { .direct = { .level = 1, .preemph = 0 } },
+ { .direct = { .level = 1, .preemph = 0 } },
+ { .direct = { .level = 1, .preemph = 2 } },
+ { .direct = { .level = 2, .preemph = 0 } },
+ { .direct = { .level = 2, .preemph = 1 } },
+ { .direct = { .level = 3, .preemph = 0 } },
+};
+
+static const struct intel_ddi_buf_trans mtl_cx0c10_trans = {
+ .entries = direct_map_trans,
+ .num_entries = ARRAY_SIZE(direct_map_trans),
+ .hdmi_default_entry = ARRAY_SIZE(direct_map_trans) - 1,
+};
+
bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
{
return table == &tgl_combo_phy_trans_edp_hbr2_hobl;
@@ -1606,12 +1630,22 @@ dg2_get_snps_buf_trans(struct intel_encoder *encoder,
return intel_get_buf_trans(&dg2_snps_trans, n_entries);
}
+static const struct intel_ddi_buf_trans *
+mtl_get_cx0_buf_trans(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int *n_entries)
+{
+ return intel_get_buf_trans(&mtl_cx0c10_trans, n_entries);
+}
+
void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
- if (IS_DG2(i915)) {
+ if (DISPLAY_VER(i915) >= 14) {
+ encoder->get_buf_trans = mtl_get_cx0_buf_trans;
+ } else if (IS_DG2(i915)) {
encoder->get_buf_trans = dg2_get_snps_buf_trans;
} else if (IS_ALDERLAKE_P(i915)) {
if (intel_phy_is_combo(i915, phy))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
index 2133984a572b..e4a857b9829d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
@@ -51,6 +51,11 @@ struct dg2_snps_phy_buf_trans {
u8 post_cursor;
};
+struct direct_phy_buf_trans {
+ u8 level;
+ u8 preemph;
+};
+
union intel_ddi_buf_trans_entry {
struct hsw_ddi_buf_trans hsw;
struct bxt_ddi_buf_trans bxt;
@@ -58,6 +63,7 @@ union intel_ddi_buf_trans_entry {
struct icl_mg_phy_ddi_buf_trans mg;
struct tgl_dkl_phy_ddi_buf_trans dkl;
struct dg2_snps_phy_buf_trans snps;
+ struct direct_phy_buf_trans direct;
};
struct intel_ddi_buf_trans {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index dc04afc6cc8f..45c3ab4e2f28 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1374,6 +1374,7 @@ I915_DECL_PW_DOMAINS(xelpdp_pwdoms_dc_off,
XELPDP_PW_2_POWER_DOMAINS,
POWER_DOMAIN_AUDIO_MMIO,
POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_DC_OFF,
POWER_DOMAIN_AUX_A,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_INIT);
--
2.34.1
[-- Attachment #2: Type: text/html, Size: 42390 bytes --]
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH 07/20] drm/i915/mtl: Add support for PM DEMAND
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (5 preceding siblings ...)
2022-10-14 12:47 ` [Intel-gfx] [PATCH 06/20] drm/i915/mtl: Add vswing programming for C10 phys Mika Kahola
@ 2022-10-14 12:47 ` Mika Kahola
2022-11-01 2:38 ` Sripada, Radhakrishna
2022-10-14 12:47 ` [Intel-gfx] [PATCH 08/20] drm/i915/mtl: C20 PLL programming Mika Kahola
` (18 subsequent siblings)
25 siblings, 1 reply; 36+ messages in thread
From: Mika Kahola @ 2022-10-14 12:47 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
Display14 introduces a new way to instruct the PUnit with
power and bandwidth requirements of DE. Add the functionality
to program the registers and handle waits using interrupts.
The current wait time for timeouts is programmed for 10 msecs to
factor in the worst case scenarios. Changes made to use REG_BIT
for a register that we touched(GEN8_DE_MISC_IER _MMIO).
Bspec: 66451, 64636, 64602, 64603
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 4 +-
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 14 +
.../drm/i915/display/intel_display_power.c | 8 +
drivers/gpu/drm/i915/i915_drv.h | 12 +
drivers/gpu/drm/i915/i915_irq.c | 22 +-
drivers/gpu/drm/i915/i915_reg.h | 33 +-
drivers/gpu/drm/i915/intel_pm.c | 286 ++++++++++++++++++
drivers/gpu/drm/i915/intel_pm.h | 35 +++
9 files changed, 411 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 4ace026b29bd..6c467b6f2234 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -716,8 +716,8 @@ static unsigned int intel_bw_num_active_planes(struct drm_i915_private *dev_priv
return num_active_planes;
}
-static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
- const struct intel_bw_state *bw_state)
+unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
+ const struct intel_bw_state *bw_state)
{
unsigned int data_rate = 0;
enum pipe pipe;
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index cb7ee3a24a58..b3eb82a71e6c 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -62,6 +62,8 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_atomic_check(struct intel_atomic_state *state);
void intel_bw_crtc_update(struct intel_bw_state *bw_state,
const struct intel_crtc_state *crtc_state);
+unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
+ const struct intel_bw_state *bw_state);
int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
u32 points_mask);
int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0a8749753e6e..5ce33319b70d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1079,6 +1079,9 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
num_encoders++;
}
+ if (!encoder)
+ return NULL;
+
drm_WARN(encoder->base.dev, num_encoders != 1,
"%d encoders for pipe %c\n",
num_encoders, pipe_name(master_crtc->pipe));
@@ -6898,6 +6901,10 @@ static int intel_atomic_check(struct drm_device *dev,
ret = intel_modeset_calc_cdclk(state);
if (ret)
return ret;
+
+ ret = intel_pmdemand_atomic_check(state);
+ if (ret)
+ goto fail;
}
ret = intel_atomic_check_crtcs(state);
@@ -7521,6 +7528,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
}
intel_sagv_pre_plane_update(state);
+ intel_pmdemand_pre_plane_update(state);
/* Complete the events for pipes that have now been disabled */
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
@@ -7622,6 +7630,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_verify_planes(state);
intel_sagv_post_plane_update(state);
+ intel_pmdemand_post_plane_update(state);
drm_atomic_helper_commit_hw_done(&state->base);
@@ -8353,6 +8362,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
intel_color_init_hooks(dev_priv);
intel_init_cdclk_hooks(dev_priv);
intel_audio_hooks_init(dev_priv);
+ intel_init_pmdemand(dev_priv);
intel_dpll_init_clock_hook(dev_priv);
@@ -8689,6 +8699,10 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
if (ret)
goto cleanup_vga_client_pw_domain_dmc;
+ ret = intel_pmdemand_init(i915);
+ if (ret)
+ goto cleanup_vga_client_pw_domain_dmc;
+
init_llist_head(&i915->display.atomic_helper.free_list);
INIT_WORK(&i915->display.atomic_helper.free_work,
intel_atomic_helper_free_state_worker);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 4f6d1463cc99..0a356409277e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -19,6 +19,7 @@
#include "intel_mchbar_regs.h"
#include "intel_pch_refclk.h"
#include "intel_pcode.h"
+#include "intel_pm.h"
#include "intel_snps_phy.h"
#include "skl_watermark.h"
#include "vlv_sideband.h"
@@ -1071,6 +1072,10 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
dev_priv->display.dbuf.enabled_slices =
intel_enabled_dbuf_slices_mask(dev_priv);
+ if (DISPLAY_VER(dev_priv) >= 14)
+ intel_program_dbuf_pmdemand(dev_priv, BIT(DBUF_S1) |
+ dev_priv->dbuf.enabled_slices);
+
/*
* Just power up at least 1 slice, we will
* figure out later which slices we have and what we need.
@@ -1082,6 +1087,9 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
{
gen9_dbuf_slices_update(dev_priv, 0);
+
+ if (DISPLAY_VER(dev_priv) >= 14)
+ intel_program_dbuf_pmdemand(dev_priv, 0);
}
static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 90ed8e6db2fe..8d1097ffc2e7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -269,6 +269,18 @@ struct drm_i915_private {
unsigned int hpll_freq;
unsigned int czclk_freq;
+ struct {
+ /* The current hardware dbuf configuration */
+ u8 enabled_slices;
+
+ struct intel_global_obj obj;
+ } dbuf;
+
+ struct {
+ wait_queue_head_t waitqueue;
+ struct mutex lock;
+ struct intel_global_obj obj;
+ } pmdemand;
/**
* wq - Driver workqueue for GEM.
*
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2b75ca5e6e61..1ae7ac004a53 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2317,6 +2317,11 @@ static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
}
+static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv)
+{
+ wake_up_all(&dev_priv->pmdemand.waitqueue);
+}
+
static void
gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
{
@@ -2353,6 +2358,18 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
}
}
+ if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR) {
+ drm_dbg(&dev_priv->drm,
+ "Error waiting for Punit PM Demand Response\n");
+ intel_pmdemand_irq_handler(dev_priv);
+ found = true;
+ }
+
+ if (iir & XELPDP_PMDEMAND_RSP) {
+ intel_pmdemand_irq_handler(dev_priv);
+ found = true;
+ }
+
if (!found)
drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n");
}
@@ -3724,7 +3741,10 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
de_port_masked |= BXT_DE_PORT_GMBUS;
- if (DISPLAY_VER(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 14)
+ de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR |
+ XELPDP_PMDEMAND_RSP;
+ else if (DISPLAY_VER(dev_priv) >= 11) {
enum port port;
if (intel_bios_is_dsi_present(dev_priv, &port))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 41f9bc4c8266..abf12d459bc2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5601,8 +5601,10 @@
#define GEN8_DE_MISC_IMR _MMIO(0x44464)
#define GEN8_DE_MISC_IIR _MMIO(0x44468)
#define GEN8_DE_MISC_IER _MMIO(0x4446c)
-#define GEN8_DE_MISC_GSE (1 << 27)
-#define GEN8_DE_EDP_PSR (1 << 19)
+#define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27)
+#define GEN8_DE_MISC_GSE REG_BIT(27)
+#define GEN8_DE_EDP_PSR REG_BIT(19)
+#define XELPDP_PMDEMAND_RSP REG_BIT(3)
#define GEN8_PCU_ISR _MMIO(0x444e0)
#define GEN8_PCU_IMR _MMIO(0x444e4)
@@ -5665,6 +5667,33 @@
#define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
#define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword))
+#define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16)
+#define XELPDP_PMDEMAND_QCLK_GV_BW(x) REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, x)
+#define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12)
+#define XELPDP_PMDEMAND_VOLTAGE_INDEX(x) REG_FIELD_PREP(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, x)
+#define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8)
+#define XELPDP_PMDEMAND_QCLK_GV_INDEX(x) REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, x)
+#define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6)
+#define XELPDP_PMDEMAND_PIPES(x) REG_FIELD_PREP(XELPDP_PMDEMAND_PIPES_MASK, x)
+#define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4)
+#define XELPDP_PMDEMAND_DBUFS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_DBUFS_MASK, x)
+#define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0)
+#define XELPDP_PMDEMAND_PHYS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_PHYS_MASK, x)
+
+#define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31)
+#define XELPDP_PMDEMAND_CDCLK_FREQ_MASK REG_GENMASK(30, 20)
+#define XELPDP_PMDEMAND_CDCLK_FREQ(x) REG_FIELD_PREP(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, x)
+#define XELPDP_PMDEMAND_DDICLK_FREQ_MASK REG_GENMASK(18, 8)
+#define XELPDP_PMDEMAND_DDICLK_FREQ(x) REG_FIELD_PREP(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, x)
+#define XELPDP_PMDEMAND_SCALERS_MASK REG_GENMASK(6, 4)
+#define XELPDP_PMDEMAND_SCALERS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_SCALERS_MASK, x)
+#define XELPDP_PMDEMAND_PLLS_MASK REG_GENMASK(2, 0)
+#define XELPDP_PMDEMAND_PLLS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_PLLS_MASK, x)
+
+#define GEN12_DCPR_STATUS_1 _MMIO(0x46440)
+#define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26)
+
#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
/* Required on all Ironlake and Sandybridge according to the B-Spec. */
#define ILK_ELPIN_409_SELECT (1 << 25)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9f6c58ad8bdb..8b5aed52e8bc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -25,6 +25,11 @@
*
*/
+#include <linux/bitops.h>
+
+#include "display/intel_bw.h"
+#include "display/intel_cdclk.h"
+#include "display/intel_cx0_phy.h"
#include "display/intel_de.h"
#include "display/intel_display_trace.h"
#include "display/skl_watermark.h"
@@ -4094,6 +4099,287 @@ void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
!(intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) & DISP_FBC_WM_DIS);
}
+static struct intel_global_state *intel_pmdemand_duplicate_state(struct intel_global_obj *obj)
+{
+ struct intel_pmdemand_state *pmdmnd_state;
+
+ pmdmnd_state = kmemdup(obj->state, sizeof(*pmdmnd_state), GFP_KERNEL);
+ if (!pmdmnd_state)
+ return NULL;
+
+ return &pmdmnd_state->base;
+}
+
+static void intel_pmdemand_destroy_state(struct intel_global_obj *obj,
+ struct intel_global_state *state)
+{
+ kfree(state);
+}
+
+static const struct intel_global_state_funcs intel_pmdemand_funcs = {
+ .atomic_duplicate_state = intel_pmdemand_duplicate_state,
+ .atomic_destroy_state = intel_pmdemand_destroy_state,
+};
+
+struct intel_pmdemand_state *
+intel_atomic_get_pmdemand_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_global_state *pmdemand_state;
+
+ pmdemand_state = intel_atomic_get_global_obj_state(state, &dev_priv->pmdemand.obj);
+ if (IS_ERR(pmdemand_state))
+ return ERR_CAST(pmdemand_state);
+
+ return to_intel_pmdemand_state(pmdemand_state);
+}
+
+int intel_pmdemand_init(struct drm_i915_private *dev_priv)
+{
+ struct intel_pmdemand_state *pmdemand_state;
+
+ pmdemand_state = kzalloc(sizeof(*pmdemand_state), GFP_KERNEL);
+ if (!pmdemand_state)
+ return -ENOMEM;
+
+ intel_atomic_global_obj_init(dev_priv, &dev_priv->pmdemand.obj,
+ &pmdemand_state->base, &intel_pmdemand_funcs);
+
+ return 0;
+}
+
+void intel_init_pmdemand(struct drm_i915_private *dev_priv)
+{
+ mutex_init(&dev_priv->pmdemand.lock);
+ init_waitqueue_head(&dev_priv->pmdemand.waitqueue);
+}
+
+int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_pmdemand_state *new_pmdemand_state = NULL;
+ struct intel_crtc_state *old_crtc_state, *new_crtc_state;
+ struct intel_crtc *crtc;
+ struct intel_encoder *encoder;
+ struct intel_bw_state *new_bw_state;
+ const struct intel_dbuf_state *new_dbuf_state;
+ const struct intel_cdclk_state *new_cdclk_state;
+ int port_clock = 0;
+ unsigned int data_rate;
+ enum phy phy;
+ int i, ret;
+
+ if (DISPLAY_VER(dev_priv) < 14)
+ return 0;
+
+ new_pmdemand_state = intel_atomic_get_pmdemand_state(state);
+ if (IS_ERR(new_pmdemand_state))
+ return PTR_ERR(new_pmdemand_state);
+
+ ret = intel_atomic_lock_global_state(&new_pmdemand_state->base);
+ if (ret)
+ return ret;
+
+ /* Punit figures out the voltage index based on bandwidth*/
+ new_bw_state = intel_atomic_get_bw_state(state);
+ if (IS_ERR(new_bw_state))
+ return PTR_ERR(new_bw_state);
+
+ /* firmware will calculate the qclck_gc_index, requirement is set to 0 */
+ new_pmdemand_state->qclk_gv_index = 0;
+
+ data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
+ /* To MBs then to multiples of 100MBs */
+ data_rate = DIV_ROUND_UP(data_rate, 1000);
+ data_rate = DIV_ROUND_UP(data_rate, 100);
+ new_pmdemand_state->qclk_gv_bw = data_rate;
+
+ new_dbuf_state = intel_atomic_get_dbuf_state(state);
+ if (IS_ERR(new_dbuf_state))
+ return PTR_ERR(new_dbuf_state);
+
+ i = hweight8(new_dbuf_state->active_pipes);
+ new_pmdemand_state->active_pipes = min(i, 3);
+
+ new_cdclk_state = intel_atomic_get_cdclk_state(state);
+ if (IS_ERR(new_cdclk_state))
+ return PTR_ERR(new_cdclk_state);
+
+ new_pmdemand_state->voltage_index = new_cdclk_state->logical.voltage_level;
+ /* KHz to MHz */
+ new_pmdemand_state->cdclk_freq_mhz = DIV_ROUND_UP(new_cdclk_state->logical.cdclk, 1000);
+
+ new_pmdemand_state->active_phys_plls_mask = 0;
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+ if (!new_crtc_state->hw.active)
+ continue;
+
+ encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
+ if (!encoder)
+ continue;
+
+ phy = intel_port_to_phy(dev_priv, encoder->port);
+
+ if (intel_is_c10phy(dev_priv, phy))
+ new_pmdemand_state->active_phys_plls_mask |= BIT(phy);
+
+ port_clock = max(port_clock, new_crtc_state->port_clock);
+ }
+
+ /* To MHz */
+ new_pmdemand_state->ddiclk_freq_mhz = DIV_ROUND_UP(port_clock, 1000);
+
+ /*
+ * Setting scalers to max as it can not be calculated during flips and
+ * fastsets without taking global states locks.
+ */
+ new_pmdemand_state->scalers = 7;
+
+ return 0;
+}
+
+static bool intel_pmdemand_check_prev_transaction(struct drm_i915_private *dev_priv)
+{
+ return !((intel_de_read(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) & XELPDP_PMDEMAND_REQ_ENABLE) ||
+ (intel_de_read(dev_priv, GEN12_DCPR_STATUS_1) & XELPDP_PMDEMAND_INFLIGHT_STATUS));
+}
+
+static bool intel_pmdemand_req_complete(struct drm_i915_private *dev_priv)
+{
+ return !(intel_de_read(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) & XELPDP_PMDEMAND_REQ_ENABLE);
+}
+
+static int intel_pmdemand_wait(struct drm_i915_private *dev_priv)
+{
+ DEFINE_WAIT(wait);
+ int ret;
+ const unsigned int timeout_ms = 10;
+
+ add_wait_queue(&dev_priv->pmdemand.waitqueue, &wait);
+
+ ret = wait_event_timeout(dev_priv->pmdemand.waitqueue,
+ intel_pmdemand_req_complete(dev_priv),
+ msecs_to_jiffies_timeout(timeout_ms));
+ if (ret < 0)
+ drm_err(&dev_priv->drm,
+ "timed out waiting for Punit PM Demand Response\n");
+
+ remove_wait_queue(&dev_priv->pmdemand.waitqueue, &wait);
+
+ return ret;
+}
+
+/* Required to be programmed during Display Init Sequences. */
+void intel_program_dbuf_pmdemand(struct drm_i915_private *dev_priv,
+ u8 dbuf_slices)
+{
+ mutex_lock(&dev_priv->pmdemand.lock);
+ if (drm_WARN_ON(&dev_priv->drm,
+ !intel_pmdemand_check_prev_transaction(dev_priv)))
+ goto unlock;
+
+ intel_de_rmw(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
+ XELPDP_PMDEMAND_DBUFS_MASK,
+ XELPDP_PMDEMAND_DBUFS(hweight32(dbuf_slices)));
+ intel_de_rmw(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
+ XELPDP_PMDEMAND_REQ_ENABLE);
+
+ intel_pmdemand_wait(dev_priv);
+unlock:
+ mutex_unlock(&dev_priv->pmdemand.lock);
+}
+
+static void intel_program_pmdemand(struct drm_i915_private *dev_priv,
+ const struct intel_pmdemand_state *new,
+ const struct intel_pmdemand_state *old)
+{
+ u32 val, tmp;
+
+#define UPDATE_PMDEMAND_VAL(val, F, f) do { \
+ val &= (~(XELPDP_PMDEMAND_##F##_MASK)); \
+ val |= (XELPDP_PMDEMAND_##F((u32)(old ? max(old->f, new->f) : new->f))); \
+} while (0)
+
+ mutex_lock(&dev_priv->pmdemand.lock);
+ if (drm_WARN_ON(&dev_priv->drm,
+ !intel_pmdemand_check_prev_transaction(dev_priv)))
+ goto unlock;
+
+ /*
+ * TODO: Update programming PM Demand for
+ * PHYS, PLLS, DDI_CLKFREQ, SCALARS
+ */
+ val = intel_de_read(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
+ UPDATE_PMDEMAND_VAL(val, QCLK_GV_INDEX, qclk_gv_index);
+ UPDATE_PMDEMAND_VAL(val, QCLK_GV_BW, qclk_gv_bw);
+ UPDATE_PMDEMAND_VAL(val, VOLTAGE_INDEX, voltage_index);
+ UPDATE_PMDEMAND_VAL(val, PIPES, active_pipes);
+ UPDATE_PMDEMAND_VAL(val, DBUFS, dbufs);
+ tmp = hweight32(new->active_phys_plls_mask);
+ if (old)
+ tmp = max(tmp, hweight32(old->active_phys_plls_mask));
+ val |= XELPDP_PMDEMAND_PHYS(tmp);
+
+ intel_de_write(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(0), val);
+
+ val = intel_de_read(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
+ UPDATE_PMDEMAND_VAL(val, CDCLK_FREQ, cdclk_freq_mhz);
+ UPDATE_PMDEMAND_VAL(val, DDICLK_FREQ, ddiclk_freq_mhz);
+ UPDATE_PMDEMAND_VAL(val, SCALERS, scalers);
+ /*
+ * Active_PLLs starts with 1 because of CDCLK PLL.
+ * TODO: Missing to account genlock filter when it gets used.
+ */
+ val |= XELPDP_PMDEMAND_PLLS(tmp + 1);
+
+ intel_de_write(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(1), val);
+
+#undef UPDATE_PM_DEMAND_VAL
+
+ intel_de_rmw(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0, XELPDP_PMDEMAND_REQ_ENABLE);
+
+ intel_pmdemand_wait(dev_priv);
+unlock:
+ mutex_unlock(&dev_priv->pmdemand.lock);
+}
+
+void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_pmdemand_state *new_pmdmnd_state =
+ intel_atomic_get_new_pmdemand_state(state);
+ const struct intel_pmdemand_state *old_pmdmnd_state =
+ intel_atomic_get_old_pmdemand_state(state);
+
+ if (DISPLAY_VER(dev_priv) < 14)
+ return;
+
+ if (!new_pmdmnd_state ||
+ memcmp(new_pmdmnd_state, old_pmdmnd_state, sizeof(*new_pmdmnd_state)) == 0)
+ return;
+
+ intel_program_pmdemand(dev_priv, new_pmdmnd_state, old_pmdmnd_state);
+}
+
+void intel_pmdemand_post_plane_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_pmdemand_state *new_pmdmnd_state =
+ intel_atomic_get_new_pmdemand_state(state);
+ const struct intel_pmdemand_state *old_pmdmnd_state =
+ intel_atomic_get_old_pmdemand_state(state);
+
+ if (DISPLAY_VER(dev_priv) < 14)
+ return;
+
+ if (!new_pmdmnd_state ||
+ memcmp(new_pmdmnd_state, old_pmdmnd_state, sizeof(*new_pmdmnd_state)) == 0)
+ return;
+
+ intel_program_pmdemand(dev_priv, new_pmdmnd_state, NULL);
+}
+
static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
{
/*
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index c09b872d65c8..88e8fef6c10b 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -8,6 +8,8 @@
#include <linux/types.h>
+#include "display/intel_global_state.h"
+
struct drm_i915_private;
struct intel_crtc_state;
struct intel_plane_state;
@@ -15,6 +17,7 @@ struct intel_plane_state;
void intel_init_clock_gating(struct drm_i915_private *dev_priv);
void intel_suspend_hw(struct drm_i915_private *dev_priv);
int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
+void intel_init_pmdemand(struct drm_i915_private *dev_priv);
void intel_init_pm(struct drm_i915_private *dev_priv);
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
void intel_pm_setup(struct drm_i915_private *dev_priv);
@@ -31,4 +34,36 @@ void intel_print_wm_latency(struct drm_i915_private *dev_priv,
bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable);
+struct intel_pmdemand_state {
+ struct intel_global_state base;
+
+ u16 qclk_gv_bw;
+ u8 voltage_index;
+ u8 qclk_gv_index;
+ u8 active_pipes;
+ u8 dbufs;
+ u8 active_phys_plls_mask;
+ u16 cdclk_freq_mhz;
+ u16 ddiclk_freq_mhz;
+ u8 scalers;
+};
+
+int intel_pmdemand_init(struct drm_i915_private *dev_priv);
+
+struct intel_pmdemand_state *
+intel_atomic_get_pmdemand_state(struct intel_atomic_state *state);
+
+#define to_intel_pmdemand_state(x) container_of((x), struct intel_pmdemand_state, base)
+#define intel_atomic_get_old_pmdemand_state(state) \
+ to_intel_pmdemand_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->pmdemand.obj))
+#define intel_atomic_get_new_pmdemand_state(state) \
+ to_intel_pmdemand_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->pmdemand.obj))
+
+int intel_pmdemand_init(struct drm_i915_private *dev_priv);
+void intel_program_dbuf_pmdemand(struct drm_i915_private *dev_priv,
+ u8 dbuf_slices);
+void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state);
+void intel_pmdemand_post_plane_update(struct intel_atomic_state *state);
+int intel_pmdemand_atomic_check(struct intel_atomic_state *state);
+
#endif /* __INTEL_PM_H__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [Intel-gfx] [PATCH 07/20] drm/i915/mtl: Add support for PM DEMAND
2022-10-14 12:47 ` [Intel-gfx] [PATCH 07/20] drm/i915/mtl: Add support for PM DEMAND Mika Kahola
@ 2022-11-01 2:38 ` Sripada, Radhakrishna
2022-11-15 12:56 ` Kahola, Mika
0 siblings, 1 reply; 36+ messages in thread
From: Sripada, Radhakrishna @ 2022-11-01 2:38 UTC (permalink / raw)
To: Kahola, Mika, intel-gfx@lists.freedesktop.org; +Cc: De Marchi, Lucas
> -----Original Message-----
> From: Kahola, Mika <mika.kahola@intel.com>
> Sent: Friday, October 14, 2022 5:47 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>; Atwood, Matthew S
> <matthew.s.atwood@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>;
> Souza, Jose <jose.souza@intel.com>; Sripada, Radhakrishna
> <radhakrishna.sripada@intel.com>
> Subject: [PATCH 07/20] drm/i915/mtl: Add support for PM DEMAND
>
> Display14 introduces a new way to instruct the PUnit with
> power and bandwidth requirements of DE. Add the functionality
> to program the registers and handle waits using interrupts.
> The current wait time for timeouts is programmed for 10 msecs to
> factor in the worst case scenarios. Changes made to use REG_BIT
> for a register that we touched(GEN8_DE_MISC_IER _MMIO).
>
> Bspec: 66451, 64636, 64602, 64603
>
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 4 +-
> drivers/gpu/drm/i915/display/intel_bw.h | 2 +
> drivers/gpu/drm/i915/display/intel_display.c | 14 +
> .../drm/i915/display/intel_display_power.c | 8 +
> drivers/gpu/drm/i915/i915_drv.h | 12 +
> drivers/gpu/drm/i915/i915_irq.c | 22 +-
> drivers/gpu/drm/i915/i915_reg.h | 33 +-
> drivers/gpu/drm/i915/intel_pm.c | 286 ++++++++++++++++++
> drivers/gpu/drm/i915/intel_pm.h | 35 +++
> 9 files changed, 411 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 4ace026b29bd..6c467b6f2234 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -716,8 +716,8 @@ static unsigned int intel_bw_num_active_planes(struct
> drm_i915_private *dev_priv
> return num_active_planes;
> }
>
> -static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> - const struct intel_bw_state *bw_state)
> +unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> + const struct intel_bw_state *bw_state)
> {
> unsigned int data_rate = 0;
> enum pipe pipe;
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
> b/drivers/gpu/drm/i915/display/intel_bw.h
> index cb7ee3a24a58..b3eb82a71e6c 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -62,6 +62,8 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
> int intel_bw_atomic_check(struct intel_atomic_state *state);
> void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> const struct intel_crtc_state *crtc_state);
> +unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> + const struct intel_bw_state *bw_state);
> int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> u32 points_mask);
> int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 0a8749753e6e..5ce33319b70d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1079,6 +1079,9 @@ intel_get_crtc_new_encoder(const struct
> intel_atomic_state *state,
> num_encoders++;
> }
>
> + if (!encoder)
> + return NULL;
> +
> drm_WARN(encoder->base.dev, num_encoders != 1,
> "%d encoders for pipe %c\n",
> num_encoders, pipe_name(master_crtc->pipe));
> @@ -6898,6 +6901,10 @@ static int intel_atomic_check(struct drm_device
> *dev,
> ret = intel_modeset_calc_cdclk(state);
> if (ret)
> return ret;
> +
> + ret = intel_pmdemand_atomic_check(state);
> + if (ret)
> + goto fail;
> }
>
> ret = intel_atomic_check_crtcs(state);
> @@ -7521,6 +7528,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> }
>
> intel_sagv_pre_plane_update(state);
> + intel_pmdemand_pre_plane_update(state);
>
> /* Complete the events for pipes that have now been disabled */
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> @@ -7622,6 +7630,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> intel_verify_planes(state);
>
> intel_sagv_post_plane_update(state);
> + intel_pmdemand_post_plane_update(state);
>
> drm_atomic_helper_commit_hw_done(&state->base);
>
> @@ -8353,6 +8362,7 @@ void intel_init_display_hooks(struct drm_i915_private
> *dev_priv)
> intel_color_init_hooks(dev_priv);
> intel_init_cdclk_hooks(dev_priv);
> intel_audio_hooks_init(dev_priv);
> + intel_init_pmdemand(dev_priv);
>
> intel_dpll_init_clock_hook(dev_priv);
>
> @@ -8689,6 +8699,10 @@ int intel_modeset_init_noirq(struct
> drm_i915_private *i915)
> if (ret)
> goto cleanup_vga_client_pw_domain_dmc;
>
> + ret = intel_pmdemand_init(i915);
> + if (ret)
> + goto cleanup_vga_client_pw_domain_dmc;
> +
> init_llist_head(&i915->display.atomic_helper.free_list);
> INIT_WORK(&i915->display.atomic_helper.free_work,
> intel_atomic_helper_free_state_worker);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 4f6d1463cc99..0a356409277e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -19,6 +19,7 @@
> #include "intel_mchbar_regs.h"
> #include "intel_pch_refclk.h"
> #include "intel_pcode.h"
> +#include "intel_pm.h"
> #include "intel_snps_phy.h"
> #include "skl_watermark.h"
> #include "vlv_sideband.h"
> @@ -1071,6 +1072,10 @@ static void gen9_dbuf_enable(struct
> drm_i915_private *dev_priv)
> dev_priv->display.dbuf.enabled_slices =
> intel_enabled_dbuf_slices_mask(dev_priv);
>
> + if (DISPLAY_VER(dev_priv) >= 14)
> + intel_program_dbuf_pmdemand(dev_priv, BIT(DBUF_S1) |
> + dev_priv->dbuf.enabled_slices);
> +
> /*
> * Just power up at least 1 slice, we will
> * figure out later which slices we have and what we need.
> @@ -1082,6 +1087,9 @@ static void gen9_dbuf_enable(struct
> drm_i915_private *dev_priv)
> static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
> {
> gen9_dbuf_slices_update(dev_priv, 0);
> +
> + if (DISPLAY_VER(dev_priv) >= 14)
> + intel_program_dbuf_pmdemand(dev_priv, 0);
> }
>
> static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 90ed8e6db2fe..8d1097ffc2e7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -269,6 +269,18 @@ struct drm_i915_private {
> unsigned int hpll_freq;
> unsigned int czclk_freq;
>
> + struct {
> + /* The current hardware dbuf configuration */
> + u8 enabled_slices;
> +
> + struct intel_global_obj obj;
> + } dbuf;
> +
Dbuf is already part of struct intel_display in "display/intel_display_core.h"
Might be worth moving pmdemand there as well. We might have to move the code from
intel_pm.h to display/skl_watermark.c
- Radhakrishna(RK) Sripada
> + struct {
> + wait_queue_head_t waitqueue;
> + struct mutex lock;
> + struct intel_global_obj obj;
> + } pmdemand;
> /**
> * wq - Driver workqueue for GEM.
> *
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 2b75ca5e6e61..1ae7ac004a53 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2317,6 +2317,11 @@ static u32 gen8_de_pipe_fault_mask(struct
> drm_i915_private *dev_priv)
> return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
> }
>
> +static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv)
> +{
> + wake_up_all(&dev_priv->pmdemand.waitqueue);
> +}
> +
> static void
> gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
> {
> @@ -2353,6 +2358,18 @@ gen8_de_misc_irq_handler(struct drm_i915_private
> *dev_priv, u32 iir)
> }
> }
>
> + if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR) {
> + drm_dbg(&dev_priv->drm,
> + "Error waiting for Punit PM Demand Response\n");
> + intel_pmdemand_irq_handler(dev_priv);
> + found = true;
> + }
> +
> + if (iir & XELPDP_PMDEMAND_RSP) {
> + intel_pmdemand_irq_handler(dev_priv);
> + found = true;
> + }
> +
> if (!found)
> drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n");
> }
> @@ -3724,7 +3741,10 @@ static void gen8_de_irq_postinstall(struct
> drm_i915_private *dev_priv)
> if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> de_port_masked |= BXT_DE_PORT_GMBUS;
>
> - if (DISPLAY_VER(dev_priv) >= 11) {
> + if (DISPLAY_VER(dev_priv) >= 14)
> + de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR |
> + XELPDP_PMDEMAND_RSP;
> + else if (DISPLAY_VER(dev_priv) >= 11) {
> enum port port;
>
> if (intel_bios_is_dsi_present(dev_priv, &port))
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 41f9bc4c8266..abf12d459bc2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5601,8 +5601,10 @@
> #define GEN8_DE_MISC_IMR _MMIO(0x44464)
> #define GEN8_DE_MISC_IIR _MMIO(0x44468)
> #define GEN8_DE_MISC_IER _MMIO(0x4446c)
> -#define GEN8_DE_MISC_GSE (1 << 27)
> -#define GEN8_DE_EDP_PSR (1 << 19)
> +#define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27)
> +#define GEN8_DE_MISC_GSE REG_BIT(27)
> +#define GEN8_DE_EDP_PSR REG_BIT(19)
> +#define XELPDP_PMDEMAND_RSP REG_BIT(3)
>
> #define GEN8_PCU_ISR _MMIO(0x444e0)
> #define GEN8_PCU_IMR _MMIO(0x444e4)
> @@ -5665,6 +5667,33 @@
> #define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 <<
> (_HPD_PIN_TC(hpd_pin) * 4))
> #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 <<
> (_HPD_PIN_TC(hpd_pin) * 4))
>
> +#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword)
> _MMIO(0x45230 + 4 * (dword))
> +#define XELPDP_PMDEMAND_QCLK_GV_BW_MASK
> REG_GENMASK(31, 16)
> +#define XELPDP_PMDEMAND_QCLK_GV_BW(x)
> REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, x)
> +#define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK
> REG_GENMASK(14, 12)
> +#define XELPDP_PMDEMAND_VOLTAGE_INDEX(x)
> REG_FIELD_PREP(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, x)
> +#define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK
> REG_GENMASK(11, 8)
> +#define XELPDP_PMDEMAND_QCLK_GV_INDEX(x)
> REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, x)
> +#define XELPDP_PMDEMAND_PIPES_MASK
> REG_GENMASK(7, 6)
> +#define XELPDP_PMDEMAND_PIPES(x)
> REG_FIELD_PREP(XELPDP_PMDEMAND_PIPES_MASK, x)
> +#define XELPDP_PMDEMAND_DBUFS_MASK
> REG_GENMASK(5, 4)
> +#define XELPDP_PMDEMAND_DBUFS(x)
> REG_FIELD_PREP(XELPDP_PMDEMAND_DBUFS_MASK, x)
> +#define XELPDP_PMDEMAND_PHYS_MASK
> REG_GENMASK(2, 0)
> +#define XELPDP_PMDEMAND_PHYS(x)
> REG_FIELD_PREP(XELPDP_PMDEMAND_PHYS_MASK, x)
> +
> +#define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31)
> +#define XELPDP_PMDEMAND_CDCLK_FREQ_MASK
> REG_GENMASK(30, 20)
> +#define XELPDP_PMDEMAND_CDCLK_FREQ(x)
> REG_FIELD_PREP(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, x)
> +#define XELPDP_PMDEMAND_DDICLK_FREQ_MASK
> REG_GENMASK(18, 8)
> +#define XELPDP_PMDEMAND_DDICLK_FREQ(x)
> REG_FIELD_PREP(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, x)
> +#define XELPDP_PMDEMAND_SCALERS_MASK
> REG_GENMASK(6, 4)
> +#define XELPDP_PMDEMAND_SCALERS(x)
> REG_FIELD_PREP(XELPDP_PMDEMAND_SCALERS_MASK, x)
> +#define XELPDP_PMDEMAND_PLLS_MASK
> REG_GENMASK(2, 0)
> +#define XELPDP_PMDEMAND_PLLS(x)
> REG_FIELD_PREP(XELPDP_PMDEMAND_PLLS_MASK, x)
> +
> +#define GEN12_DCPR_STATUS_1
> _MMIO(0x46440)
> +#define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26)
> +
> #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
> /* Required on all Ironlake and Sandybridge according to the B-Spec. */
> #define ILK_ELPIN_409_SELECT (1 << 25)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9f6c58ad8bdb..8b5aed52e8bc 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -25,6 +25,11 @@
> *
> */
>
> +#include <linux/bitops.h>
> +
> +#include "display/intel_bw.h"
> +#include "display/intel_cdclk.h"
> +#include "display/intel_cx0_phy.h"
> #include "display/intel_de.h"
> #include "display/intel_display_trace.h"
> #include "display/skl_watermark.h"
> @@ -4094,6 +4099,287 @@ void ilk_wm_get_hw_state(struct
> drm_i915_private *dev_priv)
> !(intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) &
> DISP_FBC_WM_DIS);
> }
>
> +static struct intel_global_state *intel_pmdemand_duplicate_state(struct
> intel_global_obj *obj)
> +{
> + struct intel_pmdemand_state *pmdmnd_state;
> +
> + pmdmnd_state = kmemdup(obj->state, sizeof(*pmdmnd_state),
> GFP_KERNEL);
> + if (!pmdmnd_state)
> + return NULL;
> +
> + return &pmdmnd_state->base;
> +}
> +
> +static void intel_pmdemand_destroy_state(struct intel_global_obj *obj,
> + struct intel_global_state *state)
> +{
> + kfree(state);
> +}
> +
> +static const struct intel_global_state_funcs intel_pmdemand_funcs = {
> + .atomic_duplicate_state = intel_pmdemand_duplicate_state,
> + .atomic_destroy_state = intel_pmdemand_destroy_state,
> +};
> +
> +struct intel_pmdemand_state *
> +intel_atomic_get_pmdemand_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_global_state *pmdemand_state;
> +
> + pmdemand_state = intel_atomic_get_global_obj_state(state,
> &dev_priv->pmdemand.obj);
> + if (IS_ERR(pmdemand_state))
> + return ERR_CAST(pmdemand_state);
> +
> + return to_intel_pmdemand_state(pmdemand_state);
> +}
> +
> +int intel_pmdemand_init(struct drm_i915_private *dev_priv)
> +{
> + struct intel_pmdemand_state *pmdemand_state;
> +
> + pmdemand_state = kzalloc(sizeof(*pmdemand_state), GFP_KERNEL);
> + if (!pmdemand_state)
> + return -ENOMEM;
> +
> + intel_atomic_global_obj_init(dev_priv, &dev_priv->pmdemand.obj,
> + &pmdemand_state->base,
> &intel_pmdemand_funcs);
> +
> + return 0;
> +}
> +
> +void intel_init_pmdemand(struct drm_i915_private *dev_priv)
> +{
> + mutex_init(&dev_priv->pmdemand.lock);
> + init_waitqueue_head(&dev_priv->pmdemand.waitqueue);
> +}
> +
> +int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_pmdemand_state *new_pmdemand_state = NULL;
> + struct intel_crtc_state *old_crtc_state, *new_crtc_state;
> + struct intel_crtc *crtc;
> + struct intel_encoder *encoder;
> + struct intel_bw_state *new_bw_state;
> + const struct intel_dbuf_state *new_dbuf_state;
> + const struct intel_cdclk_state *new_cdclk_state;
> + int port_clock = 0;
> + unsigned int data_rate;
> + enum phy phy;
> + int i, ret;
> +
> + if (DISPLAY_VER(dev_priv) < 14)
> + return 0;
> +
> + new_pmdemand_state = intel_atomic_get_pmdemand_state(state);
> + if (IS_ERR(new_pmdemand_state))
> + return PTR_ERR(new_pmdemand_state);
> +
> + ret = intel_atomic_lock_global_state(&new_pmdemand_state->base);
> + if (ret)
> + return ret;
> +
> + /* Punit figures out the voltage index based on bandwidth*/
> + new_bw_state = intel_atomic_get_bw_state(state);
> + if (IS_ERR(new_bw_state))
> + return PTR_ERR(new_bw_state);
> +
> + /* firmware will calculate the qclck_gc_index, requirement is set to 0 */
> + new_pmdemand_state->qclk_gv_index = 0;
> +
> + data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
> + /* To MBs then to multiples of 100MBs */
> + data_rate = DIV_ROUND_UP(data_rate, 1000);
> + data_rate = DIV_ROUND_UP(data_rate, 100);
> + new_pmdemand_state->qclk_gv_bw = data_rate;
> +
> + new_dbuf_state = intel_atomic_get_dbuf_state(state);
> + if (IS_ERR(new_dbuf_state))
> + return PTR_ERR(new_dbuf_state);
> +
> + i = hweight8(new_dbuf_state->active_pipes);
> + new_pmdemand_state->active_pipes = min(i, 3);
> +
> + new_cdclk_state = intel_atomic_get_cdclk_state(state);
> + if (IS_ERR(new_cdclk_state))
> + return PTR_ERR(new_cdclk_state);
> +
> + new_pmdemand_state->voltage_index = new_cdclk_state-
> >logical.voltage_level;
> + /* KHz to MHz */
> + new_pmdemand_state->cdclk_freq_mhz =
> DIV_ROUND_UP(new_cdclk_state->logical.cdclk, 1000);
> +
> + new_pmdemand_state->active_phys_plls_mask = 0;
> +
> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> + if (!new_crtc_state->hw.active)
> + continue;
> +
> + encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
> + if (!encoder)
> + continue;
> +
> + phy = intel_port_to_phy(dev_priv, encoder->port);
> +
> + if (intel_is_c10phy(dev_priv, phy))
> + new_pmdemand_state->active_phys_plls_mask |=
> BIT(phy);
> +
> + port_clock = max(port_clock, new_crtc_state->port_clock);
> + }
> +
> + /* To MHz */
> + new_pmdemand_state->ddiclk_freq_mhz =
> DIV_ROUND_UP(port_clock, 1000);
> +
> + /*
> + * Setting scalers to max as it can not be calculated during flips and
> + * fastsets without taking global states locks.
> + */
> + new_pmdemand_state->scalers = 7;
> +
> + return 0;
> +}
> +
> +static bool intel_pmdemand_check_prev_transaction(struct drm_i915_private
> *dev_priv)
> +{
> + return !((intel_de_read(dev_priv,
> XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
> XELPDP_PMDEMAND_REQ_ENABLE) ||
> + (intel_de_read(dev_priv, GEN12_DCPR_STATUS_1) &
> XELPDP_PMDEMAND_INFLIGHT_STATUS));
> +}
> +
> +static bool intel_pmdemand_req_complete(struct drm_i915_private *dev_priv)
> +{
> + return !(intel_de_read(dev_priv,
> XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
> XELPDP_PMDEMAND_REQ_ENABLE);
> +}
> +
> +static int intel_pmdemand_wait(struct drm_i915_private *dev_priv)
> +{
> + DEFINE_WAIT(wait);
> + int ret;
> + const unsigned int timeout_ms = 10;
> +
> + add_wait_queue(&dev_priv->pmdemand.waitqueue, &wait);
> +
> + ret = wait_event_timeout(dev_priv->pmdemand.waitqueue,
> + intel_pmdemand_req_complete(dev_priv),
> + msecs_to_jiffies_timeout(timeout_ms));
> + if (ret < 0)
> + drm_err(&dev_priv->drm,
> + "timed out waiting for Punit PM Demand Response\n");
> +
> + remove_wait_queue(&dev_priv->pmdemand.waitqueue, &wait);
> +
> + return ret;
> +}
> +
> +/* Required to be programmed during Display Init Sequences. */
> +void intel_program_dbuf_pmdemand(struct drm_i915_private *dev_priv,
> + u8 dbuf_slices)
> +{
> + mutex_lock(&dev_priv->pmdemand.lock);
> + if (drm_WARN_ON(&dev_priv->drm,
> + !intel_pmdemand_check_prev_transaction(dev_priv)))
> + goto unlock;
> +
> + intel_de_rmw(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
> + XELPDP_PMDEMAND_DBUFS_MASK,
> + XELPDP_PMDEMAND_DBUFS(hweight32(dbuf_slices)));
> + intel_de_rmw(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
> + XELPDP_PMDEMAND_REQ_ENABLE);
> +
> + intel_pmdemand_wait(dev_priv);
> +unlock:
> + mutex_unlock(&dev_priv->pmdemand.lock);
> +}
> +
> +static void intel_program_pmdemand(struct drm_i915_private *dev_priv,
> + const struct intel_pmdemand_state *new,
> + const struct intel_pmdemand_state *old)
> +{
> + u32 val, tmp;
> +
> +#define UPDATE_PMDEMAND_VAL(val, F, f) do { \
> + val &= (~(XELPDP_PMDEMAND_##F##_MASK)); \
> + val |= (XELPDP_PMDEMAND_##F((u32)(old ? max(old->f, new->f) : new-
> >f))); \
> +} while (0)
> +
> + mutex_lock(&dev_priv->pmdemand.lock);
> + if (drm_WARN_ON(&dev_priv->drm,
> + !intel_pmdemand_check_prev_transaction(dev_priv)))
> + goto unlock;
> +
> + /*
> + * TODO: Update programming PM Demand for
> + * PHYS, PLLS, DDI_CLKFREQ, SCALARS
> + */
> + val = intel_de_read(dev_priv,
> XELPDP_INITIATE_PMDEMAND_REQUEST(0));
> + UPDATE_PMDEMAND_VAL(val, QCLK_GV_INDEX, qclk_gv_index);
> + UPDATE_PMDEMAND_VAL(val, QCLK_GV_BW, qclk_gv_bw);
> + UPDATE_PMDEMAND_VAL(val, VOLTAGE_INDEX, voltage_index);
> + UPDATE_PMDEMAND_VAL(val, PIPES, active_pipes);
> + UPDATE_PMDEMAND_VAL(val, DBUFS, dbufs);
> + tmp = hweight32(new->active_phys_plls_mask);
> + if (old)
> + tmp = max(tmp, hweight32(old->active_phys_plls_mask));
> + val |= XELPDP_PMDEMAND_PHYS(tmp);
> +
> + intel_de_write(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
> val);
> +
> + val = intel_de_read(dev_priv,
> XELPDP_INITIATE_PMDEMAND_REQUEST(1));
> + UPDATE_PMDEMAND_VAL(val, CDCLK_FREQ, cdclk_freq_mhz);
> + UPDATE_PMDEMAND_VAL(val, DDICLK_FREQ, ddiclk_freq_mhz);
> + UPDATE_PMDEMAND_VAL(val, SCALERS, scalers);
> + /*
> + * Active_PLLs starts with 1 because of CDCLK PLL.
> + * TODO: Missing to account genlock filter when it gets used.
> + */
> + val |= XELPDP_PMDEMAND_PLLS(tmp + 1);
> +
> + intel_de_write(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
> val);
> +
> +#undef UPDATE_PM_DEMAND_VAL
> +
> + intel_de_rmw(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
> XELPDP_PMDEMAND_REQ_ENABLE);
> +
> + intel_pmdemand_wait(dev_priv);
> +unlock:
> + mutex_unlock(&dev_priv->pmdemand.lock);
> +}
> +
> +void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + const struct intel_pmdemand_state *new_pmdmnd_state =
> + intel_atomic_get_new_pmdemand_state(state);
> + const struct intel_pmdemand_state *old_pmdmnd_state =
> + intel_atomic_get_old_pmdemand_state(state);
> +
> + if (DISPLAY_VER(dev_priv) < 14)
> + return;
> +
> + if (!new_pmdmnd_state ||
> + memcmp(new_pmdmnd_state, old_pmdmnd_state,
> sizeof(*new_pmdmnd_state)) == 0)
> + return;
> +
> + intel_program_pmdemand(dev_priv, new_pmdmnd_state,
> old_pmdmnd_state);
> +}
> +
> +void intel_pmdemand_post_plane_update(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + const struct intel_pmdemand_state *new_pmdmnd_state =
> + intel_atomic_get_new_pmdemand_state(state);
> + const struct intel_pmdemand_state *old_pmdmnd_state =
> + intel_atomic_get_old_pmdemand_state(state);
> +
> + if (DISPLAY_VER(dev_priv) < 14)
> + return;
> +
> + if (!new_pmdmnd_state ||
> + memcmp(new_pmdmnd_state, old_pmdmnd_state,
> sizeof(*new_pmdmnd_state)) == 0)
> + return;
> +
> + intel_program_pmdemand(dev_priv, new_pmdmnd_state, NULL);
> +}
> +
> static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> /*
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index c09b872d65c8..88e8fef6c10b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -8,6 +8,8 @@
>
> #include <linux/types.h>
>
> +#include "display/intel_global_state.h"
> +
> struct drm_i915_private;
> struct intel_crtc_state;
> struct intel_plane_state;
> @@ -15,6 +17,7 @@ struct intel_plane_state;
> void intel_init_clock_gating(struct drm_i915_private *dev_priv);
> void intel_suspend_hw(struct drm_i915_private *dev_priv);
> int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
> +void intel_init_pmdemand(struct drm_i915_private *dev_priv);
> void intel_init_pm(struct drm_i915_private *dev_priv);
> void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
> void intel_pm_setup(struct drm_i915_private *dev_priv);
> @@ -31,4 +34,36 @@ void intel_print_wm_latency(struct drm_i915_private
> *dev_priv,
>
> bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable);
>
> +struct intel_pmdemand_state {
> + struct intel_global_state base;
> +
> + u16 qclk_gv_bw;
> + u8 voltage_index;
> + u8 qclk_gv_index;
> + u8 active_pipes;
> + u8 dbufs;
> + u8 active_phys_plls_mask;
> + u16 cdclk_freq_mhz;
> + u16 ddiclk_freq_mhz;
> + u8 scalers;
> +};
> +
> +int intel_pmdemand_init(struct drm_i915_private *dev_priv);
> +
> +struct intel_pmdemand_state *
> +intel_atomic_get_pmdemand_state(struct intel_atomic_state *state);
> +
> +#define to_intel_pmdemand_state(x) container_of((x), struct
> intel_pmdemand_state, base)
> +#define intel_atomic_get_old_pmdemand_state(state) \
> +
> to_intel_pmdemand_state(intel_atomic_get_old_global_obj_state(stat
> e, &to_i915(state->base.dev)->pmdemand.obj))
> +#define intel_atomic_get_new_pmdemand_state(state) \
> +
> to_intel_pmdemand_state(intel_atomic_get_new_global_obj_state(sta
> te, &to_i915(state->base.dev)->pmdemand.obj))
> +
> +int intel_pmdemand_init(struct drm_i915_private *dev_priv);
> +void intel_program_dbuf_pmdemand(struct drm_i915_private *dev_priv,
> + u8 dbuf_slices);
> +void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state);
> +void intel_pmdemand_post_plane_update(struct intel_atomic_state *state);
> +int intel_pmdemand_atomic_check(struct intel_atomic_state *state);
> +
> #endif /* __INTEL_PM_H__ */
> --
> 2.34.1
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [Intel-gfx] [PATCH 07/20] drm/i915/mtl: Add support for PM DEMAND
2022-11-01 2:38 ` Sripada, Radhakrishna
@ 2022-11-15 12:56 ` Kahola, Mika
0 siblings, 0 replies; 36+ messages in thread
From: Kahola, Mika @ 2022-11-15 12:56 UTC (permalink / raw)
To: Sripada, Radhakrishna, intel-gfx@lists.freedesktop.org; +Cc: De Marchi, Lucas
> -----Original Message-----
> From: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> Sent: Tuesday, November 1, 2022 4:38 AM
> To: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Atwood, Matthew S <matthew.s.atwood@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>;
> Souza, Jose <jose.souza@intel.com>
> Subject: RE: [PATCH 07/20] drm/i915/mtl: Add support for PM DEMAND
>
>
>
> > -----Original Message-----
> > From: Kahola, Mika <mika.kahola@intel.com>
> > Sent: Friday, October 14, 2022 5:47 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Kahola, Mika <mika.kahola@intel.com>; Atwood, Matthew S
> > <matthew.s.atwood@intel.com>; Roper, Matthew D
> > <matthew.d.roper@intel.com>; De Marchi, Lucas
> > <lucas.demarchi@intel.com>; Souza, Jose <jose.souza@intel.com>;
> > Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> > Subject: [PATCH 07/20] drm/i915/mtl: Add support for PM DEMAND
> >
> > Display14 introduces a new way to instruct the PUnit with power and
> > bandwidth requirements of DE. Add the functionality to program the
> > registers and handle waits using interrupts.
> > The current wait time for timeouts is programmed for 10 msecs to
> > factor in the worst case scenarios. Changes made to use REG_BIT for a
> > register that we touched(GEN8_DE_MISC_IER _MMIO).
> >
> > Bspec: 66451, 64636, 64602, 64603
> >
> > Cc: Matt Atwood <matthew.s.atwood@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> >
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_bw.c | 4 +-
> > drivers/gpu/drm/i915/display/intel_bw.h | 2 +
> > drivers/gpu/drm/i915/display/intel_display.c | 14 +
> > .../drm/i915/display/intel_display_power.c | 8 +
> > drivers/gpu/drm/i915/i915_drv.h | 12 +
> > drivers/gpu/drm/i915/i915_irq.c | 22 +-
> > drivers/gpu/drm/i915/i915_reg.h | 33 +-
> > drivers/gpu/drm/i915/intel_pm.c | 286 ++++++++++++++++++
> > drivers/gpu/drm/i915/intel_pm.h | 35 +++
> > 9 files changed, 411 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > b/drivers/gpu/drm/i915/display/intel_bw.c
> > index 4ace026b29bd..6c467b6f2234 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -716,8 +716,8 @@ static unsigned int
> > intel_bw_num_active_planes(struct drm_i915_private *dev_priv
> > return num_active_planes;
> > }
> >
> > -static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> > - const struct intel_bw_state *bw_state)
> > +unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> > + const struct intel_bw_state *bw_state)
> > {
> > unsigned int data_rate = 0;
> > enum pipe pipe;
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
> > b/drivers/gpu/drm/i915/display/intel_bw.h
> > index cb7ee3a24a58..b3eb82a71e6c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > @@ -62,6 +62,8 @@ int intel_bw_init(struct drm_i915_private
> > *dev_priv); int intel_bw_atomic_check(struct intel_atomic_state
> > *state); void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> > const struct intel_crtc_state *crtc_state);
> > +unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
> > + const struct intel_bw_state *bw_state);
> > int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> > u32 points_mask);
> > int intel_bw_calc_min_cdclk(struct intel_atomic_state *state, diff
> > --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 0a8749753e6e..5ce33319b70d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1079,6 +1079,9 @@ intel_get_crtc_new_encoder(const struct
> > intel_atomic_state *state,
> > num_encoders++;
> > }
> >
> > + if (!encoder)
> > + return NULL;
> > +
> > drm_WARN(encoder->base.dev, num_encoders != 1,
> > "%d encoders for pipe %c\n",
> > num_encoders, pipe_name(master_crtc->pipe)); @@ -6898,6
> +6901,10
> > @@ static int intel_atomic_check(struct drm_device *dev,
> > ret = intel_modeset_calc_cdclk(state);
> > if (ret)
> > return ret;
> > +
> > + ret = intel_pmdemand_atomic_check(state);
> > + if (ret)
> > + goto fail;
> > }
> >
> > ret = intel_atomic_check_crtcs(state); @@ -7521,6 +7528,7 @@ static
> > void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > }
> >
> > intel_sagv_pre_plane_update(state);
> > + intel_pmdemand_pre_plane_update(state);
> >
> > /* Complete the events for pipes that have now been disabled */
> > for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > @@ -7622,6 +7630,7 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> > intel_verify_planes(state);
> >
> > intel_sagv_post_plane_update(state);
> > + intel_pmdemand_post_plane_update(state);
> >
> > drm_atomic_helper_commit_hw_done(&state->base);
> >
> > @@ -8353,6 +8362,7 @@ void intel_init_display_hooks(struct
> > drm_i915_private
> > *dev_priv)
> > intel_color_init_hooks(dev_priv);
> > intel_init_cdclk_hooks(dev_priv);
> > intel_audio_hooks_init(dev_priv);
> > + intel_init_pmdemand(dev_priv);
> >
> > intel_dpll_init_clock_hook(dev_priv);
> >
> > @@ -8689,6 +8699,10 @@ int intel_modeset_init_noirq(struct
> > drm_i915_private *i915)
> > if (ret)
> > goto cleanup_vga_client_pw_domain_dmc;
> >
> > + ret = intel_pmdemand_init(i915);
> > + if (ret)
> > + goto cleanup_vga_client_pw_domain_dmc;
> > +
> > init_llist_head(&i915->display.atomic_helper.free_list);
> > INIT_WORK(&i915->display.atomic_helper.free_work,
> > intel_atomic_helper_free_state_worker);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 4f6d1463cc99..0a356409277e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -19,6 +19,7 @@
> > #include "intel_mchbar_regs.h"
> > #include "intel_pch_refclk.h"
> > #include "intel_pcode.h"
> > +#include "intel_pm.h"
> > #include "intel_snps_phy.h"
> > #include "skl_watermark.h"
> > #include "vlv_sideband.h"
> > @@ -1071,6 +1072,10 @@ static void gen9_dbuf_enable(struct
> > drm_i915_private *dev_priv)
> > dev_priv->display.dbuf.enabled_slices =
> > intel_enabled_dbuf_slices_mask(dev_priv);
> >
> > + if (DISPLAY_VER(dev_priv) >= 14)
> > + intel_program_dbuf_pmdemand(dev_priv, BIT(DBUF_S1) |
> > + dev_priv->dbuf.enabled_slices);
> > +
> > /*
> > * Just power up at least 1 slice, we will
> > * figure out later which slices we have and what we need.
> > @@ -1082,6 +1087,9 @@ static void gen9_dbuf_enable(struct
> > drm_i915_private *dev_priv) static void gen9_dbuf_disable(struct
> > drm_i915_private *dev_priv) {
> > gen9_dbuf_slices_update(dev_priv, 0);
> > +
> > + if (DISPLAY_VER(dev_priv) >= 14)
> > + intel_program_dbuf_pmdemand(dev_priv, 0);
> > }
> >
> > static void gen12_dbuf_slices_config(struct drm_i915_private
> > *dev_priv) diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index 90ed8e6db2fe..8d1097ffc2e7
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -269,6 +269,18 @@ struct drm_i915_private {
> > unsigned int hpll_freq;
> > unsigned int czclk_freq;
> >
> > + struct {
> > + /* The current hardware dbuf configuration */
> > + u8 enabled_slices;
> > +
> > + struct intel_global_obj obj;
> > + } dbuf;
> > +
> Dbuf is already part of struct intel_display in "display/intel_display_core.h"
> Might be worth moving pmdemand there as well. We might have to move the
> code from intel_pm.h to display/skl_watermark.c
Thanks! I will have these changes made in next revision.
Cheers,
Mika
>
> - Radhakrishna(RK) Sripada
>
> > + struct {
> > + wait_queue_head_t waitqueue;
> > + struct mutex lock;
> > + struct intel_global_obj obj;
> > + } pmdemand;
> > /**
> > * wq - Driver workqueue for GEM.
> > *
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c index 2b75ca5e6e61..1ae7ac004a53
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -2317,6 +2317,11 @@ static u32 gen8_de_pipe_fault_mask(struct
> > drm_i915_private *dev_priv)
> > return GEN8_DE_PIPE_IRQ_FAULT_ERRORS; }
> >
> > +static void intel_pmdemand_irq_handler(struct drm_i915_private
> > +*dev_priv) {
> > + wake_up_all(&dev_priv->pmdemand.waitqueue);
> > +}
> > +
> > static void
> > gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
> > { @@ -2353,6 +2358,18 @@ gen8_de_misc_irq_handler(struct
> > drm_i915_private *dev_priv, u32 iir)
> > }
> > }
> >
> > + if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR) {
> > + drm_dbg(&dev_priv->drm,
> > + "Error waiting for Punit PM Demand Response\n");
> > + intel_pmdemand_irq_handler(dev_priv);
> > + found = true;
> > + }
> > +
> > + if (iir & XELPDP_PMDEMAND_RSP) {
> > + intel_pmdemand_irq_handler(dev_priv);
> > + found = true;
> > + }
> > +
> > if (!found)
> > drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n"); }
> @@
> > -3724,7 +3741,10 @@ static void gen8_de_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> > de_port_masked |= BXT_DE_PORT_GMBUS;
> >
> > - if (DISPLAY_VER(dev_priv) >= 11) {
> > + if (DISPLAY_VER(dev_priv) >= 14)
> > + de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR |
> > + XELPDP_PMDEMAND_RSP;
> > + else if (DISPLAY_VER(dev_priv) >= 11) {
> > enum port port;
> >
> > if (intel_bios_is_dsi_present(dev_priv, &port)) diff --git
> > a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 41f9bc4c8266..abf12d459bc2 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5601,8 +5601,10 @@
> > #define GEN8_DE_MISC_IMR _MMIO(0x44464) #define GEN8_DE_MISC_IIR
> > _MMIO(0x44468) #define GEN8_DE_MISC_IER _MMIO(0x4446c)
> > -#define GEN8_DE_MISC_GSE (1 << 27)
> > -#define GEN8_DE_EDP_PSR (1 << 19)
> > +#define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27)
> > +#define GEN8_DE_MISC_GSE REG_BIT(27)
> > +#define GEN8_DE_EDP_PSR REG_BIT(19)
> > +#define XELPDP_PMDEMAND_RSP REG_BIT(3)
> >
> > #define GEN8_PCU_ISR _MMIO(0x444e0)
> > #define GEN8_PCU_IMR _MMIO(0x444e4)
> > @@ -5665,6 +5667,33 @@
> > #define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 <<
> > (_HPD_PIN_TC(hpd_pin) * 4))
> > #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 <<
> > (_HPD_PIN_TC(hpd_pin) * 4))
> >
> > +#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword)
> > _MMIO(0x45230 + 4 * (dword))
> > +#define XELPDP_PMDEMAND_QCLK_GV_BW_MASK
> > REG_GENMASK(31, 16)
> > +#define XELPDP_PMDEMAND_QCLK_GV_BW(x)
> > REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, x)
> > +#define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK
> > REG_GENMASK(14, 12)
> > +#define XELPDP_PMDEMAND_VOLTAGE_INDEX(x)
> > REG_FIELD_PREP(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, x)
> > +#define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK
> > REG_GENMASK(11, 8)
> > +#define XELPDP_PMDEMAND_QCLK_GV_INDEX(x)
> > REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, x)
> > +#define XELPDP_PMDEMAND_PIPES_MASK
> > REG_GENMASK(7, 6)
> > +#define XELPDP_PMDEMAND_PIPES(x)
> > REG_FIELD_PREP(XELPDP_PMDEMAND_PIPES_MASK, x)
> > +#define XELPDP_PMDEMAND_DBUFS_MASK
> > REG_GENMASK(5, 4)
> > +#define XELPDP_PMDEMAND_DBUFS(x)
> > REG_FIELD_PREP(XELPDP_PMDEMAND_DBUFS_MASK, x)
> > +#define XELPDP_PMDEMAND_PHYS_MASK
> > REG_GENMASK(2, 0)
> > +#define XELPDP_PMDEMAND_PHYS(x)
> > REG_FIELD_PREP(XELPDP_PMDEMAND_PHYS_MASK, x)
> > +
> > +#define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31)
> > +#define XELPDP_PMDEMAND_CDCLK_FREQ_MASK
> > REG_GENMASK(30, 20)
> > +#define XELPDP_PMDEMAND_CDCLK_FREQ(x)
> > REG_FIELD_PREP(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, x)
> > +#define XELPDP_PMDEMAND_DDICLK_FREQ_MASK
> > REG_GENMASK(18, 8)
> > +#define XELPDP_PMDEMAND_DDICLK_FREQ(x)
> > REG_FIELD_PREP(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, x)
> > +#define XELPDP_PMDEMAND_SCALERS_MASK
> > REG_GENMASK(6, 4)
> > +#define XELPDP_PMDEMAND_SCALERS(x)
> > REG_FIELD_PREP(XELPDP_PMDEMAND_SCALERS_MASK, x)
> > +#define XELPDP_PMDEMAND_PLLS_MASK
> > REG_GENMASK(2, 0)
> > +#define XELPDP_PMDEMAND_PLLS(x)
> > REG_FIELD_PREP(XELPDP_PMDEMAND_PLLS_MASK, x)
> > +
> > +#define GEN12_DCPR_STATUS_1
> > _MMIO(0x46440)
> > +#define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26)
> > +
> > #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
> > /* Required on all Ironlake and Sandybridge according to the B-Spec. */
> > #define ILK_ELPIN_409_SELECT (1 << 25)
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c index 9f6c58ad8bdb..8b5aed52e8bc
> > 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -25,6 +25,11 @@
> > *
> > */
> >
> > +#include <linux/bitops.h>
> > +
> > +#include "display/intel_bw.h"
> > +#include "display/intel_cdclk.h"
> > +#include "display/intel_cx0_phy.h"
> > #include "display/intel_de.h"
> > #include "display/intel_display_trace.h"
> > #include "display/skl_watermark.h"
> > @@ -4094,6 +4099,287 @@ void ilk_wm_get_hw_state(struct
> > drm_i915_private *dev_priv)
> > !(intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) &
> > DISP_FBC_WM_DIS); }
> >
> > +static struct intel_global_state
> > +*intel_pmdemand_duplicate_state(struct
> > intel_global_obj *obj)
> > +{
> > + struct intel_pmdemand_state *pmdmnd_state;
> > +
> > + pmdmnd_state = kmemdup(obj->state, sizeof(*pmdmnd_state),
> > GFP_KERNEL);
> > + if (!pmdmnd_state)
> > + return NULL;
> > +
> > + return &pmdmnd_state->base;
> > +}
> > +
> > +static void intel_pmdemand_destroy_state(struct intel_global_obj *obj,
> > + struct intel_global_state *state) {
> > + kfree(state);
> > +}
> > +
> > +static const struct intel_global_state_funcs intel_pmdemand_funcs = {
> > + .atomic_duplicate_state = intel_pmdemand_duplicate_state,
> > + .atomic_destroy_state = intel_pmdemand_destroy_state, };
> > +
> > +struct intel_pmdemand_state *
> > +intel_atomic_get_pmdemand_state(struct intel_atomic_state *state) {
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + struct intel_global_state *pmdemand_state;
> > +
> > + pmdemand_state = intel_atomic_get_global_obj_state(state,
> > &dev_priv->pmdemand.obj);
> > + if (IS_ERR(pmdemand_state))
> > + return ERR_CAST(pmdemand_state);
> > +
> > + return to_intel_pmdemand_state(pmdemand_state);
> > +}
> > +
> > +int intel_pmdemand_init(struct drm_i915_private *dev_priv) {
> > + struct intel_pmdemand_state *pmdemand_state;
> > +
> > + pmdemand_state = kzalloc(sizeof(*pmdemand_state), GFP_KERNEL);
> > + if (!pmdemand_state)
> > + return -ENOMEM;
> > +
> > + intel_atomic_global_obj_init(dev_priv, &dev_priv->pmdemand.obj,
> > + &pmdemand_state->base,
> > &intel_pmdemand_funcs);
> > +
> > + return 0;
> > +}
> > +
> > +void intel_init_pmdemand(struct drm_i915_private *dev_priv) {
> > + mutex_init(&dev_priv->pmdemand.lock);
> > + init_waitqueue_head(&dev_priv->pmdemand.waitqueue);
> > +}
> > +
> > +int intel_pmdemand_atomic_check(struct intel_atomic_state *state) {
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + struct intel_pmdemand_state *new_pmdemand_state = NULL;
> > + struct intel_crtc_state *old_crtc_state, *new_crtc_state;
> > + struct intel_crtc *crtc;
> > + struct intel_encoder *encoder;
> > + struct intel_bw_state *new_bw_state;
> > + const struct intel_dbuf_state *new_dbuf_state;
> > + const struct intel_cdclk_state *new_cdclk_state;
> > + int port_clock = 0;
> > + unsigned int data_rate;
> > + enum phy phy;
> > + int i, ret;
> > +
> > + if (DISPLAY_VER(dev_priv) < 14)
> > + return 0;
> > +
> > + new_pmdemand_state = intel_atomic_get_pmdemand_state(state);
> > + if (IS_ERR(new_pmdemand_state))
> > + return PTR_ERR(new_pmdemand_state);
> > +
> > + ret = intel_atomic_lock_global_state(&new_pmdemand_state->base);
> > + if (ret)
> > + return ret;
> > +
> > + /* Punit figures out the voltage index based on bandwidth*/
> > + new_bw_state = intel_atomic_get_bw_state(state);
> > + if (IS_ERR(new_bw_state))
> > + return PTR_ERR(new_bw_state);
> > +
> > + /* firmware will calculate the qclck_gc_index, requirement is set to 0 */
> > + new_pmdemand_state->qclk_gv_index = 0;
> > +
> > + data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
> > + /* To MBs then to multiples of 100MBs */
> > + data_rate = DIV_ROUND_UP(data_rate, 1000);
> > + data_rate = DIV_ROUND_UP(data_rate, 100);
> > + new_pmdemand_state->qclk_gv_bw = data_rate;
> > +
> > + new_dbuf_state = intel_atomic_get_dbuf_state(state);
> > + if (IS_ERR(new_dbuf_state))
> > + return PTR_ERR(new_dbuf_state);
> > +
> > + i = hweight8(new_dbuf_state->active_pipes);
> > + new_pmdemand_state->active_pipes = min(i, 3);
> > +
> > + new_cdclk_state = intel_atomic_get_cdclk_state(state);
> > + if (IS_ERR(new_cdclk_state))
> > + return PTR_ERR(new_cdclk_state);
> > +
> > + new_pmdemand_state->voltage_index = new_cdclk_state-
> > >logical.voltage_level;
> > + /* KHz to MHz */
> > + new_pmdemand_state->cdclk_freq_mhz =
> > DIV_ROUND_UP(new_cdclk_state->logical.cdclk, 1000);
> > +
> > + new_pmdemand_state->active_phys_plls_mask = 0;
> > +
> > + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> > new_crtc_state, i) {
> > + if (!new_crtc_state->hw.active)
> > + continue;
> > +
> > + encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
> > + if (!encoder)
> > + continue;
> > +
> > + phy = intel_port_to_phy(dev_priv, encoder->port);
> > +
> > + if (intel_is_c10phy(dev_priv, phy))
> > + new_pmdemand_state->active_phys_plls_mask |=
> > BIT(phy);
> > +
> > + port_clock = max(port_clock, new_crtc_state->port_clock);
> > + }
> > +
> > + /* To MHz */
> > + new_pmdemand_state->ddiclk_freq_mhz =
> > DIV_ROUND_UP(port_clock, 1000);
> > +
> > + /*
> > + * Setting scalers to max as it can not be calculated during flips and
> > + * fastsets without taking global states locks.
> > + */
> > + new_pmdemand_state->scalers = 7;
> > +
> > + return 0;
> > +}
> > +
> > +static bool intel_pmdemand_check_prev_transaction(struct
> > +drm_i915_private
> > *dev_priv)
> > +{
> > + return !((intel_de_read(dev_priv,
> > XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
> > XELPDP_PMDEMAND_REQ_ENABLE) ||
> > + (intel_de_read(dev_priv, GEN12_DCPR_STATUS_1) &
> > XELPDP_PMDEMAND_INFLIGHT_STATUS));
> > +}
> > +
> > +static bool intel_pmdemand_req_complete(struct drm_i915_private
> > +*dev_priv) {
> > + return !(intel_de_read(dev_priv,
> > XELPDP_INITIATE_PMDEMAND_REQUEST(1)) &
> XELPDP_PMDEMAND_REQ_ENABLE);
> > +}
> > +
> > +static int intel_pmdemand_wait(struct drm_i915_private *dev_priv) {
> > + DEFINE_WAIT(wait);
> > + int ret;
> > + const unsigned int timeout_ms = 10;
> > +
> > + add_wait_queue(&dev_priv->pmdemand.waitqueue, &wait);
> > +
> > + ret = wait_event_timeout(dev_priv->pmdemand.waitqueue,
> > + intel_pmdemand_req_complete(dev_priv),
> > + msecs_to_jiffies_timeout(timeout_ms));
> > + if (ret < 0)
> > + drm_err(&dev_priv->drm,
> > + "timed out waiting for Punit PM Demand Response\n");
> > +
> > + remove_wait_queue(&dev_priv->pmdemand.waitqueue, &wait);
> > +
> > + return ret;
> > +}
> > +
> > +/* Required to be programmed during Display Init Sequences. */ void
> > +intel_program_dbuf_pmdemand(struct drm_i915_private *dev_priv,
> > + u8 dbuf_slices)
> > +{
> > + mutex_lock(&dev_priv->pmdemand.lock);
> > + if (drm_WARN_ON(&dev_priv->drm,
> > + !intel_pmdemand_check_prev_transaction(dev_priv)))
> > + goto unlock;
> > +
> > + intel_de_rmw(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
> > + XELPDP_PMDEMAND_DBUFS_MASK,
> > + XELPDP_PMDEMAND_DBUFS(hweight32(dbuf_slices)));
> > + intel_de_rmw(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
> > + XELPDP_PMDEMAND_REQ_ENABLE);
> > +
> > + intel_pmdemand_wait(dev_priv);
> > +unlock:
> > + mutex_unlock(&dev_priv->pmdemand.lock);
> > +}
> > +
> > +static void intel_program_pmdemand(struct drm_i915_private *dev_priv,
> > + const struct intel_pmdemand_state *new,
> > + const struct intel_pmdemand_state *old) {
> > + u32 val, tmp;
> > +
> > +#define UPDATE_PMDEMAND_VAL(val, F, f) do { \
> > + val &= (~(XELPDP_PMDEMAND_##F##_MASK)); \
> > + val |= (XELPDP_PMDEMAND_##F((u32)(old ? max(old->f, new->f) : new-
> > >f))); \
> > +} while (0)
> > +
> > + mutex_lock(&dev_priv->pmdemand.lock);
> > + if (drm_WARN_ON(&dev_priv->drm,
> > + !intel_pmdemand_check_prev_transaction(dev_priv)))
> > + goto unlock;
> > +
> > + /*
> > + * TODO: Update programming PM Demand for
> > + * PHYS, PLLS, DDI_CLKFREQ, SCALARS
> > + */
> > + val = intel_de_read(dev_priv,
> > XELPDP_INITIATE_PMDEMAND_REQUEST(0));
> > + UPDATE_PMDEMAND_VAL(val, QCLK_GV_INDEX, qclk_gv_index);
> > + UPDATE_PMDEMAND_VAL(val, QCLK_GV_BW, qclk_gv_bw);
> > + UPDATE_PMDEMAND_VAL(val, VOLTAGE_INDEX, voltage_index);
> > + UPDATE_PMDEMAND_VAL(val, PIPES, active_pipes);
> > + UPDATE_PMDEMAND_VAL(val, DBUFS, dbufs);
> > + tmp = hweight32(new->active_phys_plls_mask);
> > + if (old)
> > + tmp = max(tmp, hweight32(old->active_phys_plls_mask));
> > + val |= XELPDP_PMDEMAND_PHYS(tmp);
> > +
> > + intel_de_write(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
> > val);
> > +
> > + val = intel_de_read(dev_priv,
> > XELPDP_INITIATE_PMDEMAND_REQUEST(1));
> > + UPDATE_PMDEMAND_VAL(val, CDCLK_FREQ, cdclk_freq_mhz);
> > + UPDATE_PMDEMAND_VAL(val, DDICLK_FREQ, ddiclk_freq_mhz);
> > + UPDATE_PMDEMAND_VAL(val, SCALERS, scalers);
> > + /*
> > + * Active_PLLs starts with 1 because of CDCLK PLL.
> > + * TODO: Missing to account genlock filter when it gets used.
> > + */
> > + val |= XELPDP_PMDEMAND_PLLS(tmp + 1);
> > +
> > + intel_de_write(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
> > val);
> > +
> > +#undef UPDATE_PM_DEMAND_VAL
> > +
> > + intel_de_rmw(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
> > XELPDP_PMDEMAND_REQ_ENABLE);
> > +
> > + intel_pmdemand_wait(dev_priv);
> > +unlock:
> > + mutex_unlock(&dev_priv->pmdemand.lock);
> > +}
> > +
> > +void intel_pmdemand_pre_plane_update(struct intel_atomic_state
> > +*state) {
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + const struct intel_pmdemand_state *new_pmdmnd_state =
> > + intel_atomic_get_new_pmdemand_state(state);
> > + const struct intel_pmdemand_state *old_pmdmnd_state =
> > + intel_atomic_get_old_pmdemand_state(state);
> > +
> > + if (DISPLAY_VER(dev_priv) < 14)
> > + return;
> > +
> > + if (!new_pmdmnd_state ||
> > + memcmp(new_pmdmnd_state, old_pmdmnd_state,
> > sizeof(*new_pmdmnd_state)) == 0)
> > + return;
> > +
> > + intel_program_pmdemand(dev_priv, new_pmdmnd_state,
> > old_pmdmnd_state);
> > +}
> > +
> > +void intel_pmdemand_post_plane_update(struct intel_atomic_state
> > +*state) {
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + const struct intel_pmdemand_state *new_pmdmnd_state =
> > + intel_atomic_get_new_pmdemand_state(state);
> > + const struct intel_pmdemand_state *old_pmdmnd_state =
> > + intel_atomic_get_old_pmdemand_state(state);
> > +
> > + if (DISPLAY_VER(dev_priv) < 14)
> > + return;
> > +
> > + if (!new_pmdmnd_state ||
> > + memcmp(new_pmdmnd_state, old_pmdmnd_state,
> > sizeof(*new_pmdmnd_state)) == 0)
> > + return;
> > +
> > + intel_program_pmdemand(dev_priv, new_pmdmnd_state, NULL); }
> > +
> > static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
> > {
> > /*
> > diff --git a/drivers/gpu/drm/i915/intel_pm.h
> > b/drivers/gpu/drm/i915/intel_pm.h index c09b872d65c8..88e8fef6c10b
> > 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.h
> > +++ b/drivers/gpu/drm/i915/intel_pm.h
> > @@ -8,6 +8,8 @@
> >
> > #include <linux/types.h>
> >
> > +#include "display/intel_global_state.h"
> > +
> > struct drm_i915_private;
> > struct intel_crtc_state;
> > struct intel_plane_state;
> > @@ -15,6 +17,7 @@ struct intel_plane_state; void
> > intel_init_clock_gating(struct drm_i915_private *dev_priv); void
> > intel_suspend_hw(struct drm_i915_private *dev_priv); int
> > ilk_wm_max_level(const struct drm_i915_private *dev_priv);
> > +void intel_init_pmdemand(struct drm_i915_private *dev_priv);
> > void intel_init_pm(struct drm_i915_private *dev_priv); void
> > intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
> > void intel_pm_setup(struct drm_i915_private *dev_priv); @@ -31,4
> > +34,36 @@ void intel_print_wm_latency(struct drm_i915_private
> > *dev_priv,
> >
> > bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool
> > enable);
> >
> > +struct intel_pmdemand_state {
> > + struct intel_global_state base;
> > +
> > + u16 qclk_gv_bw;
> > + u8 voltage_index;
> > + u8 qclk_gv_index;
> > + u8 active_pipes;
> > + u8 dbufs;
> > + u8 active_phys_plls_mask;
> > + u16 cdclk_freq_mhz;
> > + u16 ddiclk_freq_mhz;
> > + u8 scalers;
> > +};
> > +
> > +int intel_pmdemand_init(struct drm_i915_private *dev_priv);
> > +
> > +struct intel_pmdemand_state *
> > +intel_atomic_get_pmdemand_state(struct intel_atomic_state *state);
> > +
> > +#define to_intel_pmdemand_state(x) container_of((x), struct
> > intel_pmdemand_state, base)
> > +#define intel_atomic_get_old_pmdemand_state(state) \
> > +
> > to_intel_pmdemand_state(intel_atomic_get_old_global_obj_state(stat
> > e, &to_i915(state->base.dev)->pmdemand.obj))
> > +#define intel_atomic_get_new_pmdemand_state(state) \
> > +
> > to_intel_pmdemand_state(intel_atomic_get_new_global_obj_state(sta
> > te, &to_i915(state->base.dev)->pmdemand.obj))
> > +
> > +int intel_pmdemand_init(struct drm_i915_private *dev_priv); void
> > +intel_program_dbuf_pmdemand(struct drm_i915_private *dev_priv,
> > + u8 dbuf_slices);
> > +void intel_pmdemand_pre_plane_update(struct intel_atomic_state
> > +*state); void intel_pmdemand_post_plane_update(struct
> > +intel_atomic_state *state); int intel_pmdemand_atomic_check(struct
> > +intel_atomic_state *state);
> > +
> > #endif /* __INTEL_PM_H__ */
> > --
> > 2.34.1
^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH 08/20] drm/i915/mtl: C20 PLL programming
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (6 preceding siblings ...)
2022-10-14 12:47 ` [Intel-gfx] [PATCH 07/20] drm/i915/mtl: Add support for PM DEMAND Mika Kahola
@ 2022-10-14 12:47 ` Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 09/20] drm/i915/mtl: C20 HW readout Mika Kahola
` (17 subsequent siblings)
25 siblings, 0 replies; 36+ messages in thread
From: Mika Kahola @ 2022-10-14 12:47 UTC (permalink / raw)
To: intel-gfx
C20 phy PLL programming sequence for DP, DP2.0, HDMI2.x non-FRL and
HDMI2.x FRL. This enables C20 MPLLA and MPLLB programming sequence. add
4 lane support for c20.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 279 +++++++++++++++---
.../gpu/drm/i915/display/intel_cx0_reg_defs.h | 30 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 11 +-
.../drm/i915/display/intel_display_types.h | 19 +-
drivers/gpu/drm/i915/display/intel_dp.c | 12 +-
5 files changed, 311 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index ef874986940d..02701f9418e6 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -14,6 +14,7 @@
#include "intel_panel.h"
#include "intel_psr.h"
#include "intel_uncore.h"
+#include "intel_tc.h"
bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy)
{
@@ -234,6 +235,18 @@ static void intel_cx0_write(struct drm_i915_private *i915, enum port port,
}
}
+static void intel_c20_write(struct drm_i915_private *i915, enum port port,
+ int lane, u16 addr, u16 data)
+{
+ assert_dc_off(i915);
+
+ intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_H, (addr >> 8) & 0xff, 0);
+ intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0);
+
+ intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_H, (data >> 8) & 0xff, 0);
+ intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff, 1);
+}
+
static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
int lane, u16 addr, u8 clear, u8 set, bool committed)
{
@@ -765,7 +778,7 @@ static int intel_c10mpllb_calc_state(struct intel_crtc_state *crtc_state,
for (i = 0; tables[i]; i++) {
if (crtc_state->port_clock <= tables[i]->clock) {
- crtc_state->c10mpllb_state = *tables[i];
+ crtc_state->cx0pll_state.c10mpllb_state = *tables[i];
return 0;
}
}
@@ -825,7 +838,7 @@ static void intel_c10_pll_program(struct drm_i915_private *i915,
const struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
- const struct intel_c10mpllb_state *pll_state = &crtc_state->c10mpllb_state;
+ const struct intel_c10mpllb_state *pll_state = &crtc_state->cx0pll_state.c10mpllb_state;
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
u8 master_lane = lane_reversal ? INTEL_CX0_LANE1 :
@@ -907,6 +920,218 @@ void intel_c10mpllb_dump_hw_state(struct drm_i915_private *dev_priv,
i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
}
+static bool intel_c20_use_mplla(u32 clock)
+{
+ /* 10G and 20G rates use MPLLA */
+ if (clock == 312500 || clock == 625000)
+ return true;
+
+ return false;
+}
+
+static u8 intel_c20_get_dp_rate(u32 clock)
+{
+ switch (clock) {
+ case 162000: /* 1.62 Gbps DP1.4 */
+ return 0;
+ case 270000: /* 2.7 Gbps DP1.4 */
+ return 1;
+ case 540000: /* 5.4 Gbps DP 1.4 */
+ return 2;
+ case 810000: /* 8.1 Gbps DP1.4 */
+ return 3;
+ case 216000: /* 2.16 Gbps eDP */
+ return 4;
+ case 243000: /* 2.43 Gbps eDP */
+ return 5;
+ case 324000: /* 3.24 Gbps eDP */
+ return 6;
+ case 432000: /* 4.32 Gbps eDP */
+ return 7;
+ case 312500: /* 10 Gbps DP2.0 */
+ return 8;
+ case 421875: /* 13.5 Gbps DP2.0 */
+ return 9;
+ case 625000: /* 20 Gbps DP2.0*/
+ return 10;
+ default:
+ MISSING_CASE(clock);
+ return 0;
+ }
+}
+
+static u8 intel_c20_get_hdmi_rate(u32 clock)
+{
+ switch (clock) {
+ case 25175:
+ case 27000:
+ case 74250:
+ case 148500:
+ case 594000:
+ return 0;
+ case 166670: /* 3 Gbps */
+ case 333330: /* 6 Gbps */
+ case 666670: /* 12 Gbps */
+ return 1;
+ case 444440: /* 8 Gbps */
+ return 2;
+ case 555560: /* 10 Gbps */
+ return 3;
+ default:
+ MISSING_CASE(clock);
+ return 0;
+ }
+}
+
+static bool is_dp2(u32 clock)
+{
+ /* DP2.0 clock rates */
+ if (clock == 312500 || clock == 421875 || clock == 625000)
+ return true;
+
+ return false;
+}
+
+static bool is_hdmi_frl(u32 clock)
+{
+ switch (clock) {
+ case 166670: /* 3 Gbps */
+ case 333330: /* 6 Gbps */
+ case 444440: /* 8 Gbps */
+ case 555560: /* 10 Gbps */
+ case 666670: /* 12 Gbps */
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder)
+{
+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
+
+ /* banks should not be cleared for DPALT/USB4/TBT modes */
+ /* TODO: optimize re-calibration in legacy mode */
+ return intel_tc_port_in_legacy_mode(intel_dig_port);
+}
+
+static void intel_c20_pll_program(struct drm_i915_private *i915,
+ const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
+{
+ const struct intel_c20pll_state *pll_state = &crtc_state->cx0pll_state.c20pll_state;
+ bool dp = false;
+ int lane_count = crtc_state->lane_count;
+ bool cntx;
+ int i;
+
+ if (intel_crtc_has_dp_encoder(crtc_state))
+ dp = true;
+
+ /* 1. Read current context selection */
+ cntx = intel_cx0_read(i915, encoder->port, 0, PHY_C20_VDR_CUSTOM_SERDES_RATE) &
+ PHY_C20_CONTEXT_TOGGLE;
+
+ /* 2. If there is a protocol switch from HDMI to DP or vice versa, clear
+ * the lane #0 MPLLB CAL_DONE_BANK DP2.0 10G and 20G rates enable MPLLA.
+ * Protocol switch is only applicable for MPLLA
+ */
+ if (intel_c20_protocol_switch_valid(encoder)) {
+ for (i = 0; i < 4; i++)
+ intel_c20_write(i915, encoder->port, 0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0);
+ }
+
+ /* 3. Write SRAM configuration context. If A in use, write configuration to B context */
+ /* 3.1 Tx configuration */
+ for (i = 0; i < 3; i++) {
+ if (cntx)
+ intel_c20_write(i915, encoder->port, 0, PHY_C20_A_TX_CNTX_CFG(i), pll_state->tx[i]);
+ else
+ intel_c20_write(i915, encoder->port, 0, PHY_C20_B_TX_CNTX_CFG(i), pll_state->tx[i]);
+ }
+
+ /* 3.2 common configuration */
+ for (i = 0; i < 4; i++) {
+ if (cntx)
+ intel_c20_write(i915, encoder->port, 0, PHY_C20_A_CMN_CNTX_CFG(i), pll_state->cmn[i]);
+ else
+ intel_c20_write(i915, encoder->port, 0, PHY_C20_B_CMN_CNTX_CFG(i), pll_state->cmn[i]);
+ }
+
+ /* 3.3 mpllb or mplla configuration */
+ if (intel_c20_use_mplla(pll_state->clock)) {
+ for (i = 0; i < 10; i++) {
+ if (cntx)
+ intel_c20_write(i915, encoder->port, 0,
+ PHY_C20_A_MPLLA_CNTX_CFG(i),
+ pll_state->mplla[i]);
+ else
+ intel_c20_write(i915, encoder->port, 0,
+ PHY_C20_B_MPLLA_CNTX_CFG(i),
+ pll_state->mplla[i]);
+ }
+ } else {
+ for (i = 0; i < 11; i++) {
+ if (cntx)
+ intel_c20_write(i915, encoder->port, 0,
+ PHY_C20_A_MPLLB_CNTX_CFG(i),
+ pll_state->mpllb[i]);
+ else
+ intel_c20_write(i915, encoder->port, 0,
+ PHY_C20_B_MPLLB_CNTX_CFG(i),
+ pll_state->mpllb[i]);
+ }
+ }
+
+ /* 4. Program custom width to match the link protocol */
+ if (dp) {
+ intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_WIDTH,
+ is_dp2(pll_state->clock) ? 2 : 0,
+ MB_WRITE_COMMITTED);
+ if (lane_count == 4)
+ intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE1, PHY_C20_VDR_CUSTOM_WIDTH,
+ is_dp2(pll_state->clock) ? 2 : 0,
+ MB_WRITE_COMMITTED);
+ } else if (is_hdmi_frl(pll_state->clock)) {
+ intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_WIDTH,
+ 1, MB_WRITE_COMMITTED);
+ if (lane_count == 4)
+ intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE1,
+ PHY_C20_VDR_CUSTOM_WIDTH, 1, MB_WRITE_COMMITTED);
+ } else
+ intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_CUSTOM_WIDTH,
+ 0, MB_WRITE_COMMITTED);
+
+ /* 5. For DP or 6. For HDMI */
+ if (dp) {
+ intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE,
+ BIT(6) | (intel_c20_get_dp_rate(pll_state->clock) << 1),
+ MB_WRITE_COMMITTED);
+ if (lane_count == 4)
+ intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE1, PHY_C20_VDR_CUSTOM_SERDES_RATE,
+ BIT(6) | (intel_c20_get_dp_rate(pll_state->clock) << 1),
+ MB_WRITE_COMMITTED);
+ } else {
+ intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_CUSTOM_SERDES_RATE,
+ ((is_hdmi_frl(pll_state->clock) ? 1 : 0) << 7),
+ MB_WRITE_COMMITTED);
+
+ intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
+ (intel_c20_get_hdmi_rate(pll_state->clock) << 0),
+ MB_WRITE_COMMITTED);
+ }
+
+ /*
+ * 7. Write Vendor specific registers to toggle context setting to load
+ * the updated programming toggle context bit
+ */
+ intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE,
+ cntx ? 0 : 1, MB_WRITE_COMMITTED);
+ if (lane_count == 4)
+ intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE1, PHY_C20_VDR_CUSTOM_SERDES_RATE,
+ cntx ? 0 : 1, MB_WRITE_COMMITTED);
+}
+
int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
const struct intel_c10mpllb_state *pll_state)
{
@@ -945,7 +1170,11 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
val |= XELPDP_LANE1_PHY_CLOCK_SELECT;
val |= XELPDP_FORWARD_CLOCK_UNGATE;
- val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
+
+ if (is_hdmi_frl(crtc_state->port_clock))
+ val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
+ else
+ val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
if (intel_crtc_has_dp_encoder(crtc_state)) {
intel_dp = enc_to_intel_dp(encoder);
@@ -1175,8 +1404,8 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane)
XELPDP_LANE1_PCLK_REFCLK_REQUEST;
}
-static void intel_c10pll_enable(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
+void intel_cx0pll_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
@@ -1184,6 +1413,7 @@ static void intel_c10pll_enable(struct intel_encoder *encoder,
bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 :
INTEL_CX0_LANE0;
+ intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);
/*
* 1. Program PORT_CLOCK_CTL REGISTER to configure
@@ -1202,7 +1432,10 @@ static void intel_c10pll_enable(struct intel_encoder *encoder,
CX0_P2_STATE_READY);
/* 4. Program PHY internal PLL internal registers. */
- intel_c10_pll_program(i915, crtc_state, encoder);
+ if (intel_is_c10phy(i915, phy))
+ intel_c10_pll_program(i915, crtc_state, encoder);
+ else
+ intel_c20_pll_program(i915, crtc_state, encoder);
/*
* 5. Program the enabled and disabled owned PHY lane
@@ -1241,31 +1474,21 @@ static void intel_c10pll_enable(struct intel_encoder *encoder,
* 10. Follow the Display Voltage Frequency Switching Sequence After
* Frequency Change. We handle this step in bxt_set_cdclk().
*/
-}
-
-void intel_cx0pll_enable(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
-{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- enum phy phy = intel_port_to_phy(i915, encoder->port);
- intel_wakeref_t wakeref;
-
- wakeref = intel_cx0_phy_transaction_begin(encoder);
-
- drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
- intel_c10pll_enable(encoder, crtc_state);
intel_cx0_phy_transaction_end(encoder, wakeref);
}
-static void intel_c10pll_disable(struct intel_encoder *encoder)
+void intel_cx0pll_disable(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
+ bool is_c10 = intel_is_c10phy(i915, phy);
+ intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);
/* 1. Change owned PHY lane power to Disable state. */
intel_cx0_powerdown_change_sequence(i915, encoder->port, INTEL_CX0_BOTH_LANES,
- CX0_P2PG_STATE_DISABLE);
+ is_c10 ? CX0_P2PG_STATE_DISABLE :
+ CX0_P4PG_STATE_DISABLE);
/*
* 2. Follow the Display Voltage Frequency Switching Sequence Before
@@ -1303,18 +1526,6 @@ static void intel_c10pll_disable(struct intel_encoder *encoder)
XELPDP_DDI_CLOCK_SELECT_MASK, 0);
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
XELPDP_FORWARD_CLOCK_UNGATE, 0);
-}
-
-void intel_cx0pll_disable(struct intel_encoder *encoder)
-{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- enum phy phy = intel_port_to_phy(i915, encoder->port);
- intel_wakeref_t wakeref;
-
- wakeref = intel_cx0_phy_transaction_begin(encoder);
-
- drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
- intel_c10pll_disable(encoder);
intel_cx0_phy_transaction_end(encoder, wakeref);
}
@@ -1324,7 +1535,7 @@ void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_c10mpllb_state mpllb_hw_state = { 0 };
- struct intel_c10mpllb_state *mpllb_sw_state = &new_crtc_state->c10mpllb_state;
+ struct intel_c10mpllb_state *mpllb_sw_state = &new_crtc_state->cx0pll_state.c10mpllb_state;
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct intel_encoder *encoder;
struct intel_dp *intel_dp;
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
index fad6308bbf77..b3912d15a823 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
@@ -170,4 +170,34 @@
#define C10_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(1, 0)
#define C10_PHY_VSWING_PREEMPH(val) REG_FIELD_PREP8(C10_PHY_VSWING_PREEMPH_MASK, val)
+/* C20 Registers */
+#define PHY_C20_WR_ADDRESS_L 0xC02
+#define PHY_C20_WR_ADDRESS_H 0xC03
+#define PHY_C20_WR_DATA_L 0xC04
+#define PHY_C20_WR_DATA_H 0xC05
+#define PHY_C20_RD_ADDRESS_L 0xC06
+#define PHY_C20_RD_ADDRESS_H 0xC07
+#define PHY_C20_RD_DATA_L 0xC08
+#define PHY_C20_RD_DATA_H 0xC09
+#define PHY_C20_VDR_CUSTOM_SERDES_RATE 0xD00
+#define PHY_C20_VDR_HDMI_RATE 0xD01
+#define PHY_C20_CONTEXT_TOGGLE REG_BIT8(0)
+#define PHY_C20_VDR_CUSTOM_WIDTH 0xD02
+#define PHY_C20_A_TX_CNTX_CFG(idx) (0xCF2E - (idx))
+#define PHY_C20_B_TX_CNTX_CFG(idx) (0xCF2A - (idx))
+#define PHY_C20_A_CMN_CNTX_CFG(idx) (0xCDAA - (idx))
+#define PHY_C20_B_CMN_CNTX_CFG(idx) (0xCDA5 - (idx))
+#define PHY_C20_A_MPLLA_CNTX_CFG(idx) (0xCCF0 - (idx))
+#define PHY_C20_B_MPLLA_CNTX_CFG(idx) (0xCCE5 - (idx))
+#define PHY_C20_A_MPLLB_CNTX_CFG(idx) (0xCB5A - (idx))
+#define PHY_C20_B_MPLLB_CNTX_CFG(idx) (0xCB4E - (idx))
+
+#define C20_MPLLB_FRACEN REG_BIT(13)
+#define C20_MPLLA_FRACEN REG_BIT(14)
+#define C20_MULTIPLIER_MASK REG_GENMASK(11, 0)
+#define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13)
+#define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8)
+
+#define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx) (0x303D + (idx))
+
#endif /* __INTEL_CX0_REG_DEFS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1380ed2221ad..7d57cbf7e686 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3038,6 +3038,11 @@ intel_ddi_update_prepare(struct intel_atomic_state *state,
intel_tc_port_get_link(enc_to_dig_port(encoder),
required_lanes);
+
+ /* FIXME: Add MTL pll_mgr */
+ if (DISPLAY_VER(i915) >= 14)
+ return;
+
if (crtc_state && crtc_state->hw.active) {
struct intel_crtc *slave_crtc;
@@ -3496,9 +3501,9 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder,
drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
- intel_c10mpllb_readout_hw_state(encoder, &crtc_state->c10mpllb_state);
- intel_c10mpllb_dump_hw_state(i915, &crtc_state->c10mpllb_state);
- crtc_state->port_clock = intel_c10mpllb_calc_port_clock(encoder, &crtc_state->c10mpllb_state);
+ intel_c10mpllb_readout_hw_state(encoder, &crtc_state->cx0pll_state.c10mpllb_state);
+ intel_c10mpllb_dump_hw_state(i915, &crtc_state->cx0pll_state.c10mpllb_state);
+ crtc_state->port_clock = intel_c10mpllb_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10mpllb_state);
intel_ddi_get_config(encoder, crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index be6ff6cdfb0b..641aa546c25f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -974,6 +974,23 @@ struct intel_c10mpllb_state {
u8 pll[20];
};
+struct intel_c20pll_state {
+ u32 clock; /* in kHz */
+ u16 tx[3];
+ u16 cmn[4];
+ union {
+ u16 mplla[10];
+ u16 mpllb[11];
+ };
+};
+
+struct intel_cx0pll_state {
+ union {
+ struct intel_c10mpllb_state c10mpllb_state;
+ struct intel_c20pll_state c20pll_state;
+ };
+};
+
struct intel_crtc_state {
/*
* uapi (drm) state. This is the software state shown to userspace.
@@ -1113,7 +1130,7 @@ struct intel_crtc_state {
union {
struct intel_dpll_hw_state dpll_hw_state;
struct intel_mpllb_state mpllb_state;
- struct intel_c10mpllb_state c10mpllb_state;
+ struct intel_cx0pll_state cx0pll_state;
};
/*
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0c96444776c4..adaf0ee6cf27 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -52,6 +52,7 @@
#include "intel_combo_phy_regs.h"
#include "intel_connector.h"
#include "intel_crtc.h"
+#include "intel_cx0_phy.h"
#include "intel_ddi.h"
#include "intel_de.h"
#include "intel_display_types.h"
@@ -422,7 +423,14 @@ static int ehl_max_source_rate(struct intel_dp *intel_dp)
static int mtl_max_source_rate(struct intel_dp *intel_dp)
{
- return intel_dp_is_edp(intel_dp) ? 675000 : 810000;
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
+
+ if (intel_is_c10phy(i915, phy))
+ return intel_dp_is_edp(intel_dp) ? 675000 : 810000;
+
+ return 2000000;
}
static int vbt_max_link_rate(struct intel_dp *intel_dp)
@@ -451,7 +459,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
/* The values must be in increasing order */
static const int mtl_rates[] = {
162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
- 810000,
+ 810000, 1000000, 1350000, 2000000,
};
static const int icl_rates[] = {
162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 09/20] drm/i915/mtl: C20 HW readout
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (7 preceding siblings ...)
2022-10-14 12:47 ` [Intel-gfx] [PATCH 08/20] drm/i915/mtl: C20 PLL programming Mika Kahola
@ 2022-10-14 12:47 ` Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 10/20] drm/i915/mtl: C20 port clock calculation Mika Kahola
` (16 subsequent siblings)
25 siblings, 0 replies; 36+ messages in thread
From: Mika Kahola @ 2022-10-14 12:47 UTC (permalink / raw)
To: intel-gfx
Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
The PLL settings are based on table, not for algorithmic alternative.
For DP 1.4 only MPLLB is in use.
Once register settings are done, we read back C20 HW state.
BSpec: 64568
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 495 ++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 10 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 9 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +-
drivers/gpu/drm/i915/display/intel_hdmi.h | 1 +
5 files changed, 513 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 02701f9418e6..dcd74042c001 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -11,6 +11,7 @@
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_dp.h"
+#include "intel_hdmi.h"
#include "intel_panel.h"
#include "intel_psr.h"
#include "intel_uncore.h"
@@ -247,6 +248,23 @@ static void intel_c20_write(struct drm_i915_private *i915, enum port port,
intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff, 1);
}
+static u16 intel_c20_read(struct drm_i915_private *i915, enum port port,
+ int lane, u16 addr)
+{
+ u16 val;
+
+ assert_dc_off(i915);
+
+ intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 0);
+ intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_H, (addr >> 8) & 0xff, 1);
+
+ val = intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_H);
+ val <<= 8;
+ val |= intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_L);
+
+ return val;
+}
+
static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
int lane, u16 addr, u8 clear, u8 set, bool committed)
{
@@ -592,6 +610,192 @@ static const struct intel_c10mpllb_state * const mtl_c10_edp_tables[] = {
NULL,
};
+/* C20 basic DP 1.4 tables */
+static const struct intel_c20pll_state mtl_c20_dp_rbr = {
+ .clock = 162000,
+ .tx = { 0xbe88, /* tx cfg0 */
+ 0x5800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = {0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mpllb = { 0x50a8, /* mpllb cfg0 */
+ 0x2120, /* mpllb cfg1 */
+ 0xcd9a, /* mpllb cfg2 */
+ 0xbfc1, /* mpllb cfg3 */
+ 0x6c00, /* mpllb cfg4 */
+ 0x5ab8, /* mpllb cfg5 */
+ 0x2000, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x6000, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0000, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
+ .clock = 270000,
+ .tx = { 0xbe88, /* tx cfg0 */
+ 0x4800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = {0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mpllb = { 0x308c, /* mpllb cfg0 */
+ 0x2110, /* mpllb cfg1 */
+ 0xcc9c, /* mpllb cfg2 */
+ 0xbfc1, /* mpllb cfg3 */
+ 0x5a00, /* mpllb cfg4 */
+ 0x4b9a, /* mpllb cfg5 */
+ 0x2000, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x5000, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0000, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
+ .clock = 540000,
+ .tx = { 0xbe88, /* tx cfg0 */
+ 0x4800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = {0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mpllb = { 0x108c, /* mpllb cfg0 */
+ 0x2108, /* mpllb cfg1 */
+ 0xcc9c, /* mpllb cfg2 */
+ 0xbfc1, /* mpllb cfg3 */
+ 0x5a00, /* mpllb cfg4 */
+ 0x4b9a, /* mpllb cfg5 */
+ 0x2000, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x5000, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0000, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
+ .clock = 810000,
+ .tx = { 0xbe88, /* tx cfg0 */
+ 0x4800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = {0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mpllb = { 0x10d2, /* mpllb cfg0 */
+ 0x2108, /* mpllb cfg1 */
+ 0x8d98, /* mpllb cfg2 */
+ 0xbfc1, /* mpllb cfg3 */
+ 0x8700, /* mpllb cfg4 */
+ 0x7166, /* mpllb cfg5 */
+ 0x2000, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x7800, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0000, /* mpllb cfg10 */
+ },
+};
+
+/* C20 basic DP 2.0 tables */
+static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
+ .clock = 312500,
+ .tx = { 0xbe21, /* tx cfg0 */
+ 0x4800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = {0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mplla = { 0x3104, /* mplla cfg0 */
+ 0xd105, /* mplla cfg1 */
+ 0xc025, /* mplla cfg2 */
+ 0xc025, /* mplla cfg3 */
+ 0xa6ab, /* mplla cfg4 */
+ 0x8c00, /* mplla cfg5 */
+ 0x4000, /* mplla cfg6 */
+ 0x0003, /* mplla cfg7 */
+ 0x3555, /* mplla cfg8 */
+ 0x0001, /* mplla cfg9 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
+ .clock = 421875,
+ .tx = { 0xbea0, /* tx cfg0 */
+ 0x4800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = {0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mpllb = { 0x015f, /* mpllb cfg0 */
+ 0x2205, /* mpllb cfg1 */
+ 0x1b17, /* mpllb cfg2 */
+ 0xffc1, /* mpllb cfg3 */
+ 0xe100, /* mpllb cfg4 */
+ 0xbd00, /* mpllb cfg5 */
+ 0x2000, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x4800, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0000, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
+ .clock = 625000,
+ .tx = { 0xbe20, /* tx cfg0 */
+ 0x4800, /* tx cfg1 */
+ 0x0000, /* tx cfg2 */
+ },
+ .cmn = {0x0500, /* cmn cfg0*/
+ 0x0005, /* cmn cfg1 */
+ 0x0000, /* cmn cfg2 */
+ 0x0000, /* cmn cfg3 */
+ },
+ .mplla = { 0x3104, /* mplla cfg0 */
+ 0xd105, /* mplla cfg1 */
+ 0xc025, /* mplla cfg2 */
+ 0xc025, /* mplla cfg3 */
+ 0xa6ab, /* mplla cfg4 */
+ 0x8c00, /* mplla cfg5 */
+ 0x4000, /* mplla cfg6 */
+ 0x0003, /* mplla cfg7 */
+ 0x3555, /* mplla cfg8 */
+ 0x0001, /* mplla cfg9 */
+ },
+};
+
+static const struct intel_c20pll_state * const mtl_c20_dp_tables[] = {
+ &mtl_c20_dp_rbr,
+ &mtl_c20_dp_hbr1,
+ &mtl_c20_dp_hbr2,
+ &mtl_c20_dp_hbr3,
+ &mtl_c20_dp_uhbr10,
+ &mtl_c20_dp_uhbr13_5,
+ &mtl_c20_dp_uhbr20,
+ NULL,
+};
+
/*
* HDMI link rates with 38.4 MHz reference clock.
*/
@@ -725,7 +929,181 @@ static const struct intel_c10mpllb_state * const mtl_c10_hdmi_tables[] = {
NULL,
};
-int intel_c10_phy_check_hdmi_link_rate(int clock)
+static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
+ .clock = 25175,
+ .mpllb = { 0xa0d2, /* mpllb cfg0 */
+ 0x7d80, /* mpllb cfg1 */
+ 0x0906, /* mpllb cfg2 */
+ 0xbe40, /* mpllb cfg3 */
+ 0x0000, /* mpllb cfg4 */
+ 0x0000, /* mpllb cfg5 */
+ 0x0200, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x0000, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0001, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
+ .clock = 27000,
+ .mpllb = { 0xa0e0, /* mpllb cfg0 */
+ 0x7d80, /* mpllb cfg1 */
+ 0x0906, /* mpllb cfg2 */
+ 0xbe40, /* mpllb cfg3 */
+ 0x0000, /* mpllb cfg4 */
+ 0x0000, /* mpllb cfg5 */
+ 0x2200, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x8000, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0001, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
+ .clock = 74250,
+ .mpllb = { 0x609a, /* mpllb cfg0 */
+ 0x7d40, /* mpllb cfg1 */
+ 0xca06, /* mpllb cfg2 */
+ 0xbe40, /* mpllb cfg3 */
+ 0x0000, /* mpllb cfg4 */
+ 0x0000, /* mpllb cfg5 */
+ 0x2200, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x5800, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0001, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
+ .clock = 148500,
+ .mpllb = { 0x409a, /* mpllb cfg0 */
+ 0x7d20, /* mpllb cfg1 */
+ 0xca06, /* mpllb cfg2 */
+ 0xbe40, /* mpllb cfg3 */
+ 0x0000, /* mpllb cfg4 */
+ 0x0000, /* mpllb cfg5 */
+ 0x2200, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x5800, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0001, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
+ .clock = 594000,
+ .mpllb = { 0x009a, /* mpllb cfg0 */
+ 0x7d08, /* mpllb cfg1 */
+ 0xca06, /* mpllb cfg2 */
+ 0xbe40, /* mpllb cfg3 */
+ 0x0000, /* mpllb cfg4 */
+ 0x0000, /* mpllb cfg5 */
+ 0x2200, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x5800, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0001, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
+ .clock = 166670,
+ .mpllb = { 0x209c, /* mpllb cfg0 */
+ 0x7d10, /* mpllb cfg1 */
+ 0xca06, /* mpllb cfg2 */
+ 0xbe40, /* mpllb cfg3 */
+ 0x0000, /* mpllb cfg4 */
+ 0x0000, /* mpllb cfg5 */
+ 0x2200, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x2000, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0004, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
+ .clock = 333330,
+ .mpllb = { 0x009c, /* mpllb cfg0 */
+ 0x7d08, /* mpllb cfg1 */
+ 0xca06, /* mpllb cfg2 */
+ 0xbe40, /* mpllb cfg3 */
+ 0x0000, /* mpllb cfg4 */
+ 0x0000, /* mpllb cfg5 */
+ 0x2200, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x2000, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0004, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
+ .clock = 444440,
+ .mpllb = { 0x00d0, /* mpllb cfg0 */
+ 0x7d08, /* mpllb cfg1 */
+ 0x4a06, /* mpllb cfg2 */
+ 0xbe40, /* mpllb cfg3 */
+ 0x0000, /* mpllb cfg4 */
+ 0x0000, /* mpllb cfg5 */
+ 0x2200, /* mpllb cfg6 */
+ 0x0003, /* mpllb cfg7 */
+ 0x2aaa, /* mpllb cfg8 */
+ 0x0002, /* mpllb cfg9 */
+ 0x0004, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
+ .clock = 555560,
+ .mpllb = { 0x1104, /* mpllb cfg0 */
+ 0x7d08, /* mpllb cfg1 */
+ 0x0a06, /* mpllb cfg2 */
+ 0xbe40, /* mpllb cfg3 */
+ 0x0000, /* mpllb cfg4 */
+ 0x0000, /* mpllb cfg5 */
+ 0x2200, /* mpllb cfg6 */
+ 0x0003, /* mpllb cfg7 */
+ 0x3555, /* mpllb cfg8 */
+ 0x0001, /* mpllb cfg9 */
+ 0x0004, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
+ .clock = 666670,
+ .mpllb = { 0x0138, /* mpllb cfg0 */
+ 0x7d08, /* mpllb cfg1 */
+ 0x5486, /* mpllb cfg2 */
+ 0xfe40, /* mpllb cfg3 */
+ 0x0000, /* mpllb cfg4 */
+ 0x0000, /* mpllb cfg5 */
+ 0x2200, /* mpllb cfg6 */
+ 0x0001, /* mpllb cfg7 */
+ 0x4000, /* mpllb cfg8 */
+ 0x0000, /* mpllb cfg9 */
+ 0x0004, /* mpllb cfg10 */
+ },
+};
+
+static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = {
+ &mtl_c20_hdmi_25_175,
+ &mtl_c20_hdmi_27_0,
+ &mtl_c20_hdmi_74_25,
+ &mtl_c20_hdmi_148_5,
+ &mtl_c20_hdmi_594,
+ &mtl_c20_hdmi_300,
+ &mtl_c20_hdmi_600,
+ &mtl_c20_hdmi_800,
+ &mtl_c20_hdmi_1000,
+ &mtl_c20_hdmi_1200,
+ NULL,
+};
+
+static int intel_c10_phy_check_hdmi_link_rate(int clock)
{
const struct intel_c10mpllb_state * const *tables = mtl_c10_hdmi_tables;
int i;
@@ -738,6 +1116,17 @@ int intel_c10_phy_check_hdmi_link_rate(int clock)
return MODE_CLOCK_RANGE;
}
+int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock)
+{
+ struct intel_digital_port *dig_port = hdmi_to_dig_port(hdmi);
+ struct drm_i915_private *i915 = intel_hdmi_to_i915(hdmi);
+ enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
+
+ if (intel_is_c10phy(i915, phy))
+ return intel_c10_phy_check_hdmi_link_rate(clock);
+ return intel_c20_phy_check_hdmi_link_rate(clock);
+}
+
static const struct intel_c10mpllb_state * const *
intel_c10_mpllb_tables_get(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
@@ -920,6 +1309,53 @@ void intel_c10mpllb_dump_hw_state(struct drm_i915_private *dev_priv,
i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
}
+int intel_c20_phy_check_hdmi_link_rate(int clock)
+{
+ const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables;
+ int i;
+
+ for (i = 0; tables[i]; i++) {
+ if (clock == tables[i]->clock)
+ return MODE_OK;
+ }
+
+ return MODE_CLOCK_RANGE;
+}
+
+static const struct intel_c20pll_state * const *
+intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
+{
+ if (intel_crtc_has_dp_encoder(crtc_state)) {
+ return mtl_c20_dp_tables;
+ } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+ return mtl_c20_hdmi_tables;
+ }
+
+ MISSING_CASE(encoder->type);
+ return NULL;
+}
+
+int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
+{
+ const struct intel_c20pll_state * const *tables;
+ int i;
+
+ tables = intel_c20_pll_tables_get(crtc_state, encoder);
+ if (!tables)
+ return -EINVAL;
+
+ for (i = 0; tables[i]; i++) {
+ if (crtc_state->port_clock <= tables[i]->clock) {
+ crtc_state->cx0pll_state.c20pll_state = *tables[i];
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
static bool intel_c20_use_mplla(u32 clock)
{
/* 10G and 20G rates use MPLLA */
@@ -929,6 +1365,63 @@ static bool intel_c20_use_mplla(u32 clock)
return false;
}
+void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
+ struct intel_c20pll_state *pll_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ bool cntx, use_mplla;
+ u32 val;
+ int i;
+
+ /* 1. Read current context selection */
+ cntx = intel_cx0_read(i915, encoder->port, 0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;
+
+ /* Read Tx configuration */
+ for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
+ if (cntx)
+ pll_state->tx[i] = intel_c20_read(i915, encoder->port, 0,
+ PHY_C20_B_TX_CNTX_CFG(i));
+ else
+ pll_state->tx[i] = intel_c20_read(i915, encoder->port, 0,
+ PHY_C20_A_TX_CNTX_CFG(i));
+ }
+
+ /* Read common configuration */
+ for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
+ if (cntx)
+ pll_state->cmn[i] = intel_c20_read(i915, encoder->port, 0,
+ PHY_C20_B_CMN_CNTX_CFG(i));
+ else
+ pll_state->cmn[i] = intel_c20_read(i915, encoder->port, 0,
+ PHY_C20_A_CMN_CNTX_CFG(i));
+ }
+
+ val = intel_c20_read(i915, encoder->port, 0, PHY_C20_A_MPLLA_CNTX_CFG(6));
+ use_mplla = val & C20_MPLLB_FRACEN;
+
+ if (use_mplla) {
+ /* MPLLA configuration */
+ for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
+ if (cntx)
+ pll_state->mplla[i] = intel_c20_read(i915, encoder->port, 0,
+ PHY_C20_B_MPLLA_CNTX_CFG(i));
+ else
+ pll_state->mplla[i] = intel_c20_read(i915, encoder->port, 0,
+ PHY_C20_A_MPLLA_CNTX_CFG(i));
+ }
+ } else {
+ /* MPLLB configuration */
+ for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
+ if (cntx)
+ pll_state->mpllb[i] = intel_c20_read(i915, encoder->port, 0,
+ PHY_C20_B_MPLLB_CNTX_CFG(i));
+ else
+ pll_state->mpllb[i] = intel_c20_read(i915, encoder->port, 0,
+ PHY_C20_A_MPLLB_CNTX_CFG(i));
+ }
+ }
+}
+
static u8 intel_c20_get_dp_rate(u32 clock)
{
switch (clock) {
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 952c7deeffaa..86edbc4b1718 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -33,14 +33,22 @@ void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
struct intel_c10mpllb_state *pll_state);
int intel_cx0mpllb_calc_state(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder);
+int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder);
+void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
+ struct intel_c20pll_state *pll_state);
void intel_c10mpllb_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_c10mpllb_state *hw_state);
int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
const struct intel_c10mpllb_state *pll_state);
void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
struct intel_crtc_state *new_crtc_state);
-int intel_c10_phy_check_hdmi_link_rate(int clock);
+int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
+int intel_c20_phy_check_hdmi_link_rate(int clock);
+void intel_cx0_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ u32 level);
#endif /* __INTEL_CX0_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 7d57cbf7e686..d6a03ae19dc2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3499,10 +3499,13 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder,
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
- drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
+ if (intel_is_c10phy(i915, phy)) {
+ intel_c10mpllb_readout_hw_state(encoder, &crtc_state->cx0pll_state.c10mpllb_state);
+ intel_c10mpllb_dump_hw_state(i915, &crtc_state->cx0pll_state.c10mpllb_state);
+ } else {
+ intel_c20pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c20pll_state);
+ }
- intel_c10mpllb_readout_hw_state(encoder, &crtc_state->cx0pll_state.c10mpllb_state);
- intel_c10mpllb_dump_hw_state(i915, &crtc_state->cx0pll_state.c10mpllb_state);
crtc_state->port_clock = intel_c10mpllb_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10mpllb_state);
intel_ddi_get_config(encoder, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index c274098f2196..c31b947d8042 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -57,7 +57,7 @@
#include "intel_panel.h"
#include "intel_snps_phy.h"
-static struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi)
+inline struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi)
{
return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev);
}
@@ -1876,8 +1876,8 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
* FIXME: We will hopefully get an algorithmic way of programming
* the MPLLB for HDMI in the future.
*/
- if (IS_METEORLAKE(dev_priv))
- return intel_c10_phy_check_hdmi_link_rate(clock);
+ if (DISPLAY_VER(dev_priv) >= 14)
+ return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock);
else if (IS_DG2(dev_priv))
return intel_snps_phy_check_hdmi_link_rate(clock);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index 93f65a917c36..0bb1201bab04 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -54,5 +54,6 @@ int intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
int src_max_slices, int src_max_slice_width,
int hdmi_max_slices, int hdmi_throughput);
int intel_hdmi_dsc_get_slice_height(int vactive);
+struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi);
#endif /* __INTEL_HDMI_H__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 10/20] drm/i915/mtl: C20 port clock calculation
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (8 preceding siblings ...)
2022-10-14 12:47 ` [Intel-gfx] [PATCH 09/20] drm/i915/mtl: C20 HW readout Mika Kahola
@ 2022-10-14 12:47 ` Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 11/20] drm/i915/mtl: C20 HDMI state calculations Mika Kahola
` (15 subsequent siblings)
25 siblings, 0 replies; 36+ messages in thread
From: Mika Kahola @ 2022-10-14 12:47 UTC (permalink / raw)
To: intel-gfx
Calculate port clock with C20 phy.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 32 ++++++++++++++++++--
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +--
3 files changed, 33 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index dcd74042c001..3c0c6bf190d6 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -1181,9 +1181,10 @@ int intel_cx0mpllb_calc_state(struct intel_crtc_state *crtc_state,
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
- drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
-
- return intel_c10mpllb_calc_state(crtc_state, encoder);
+ if (intel_is_c10phy(i915, phy))
+ return intel_c10mpllb_calc_state(crtc_state, encoder);
+ else
+ return intel_c20pll_calc_state(crtc_state, encoder);
}
void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
@@ -1647,6 +1648,31 @@ int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
10 << (tx_clk_div + 16));
}
+int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
+ const struct intel_c20pll_state *pll_state)
+{
+ unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
+ unsigned int multiplier, tx_clk_div, refclk = 38400;
+
+ if (pll_state->mpllb[6] & C20_MPLLB_FRACEN) {
+ frac_quot = pll_state->mpllb[8];
+ frac_rem = pll_state->mpllb[9];
+ frac_den = pll_state->mpllb[7];
+ multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]);
+ tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]);
+ } else if (pll_state->mplla[6] & C20_MPLLA_FRACEN) {
+ frac_quot = pll_state->mplla[8];
+ frac_rem = pll_state->mplla[9];
+ frac_den = pll_state->mplla[7];
+ multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]);
+ tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]);
+ }
+
+ return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
+ DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
+ 10 << (tx_clk_div + 16));
+}
+
static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
bool lane_reversal)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 86edbc4b1718..8ca77dfea24b 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -43,6 +43,8 @@ int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
const struct intel_c10mpllb_state *pll_state);
void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
struct intel_crtc_state *new_crtc_state);
+int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
+ const struct intel_c20pll_state *pll_state);
int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d6a03ae19dc2..bdf38905276e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3502,12 +3502,12 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder,
if (intel_is_c10phy(i915, phy)) {
intel_c10mpllb_readout_hw_state(encoder, &crtc_state->cx0pll_state.c10mpllb_state);
intel_c10mpllb_dump_hw_state(i915, &crtc_state->cx0pll_state.c10mpllb_state);
+ crtc_state->port_clock = intel_c10mpllb_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10mpllb_state);
} else {
intel_c20pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c20pll_state);
+ crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20pll_state);
}
- crtc_state->port_clock = intel_c10mpllb_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10mpllb_state);
-
intel_ddi_get_config(encoder, crtc_state);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 11/20] drm/i915/mtl: C20 HDMI state calculations
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (9 preceding siblings ...)
2022-10-14 12:47 ` [Intel-gfx] [PATCH 10/20] drm/i915/mtl: C20 port clock calculation Mika Kahola
@ 2022-10-14 12:47 ` Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 12/20] drm/i915/mtl: Add voltage swing sequence for C20 Mika Kahola
` (14 subsequent siblings)
25 siblings, 0 replies; 36+ messages in thread
From: Mika Kahola @ 2022-10-14 12:47 UTC (permalink / raw)
To: intel-gfx
Add C20 HDMI state calculations and put HDMI table definitions
in use.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 3c0c6bf190d6..088f59c26dde 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -1340,9 +1340,19 @@ intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
const struct intel_c20pll_state * const *tables;
int i;
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+ if (intel_c20_phy_check_hdmi_link_rate(crtc_state->port_clock) != MODE_OK) {
+ drm_dbg_kms(&i915->drm, "Can't support HDMI link rate %d on phy %c.\n",
+ crtc_state->port_clock, phy_name(phy));
+ return -EINVAL;
+ }
+ }
+
tables = intel_c20_pll_tables_get(crtc_state, encoder);
if (!tables)
return -EINVAL;
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 12/20] drm/i915/mtl: Add voltage swing sequence for C20
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (10 preceding siblings ...)
2022-10-14 12:47 ` [Intel-gfx] [PATCH 11/20] drm/i915/mtl: C20 HDMI state calculations Mika Kahola
@ 2022-10-14 12:47 ` Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 13/20] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA Mika Kahola
` (13 subsequent siblings)
25 siblings, 0 replies; 36+ messages in thread
From: Mika Kahola @ 2022-10-14 12:47 UTC (permalink / raw)
To: intel-gfx
DP1.4 and DP20 voltage swing sequence for C20 phy.
Bspec: 65449, 67636, 67610
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 31 ++++++++++++-----
.../gpu/drm/i915/display/intel_cx0_reg_defs.h | 4 +++
.../drm/i915/display/intel_ddi_buf_trans.c | 33 +++++++++++++++++--
3 files changed, 58 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 088f59c26dde..aab606520a62 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -340,14 +340,29 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
lane = ln / 2;
tx = ln % 2 + 1;
- intel_cx0_rmw(i915, encoder->port, lane, PHY_CX0_TX_CONTROL(tx, 2),
- C10_PHY_VSWING_PREEMPH_MASK,
- C10_PHY_VSWING_PREEMPH(trans->entries[level].direct.preemph),
- MB_WRITE_COMMITTED);
- intel_cx0_rmw(i915, encoder->port, lane, PHY_CX0_TX_CONTROL(tx, 8),
- C10_PHY_VSWING_LEVEL_MASK,
- C10_PHY_VSWING_LEVEL(trans->entries[level].direct.level),
- MB_WRITE_COMMITTED);
+ if (crtc_state->port_clock > 1000000) {
+ intel_cx0_rmw(i915, encoder->port, lane, PHY_CX0_TX_CONTROL(tx, 2),
+ C20_PHY_VSWING_PREEMPH_MASK,
+ C20_PHY_VSWING_PREEMPH(trans->entries[level].snps.pre_cursor),
+ MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, encoder->port, lane, PHY_CX0_TX_CONTROL(tx, 3),
+ C20_PHY_VSWING_PREEMPH_MASK,
+ C20_PHY_VSWING_PREEMPH(trans->entries[level].snps.vswing),
+ MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, encoder->port, lane, PHY_CX0_TX_CONTROL(tx, 4),
+ C20_PHY_VSWING_PREEMPH_MASK,
+ C20_PHY_VSWING_PREEMPH(trans->entries[level].snps.post_cursor),
+ MB_WRITE_COMMITTED);
+ } else {
+ intel_cx0_rmw(i915, encoder->port, lane, PHY_CX0_TX_CONTROL(tx, 2),
+ C10_PHY_VSWING_PREEMPH_MASK,
+ C10_PHY_VSWING_PREEMPH(trans->entries[level].direct.preemph),
+ MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, encoder->port, lane, PHY_CX0_TX_CONTROL(tx, 8),
+ C10_PHY_VSWING_LEVEL_MASK,
+ C10_PHY_VSWING_LEVEL(trans->entries[level].direct.level),
+ MB_WRITE_COMMITTED);
+ }
}
intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CONTROL(1),
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
index b3912d15a823..de5bce5037dd 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h
@@ -198,6 +198,10 @@
#define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13)
#define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8)
+/* C20 Phy VSwing Masks */
+#define C20_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(5, 0)
+#define C20_PHY_VSWING_PREEMPH(val) REG_FIELD_PREP8(C20_PHY_VSWING_PREEMPH_MASK, val)
+
#define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx) (0x303D + (idx))
#endif /* __INTEL_CX0_REG_DEFS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 49f8a0a6593b..916b5dc28abe 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -9,6 +9,7 @@
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_dp.h"
+#include "intel_cx0_phy.h"
/* HDMI/DVI modes ignore everything but the last 2 items. So we share
* them for both DP and FDI transports, allowing those ports to
@@ -1053,12 +1054,37 @@ static const union intel_ddi_buf_trans_entry direct_map_trans[] = {
{ .direct = { .level = 3, .preemph = 0 } },
};
-static const struct intel_ddi_buf_trans mtl_cx0c10_trans = {
+static const struct intel_ddi_buf_trans mtl_cx0_trans = {
.entries = direct_map_trans,
.num_entries = ARRAY_SIZE(direct_map_trans),
.hdmi_default_entry = ARRAY_SIZE(direct_map_trans) - 1,
};
+/* DP2.0 */
+static const union intel_ddi_buf_trans_entry _mtl_c20_trans_uhbr[] = {
+ { .snps = { 48, 0, 0 } }, /* preset 0 */
+ { .snps = { 43, 0, 5 } }, /* preset 1 */
+ { .snps = { 40, 0, 8 } }, /* preset 2 */
+ { .snps = { 37, 0, 11 } }, /* preset 3 */
+ { .snps = { 33, 0, 15 } }, /* preset 4 */
+ { .snps = { 46, 2, 0 } }, /* preset 5 */
+ { .snps = { 42, 2, 4 } }, /* preset 6 */
+ { .snps = { 38, 2, 8 } }, /* preset 7 */
+ { .snps = { 35, 2, 11 } }, /* preset 8 */
+ { .snps = { 33, 2, 13 } }, /* preset 9 */
+ { .snps = { 44, 4, 0 } }, /* preset 10 */
+ { .snps = { 40, 4, 4 } }, /* preset 11 */
+ { .snps = { 37, 4, 7 } }, /* preset 12 */
+ { .snps = { 33, 4, 11 } }, /* preset 13 */
+ { .snps = { 36, 6, 6 } }, /* preset 14 */
+ { .snps = { 28, 6, 2 } }, /* preset 15 */
+};
+
+static const struct intel_ddi_buf_trans mtl_c20_trans_uhbr = {
+ .entries = _mtl_c20_trans_uhbr,
+ .num_entries = ARRAY_SIZE(_mtl_c20_trans_uhbr),
+};
+
bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
{
return table == &tgl_combo_phy_trans_edp_hbr2_hobl;
@@ -1635,7 +1661,10 @@ mtl_get_cx0_buf_trans(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries)
{
- return intel_get_buf_trans(&mtl_cx0c10_trans, n_entries);
+ if (crtc_state->port_clock > 1000000)
+ return intel_get_buf_trans(&mtl_c20_trans_uhbr, n_entries);
+ else
+ return intel_get_buf_trans(&mtl_cx0_trans, n_entries);
}
void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 13/20] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (11 preceding siblings ...)
2022-10-14 12:47 ` [Intel-gfx] [PATCH 12/20] drm/i915/mtl: Add voltage swing sequence for C20 Mika Kahola
@ 2022-10-14 12:47 ` Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 14/20] drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll Mika Kahola
` (12 subsequent siblings)
25 siblings, 0 replies; 36+ messages in thread
From: Mika Kahola @ 2022-10-14 12:47 UTC (permalink / raw)
To: intel-gfx
Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index aab606520a62..9ce55b0c1cdc 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -1728,8 +1728,12 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
if (intel_dp_is_edp(intel_dp) && !intel_panel_use_ssc(i915))
ssc_enabled = false;
- /* TODO: DP2.0 10G and 20G rates enable MPLLA*/
- val |= ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
+ /* DP2.0 10G and 20G rates enable MPLLA*/
+ if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000) {
+ val |= ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0;
+ } else {
+ val |= ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
+ }
}
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 14/20] drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (12 preceding siblings ...)
2022-10-14 12:47 ` [Intel-gfx] [PATCH 13/20] drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA Mika Kahola
@ 2022-10-14 12:47 ` Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 15/20] drm/i915/mtl: Readout Thunderbolt HW state Mika Kahola
` (11 subsequent siblings)
25 siblings, 0 replies; 36+ messages in thread
From: Mika Kahola @ 2022-10-14 12:47 UTC (permalink / raw)
To: intel-gfx
Enabling and disabling sequence for Thunderbolt PLL.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 137 ++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 7 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
3 files changed, 139 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 9ce55b0c1cdc..04b77f113403 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -14,8 +14,8 @@
#include "intel_hdmi.h"
#include "intel_panel.h"
#include "intel_psr.h"
-#include "intel_uncore.h"
#include "intel_tc.h"
+#include "intel_uncore.h"
bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy)
{
@@ -1952,8 +1952,8 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane)
XELPDP_LANE1_PCLK_REFCLK_REQUEST;
}
-void intel_cx0pll_enable(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
+static void intel_cx0pll_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
@@ -2026,7 +2026,86 @@ void intel_cx0pll_enable(struct intel_encoder *encoder,
intel_cx0_phy_transaction_end(encoder, wakeref);
}
-void intel_cx0pll_disable(struct intel_encoder *encoder)
+static int intel_mtl_tbt_clock_select(struct drm_i915_private *i915, int clock)
+{
+ switch (clock) {
+ case 162000:
+ return XELPDP_DDI_CLOCK_SELECT_TBT_162;
+ case 270000:
+ return XELPDP_DDI_CLOCK_SELECT_TBT_270;
+ case 540000:
+ return XELPDP_DDI_CLOCK_SELECT_TBT_540;
+ case 810000:
+ return XELPDP_DDI_CLOCK_SELECT_TBT_810;
+ default:
+ MISSING_CASE(clock);
+ return XELPDP_DDI_CLOCK_SELECT_TBT_162;
+ }
+}
+
+static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+ u32 val = 0;
+
+ /*
+ * 1. Program PORT_CLOCK_CTL REGISTER to configure
+ * clock muxes, gating and SSC
+ */
+ val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, crtc_state->port_clock));
+ val |= XELPDP_FORWARD_CLOCK_UNGATE;
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_FORWARD_CLOCK_UNGATE, val);
+
+ /* 2. Read back PORT_CLOCK_CTL REGISTER */
+ val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
+
+ /*
+ * 3. Follow the Display Voltage Frequency Switching - Sequence
+ * Before Frequency Change. We handle this step in bxt_set_cdclk().
+ */
+
+ /*
+ * 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL.
+ */
+ val |= XELPDP_TBT_CLOCK_REQUEST;
+ intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), val);
+
+ /* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
+ if (__intel_wait_for_register(&i915->uncore, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ XELPDP_TBT_CLOCK_ACK,
+ XELPDP_TBT_CLOCK_ACK,
+ 100, 0, NULL))
+ drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not locked after 100us.\n",
+ encoder->base.base.id, encoder->base.name, phy_name(phy));
+
+ /*
+ * 6. Follow the Display Voltage Frequency Switching Sequence After
+ * Frequency Change. We handle this step in bxt_set_cdclk().
+ */
+
+ /*
+ * 7. Program DDI_CLK_VALFREQ to match intended DDI
+ * clock frequency.
+ */
+ intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
+ crtc_state->port_clock);
+}
+
+void intel_mtl_pll_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+
+ if (intel_tc_port_in_tbt_alt_mode(dig_port))
+ intel_mtl_tbt_pll_enable(encoder, crtc_state);
+ else
+ intel_cx0pll_enable(encoder, crtc_state);
+}
+
+static void intel_cx0pll_disable(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
@@ -2078,6 +2157,56 @@ void intel_cx0pll_disable(struct intel_encoder *encoder)
intel_cx0_phy_transaction_end(encoder, wakeref);
}
+static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ /*
+ * 1. Follow the Display Voltage Frequency Switching Sequence Before
+ * Frequency Change. We handle this step in bxt_set_cdclk().
+ */
+
+ /*
+ * 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL.
+ */
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ XELPDP_TBT_CLOCK_REQUEST, 0);
+
+ /* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
+ if (__intel_wait_for_register(&i915->uncore, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ XELPDP_TBT_CLOCK_ACK,
+ ~XELPDP_TBT_CLOCK_ACK,
+ 10, 0, NULL))
+ drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",
+ encoder->base.base.id, encoder->base.name, phy_name(phy));
+
+ /*
+ * 4. Follow the Display Voltage Frequency Switching Sequence After
+ * Frequency Change. We handle this step in bxt_set_cdclk().
+ */
+
+ /*
+ * 5. Program PORT CLOCK CTRL register to disable and gate clocks
+ */
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ XELPDP_DDI_CLOCK_SELECT_MASK |
+ XELPDP_FORWARD_CLOCK_UNGATE, 0);
+
+ /* 6. Program DDI_CLK_VALFREQ to 0. */
+ intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0);
+}
+
+void intel_mtl_pll_disable(struct intel_encoder *encoder)
+{
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+
+ if (intel_tc_port_in_tbt_alt_mode(dig_port))
+ intel_mtl_tbt_pll_disable(encoder);
+ else
+ intel_cx0pll_disable(encoder);
+}
+
void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
struct intel_crtc_state *new_crtc_state)
{
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 8ca77dfea24b..141802038f12 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -26,9 +26,9 @@ enum phy;
#define MB_WRITE_UNCOMMITTED 0
bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy);
-void intel_cx0pll_enable(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state);
-void intel_cx0pll_disable(struct intel_encoder *encoder);
+void intel_mtl_pll_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
+void intel_mtl_pll_disable(struct intel_encoder *encoder);
void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
struct intel_c10mpllb_state *pll_state);
int intel_cx0mpllb_calc_state(struct intel_crtc_state *crtc_state,
@@ -53,4 +53,5 @@ int intel_c20_phy_check_hdmi_link_rate(int clock);
void intel_cx0_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
u32 level);
+int intel_mtl_tbt_readout_hw_state(struct intel_encoder *encoder);
#endif /* __INTEL_CX0_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index bdf38905276e..07ea0dc6d5d0 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4392,8 +4392,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->pipe_mask = ~0;
if (DISPLAY_VER(dev_priv) >= 14) {
- encoder->enable_clock = intel_cx0pll_enable;
- encoder->disable_clock = intel_cx0pll_disable;
+ encoder->enable_clock = intel_mtl_pll_enable;
+ encoder->disable_clock = intel_mtl_pll_disable;
encoder->get_config = mtl_ddi_get_config;
} else if (IS_DG2(dev_priv)) {
encoder->enable_clock = intel_mpllb_enable;
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 15/20] drm/i915/mtl: Readout Thunderbolt HW state
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (13 preceding siblings ...)
2022-10-14 12:47 ` [Intel-gfx] [PATCH 14/20] drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll Mika Kahola
@ 2022-10-14 12:47 ` Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 16/20] drm/i915/mtl: Enable TC ports Mika Kahola
` (10 subsequent siblings)
25 siblings, 0 replies; 36+ messages in thread
From: Mika Kahola @ 2022-10-14 12:47 UTC (permalink / raw)
To: intel-gfx
Readout hw state for Thunderbolt.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27 ++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++-
3 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 04b77f113403..377ae5f6ac3f 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2026,6 +2026,33 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
intel_cx0_phy_transaction_end(encoder, wakeref);
}
+int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ u32 clock;
+ u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
+
+ clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
+
+ drm_WARN_ON(&i915->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE));
+ drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_REQUEST));
+ drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_ACK));
+
+ switch (clock) {
+ case XELPDP_DDI_CLOCK_SELECT_TBT_162:
+ return 162000;
+ case XELPDP_DDI_CLOCK_SELECT_TBT_270:
+ return 270000;
+ case XELPDP_DDI_CLOCK_SELECT_TBT_540:
+ return 540000;
+ case XELPDP_DDI_CLOCK_SELECT_TBT_810:
+ return 810000;
+ default:
+ MISSING_CASE(clock);
+ return 162000;
+ }
+}
+
static int intel_mtl_tbt_clock_select(struct drm_i915_private *i915, int clock)
{
switch (clock) {
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 141802038f12..aaaa971111a3 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -53,5 +53,5 @@ int intel_c20_phy_check_hdmi_link_rate(int clock);
void intel_cx0_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
u32 level);
-int intel_mtl_tbt_readout_hw_state(struct intel_encoder *encoder);
+int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
#endif /* __INTEL_CX0_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 07ea0dc6d5d0..e538bfed5cca 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3498,8 +3498,11 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder,
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
- if (intel_is_c10phy(i915, phy)) {
+ if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
+ crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
+ } else if (intel_is_c10phy(i915, phy)) {
intel_c10mpllb_readout_hw_state(encoder, &crtc_state->cx0pll_state.c10mpllb_state);
intel_c10mpllb_dump_hw_state(i915, &crtc_state->cx0pll_state.c10mpllb_state);
crtc_state->port_clock = intel_c10mpllb_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10mpllb_state);
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 16/20] drm/i915/mtl: Enable TC ports
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (14 preceding siblings ...)
2022-10-14 12:47 ` [Intel-gfx] [PATCH 15/20] drm/i915/mtl: Readout Thunderbolt HW state Mika Kahola
@ 2022-10-14 12:47 ` Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 17/20] drm/i915/mtl: MTL PICA hotplug detection Mika Kahola
` (9 subsequent siblings)
25 siblings, 0 replies; 36+ messages in thread
From: Mika Kahola @ 2022-10-14 12:47 UTC (permalink / raw)
To: intel-gfx
Finally, we can enable TC ports for Meteorlake.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5ce33319b70d..1d63b1adef48 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7911,9 +7911,12 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
return;
if (IS_METEORLAKE(dev_priv)) {
- /* TODO: initialize TC ports as well */
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
+ intel_ddi_init(dev_priv, PORT_TC1);
+ intel_ddi_init(dev_priv, PORT_TC2);
+ intel_ddi_init(dev_priv, PORT_TC3);
+ intel_ddi_init(dev_priv, PORT_TC4);
} else if (IS_DG2(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 17/20] drm/i915/mtl: MTL PICA hotplug detection
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (15 preceding siblings ...)
2022-10-14 12:47 ` [Intel-gfx] [PATCH 16/20] drm/i915/mtl: Enable TC ports Mika Kahola
@ 2022-10-14 12:47 ` Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 18/20] drm/i915/mtl: Define mask for DDI AUX interrupts Mika Kahola
` (8 subsequent siblings)
25 siblings, 0 replies; 36+ messages in thread
From: Mika Kahola @ 2022-10-14 12:47 UTC (permalink / raw)
To: intel-gfx
PICA is used for DP alt mode and TBT modes. Hotplug interruption is routed
from PICA chip to south display engine and from there to north display
engine. This patch adds functionality to enable hotplug detection for
all Type-C ports (4 ports available).
Differently from HPD in south display, PICA provides a dedicated HPD
control register for each supported port, so we loop over ports
ourselves instead of using intel_hpd_hotplug_enables() or
intel_get_hpd_pins().
BSpec: 49305, 55726, 65107, 65300
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 226 +++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 31 ++++-
2 files changed, 252 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1ae7ac004a53..52517d7bbc75 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -163,6 +163,13 @@ static const u32 hpd_gen11[HPD_NUM_PINS] = {
[HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6),
};
+static const u32 hpd_xelpdp[HPD_NUM_PINS] = {
+ [HPD_PORT_TC1] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC1) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC1),
+ [HPD_PORT_TC2] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC2) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC2),
+ [HPD_PORT_TC3] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC3) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC3),
+ [HPD_PORT_TC4] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC4) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC4),
+};
+
static const u32 hpd_icp[HPD_NUM_PINS] = {
[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
@@ -183,6 +190,16 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
[HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),
};
+static const u32 hpd_mtp[HPD_NUM_PINS] = {
+ [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
+ [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
+ [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
+ [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
+ [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
+ [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
+};
+
+
static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
{
struct intel_hotplug *hpd = &dev_priv->display.hotplug;
@@ -196,7 +213,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
return;
}
- if (DISPLAY_VER(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 14)
+ hpd->hpd = hpd_xelpdp;
+ else if (DISPLAY_VER(dev_priv) >= 11)
hpd->hpd = hpd_gen11;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
hpd->hpd = hpd_bxt;
@@ -213,6 +232,8 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
hpd->pch_hpd = hpd_sde_dg1;
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
+ hpd->pch_hpd = hpd_mtp;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
hpd->pch_hpd = hpd_icp;
else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
@@ -1965,6 +1986,44 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
cpt_serr_int_handler(dev_priv);
}
+static void xelpdp_pica_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
+{
+ enum hpd_pin pin;
+ u32 hotplug_trigger = iir & (XELPDP_DP_ALT_HOTPLUG_MASK | XELPDP_TBT_HOTPLUG_MASK);
+ u32 trigger_aux = iir & XELPDP_AUX_TC_MASK;
+ u32 pin_mask = 0, long_mask = 0;
+
+ for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) {
+ u32 val;
+
+ if (!(dev_priv->display.hotplug.hpd[pin] & hotplug_trigger))
+ continue;
+
+ pin_mask |= BIT(pin);
+
+ val = intel_uncore_read(&dev_priv->uncore, XELPDP_PORT_HOTPLUG_CTL(pin));
+ intel_uncore_write(&dev_priv->uncore, XELPDP_PORT_HOTPLUG_CTL(pin), val);
+
+ if (val & (XELPDP_DP_ALT_HPD_LONG_DETECT | XELPDP_TBT_HPD_LONG_DETECT))
+ long_mask |= BIT(pin);
+ }
+
+ if (pin_mask) {
+ drm_dbg(&dev_priv->drm,
+ "pica hotplug event received, stat 0x%08x, pins 0x%08x, long 0x%08x\n",
+ hotplug_trigger, pin_mask, long_mask);
+
+ intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
+ }
+
+ if (trigger_aux)
+ dp_aux_irq_handler(dev_priv);
+
+ if (!pin_mask && !trigger_aux)
+ drm_err(&dev_priv->drm,
+ "Unexpected DE HPD/AUX interrupt 0x%08x\n", iir);
+}
+
static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
{
u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;
@@ -1993,6 +2052,15 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
icp_tc_port_hotplug_long_detect);
}
+ if (pch_iir & SDE_PICAINTERRUPT) {
+ u32 iir = intel_uncore_read(&dev_priv->uncore, PICAINTERRUPT_IIR);
+
+ if (iir) {
+ intel_uncore_write(&dev_priv->uncore, PICAINTERRUPT_IIR, iir);
+ xelpdp_pica_hpd_irq_handler(dev_priv, iir);
+ }
+ }
+
if (pin_mask)
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
@@ -3159,7 +3227,11 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
- GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
+
+ if (DISPLAY_VER(dev_priv) >= 14)
+ GEN3_IRQ_RESET(uncore, PICAINTERRUPT_);
+ else
+ GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
GEN3_IRQ_RESET(uncore, SDE);
@@ -3452,6 +3524,131 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
icp_hpd_irq_setup(dev_priv);
}
+static u32 mtp_ddi_hotplug_enables(struct drm_i915_private *i915,
+ enum hpd_pin pin)
+{
+ switch (pin) {
+ case HPD_PORT_A:
+ case HPD_PORT_B:
+ return SHOTPLUG_CTL_DDI_HPD_ENABLE(pin);
+ default:
+ return 0;
+ }
+}
+
+static u32 mtp_tc_hotplug_enables(struct drm_i915_private *i915,
+ enum hpd_pin pin)
+{
+ switch (pin) {
+ case HPD_PORT_TC1:
+ case HPD_PORT_TC2:
+ case HPD_PORT_TC3:
+ case HPD_PORT_TC4:
+ return ICP_TC_HPD_ENABLE(pin);
+ default:
+ return 0;
+ }
+}
+
+static void mtp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv)
+{
+ u32 hotplug;
+
+ hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI);
+ hotplug &= ~(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A) |
+ SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B));
+ hotplug |= intel_hpd_hotplug_enables(dev_priv, mtp_ddi_hotplug_enables);
+ intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, hotplug);
+}
+
+static void mtp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
+{
+ u32 hotplug;
+
+ hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC);
+ hotplug &= ~(ICP_TC_HPD_ENABLE(HPD_PORT_TC1) |
+ ICP_TC_HPD_ENABLE(HPD_PORT_TC2) |
+ ICP_TC_HPD_ENABLE(HPD_PORT_TC3) |
+ ICP_TC_HPD_ENABLE(HPD_PORT_TC4));
+ hotplug |= intel_hpd_hotplug_enables(dev_priv, mtp_tc_hotplug_enables);
+ intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, hotplug);
+}
+
+static void mtp_hpd_invert(struct drm_i915_private *i915)
+{
+ u32 val = (INVERT_DDIA_HPD |
+ INVERT_DDIB_HPD |
+ INVERT_DDIC_HPD |
+ INVERT_TC1_HPD |
+ INVERT_TC2_HPD |
+ INVERT_TC3_HPD |
+ INVERT_TC4_HPD |
+ INVERT_DDID_HPD_MTP |
+ INVERT_DDIE_HPD);
+ intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN1, 0, val);
+}
+
+static void mtp_hpd_irq_setup(struct drm_i915_private *dev_priv)
+{
+ u32 hotplug_irqs, enabled_irqs;
+
+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
+
+ intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
+
+ mtp_hpd_invert(dev_priv);
+
+ ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
+
+ mtp_ddi_hpd_detection_setup(dev_priv);
+ mtp_tc_hpd_detection_setup(dev_priv);
+
+}
+
+static void xelpdp_pica_hpd_detection_setup(struct drm_i915_private *dev_priv)
+{
+ struct intel_encoder *encoder;
+ enum hpd_pin pin;
+ u32 available_pins = 0;
+
+ BUILD_BUG_ON(BITS_PER_TYPE(available_pins) < HPD_NUM_PINS);
+
+ for_each_intel_encoder(&dev_priv->drm, encoder)
+ available_pins |= BIT(encoder->hpd_pin);
+
+ for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) {
+ u32 mask = (available_pins & BIT(pin)) ? ~(u32)0 : 0;
+ u32 val = XELPDP_TBT_HOTPLUG_ENABLE |
+ XELPDP_DP_ALT_HOTPLUG_ENABLE;
+
+ intel_uncore_rmw(&dev_priv->uncore,
+ XELPDP_PORT_HOTPLUG_CTL(pin),
+ ~mask & val, mask & val);
+ }
+}
+
+static void xelpdp_hpd_irq_setup(struct drm_i915_private *dev_priv)
+{
+ u32 hotplug_irqs, enabled_irqs;
+ u32 val;
+
+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
+
+ val = intel_uncore_read(&dev_priv->uncore, PICAINTERRUPT_IMR);
+ val &= ~hotplug_irqs;
+ val |= ~enabled_irqs & hotplug_irqs;
+ intel_uncore_write(&dev_priv->uncore, PICAINTERRUPT_IMR, val);
+ intel_uncore_posting_read(&dev_priv->uncore, PICAINTERRUPT_IMR);
+
+ xelpdp_pica_hpd_detection_setup(dev_priv);
+
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP) {
+ mtp_hpd_irq_setup(dev_priv);
+ }
+}
+
static u32 spt_hotplug_enables(struct drm_i915_private *i915,
enum hpd_pin pin)
{
@@ -3791,7 +3988,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
- if (DISPLAY_VER(dev_priv) >= 11) {
+ if (IS_DISPLAY_VER(dev_priv, 11, 13)) {
u32 de_hpd_masked = 0;
u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
GEN11_DE_TBT_HOTPLUG_MASK;
@@ -3801,6 +3998,20 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
}
}
+static void mtp_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+ u32 sde_mask = SDE_GMBUS_ICP | SDE_PICAINTERRUPT;
+ u32 de_hpd_mask = XELPDP_AUX_TC_MASK;
+ u32 de_hpd_enables = de_hpd_mask | XELPDP_DP_ALT_HOTPLUG_MASK |
+ XELPDP_TBT_HOTPLUG_MASK;
+
+ GEN3_IRQ_INIT(uncore, PICAINTERRUPT_, ~de_hpd_mask,
+ de_hpd_enables);
+
+ GEN3_IRQ_INIT(uncore, SDE, ~sde_mask, 0xffffffff);
+}
+
static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = &dev_priv->uncore;
@@ -3862,7 +4073,11 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv)
GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
if (HAS_DISPLAY(dev_priv)) {
- icp_irq_postinstall(dev_priv);
+ if (DISPLAY_VER(dev_priv) >= 14)
+ mtp_irq_postinstall(dev_priv);
+ else
+ icp_irq_postinstall(dev_priv);
+
gen8_de_irq_postinstall(dev_priv);
intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL,
GEN11_DISPLAY_IRQ_ENABLE);
@@ -4320,6 +4535,7 @@ static const struct intel_hotplug_funcs platform##_hpd_funcs = { \
}
HPD_FUNCS(i915);
+HPD_FUNCS(xelpdp);
HPD_FUNCS(dg1);
HPD_FUNCS(gen11);
HPD_FUNCS(bxt);
@@ -4380,6 +4596,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev_priv->display.funcs.hotplug = &icp_hpd_funcs;
else if (HAS_PCH_DG1(dev_priv))
dev_priv->display.funcs.hotplug = &dg1_hpd_funcs;
+ else if (DISPLAY_VER(dev_priv) >= 14)
+ dev_priv->display.funcs.hotplug = &xelpdp_hpd_funcs;
else if (DISPLAY_VER(dev_priv) >= 11)
dev_priv->display.funcs.hotplug = &gen11_hpd_funcs;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index abf12d459bc2..7dfe4bd2618b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5667,6 +5667,28 @@
#define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
#define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define PICAINTERRUPT_ISR _MMIO(0x16FE50)
+#define PICAINTERRUPT_IMR _MMIO(0x16FE54)
+#define PICAINTERRUPT_IIR _MMIO(0x16FE58)
+#define PICAINTERRUPT_IER _MMIO(0x16FE5C)
+
+#define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
+#define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19, 16)
+
+#define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin))
+#define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8)
+
+#define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
+#define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0)
+
+#define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200))
+#define XELPDP_TBT_HOTPLUG_ENABLE REG_BIT(6)
+#define XELPDP_TBT_HPD_LONG_DETECT REG_BIT(5)
+#define XELPDP_TBT_HPD_SHORT_DETECT REG_BIT(4)
+#define XELPDP_DP_ALT_HOTPLUG_ENABLE REG_BIT(2)
+#define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1)
+#define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0)
+
#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword))
#define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16)
#define XELPDP_PMDEMAND_QCLK_GV_BW(x) REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, x)
@@ -6002,7 +6024,8 @@
SDE_FDI_RXB_CPT | \
SDE_FDI_RXA_CPT)
-/* south display engine interrupt: ICP/TGP */
+/* south display engine interrupt: ICP/TGP/MTP */
+#define SDE_PICAINTERRUPT REG_BIT(31)
#define SDE_GMBUS_ICP (1 << 23)
#define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
#define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
@@ -6355,6 +6378,12 @@
#define SOUTH_CHICKEN1 _MMIO(0xc2000)
#define FDIA_PHASE_SYNC_SHIFT_OVR 19
#define FDIA_PHASE_SYNC_SHIFT_EN 18
+#define INVERT_DDIE_HPD REG_BIT(28)
+#define INVERT_DDID_HPD_MTP REG_BIT(27)
+#define INVERT_TC4_HPD REG_BIT(26)
+#define INVERT_TC3_HPD REG_BIT(25)
+#define INVERT_TC2_HPD REG_BIT(24)
+#define INVERT_TC1_HPD REG_BIT(23)
#define INVERT_DDID_HPD (1 << 18)
#define INVERT_DDIC_HPD (1 << 17)
#define INVERT_DDIB_HPD (1 << 16)
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 18/20] drm/i915/mtl: Define mask for DDI AUX interrupts
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (16 preceding siblings ...)
2022-10-14 12:47 ` [Intel-gfx] [PATCH 17/20] drm/i915/mtl: MTL PICA hotplug detection Mika Kahola
@ 2022-10-14 12:47 ` Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 19/20] drm/i915/mtl: Power up TCSS Mika Kahola
` (7 subsequent siblings)
25 siblings, 0 replies; 36+ messages in thread
From: Mika Kahola @ 2022-10-14 12:47 UTC (permalink / raw)
To: intel-gfx
From: Gustavo Sousa <gustavo.sousa@intel.com>
Xe_LPD+ defines interrupt bits for only DDI ports in the DE Port
Interrupt registers. The bits for Type-C ports are defined in the PICA
interrupt registers.
BSpec: 50064
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 52517d7bbc75..1456c5336fc8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2337,7 +2337,10 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
{
u32 mask;
- if (DISPLAY_VER(dev_priv) >= 13)
+ if (DISPLAY_VER(dev_priv) >= 14)
+ return TGL_DE_PORT_AUX_DDIA |
+ TGL_DE_PORT_AUX_DDIB;
+ else if (DISPLAY_VER(dev_priv) >= 13)
return TGL_DE_PORT_AUX_DDIA |
TGL_DE_PORT_AUX_DDIB |
TGL_DE_PORT_AUX_DDIC |
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 19/20] drm/i915/mtl: Power up TCSS
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (17 preceding siblings ...)
2022-10-14 12:47 ` [Intel-gfx] [PATCH 18/20] drm/i915/mtl: Define mask for DDI AUX interrupts Mika Kahola
@ 2022-10-14 12:47 ` Mika Kahola
2022-10-14 12:47 ` [Intel-gfx] [PATCH 20/20] drm/i915/mtl: Pin assignment for TypeC Mika Kahola
` (6 subsequent siblings)
25 siblings, 0 replies; 36+ messages in thread
From: Mika Kahola @ 2022-10-14 12:47 UTC (permalink / raw)
To: intel-gfx
Add register writes to enable powering up Type-C subsystem i.e. TCSS.
For MeteorLake we need to request TCSS to power up and check the TCSS
power state after 500 us.
In addition, for PICA we need to set/clear the Type-C PHY ownnership
bit when Type-C device is connected/disconnected.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_tc.c | 115 ++++++++++++++++++-
2 files changed, 112 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1d63b1adef48..384c503f37ca 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2112,7 +2112,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
if (IS_DG2(dev_priv))
/* DG2's "TC1" output uses a SNPS PHY */
return false;
- else if (IS_ALDERLAKE_P(dev_priv))
+ else if (IS_ALDERLAKE_P(dev_priv) || IS_METEORLAKE(dev_priv))
return phy >= PHY_F && phy <= PHY_I;
else if (IS_TIGERLAKE(dev_priv))
return phy >= PHY_D && phy <= PHY_I;
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 8cecd41ed003..dba10bcc6b66 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -5,6 +5,7 @@
#include "i915_drv.h"
#include "i915_reg.h"
+#include "intel_cx0_reg_defs.h"
#include "intel_display.h"
#include "intel_display_power_map.h"
#include "intel_display_types.h"
@@ -308,7 +309,7 @@ static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- if (IS_ALDERLAKE_P(i915))
+ if (DISPLAY_VER(i915) >= 13)
return adl_tc_port_live_status_mask(dig_port);
return icl_tc_port_live_status_mask(dig_port);
@@ -365,11 +366,69 @@ static bool adl_tc_phy_status_complete(struct intel_digital_port *dig_port)
return val & TCSS_DDI_STATUS_READY;
}
+static bool xelpdp_wait_phy_status_complete(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+
+ if (intel_wait_for_register(&i915->uncore,
+ TCSS_DDI_STATUS(tc_port),
+ TCSS_DDI_STATUS_READY,
+ TCSS_DDI_STATUS_READY,
+ 1)) {
+ drm_dbg_kms(&i915->drm,
+ "Port %s: PHY in TCCOLD, assuming not complete\n",
+ dig_port->tc_port_name);
+ return false;
+ }
+
+ return true;
+}
+
+static bool xelpdp_wait_for_tcss_power(struct intel_digital_port *dig_port,
+ bool enabled)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+
+ if (intel_wait_for_register(&i915->uncore,
+ XELPDP_PORT_BUF_CTL1(dig_port->base.port),
+ XELPDP_TCSS_POWER_STATE,
+ enabled ? XELPDP_TCSS_POWER_STATE : 0,
+ 1)) {
+ drm_dbg_kms(&i915->drm,
+ "Port %s: TCSS power state not as expected\n",
+ dig_port->tc_port_name);
+ return false;
+ }
+
+ return true;
+}
+
+static bool xelpdp_tc_power_request(struct intel_digital_port *dig_port, bool request)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_uncore *uncore = &i915->uncore;
+ enum port port = dig_port->base.port;
+ u32 val;
+
+ val = intel_uncore_read(uncore, XELPDP_PORT_BUF_CTL1(port));
+ if (request)
+ val |= XELPDP_TCSS_POWER_REQUEST;
+ else
+ val &= ~XELPDP_TCSS_POWER_REQUEST;
+ intel_uncore_write(uncore, XELPDP_PORT_BUF_CTL1(port), val);
+
+ return xelpdp_wait_phy_status_complete(dig_port) &&
+ xelpdp_wait_for_tcss_power(dig_port, true);
+}
+
static bool tc_phy_status_complete(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- if (IS_ALDERLAKE_P(i915))
+ if (DISPLAY_VER(i915) >= 14)
+ return xelpdp_wait_phy_status_complete(dig_port);
+ else if (IS_ALDERLAKE_P(i915))
return adl_tc_phy_status_complete(dig_port);
return icl_tc_phy_status_complete(dig_port);
@@ -415,11 +474,31 @@ static bool adl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
return true;
}
+static bool xelpdp_tc_phy_take_ownership(struct intel_digital_port *dig_port,
+ bool take)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_uncore *uncore = &i915->uncore;
+ enum port port = dig_port->base.port;
+ u32 val;
+
+ val = intel_uncore_read(uncore, XELPDP_PORT_BUF_CTL1(port));
+ if (take)
+ val |= XELPDP_TC_PHY_OWNERSHIP;
+ else
+ val &= ~XELPDP_TC_PHY_OWNERSHIP;
+ intel_uncore_write(uncore, XELPDP_PORT_BUF_CTL1(port), val);
+
+ return true;
+}
+
static bool tc_phy_take_ownership(struct intel_digital_port *dig_port, bool take)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- if (IS_ALDERLAKE_P(i915))
+ if (DISPLAY_VER(i915) >= 14)
+ return xelpdp_tc_phy_take_ownership(dig_port, take);
+ else if (IS_ALDERLAKE_P(i915))
return adl_tc_phy_take_ownership(dig_port, take);
return icl_tc_phy_take_ownership(dig_port, take);
@@ -454,11 +533,23 @@ static bool adl_tc_phy_is_owned(struct intel_digital_port *dig_port)
return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP;
}
+static bool xelpdp_tc_phy_is_owned(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_uncore *uncore = &i915->uncore;
+ enum port port = dig_port->base.port;
+
+ return intel_uncore_read(uncore, XELPDP_PORT_BUF_CTL1(port)) &
+ XELPDP_TC_PHY_OWNERSHIP;
+}
+
static bool tc_phy_is_owned(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- if (IS_ALDERLAKE_P(i915))
+ if (DISPLAY_VER(i915) >= 14)
+ return xelpdp_tc_phy_is_owned(dig_port);
+ else if (IS_ALDERLAKE_P(i915))
return adl_tc_phy_is_owned(dig_port);
return icl_tc_phy_is_owned(dig_port);
@@ -482,6 +573,9 @@ static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
u32 live_status_mask;
int max_lanes;
+ if (DISPLAY_VER(i915) >= 14)
+ xelpdp_tc_power_request(dig_port, true);
+
if (!tc_phy_status_complete(dig_port)) {
drm_dbg_kms(&i915->drm, "Port %s: PHY not ready\n",
dig_port->tc_port_name);
@@ -532,6 +626,10 @@ static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
out_release_phy:
tc_phy_take_ownership(dig_port, false);
+
+ if (DISPLAY_VER(i915) >= 14)
+ xelpdp_tc_power_request(dig_port, false);
+
out_set_tbt_alt_mode:
dig_port->tc_mode = TC_PORT_TBT_ALT;
}
@@ -542,6 +640,8 @@ static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
*/
static void icl_tc_phy_disconnect(struct intel_digital_port *dig_port)
{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+
switch (dig_port->tc_mode) {
case TC_PORT_LEGACY:
case TC_PORT_DP_ALT:
@@ -555,6 +655,9 @@ static void icl_tc_phy_disconnect(struct intel_digital_port *dig_port)
default:
MISSING_CASE(dig_port->tc_mode);
}
+
+ if (DISPLAY_VER(i915) >= 14)
+ xelpdp_tc_power_request(dig_port, false);
}
static bool icl_tc_phy_is_connected(struct intel_digital_port *dig_port)
@@ -904,6 +1007,10 @@ tc_has_modular_fia(struct drm_i915_private *i915, struct intel_digital_port *dig
if (!INTEL_INFO(i915)->display.has_modular_fia)
return false;
+ /* for MTL, FIA is always modular */
+ if (DISPLAY_VER(i915) >= 14)
+ return true;
+
mutex_lock(&dig_port->tc_lock);
wakeref = tc_cold_block(dig_port, &domain);
val = intel_uncore_read(&i915->uncore, PORT_TX_DFLEXDPSP(FIA1));
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Intel-gfx] [PATCH 20/20] drm/i915/mtl: Pin assignment for TypeC
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (18 preceding siblings ...)
2022-10-14 12:47 ` [Intel-gfx] [PATCH 19/20] drm/i915/mtl: Power up TCSS Mika Kahola
@ 2022-10-14 12:47 ` Mika Kahola
2022-10-26 14:26 ` Imre Deak
2022-10-14 13:11 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Add C10 and C20 phy support Patchwork
` (5 subsequent siblings)
25 siblings, 1 reply; 36+ messages in thread
From: Mika Kahola @ 2022-10-14 12:47 UTC (permalink / raw)
To: intel-gfx
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
Unlike previous platforms that used PORT_TX_DFLEXDPSP
for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
from which the max_lanes has to be calculated.
Bspec: 50235, 65380
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Jose Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_tc.c | 30 +++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index dba10bcc6b66..1bc81adf1ad7 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -13,6 +13,10 @@
#include "intel_tc.h"
#include "intel_tc_phy_regs.h"
+#define DP_PIN_ASSIGNMENT_C 0x3
+#define DP_PIN_ASSIGNMENT_D 0x4
+#define DP_PIN_ASSIGNMENT_E 0x5
+
static const char *tc_port_mode_name(enum tc_port_mode mode)
{
static const char * const names[] = {
@@ -149,6 +153,29 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
}
+static int mtl_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ intel_wakeref_t wakeref;
+ u32 pin_mask;
+
+ assert_tc_cold_blocked(dig_port);
+
+ with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
+ pin_mask = intel_tc_port_get_pin_assignment_mask(dig_port);
+
+ switch(pin_mask) {
+ default:
+ MISSING_CASE(pin_mask);
+ fallthrough;
+ case DP_PIN_ASSIGNMENT_D:
+ return 2;
+ case DP_PIN_ASSIGNMENT_C:
+ case DP_PIN_ASSIGNMENT_E:
+ return 4;
+ }
+}
+
int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -158,6 +185,9 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
if (dig_port->tc_mode != TC_PORT_DP_ALT)
return 4;
+ if (DISPLAY_VER(i915) >= 14)
+ return mtl_tc_port_get_pin_assignment_mask(dig_port);
+
assert_tc_cold_blocked(dig_port);
lane_mask = 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [Intel-gfx] [PATCH 20/20] drm/i915/mtl: Pin assignment for TypeC
2022-10-14 12:47 ` [Intel-gfx] [PATCH 20/20] drm/i915/mtl: Pin assignment for TypeC Mika Kahola
@ 2022-10-26 14:26 ` Imre Deak
2022-10-27 8:15 ` Kahola, Mika
0 siblings, 1 reply; 36+ messages in thread
From: Imre Deak @ 2022-10-26 14:26 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
On Fri, Oct 14, 2022 at 03:47:40PM +0300, Mika Kahola wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> Unlike previous platforms that used PORT_TX_DFLEXDPSP
> for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
> from which the max_lanes has to be calculated.
>
> Bspec: 50235, 65380
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Jose Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_tc.c | 30 +++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index dba10bcc6b66..1bc81adf1ad7 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -13,6 +13,10 @@
> #include "intel_tc.h"
> #include "intel_tc_phy_regs.h"
>
> +#define DP_PIN_ASSIGNMENT_C 0x3
> +#define DP_PIN_ASSIGNMENT_D 0x4
> +#define DP_PIN_ASSIGNMENT_E 0x5
The above are flags for the PORT_TX_DFLEXPA1 register, so should be
defined next to it.
TGL handles a few more encodings, not sure if that's correct or the
register description, opened a bspec ticket to clarify that.
> +
> static const char *tc_port_mode_name(enum tc_port_mode mode)
> {
> static const char * const names[] = {
> @@ -149,6 +153,29 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
> DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
> }
>
> +static int mtl_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
The function returns the maximum number of lanes, so should be named
accordingly.
> +{
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + intel_wakeref_t wakeref;
> + u32 pin_mask;
> +
> + assert_tc_cold_blocked(dig_port);
> +
> + with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
> + pin_mask = intel_tc_port_get_pin_assignment_mask(dig_port);
The called function handles all the above, so it can be just:
switch (intel_tc_port_get_pin_assignment_mask()):
> +
> + switch(pin_mask) {
> + default:
> + MISSING_CASE(pin_mask);
> + fallthrough;
> + case DP_PIN_ASSIGNMENT_D:
> + return 2;
> + case DP_PIN_ASSIGNMENT_C:
> + case DP_PIN_ASSIGNMENT_E:
> + return 4;
> + }
> +}
> +
> int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> @@ -158,6 +185,9 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
> if (dig_port->tc_mode != TC_PORT_DP_ALT)
> return 4;
>
> + if (DISPLAY_VER(i915) >= 14)
> + return mtl_tc_port_get_pin_assignment_mask(dig_port);
> +
> assert_tc_cold_blocked(dig_port);
>
> lane_mask = 0;
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [Intel-gfx] [PATCH 20/20] drm/i915/mtl: Pin assignment for TypeC
2022-10-26 14:26 ` Imre Deak
@ 2022-10-27 8:15 ` Kahola, Mika
0 siblings, 0 replies; 36+ messages in thread
From: Kahola, Mika @ 2022-10-27 8:15 UTC (permalink / raw)
To: Deak, Imre; +Cc: intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Deak, Imre <imre.deak@intel.com>
> Sent: Wednesday, October 26, 2022 5:27 PM
> To: Kahola, Mika <mika.kahola@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Srivatsa, Anusha
> <anusha.srivatsa@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; Souza, Jose <jose.souza@intel.com>
> Subject: Re: [PATCH 20/20] drm/i915/mtl: Pin assignment for TypeC
>
> On Fri, Oct 14, 2022 at 03:47:40PM +0300, Mika Kahola wrote:
> > From: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >
> > Unlike previous platforms that used PORT_TX_DFLEXDPSP for max_lane
> > calculation, MTL uses only PORT_TX_DFLEXPA1 from which the max_lanes
> > has to be calculated.
> >
> > Bspec: 50235, 65380
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > Signed-off-by: Jose Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_tc.c | 30
> > +++++++++++++++++++++++++
> > 1 file changed, 30 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> > b/drivers/gpu/drm/i915/display/intel_tc.c
> > index dba10bcc6b66..1bc81adf1ad7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_tc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> > @@ -13,6 +13,10 @@
> > #include "intel_tc.h"
> > #include "intel_tc_phy_regs.h"
> >
> > +#define DP_PIN_ASSIGNMENT_C 0x3
> > +#define DP_PIN_ASSIGNMENT_D 0x4
> > +#define DP_PIN_ASSIGNMENT_E 0x5
>
> The above are flags for the PORT_TX_DFLEXPA1 register, so should be defined
> next to it.
Ok. I will move these defines to the correct place.
>
> TGL handles a few more encodings, not sure if that's correct or the register
> description, opened a bspec ticket to clarify that.
>
> > +
> > static const char *tc_port_mode_name(enum tc_port_mode mode) {
> > static const char * const names[] = { @@ -149,6 +153,29 @@ u32
> > intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
> > DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
> > }
> >
> > +static int mtl_tc_port_get_pin_assignment_mask(struct
> > +intel_digital_port *dig_port)
>
> The function returns the maximum number of lanes, so should be named
> accordingly.
Yes, I will figure out a different name for that function.
>
> > +{
> > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > + intel_wakeref_t wakeref;
> > + u32 pin_mask;
> > +
> > + assert_tc_cold_blocked(dig_port);
> > +
> > + with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE,
> wakeref)
> > + pin_mask = intel_tc_port_get_pin_assignment_mask(dig_port);
>
> The called function handles all the above, so it can be just:
>
> switch (intel_tc_port_get_pin_assignment_mask()):
Yes. This simplifies the code a bit.
Thanks for a review and comments!
Cheers,
Mika
>
> > +
> > + switch(pin_mask) {
> > + default:
> > + MISSING_CASE(pin_mask);
> > + fallthrough;
> > + case DP_PIN_ASSIGNMENT_D:
> > + return 2;
> > + case DP_PIN_ASSIGNMENT_C:
> > + case DP_PIN_ASSIGNMENT_E:
> > + return 4;
> > + }
> > +}
> > +
> > int intel_tc_port_fia_max_lane_count(struct intel_digital_port
> > *dig_port) {
> > struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); @@
> > -158,6 +185,9 @@ int intel_tc_port_fia_max_lane_count(struct
> intel_digital_port *dig_port)
> > if (dig_port->tc_mode != TC_PORT_DP_ALT)
> > return 4;
> >
> > + if (DISPLAY_VER(i915) >= 14)
> > + return mtl_tc_port_get_pin_assignment_mask(dig_port);
> > +
> > assert_tc_cold_blocked(dig_port);
> >
> > lane_mask = 0;
> > --
> > 2.34.1
> >
^ permalink raw reply [flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Add C10 and C20 phy support
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (19 preceding siblings ...)
2022-10-14 12:47 ` [Intel-gfx] [PATCH 20/20] drm/i915/mtl: Pin assignment for TypeC Mika Kahola
@ 2022-10-14 13:11 ` Patchwork
2022-10-14 13:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (4 subsequent siblings)
25 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2022-10-14 13:11 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/mtl: Add C10 and C20 phy support
URL : https://patchwork.freedesktop.org/series/109714/
State : warning
== Summary ==
Error: dim checkpatch failed
17498f64790a drm/i915/mtl: Initial DDI port setup
c7a2fc56a9d0 drm/i915/mtl: Add DP rates
919c8b25d4b3 drm/i915/mtl: Create separate reg file for PICA registers
-:13: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#13:
new file mode 100644
-:18: WARNING:SPDX_LICENSE_TAG: Improper SPDX comment style for 'drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h', please use '/*' instead
#18: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:1:
+// SPDX-License-Identifier: MIT
-:18: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#18: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:1:
+// SPDX-License-Identifier: MIT
-:33: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#33: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:16:
+ [PORT_A] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
-:34: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#34: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:17:
+ [PORT_B] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
-:35: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#35: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:18:
+ [PORT_TC1] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
-:36: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#36: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:19:
+ [PORT_TC2] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2, \
-:37: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#37: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:20:
+ [PORT_TC3] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC3, \
-:38: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#38: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:21:
+ [PORT_TC4] = _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC4) + ((lane) * 4))
-:40: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#40: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:23:
+#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_XELPDP_PORT_M2P_MSGBUS_CTL(port, lane))
-:43: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#43: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:26:
+#define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1)
-:44: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#44: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:27:
+#define XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2)
-:45: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#45: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:28:
+#define XELPDP_PORT_M2P_COMMAND_READ REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3)
-:47: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#47: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:30:
+#define XELPDP_PORT_M2P_DATA(val) REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val)
-:50: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#50: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:33:
+#define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
-:52: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#52: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:35:
+#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) + 8)
-:58: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#58: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:41:
+#define XELPDP_PORT_P2M_DATA(val) REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val)
-:80: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#80: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:63:
+ [PORT_TC1] = _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
-:81: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#81: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:64:
+ [PORT_TC2] = _XELPDP_PORT_BUF_CTL1_LN0_USBC2, \
-:82: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#82: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:65:
+ [PORT_TC3] = _XELPDP_PORT_BUF_CTL1_LN0_USBC3, \
-:83: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#83: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:66:
+ [PORT_TC4] = _XELPDP_PORT_BUF_CTL1_LN0_USBC4))
-:103: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#103: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:86:
+#define XELPDP_LANE0_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK, val)
-:105: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#105: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:88:
+#define XELPDP_LANE1_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK, val)
-:107: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#107: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:90:
+#define XELPDP_POWER_STATE_READY(val) REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
-:111: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#111: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:94:
+#define XELPDP_PLL_LANE_STAGGERING_DELAY(val) REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val)
-:113: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#113: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:96:
+#define XELPDP_POWER_STATE_ACTIVE(val) REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val)
-:140: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#140: FILE: drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h:123:
+#define XELPDP_DDI_CLOCK_SELECT(val) REG_FIELD_PREP(XELPDP_DDI_CLOCK_SELECT_MASK, val)
total: 0 errors, 27 warnings, 0 checks, 136 lines checked
f1081dbf0bb3 drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:24: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#24:
Move register definitions to a new file i.e. intel_cx0_reg_defs.h (Jani)
-:52: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#52:
new file mode 100644
-:72: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'phy < PHY_C'
#72: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:16:
+ if (IS_METEORLAKE(dev_priv) && (phy < PHY_C))
-:107: WARNING:LONG_LINE: line length of 119 exceeds 100 columns
#107: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:51:
+ drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n", phy_name(phy), *val);
-:115: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#115: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:59:
+static int __intel_cx0_read(struct drm_i915_private *i915, enum port port,
+ int lane, u16 addr, u32 *val)
-:124: WARNING:LONG_LINE: line length of 146 exceeds 100 columns
#124: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:68:
+ drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
-:144: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#144: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:88:
+ drm_dbg_kms(&i915->drm, "PHY %c Error occurred during read command. Status: 0x%x\n", phy_name(phy), *val);
-:152: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#152: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:96:
+ drm_dbg_kms(&i915->drm, "PHY %c Not a Read response. MSGBUS Status: 0x%x.\n", phy_name(phy), *val);
-:175: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#175: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:119:
+ drm_err_once(&i915->drm, "PHY %c Read %04x failed after %d retries.\n", phy_name(phy), addr, i);
-:186: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#186: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:130:
+static int intel_cx0_wait_cwrite_ack(struct drm_i915_private *i915,
+ enum port port, int lane)
-:199: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#199: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:143:
+ drm_dbg_kms(&i915->drm, "PHY %c Unexpected ACK received. MSGBUS STATUS: 0x%x.\n", phy_name(phy), val);
-:215: WARNING:LONG_LINE: line length of 146 exceeds 100 columns
#215: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:159:
+ drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
-:236: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#236: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:180:
+ drm_dbg_kms(&i915->drm, "PHY %c Error occurred during write command.\n", phy_name(phy));
-:258: WARNING:LONG_LINE: line length of 113 exceeds 100 columns
#258: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:202:
+ drm_err_once(&i915->drm, "PHY %c Write %04x failed after %d retries.\n", phy_name(phy), addr, i);
-:665: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#665: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:609:
+ intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CMN(0), cmn0, MB_WRITE_COMMITTED);
-:666: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#666: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:610:
+ intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_TX(0), C10_TX0_VAL, MB_WRITE_COMMITTED);
-:780: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#780: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:724:
+ XELPDP_LANE0_POWERDOWN_NEW_STATE(state) | XELPDP_LANE1_POWERDOWN_NEW_STATE(state));
-:847: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#847: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:791:
+ XELPDP_LANE0_PHY_CURRENT_STATUS | XELPDP_LANE1_PHY_CURRENT_STATUS,
-:848: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#848: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:792:
+ XELPDP_LANE0_PHY_CURRENT_STATUS | XELPDP_LANE1_PHY_CURRENT_STATUS,
-:1153: WARNING:SPDX_LICENSE_TAG: Improper SPDX comment style for 'drivers/gpu/drm/i915/display/intel_cx0_phy.h', please use '/*' instead
#1153: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.h:1:
+// SPDX-License-Identifier: MIT
-:1153: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#1153: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.h:1:
+// SPDX-License-Identifier: MIT
-:1202: WARNING:SPDX_LICENSE_TAG: Improper SPDX comment style for 'drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h', please use '/*' instead
#1202: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:1:
+// SPDX-License-Identifier: MIT
-:1202: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#1202: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:1:
+// SPDX-License-Identifier: MIT
-:1293: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#1293: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:3501:
+ crtc_state->port_clock = intel_c10mpllb_calc_port_clock(encoder, &crtc_state->c10mpllb_state);
-:1496: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__n' - possible side-effects?
#1496: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:33:
+#define REG_BIT8(__n) \
+ ((u8)(BIT(__n) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
+ ((__n) < 0 || (__n) > 7))))
-:1517: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__high' - possible side-effects?
#1517: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:77:
+#define REG_GENMASK8(__high, __low) \
+ ((u8)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || (__high) > 7 || (__low) > (__high)))))
-:1517: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__low' - possible side-effects?
#1517: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:77:
+#define REG_GENMASK8(__high, __low) \
+ ((u8)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || (__high) > 7 || (__low) > (__high)))))
-:1540: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__mask' - possible side-effects?
#1540: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:115:
+#define REG_FIELD_PREP8(__mask, __val) \
+ ((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) + \
+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-:1540: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__val' - possible side-effects?
#1540: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:115:
+#define REG_FIELD_PREP8(__mask, __val) \
+ ((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) + \
+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-:1545: WARNING:LONG_LINE: line length of 128 exceeds 100 columns
#1545: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:120:
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
total: 0 errors, 22 warnings, 8 checks, 1442 lines checked
0d826c400a1a drm/i915/mtl: Add C10 phy programming for HDMI
-:207: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#207: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:662:
+ drm_dbg_kms(&i915->drm, "Can't support HDMI link rate %d on phy %c.\n",
+ crtc_state->port_clock, phy_name(phy));
total: 0 errors, 0 warnings, 1 checks, 272 lines checked
4d111ad8c2f0 drm/i915/mtl: Add vswing programming for C10 phys
-:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#6:
C10 phys uses direct mapping internally for voltage and pre-emphasis levels.
-:139: WARNING:IF_0: Consider removing the code enclosed by this #if 0 and its #endif
#139: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:325:
+#if 0
-:145: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#145: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:331:
+ C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_UPDATE_CFG, C10_VDR_CTRL_UPDATE_CFG,
-:145: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#145: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:331:
+ intel_cx0_rmw(i915, encoder->port, !master_lane, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_UPDATE_CFG, C10_VDR_CTRL_UPDATE_CFG,
-:326: WARNING:REPEATED_WORD: Possible repeated word: 'to'
#326: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1040:
+ * Some platforms don't need a mapping table and only expect us to
+ * to program the vswing + preemphasis levels directly since the
-:330: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#330: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1044:
+ { .direct = { .level = 0, .preemph = 0 } },$
-:331: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#331: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1045:
+ { .direct = { .level = 0, .preemph = 1 } },$
-:332: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#332: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1046:
+ { .direct = { .level = 0, .preemph = 2 } },$
-:333: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#333: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1047:
+ { .direct = { .level = 0, .preemph = 3 } },$
-:334: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#334: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1048:
+ { .direct = { .level = 1, .preemph = 0 } },$
-:335: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#335: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1049:
+ { .direct = { .level = 1, .preemph = 0 } },$
-:336: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#336: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1050:
+ { .direct = { .level = 1, .preemph = 2 } },$
-:337: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#337: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1051:
+ { .direct = { .level = 2, .preemph = 0 } },$
-:338: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#338: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1052:
+ { .direct = { .level = 2, .preemph = 1 } },$
-:339: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#339: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1053:
+ { .direct = { .level = 3, .preemph = 0 } },$
total: 0 errors, 14 warnings, 1 checks, 345 lines checked
e9473def4708 drm/i915/mtl: Add support for PM DEMAND
-:154: ERROR:CODE_INDENT: code indent should use tabs where possible
#154: FILE: drivers/gpu/drm/i915/i915_drv.h:272:
+ struct {$
-:154: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#154: FILE: drivers/gpu/drm/i915/i915_drv.h:272:
+ struct {$
-:163: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment
#163: FILE: drivers/gpu/drm/i915/i915_drv.h:281:
+ struct mutex lock;
-:239: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#239: FILE: drivers/gpu/drm/i915/i915_reg.h:5672:
+#define XELPDP_PMDEMAND_QCLK_GV_BW(x) REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, x)
-:241: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#241: FILE: drivers/gpu/drm/i915/i915_reg.h:5674:
+#define XELPDP_PMDEMAND_VOLTAGE_INDEX(x) REG_FIELD_PREP(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, x)
-:243: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#243: FILE: drivers/gpu/drm/i915/i915_reg.h:5676:
+#define XELPDP_PMDEMAND_QCLK_GV_INDEX(x) REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, x)
-:245: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#245: FILE: drivers/gpu/drm/i915/i915_reg.h:5678:
+#define XELPDP_PMDEMAND_PIPES(x) REG_FIELD_PREP(XELPDP_PMDEMAND_PIPES_MASK, x)
-:247: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#247: FILE: drivers/gpu/drm/i915/i915_reg.h:5680:
+#define XELPDP_PMDEMAND_DBUFS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_DBUFS_MASK, x)
-:249: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#249: FILE: drivers/gpu/drm/i915/i915_reg.h:5682:
+#define XELPDP_PMDEMAND_PHYS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_PHYS_MASK, x)
-:253: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#253: FILE: drivers/gpu/drm/i915/i915_reg.h:5686:
+#define XELPDP_PMDEMAND_CDCLK_FREQ(x) REG_FIELD_PREP(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, x)
-:255: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#255: FILE: drivers/gpu/drm/i915/i915_reg.h:5688:
+#define XELPDP_PMDEMAND_DDICLK_FREQ(x) REG_FIELD_PREP(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, x)
-:257: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#257: FILE: drivers/gpu/drm/i915/i915_reg.h:5690:
+#define XELPDP_PMDEMAND_SCALERS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_SCALERS_MASK, x)
-:429: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#429: FILE: drivers/gpu/drm/i915/intel_pm.c:4244:
+ return !((intel_de_read(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) & XELPDP_PMDEMAND_REQ_ENABLE) ||
-:435: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#435: FILE: drivers/gpu/drm/i915/intel_pm.c:4250:
+ return !(intel_de_read(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) & XELPDP_PMDEMAND_REQ_ENABLE);
-:484: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'val' - possible side-effects?
#484: FILE: drivers/gpu/drm/i915/intel_pm.c:4299:
+#define UPDATE_PMDEMAND_VAL(val, F, f) do { \
+ val &= (~(XELPDP_PMDEMAND_##F##_MASK)); \
+ val |= (XELPDP_PMDEMAND_##F((u32)(old ? max(old->f, new->f) : new->f))); \
+} while (0)
-:484: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'val' may be better as '(val)' to avoid precedence issues
#484: FILE: drivers/gpu/drm/i915/intel_pm.c:4299:
+#define UPDATE_PMDEMAND_VAL(val, F, f) do { \
+ val &= (~(XELPDP_PMDEMAND_##F##_MASK)); \
+ val |= (XELPDP_PMDEMAND_##F((u32)(old ? max(old->f, new->f) : new->f))); \
+} while (0)
-:484: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'f' - possible side-effects?
#484: FILE: drivers/gpu/drm/i915/intel_pm.c:4299:
+#define UPDATE_PMDEMAND_VAL(val, F, f) do { \
+ val &= (~(XELPDP_PMDEMAND_##F##_MASK)); \
+ val |= (XELPDP_PMDEMAND_##F((u32)(old ? max(old->f, new->f) : new->f))); \
+} while (0)
-:484: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'f' may be better as '(f)' to avoid precedence issues
#484: FILE: drivers/gpu/drm/i915/intel_pm.c:4299:
+#define UPDATE_PMDEMAND_VAL(val, F, f) do { \
+ val &= (~(XELPDP_PMDEMAND_##F##_MASK)); \
+ val |= (XELPDP_PMDEMAND_##F((u32)(old ? max(old->f, new->f) : new->f))); \
+} while (0)
-:616: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'state' - possible side-effects?
#616: FILE: drivers/gpu/drm/i915/intel_pm.h:57:
+#define intel_atomic_get_old_pmdemand_state(state) \
+ to_intel_pmdemand_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->pmdemand.obj))
-:617: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#617: FILE: drivers/gpu/drm/i915/intel_pm.h:58:
+ to_intel_pmdemand_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->pmdemand.obj))
-:618: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'state' - possible side-effects?
#618: FILE: drivers/gpu/drm/i915/intel_pm.h:59:
+#define intel_atomic_get_new_pmdemand_state(state) \
+ to_intel_pmdemand_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->pmdemand.obj))
-:619: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#619: FILE: drivers/gpu/drm/i915/intel_pm.h:60:
+ to_intel_pmdemand_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->pmdemand.obj))
-:628: ERROR:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Mika Kahola <mika.kahola@intel.com>'
total: 2 errors, 14 warnings, 7 checks, 546 lines checked
5035128585f4 drm/i915/mtl: C20 PLL programming
-:189: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#189: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1041:
+ intel_c20_write(i915, encoder->port, 0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0);
-:196: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#196: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1048:
+ intel_c20_write(i915, encoder->port, 0, PHY_C20_A_TX_CNTX_CFG(i), pll_state->tx[i]);
-:198: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#198: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1050:
+ intel_c20_write(i915, encoder->port, 0, PHY_C20_B_TX_CNTX_CFG(i), pll_state->tx[i]);
-:204: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#204: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1056:
+ intel_c20_write(i915, encoder->port, 0, PHY_C20_A_CMN_CNTX_CFG(i), pll_state->cmn[i]);
-:206: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#206: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1058:
+ intel_c20_write(i915, encoder->port, 0, PHY_C20_B_CMN_CNTX_CFG(i), pll_state->cmn[i]);
-:240: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#240: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1092:
+ intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE1, PHY_C20_VDR_CUSTOM_WIDTH,
-:249: CHECK:BRACES: Unbalanced braces around else statement
#249: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1101:
+ } else
-:255: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#255: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1107:
+ intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE,
-:259: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#259: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1111:
+ intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE1, PHY_C20_VDR_CUSTOM_SERDES_RATE,
-:263: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#263: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1115:
+ intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_CUSTOM_SERDES_RATE,
-:279: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#279: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1131:
+ intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE1, PHY_C20_VDR_CUSTOM_SERDES_RATE,
-:459: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#459: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:3506:
+ crtc_state->port_clock = intel_c10mpllb_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10mpllb_state);
total: 0 errors, 11 warnings, 1 checks, 479 lines checked
d597de60b7b7 drm/i915/mtl: C20 HW readout
-:33: ERROR:CODE_INDENT: code indent should use tabs where possible
#33: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:252:
+ int lane, u16 addr)$
-:33: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#33: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:252:
+ int lane, u16 addr)$
-:35: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#35: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:254:
+ u16 val;$
-:37: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#37: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:256:
+ assert_dc_off(i915);$
-:39: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#39: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:258:
+ intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 0);$
-:40: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#40: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:259:
+ intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_H, (addr >> 8) & 0xff, 1);$
-:42: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#42: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:261:
+ val = intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_H);$
-:43: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#43: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:262:
+ val <<= 8;$
-:44: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#44: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:263:
+ val |= intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_L);$
-:46: ERROR:CODE_INDENT: code indent should use tabs where possible
#46: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:265:
+ return val;$
-:46: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#46: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:265:
+ return val;$
-:232: ERROR:CODE_INDENT: code indent should use tabs where possible
#232: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:789:
+ &mtl_c20_dp_rbr,$
-:232: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#232: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:789:
+ &mtl_c20_dp_rbr,$
-:233: ERROR:CODE_INDENT: code indent should use tabs where possible
#233: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:790:
+ &mtl_c20_dp_hbr1,$
-:233: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#233: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:790:
+ &mtl_c20_dp_hbr1,$
-:234: ERROR:CODE_INDENT: code indent should use tabs where possible
#234: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:791:
+ &mtl_c20_dp_hbr2,$
-:234: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#234: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:791:
+ &mtl_c20_dp_hbr2,$
-:235: ERROR:CODE_INDENT: code indent should use tabs where possible
#235: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:792:
+ &mtl_c20_dp_hbr3,$
-:235: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#235: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:792:
+ &mtl_c20_dp_hbr3,$
-:239: ERROR:CODE_INDENT: code indent should use tabs where possible
#239: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:796:
+ NULL,$
-:239: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#239: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:796:
+ NULL,$
-:452: ERROR:CODE_INDENT: code indent should use tabs where possible
#452: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1314:
+ const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables;$
-:452: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#452: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1314:
+ const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables;$
-:453: ERROR:CODE_INDENT: code indent should use tabs where possible
#453: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1315:
+ int i;$
-:453: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#453: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1315:
+ int i;$
-:455: ERROR:CODE_INDENT: code indent should use tabs where possible
#455: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1317:
+ for (i = 0; tables[i]; i++) {$
-:455: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#455: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1317:
+ for (i = 0; tables[i]; i++) {$
-:456: ERROR:CODE_INDENT: code indent should use tabs where possible
#456: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1318:
+ if (clock == tables[i]->clock)$
-:456: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#456: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1318:
+ if (clock == tables[i]->clock)$
-:457: ERROR:CODE_INDENT: code indent should use tabs where possible
#457: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1319:
+ return MODE_OK;$
-:457: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#457: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1319:
+ return MODE_OK;$
-:458: ERROR:CODE_INDENT: code indent should use tabs where possible
#458: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1320:
+ }$
-:458: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#458: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1320:
+ }$
-:460: ERROR:CODE_INDENT: code indent should use tabs where possible
#460: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1322:
+ return MODE_CLOCK_RANGE;$
-:460: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#460: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1322:
+ return MODE_CLOCK_RANGE;$
-:467: WARNING:BRACES: braces {} are not necessary for any arm of this statement
#467: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1329:
+ if (intel_crtc_has_dp_encoder(crtc_state)) {
[...]
+ } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
[...]
-:478: ERROR:CODE_INDENT: code indent should use tabs where possible
#478: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1340:
+^I struct intel_encoder *encoder)$
-:478: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#478: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1340:
+int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
-:512: ERROR:CODE_INDENT: code indent should use tabs where possible
#512: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1376:
+ /* 1. Read current context selection */$
-:513: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#513: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1377:
+ cntx = intel_cx0_read(i915, encoder->port, 0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;
-:513: ERROR:CODE_INDENT: code indent should use tabs where possible
#513: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1377:
+ cntx = intel_cx0_read(i915, encoder->port, 0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;$
-:513: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#513: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1377:
+ cntx = intel_cx0_read(i915, encoder->port, 0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;$
-:575: ERROR:CODE_INDENT: code indent should use tabs where possible
#575: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.h:39:
+ struct intel_c20pll_state *pll_state);$
-:575: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#575: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.h:39:
+ struct intel_c20pll_state *pll_state);$
total: 18 errors, 25 warnings, 1 checks, 600 lines checked
a3d8325cce42 drm/i915/mtl: C20 port clock calculation
-:50: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#50: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:1669:
+ }$
-:81: WARNING:LONG_LINE: line length of 123 exceeds 100 columns
#81: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:3505:
+ crtc_state->port_clock = intel_c10mpllb_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10mpllb_state);
-:84: WARNING:LONG_LINE: line length of 119 exceeds 100 columns
#84: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:3508:
+ crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder, &crtc_state->cx0pll_state.c20pll_state);
total: 0 errors, 3 warnings, 0 checks, 66 lines checked
895f024ecb44 drm/i915/mtl: C20 HDMI state calculations
2be28e185747 drm/i915/mtl: Add voltage swing sequence for C20
-:40: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#40: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:354:
+ C20_PHY_VSWING_PREEMPH(trans->entries[level].snps.post_cursor),
total: 0 errors, 1 warnings, 0 checks, 103 lines checked
57ad27362fd8 drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA
4a4dbdf3bd62 drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll
-:54: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#54: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2043:
+ }$
total: 0 errors, 1 warnings, 0 checks, 189 lines checked
d553525ce876 drm/i915/mtl: Readout Thunderbolt HW state
-:42: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#42: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2053:
+ }$
total: 0 errors, 1 warnings, 0 checks, 51 lines checked
42dc73e57c8e drm/i915/mtl: Enable TC ports
8cb2db71ab71 drm/i915/mtl: MTL PICA hotplug detection
-:53: CHECK:LINE_SPACING: Please don't use multiple blank lines
#53: FILE: drivers/gpu/drm/i915/i915_irq.c:202:
+
+
-:235: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#235: FILE: drivers/gpu/drm/i915/i915_irq.c:3607:
+
+}
total: 0 errors, 0 warnings, 2 checks, 353 lines checked
507382c65d05 drm/i915/mtl: Define mask for DDI AUX interrupts
24b5d50c8990 drm/i915/mtl: Power up TCSS
bd30536c462b drm/i915/mtl: Pin assignment for TypeC
-:47: ERROR:SPACING: space required before the open parenthesis '('
#47: FILE: drivers/gpu/drm/i915/display/intel_tc.c:167:
+ switch(pin_mask) {
total: 1 errors, 0 warnings, 0 checks, 48 lines checked
^ permalink raw reply [flat|nested] 36+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: Add C10 and C20 phy support
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (20 preceding siblings ...)
2022-10-14 13:11 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Add C10 and C20 phy support Patchwork
@ 2022-10-14 13:11 ` Patchwork
2022-10-14 13:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (3 subsequent siblings)
25 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2022-10-14 13:11 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/mtl: Add C10 and C20 phy support
URL : https://patchwork.freedesktop.org/series/109714/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 36+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Add C10 and C20 phy support
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (21 preceding siblings ...)
2022-10-14 13:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-10-14 13:34 ` Patchwork
2022-10-14 14:50 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
` (2 subsequent siblings)
25 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2022-10-14 13:34 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 9627 bytes --]
== Series Details ==
Series: drm/i915/mtl: Add C10 and C20 phy support
URL : https://patchwork.freedesktop.org/series/109714/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12242 -> Patchwork_109714v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/index.html
Participating hosts (45 -> 44)
------------------------------
Additional (3): fi-tgl-u2 bat-atsm-1 fi-pnv-d510
Missing (4): fi-ilk-m540 fi-kbl-x1275 bat-jsl-1 fi-hsw-4200u
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_109714v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@reset:
- {bat-rpls-1}: [DMESG-FAIL][1] ([i915#4983]) -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/bat-rpls-1/igt@i915_selftest@live@reset.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/bat-rpls-1/igt@i915_selftest@live@reset.html
* igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-3:
- {bat-dg2-11}: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-3.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-3.html
Known issues
------------
Here are the changes found in Patchwork_109714v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-tgl-u2: NOTRUN -> [SKIP][5] ([i915#2190])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/fi-tgl-u2/igt@gem_huc_copy@huc-copy.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-tgl-u2: NOTRUN -> [SKIP][6] ([fdo#109284] / [fdo#111827]) +7 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/fi-tgl-u2/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-tgl-u2: NOTRUN -> [SKIP][7] ([i915#4103])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/fi-tgl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-u2: NOTRUN -> [SKIP][8] ([fdo#109285])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/fi-tgl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_psr@primary_page_flip:
- fi-pnv-d510: NOTRUN -> [SKIP][9] ([fdo#109271]) +43 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/fi-pnv-d510/igt@kms_psr@primary_page_flip.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-tgl-u2: NOTRUN -> [SKIP][10] ([i915#3555])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/fi-tgl-u2/igt@kms_setmode@basic-clone-single-crtc.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@lmem0:
- {bat-dg2-11}: [DMESG-WARN][11] ([i915#6816]) -> [PASS][12] +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/bat-dg2-11/igt@gem_exec_suspend@basic-s0@lmem0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/bat-dg2-11/igt@gem_exec_suspend@basic-s0@lmem0.html
* igt@i915_module_load@reload:
- {bat-rpls-2}: [DMESG-WARN][13] ([i915#5537]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/bat-rpls-2/igt@i915_module_load@reload.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/bat-rpls-2/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@basic-rte:
- {bat-rplp-1}: [DMESG-WARN][15] ([i915#7077]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/bat-rplp-1/igt@i915_pm_rpm@basic-rte.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/bat-rplp-1/igt@i915_pm_rpm@basic-rte.html
* igt@i915_pm_rpm@module-reload:
- {fi-tgl-mst}: [DMESG-WARN][17] ([i915#5537]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/fi-tgl-mst/igt@i915_pm_rpm@module-reload.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/fi-tgl-mst/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@reset:
- {bat-rpls-2}: [DMESG-FAIL][19] ([i915#4983]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/bat-rpls-2/igt@i915_selftest@live@reset.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/bat-rpls-2/igt@i915_selftest@live@reset.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka: [FAIL][21] ([i915#6298]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-dp-3:
- {bat-dg2-11}: [FAIL][23] ([i915#6818]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-dp-3.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-dp-3.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5278]: https://gitlab.freedesktop.org/drm/intel/issues/5278
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6559]: https://gitlab.freedesktop.org/drm/intel/issues/6559
[i915#6596]: https://gitlab.freedesktop.org/drm/intel/issues/6596
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6816]: https://gitlab.freedesktop.org/drm/intel/issues/6816
[i915#6818]: https://gitlab.freedesktop.org/drm/intel/issues/6818
[i915#7029]: https://gitlab.freedesktop.org/drm/intel/issues/7029
[i915#7030]: https://gitlab.freedesktop.org/drm/intel/issues/7030
[i915#7031]: https://gitlab.freedesktop.org/drm/intel/issues/7031
[i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
Build changes
-------------
* Linux: CI_DRM_12242 -> Patchwork_109714v1
CI-20190529: 20190529
CI_DRM_12242: 075a81b1efd29300194bdf7877e08b6dbe3079d9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7012: ca6f5bdd537d26692c4b1ca011b8c4f227d95703 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_109714v1: 075a81b1efd29300194bdf7877e08b6dbe3079d9 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
4741dedba5a6 drm/i915/mtl: Pin assignment for TypeC
070326bc736c drm/i915/mtl: Power up TCSS
ec5f05446388 drm/i915/mtl: Define mask for DDI AUX interrupts
0fa5ddba0476 drm/i915/mtl: MTL PICA hotplug detection
6002f2998c09 drm/i915/mtl: Enable TC ports
8fb8d0dbc7dd drm/i915/mtl: Readout Thunderbolt HW state
ccc1e99a8db7 drm/i915/mtl: Enabling/disabling sequence Thunderbolt pll
87fbab473255 drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA
ef5c683f4906 drm/i915/mtl: Add voltage swing sequence for C20
2fa0f5d8252a drm/i915/mtl: C20 HDMI state calculations
7d3092617045 drm/i915/mtl: C20 port clock calculation
3d61a66bad51 drm/i915/mtl: C20 HW readout
a6ad0b3e3093 drm/i915/mtl: C20 PLL programming
61e3d9be3776 drm/i915/mtl: Add support for PM DEMAND
9a45e057d8eb drm/i915/mtl: Add vswing programming for C10 phys
6c1ccfaefb87 drm/i915/mtl: Add C10 phy programming for HDMI
f36ddc622f42 drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
8688dd8ab069 drm/i915/mtl: Create separate reg file for PICA registers
de70a43fc944 drm/i915/mtl: Add DP rates
b8b3034990a8 drm/i915/mtl: Initial DDI port setup
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/index.html
[-- Attachment #2: Type: text/html, Size: 9653 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/mtl: Add C10 and C20 phy support
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (22 preceding siblings ...)
2022-10-14 13:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-10-14 14:50 ` Patchwork
2022-10-31 21:49 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/mtl: Add C10 and C20 phy support (rev2) Patchwork
2022-11-01 7:55 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/mtl: Add C10 and C20 phy support (rev3) Patchwork
25 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2022-10-14 14:50 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 36404 bytes --]
== Series Details ==
Series: drm/i915/mtl: Add C10 and C20 phy support
URL : https://patchwork.freedesktop.org/series/109714/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12242_full -> Patchwork_109714v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (9 -> 11)
------------------------------
Additional (2): shard-rkl shard-dg1
Known issues
------------
Here are the changes found in Patchwork_109714v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [PASS][1] -> [FAIL][2] ([i915#6268])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-tglb2/igt@gem_ctx_exec@basic-nohangcheck.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-tglb7/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [PASS][3] -> [SKIP][4] ([i915#4525]) +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-iclb2/igt@gem_exec_balancer@parallel-keep-in-fence.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-iclb5/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][5] ([i915#2842])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-iclb2/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-iclb: [PASS][6] -> [FAIL][7] ([i915#2842])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-iclb8/igt@gem_exec_fair@basic-pace@vecs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-iclb3/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_lmem_swapping@heavy-random:
- shard-skl: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-skl1/igt@gem_lmem_swapping@heavy-random.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-skl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#3323])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-skl10/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-apl: [PASS][10] -> [DMESG-WARN][11] ([i915#180])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-apl3/igt@gem_workarounds@suspend-resume-fd.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-apl2/igt@gem_workarounds@suspend-resume-fd.html
* igt@i915_pipe_stress@stress-xrgb8888-untiled:
- shard-apl: NOTRUN -> [FAIL][12] ([i915#7036])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-apl2/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
- shard-skl: NOTRUN -> [FAIL][13] ([i915#7036])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-skl2/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
* igt@i915_pm_rc6_residency@rc6-idle@vecs0:
- shard-glk: [PASS][14] -> [DMESG-WARN][15] ([i915#118])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-glk9/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-glk1/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
* igt@kms_addfb_basic@legacy-format:
- shard-tglb: [PASS][16] -> [INCOMPLETE][17] ([i915#6987] / [i915#7190])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-tglb5/igt@kms_addfb_basic@legacy-format.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-tglb3/igt@kms_addfb_basic@legacy-format.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1:
- shard-skl: [PASS][18] -> [FAIL][19] ([i915#2521])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl10/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-skl4/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1.html
* igt@kms_atomic@plane-cursor-legacy:
- shard-snb: [PASS][20] -> [SKIP][21] ([fdo#109271])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-snb4/igt@kms_atomic@plane-cursor-legacy.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-snb4/igt@kms_atomic@plane-cursor-legacy.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#3886]) +2 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-skl1/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#3886]) +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-apl2/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html
- shard-glk: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#3886])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-glk3/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_dg2_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][25] ([fdo#109271]) +52 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-apl2/igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs:
- shard-glk: NOTRUN -> [SKIP][26] ([fdo#109271]) +27 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-glk3/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs.html
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-apl: NOTRUN -> [SKIP][27] ([fdo#109271] / [fdo#111827]) +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-apl2/igt@kms_chamelium@hdmi-hpd-storm.html
- shard-glk: NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-glk3/igt@kms_chamelium@hdmi-hpd-storm.html
* igt@kms_chamelium@hdmi-hpd-with-enabled-mode:
- shard-skl: NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827]) +6 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-skl2/igt@kms_chamelium@hdmi-hpd-with-enabled-mode.html
* igt@kms_color@ctm-0-25:
- shard-skl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3546])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-skl1/igt@kms_color@ctm-0-25.html
* igt@kms_cursor_crc@cursor-suspend@pipe-c-edp-1:
- shard-skl: [PASS][31] -> [INCOMPLETE][32] ([i915#4939] / [i915#7192])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl7/igt@kms_cursor_crc@cursor-suspend@pipe-c-edp-1.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-skl7/igt@kms_cursor_crc@cursor-suspend@pipe-c-edp-1.html
* igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic:
- shard-glk: [PASS][33] -> [FAIL][34] ([i915#2346])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][35] -> [INCOMPLETE][36] ([i915#180] / [i915#4939])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-apl3/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: NOTRUN -> [FAIL][37] ([i915#4767])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-skl10/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-skl: [PASS][38] -> [FAIL][39] ([i915#2122])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][40] ([i915#2587] / [i915#2672])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-iclb5/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][41] ([i915#2672]) +8 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-skl: NOTRUN -> [SKIP][42] ([fdo#109271]) +144 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-skl1/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-dp-1:
- shard-apl: NOTRUN -> [FAIL][43] ([i915#4573]) +2 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-apl2/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-dp-1.html
* igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-b-edp-1:
- shard-skl: NOTRUN -> [FAIL][44] ([i915#4573]) +2 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-skl2/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-b-edp-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1:
- shard-iclb: [PASS][45] -> [SKIP][46] ([i915#5235]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-iclb3/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-skl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#658]) +2 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-skl10/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][48] -> [SKIP][49] ([fdo#109441]) +3 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_vblank@pipe-c-query-forked:
- shard-skl: [PASS][50] -> [DMESG-WARN][51] ([i915#1982])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl9/igt@kms_vblank@pipe-c-query-forked.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-skl9/igt@kms_vblank@pipe-c-query-forked.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-skl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#2437])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-skl1/igt@kms_writeback@writeback-invalid-parameters.html
* igt@sysfs_clients@create:
- shard-apl: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#2994])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-apl2/igt@sysfs_clients@create.html
- shard-skl: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#2994])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-skl2/igt@sysfs_clients@create.html
#### Possible fixes ####
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [SKIP][55] ([i915#4525]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-iclb5/igt@gem_exec_balancer@parallel-balancer.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-iclb1/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][57] ([i915#2846]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-glk7/igt@gem_exec_fair@basic-deadline.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-glk2/igt@gem_exec_fair@basic-deadline.html
* igt@gen9_exec_parse@allowed-all:
- shard-skl: [DMESG-WARN][59] ([i915#5566] / [i915#716]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl10/igt@gen9_exec_parse@allowed-all.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-skl2/igt@gen9_exec_parse@allowed-all.html
- shard-apl: [DMESG-WARN][61] ([i915#5566] / [i915#716]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-apl2/igt@gen9_exec_parse@allowed-all.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-apl2/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [SKIP][63] ([i915#4281]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-iclb1/igt@i915_pm_dc@dc9-dpms.html
* igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic:
- shard-skl: [FAIL][65] ([i915#2346]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][67] ([i915#2122]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-glk8/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-glk8/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1:
- shard-apl: [DMESG-WARN][69] ([i915#180]) -> [PASS][70] +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-apl3/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-apl2/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1:
- shard-iclb: [SKIP][71] ([i915#5235]) -> [PASS][72] +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-iclb5/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][73] ([fdo#109441]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-iclb3/igt@kms_psr@psr2_cursor_mmap_cpu.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@perf@polling-parameterized:
- shard-skl: [FAIL][75] ([i915#5639]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl10/igt@perf@polling-parameterized.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-skl4/igt@perf@polling-parameterized.html
* igt@perf@stress-open-close:
- shard-glk: [INCOMPLETE][77] ([i915#5213]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-glk1/igt@perf@stress-open-close.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-glk3/igt@perf@stress-open-close.html
#### Warnings ####
* igt@dmabuf@all@dma_fence_chain:
- shard-skl: [INCOMPLETE][79] ([i915#6949] / [i915#7165]) -> [INCOMPLETE][80] ([i915#6949] / [i915#7065] / [i915#7165] / [i915#7192])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl6/igt@dmabuf@all@dma_fence_chain.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-skl5/igt@dmabuf@all@dma_fence_chain.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][81] ([i915#4525]) -> [FAIL][82] ([i915#6117])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-iclb3/igt@gem_exec_balancer@parallel-ordering.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_fair@basic-none@bcs0:
- shard-tglb: [FAIL][83] ([i915#2842]) -> [SKIP][84] ([i915#2848]) +6 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-tglb2/igt@gem_exec_fair@basic-none@bcs0.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-tglb2/igt@gem_exec_fair@basic-none@bcs0.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-apl: [SKIP][85] ([fdo#109271]) -> [SKIP][86] ([fdo#109271] / [i915#7206])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-apl7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-apl8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
- shard-glk: [SKIP][87] ([fdo#109271]) -> [SKIP][88] ([fdo#109271] / [i915#7206])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-glk9/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-glk1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-glk: [SKIP][89] ([fdo#109271]) -> [SKIP][90] ([fdo#109271] / [i915#7205])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-glk9/igt@kms_dsc@dsc-with-bpc-formats.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-glk1/igt@kms_dsc@dsc-with-bpc-formats.html
- shard-apl: [SKIP][91] ([fdo#109271]) -> [SKIP][92] ([fdo#109271] / [i915#7205])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-apl7/igt@kms_dsc@dsc-with-bpc-formats.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-apl8/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-default-mode:
- shard-skl: [SKIP][93] ([fdo#109271]) -> [SKIP][94] ([fdo#109271] / [i915#7207])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-skl9/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-default-mode.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-skl6/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-iclb: [SKIP][95] ([i915#658]) -> [SKIP][96] ([i915#2920])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-iclb1/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf:
- shard-iclb: [SKIP][97] ([i915#2920]) -> [SKIP][98] ([i915#658]) +1 similar issue
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-iclb5/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][99] ([i915#2920]) -> [SKIP][100] ([fdo#111068] / [i915#658])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-iclb5/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-iclb: [SKIP][101] ([fdo#111068] / [i915#658]) -> [SKIP][102] ([i915#2920])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-iclb6/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@runner@aborted:
- shard-apl: ([FAIL][103], [FAIL][104], [FAIL][105], [FAIL][106], [FAIL][107]) ([fdo#109271] / [i915#3002] / [i915#4312]) -> ([FAIL][108], [FAIL][109], [FAIL][110]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-apl3/igt@runner@aborted.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-apl3/igt@runner@aborted.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-apl6/igt@runner@aborted.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-apl2/igt@runner@aborted.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12242/shard-apl8/igt@runner@aborted.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-apl6/igt@runner@aborted.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-apl3/igt@runner@aborted.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/shard-apl2/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110254]: https://bugs.freedesktop.org/show_bug.cgi?id=110254
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2232]: https://gitlab.freedesktop.org/drm/intel/issues/2232
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2848]: https://gitlab.freedesktop.org/drm/intel/issues/2848
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
[i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6251]: https://gitlab.freedesktop.org/drm/intel/issues/6251
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#6355]: https://gitlab.freedesktop.org/drm/intel/issues/6355
[i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6463]: https://gitlab.freedesktop.org/drm/intel/issues/6463
[i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6949]: https://gitlab.freedesktop.org/drm/intel/issues/6949
[i915#6987]: https://gitlab.freedesktop.org/drm/intel/issues/6987
[i915#7036]: https://gitlab.freedesktop.org/drm/intel/issues/7036
[i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
[i915#7065]: https://gitlab.freedesktop.org/drm/intel/issues/7065
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#7165]: https://gitlab.freedesktop.org/drm/intel/issues/7165
[i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178
[i915#7190]: https://gitlab.freedesktop.org/drm/intel/issues/7190
[i915#7192]: https://gitlab.freedesktop.org/drm/intel/issues/7192
[i915#7205]: https://gitlab.freedesktop.org/drm/intel/issues/7205
[i915#7206]: https://gitlab.freedesktop.org/drm/intel/issues/7206
[i915#7207]: https://gitlab.freedesktop.org/drm/intel/issues/7207
Build changes
-------------
* Linux: CI_DRM_12242 -> Patchwork_109714v1
CI-20190529: 20190529
CI_DRM_12242: 075a81b1efd29300194bdf7877e08b6dbe3079d9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7012: ca6f5bdd537d26692c4b1ca011b8c4f227d95703 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_109714v1: 075a81b1efd29300194bdf7877e08b6dbe3079d9 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_109714v1/index.html
[-- Attachment #2: Type: text/html, Size: 33451 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread* [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/mtl: Add C10 and C20 phy support (rev2)
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (23 preceding siblings ...)
2022-10-14 14:50 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2022-10-31 21:49 ` Patchwork
2022-11-01 7:55 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/mtl: Add C10 and C20 phy support (rev3) Patchwork
25 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2022-10-31 21:49 UTC (permalink / raw)
To: Taylor, Clinton A; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/mtl: Add C10 and C20 phy support (rev2)
URL : https://patchwork.freedesktop.org/series/109714/
State : failure
== Summary ==
Error: patch https://patchwork.freedesktop.org/api/1.0/series/109714/revisions/2/mbox/ not applied
warning: quoted CRLF detected
Applying: drm/i915/mtl: Initial DDI port setup
Applying: drm/i915/mtl: Add DP rates
Applying: drm/i915/mtl: Create separate reg file for PICA registers
Applying: drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
Applying: drm/i915/mtl: Add C10 phy programming for HDMI
Applying: drm/i915/mtl: Add vswing programming for C10 phys
error: corrupt patch at line 30
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0006 drm/i915/mtl: Add vswing programming for C10 phys
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
^ permalink raw reply [flat|nested] 36+ messages in thread* [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/mtl: Add C10 and C20 phy support (rev3)
2022-10-14 12:47 [Intel-gfx] [PATCH 00/20] drm/i915/mtl: Add C10 and C20 phy support Mika Kahola
` (24 preceding siblings ...)
2022-10-31 21:49 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/mtl: Add C10 and C20 phy support (rev2) Patchwork
@ 2022-11-01 7:55 ` Patchwork
25 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2022-11-01 7:55 UTC (permalink / raw)
To: Kahola, Mika; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/mtl: Add C10 and C20 phy support (rev3)
URL : https://patchwork.freedesktop.org/series/109714/
State : failure
== Summary ==
Error: patch https://patchwork.freedesktop.org/api/1.0/series/109714/revisions/3/mbox/ not applied
warning: quoted CRLF detected
Applying: drm/i915/mtl: Initial DDI port setup
Applying: drm/i915/mtl: Add DP rates
Applying: drm/i915/mtl: Create separate reg file for PICA registers
Applying: drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
Applying: drm/i915/mtl: Add C10 phy programming for HDMI
Applying: drm/i915/mtl: Add vswing programming for C10 phys
error: corrupt patch at line 30
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0006 drm/i915/mtl: Add vswing programming for C10 phys
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
^ permalink raw reply [flat|nested] 36+ messages in thread