[PATCH 1/2] drm/i915: Apply B-spec mandated workaround for read flushes on Ironlake.

[PATCH 1/2] drm/i915: Apply B-spec mandated workaround for read flushes on Ironlake.

[Eric Anholt]

This is not known to fix any particular bugs we have, but the spec
says to do it, and the BIOS hadn't already set it up on my system.

Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/i915_reg.h      |   13 +++++++++++++
 drivers/gpu/drm/i915/intel_display.c |    6 ++++++
 2 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 25ed911..f338499 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -306,6 +306,19 @@
 #define NOPID		0x02094
 #define HWSTAM		0x02098
 
+/* GM45+ chicken bits -- debug workaround bits that may be required
+ * for various sorts of correct behavior.  The top 16 bits of each are
+ * the enables for writing to the corresponding low bit.
+ */
+#define _3D_CHICKEN	0x02084
+#define _3D_CHICKEN2	0x0208c
+/* Disables pipelining of read flushes past the SF-WIZ interface.
+ * Required on all Ironlake steppings according to the B-Spec, but the
+ * particular danger of not doing so is not specified.
+ */
+# define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
+#define _3D_CHICKEN3	0x02090
+
 #define MI_MODE		0x0209c
 # define VS_TIMER_DISPATCH				(1 << 6)
 # define MI_FLUSH_ENABLE				(1 << 11)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 48d8fd6..360f17d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5812,6 +5812,12 @@ void intel_init_clock_gating(struct drm_device *dev)
 				   ILK_DPFC_DIS2 |
 				   ILK_CLK_FBC);
 		}
+
+		if (IS_GEN5(dev)) {
+			I915_WRITE(_3D_CHICKEN2,
+				   _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
+				   _3D_CHICKEN2_WM_READ_PIPELINED);
+		}
 		return;
 	} else if (IS_G4X(dev)) {
 		uint32_t dspclk_gate;
-- 
1.7.2.3

[PATCH 2/2] drm/i915: Apply display workaround required according to the B-Spec.

[Eric Anholt]

Not known to fix any current bugs.

Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/i915_reg.h      |    2 ++
 drivers/gpu/drm/i915/intel_display.c |    4 ++++
 2 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f338499..308f0a9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2599,6 +2599,8 @@
 #define GTIER   0x4401c
 
 #define ILK_DISPLAY_CHICKEN2	0x42004
+/* Required on all Ironlake and Sandybridge according to the B-Spec. */
+#define  ILK_ELPIN_409_SELECT	(1 << 25)
 #define  ILK_DPARB_GATE	(1<<22)
 #define  ILK_VSDPFD_FULL	(1<<21)
 #define ILK_DSPCLK_GATE		0x42020
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 360f17d..8f564ce 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5813,6 +5813,10 @@ void intel_init_clock_gating(struct drm_device *dev)
 				   ILK_CLK_FBC);
 		}
 
+		I915_WRITE(ILK_DISPLAY_CHICKEN2,
+			   I915_READ(ILK_DISPLAY_CHICKEN2) |
+			   ILK_ELPIN_409_SELECT);
+
 		if (IS_GEN5(dev)) {
 			I915_WRITE(_3D_CHICKEN2,
 				   _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
-- 
1.7.2.3

Re: [PATCH 2/2] drm/i915: Apply display workaround required according to the B-Spec.

[Chris Wilson]

On Sat,  6 Nov 2010 14:53:33 -0700, Eric Anholt <eric@anholt.net> wrote:
> Not known to fix any current bugs.

If the specs warn us that dragons lie beneath, we should respect them.
Both applied to -fixes and cc'ed stable.

Thanks,
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 1/2] drm/i915: Apply B-spec mandated workaround for read flushes on Ironlake.

[Chris Wilson]

On Sat,  6 Nov 2010 14:53:32 -0700, Eric Anholt <eric@anholt.net> wrote:
> This is not known to fix any particular bugs we have, but the spec
> says to do it, and the BIOS hadn't already set it up on my system.

Whilst you haven't directly identified any bug caused by these two,
adhering to the spec sounds like a stability fix. Worth applying to -fixes
and CC'ing stable?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 1/2] drm/i915: Apply B-spec mandated workaround for read flushes on Ironlake.

[Eric Anholt]

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On Sat, 06 Nov 2010 22:07:40 +0000, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Sat,  6 Nov 2010 14:53:32 -0700, Eric Anholt <eric@anholt.net> wrote:
> > This is not known to fix any particular bugs we have, but the spec
> > says to do it, and the BIOS hadn't already set it up on my system.
> 
> Whilst you haven't directly identified any bug caused by these two,
> adhering to the spec sounds like a stability fix. Worth applying to -fixes
> and CC'ing stable?
> -Chris

I'd rather not unless we find that it does really fix someone.

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Re: [PATCH 1/2] drm/i915: Apply B-spec mandated workaround for read flushes on Ironlake.

[Chris Wilson]

On Mon, 08 Nov 2010 00:19:11 -0800, Eric Anholt <eric@anholt.net> wrote:
> I'd rather not unless we find that it does really fix someone.

Moved to -next instead.
Thanks!
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre