[PATCH 1/2] drm/i915: Apply B-spec mandated workaround for read flushes on Ironlake.

* [PATCH 1/2] drm/i915: Apply B-spec mandated workaround for read flushes on Ironlake.
@ 2010-11-06 21:53 Eric Anholt
  2010-11-06 21:53 ` [PATCH 2/2] drm/i915: Apply display workaround required according to the B-Spec Eric Anholt
  2010-11-06 22:07 ` [PATCH 1/2] drm/i915: Apply B-spec mandated workaround for read flushes on Ironlake Chris Wilson
  0 siblings, 2 replies; 6+ messages in thread
From: Eric Anholt @ 2010-11-06 21:53 UTC (permalink / raw)
  To: intel-gfx

This is not known to fix any particular bugs we have, but the spec
says to do it, and the BIOS hadn't already set it up on my system.

Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/i915/i915_reg.h      |   13 +++++++++++++
 drivers/gpu/drm/i915/intel_display.c |    6 ++++++
 2 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 25ed911..f338499 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -306,6 +306,19 @@
 #define NOPID		0x02094
 #define HWSTAM		0x02098
 
+/* GM45+ chicken bits -- debug workaround bits that may be required
+ * for various sorts of correct behavior.  The top 16 bits of each are
+ * the enables for writing to the corresponding low bit.
+ */
+#define _3D_CHICKEN	0x02084
+#define _3D_CHICKEN2	0x0208c
+/* Disables pipelining of read flushes past the SF-WIZ interface.
+ * Required on all Ironlake steppings according to the B-Spec, but the
+ * particular danger of not doing so is not specified.
+ */
+# define _3D_CHICKEN2_WM_READ_PIPELINED			(1 << 14)
+#define _3D_CHICKEN3	0x02090
+
 #define MI_MODE		0x0209c
 # define VS_TIMER_DISPATCH				(1 << 6)
 # define MI_FLUSH_ENABLE				(1 << 11)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 48d8fd6..360f17d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5812,6 +5812,12 @@ void intel_init_clock_gating(struct drm_device *dev)
 				   ILK_DPFC_DIS2 |
 				   ILK_CLK_FBC);
 		}
+
+		if (IS_GEN5(dev)) {
+			I915_WRITE(_3D_CHICKEN2,
+				   _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
+				   _3D_CHICKEN2_WM_READ_PIPELINED);
+		}
 		return;
 	} else if (IS_G4X(dev)) {
 		uint32_t dspclk_gate;
-- 
1.7.2.3

^ permalink raw reply related	[flat|nested] 6+ messages in thread