* [Intel-gfx] [PATCH 1/5] drm/i915/dp: Add helper to check DSC1.2 for HDMI2.1 DFP
2022-08-22 10:54 [Intel-gfx] [PATCH 0/5] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
@ 2022-08-22 10:54 ` Ankit Nautiyal
2022-08-23 11:02 ` Jani Nikula
2022-08-22 10:54 ` [Intel-gfx] [PATCH 2/5] drm/i915/dp: Reset frl trained flag before restarting FRL training Ankit Nautiyal
` (5 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Ankit Nautiyal @ 2022-08-22 10:54 UTC (permalink / raw)
To: intel-gfx
Add helper function to check if Downstream HDMI 2.1 sink supports
DSC1.2.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 32292c0be2bd..fdf82373a22d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -118,6 +118,15 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
+static bool
+is_dfp_hdmi_sink_dsc_1_2(struct intel_dp *intel_dp)
+{
+ struct intel_connector *intel_connector = intel_dp->attached_connector;
+ struct drm_connector *connector = &intel_connector->base;
+
+ return connector->display_info.hdmi.dsc_cap.v_1p2;
+}
+
/* Is link rate UHBR and thus 128b/132b? */
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
{
@@ -2393,7 +2402,7 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
max_frl_rate = max_lanes * rate_per_lane;
- if (connector->display_info.hdmi.dsc_cap.v_1p2) {
+ if (is_dfp_hdmi_sink_dsc_1_2(intel_dp)) {
max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
if (max_dsc_lanes && dsc_rate_per_lane)
@@ -2605,7 +2614,7 @@ intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
if (!intel_connector)
return;
connector = &intel_connector->base;
- hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
+ hdmi_is_dsc_1_2 = is_dfp_hdmi_sink_dsc_1_2(intel_dp);
if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
!hdmi_is_dsc_1_2)
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [Intel-gfx] [PATCH 1/5] drm/i915/dp: Add helper to check DSC1.2 for HDMI2.1 DFP
2022-08-22 10:54 ` [Intel-gfx] [PATCH 1/5] drm/i915/dp: Add helper to check DSC1.2 for HDMI2.1 DFP Ankit Nautiyal
@ 2022-08-23 11:02 ` Jani Nikula
2022-08-24 7:46 ` Nautiyal, Ankit K
0 siblings, 1 reply; 14+ messages in thread
From: Jani Nikula @ 2022-08-23 11:02 UTC (permalink / raw)
To: Ankit Nautiyal, intel-gfx
On Mon, 22 Aug 2022, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> Add helper function to check if Downstream HDMI 2.1 sink supports
> DSC1.2.
If we do this, are we going to add helpers for all the details in
display_info, when there's no conversions being done? I think the answer
should be "no".
i.e. why do we really need this?
BR,
Jani.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 13 +++++++++++--
> 1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 32292c0be2bd..fdf82373a22d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -118,6 +118,15 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
> static void intel_dp_unset_edid(struct intel_dp *intel_dp);
> static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
>
> +static bool
> +is_dfp_hdmi_sink_dsc_1_2(struct intel_dp *intel_dp)
> +{
> + struct intel_connector *intel_connector = intel_dp->attached_connector;
> + struct drm_connector *connector = &intel_connector->base;
> +
> + return connector->display_info.hdmi.dsc_cap.v_1p2;
> +}
> +
> /* Is link rate UHBR and thus 128b/132b? */
> bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
> {
> @@ -2393,7 +2402,7 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
> rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
> max_frl_rate = max_lanes * rate_per_lane;
>
> - if (connector->display_info.hdmi.dsc_cap.v_1p2) {
> + if (is_dfp_hdmi_sink_dsc_1_2(intel_dp)) {
> max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
> dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
> if (max_dsc_lanes && dsc_rate_per_lane)
> @@ -2605,7 +2614,7 @@ intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
> if (!intel_connector)
> return;
> connector = &intel_connector->base;
> - hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
> + hdmi_is_dsc_1_2 = is_dfp_hdmi_sink_dsc_1_2(intel_dp);
>
> if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
> !hdmi_is_dsc_1_2)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [Intel-gfx] [PATCH 1/5] drm/i915/dp: Add helper to check DSC1.2 for HDMI2.1 DFP
2022-08-23 11:02 ` Jani Nikula
@ 2022-08-24 7:46 ` Nautiyal, Ankit K
0 siblings, 0 replies; 14+ messages in thread
From: Nautiyal, Ankit K @ 2022-08-24 7:46 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 8/23/2022 4:32 PM, Jani Nikula wrote:
> On Mon, 22 Aug 2022, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>> Add helper function to check if Downstream HDMI 2.1 sink supports
>> DSC1.2.
> If we do this, are we going to add helpers for all the details in
> display_info, when there's no conversions being done? I think the answer
> should be "no".
>
> i.e. why do we really need this?
Hmm well initially I was checking both the dsc_max_frl rate and dsc
version, but dropped the dsc_max_frl rate check later.
(need another patch series to fix DSC parsing from HFVSDB:
https://patchwork.freedesktop.org/series/107146/ )
In current form, this function does seem unnecessary, I will drop this
patch from the series.
Thanks & Regards,
Ankit
> BR,
> Jani.
>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_dp.c | 13 +++++++++++--
>> 1 file changed, 11 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 32292c0be2bd..fdf82373a22d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -118,6 +118,15 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
>> static void intel_dp_unset_edid(struct intel_dp *intel_dp);
>> static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
>>
>> +static bool
>> +is_dfp_hdmi_sink_dsc_1_2(struct intel_dp *intel_dp)
>> +{
>> + struct intel_connector *intel_connector = intel_dp->attached_connector;
>> + struct drm_connector *connector = &intel_connector->base;
>> +
>> + return connector->display_info.hdmi.dsc_cap.v_1p2;
>> +}
>> +
>> /* Is link rate UHBR and thus 128b/132b? */
>> bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
>> {
>> @@ -2393,7 +2402,7 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
>> rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
>> max_frl_rate = max_lanes * rate_per_lane;
>>
>> - if (connector->display_info.hdmi.dsc_cap.v_1p2) {
>> + if (is_dfp_hdmi_sink_dsc_1_2(intel_dp)) {
>> max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
>> dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
>> if (max_dsc_lanes && dsc_rate_per_lane)
>> @@ -2605,7 +2614,7 @@ intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
>> if (!intel_connector)
>> return;
>> connector = &intel_connector->base;
>> - hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
>> + hdmi_is_dsc_1_2 = is_dfp_hdmi_sink_dsc_1_2(intel_dp);
>>
>> if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
>> !hdmi_is_dsc_1_2)
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 2/5] drm/i915/dp: Reset frl trained flag before restarting FRL training
2022-08-22 10:54 [Intel-gfx] [PATCH 0/5] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
2022-08-22 10:54 ` [Intel-gfx] [PATCH 1/5] drm/i915/dp: Add helper to check DSC1.2 for HDMI2.1 DFP Ankit Nautiyal
@ 2022-08-22 10:54 ` Ankit Nautiyal
2022-08-22 10:54 ` [Intel-gfx] [PATCH 3/5] drm/i915/dp: Fix DFP RGB->YCBCR conversion Ankit Nautiyal
` (4 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Ankit Nautiyal @ 2022-08-22 10:54 UTC (permalink / raw)
To: intel-gfx
For cases where DP has HDMI2.1 sink and FRL Link issues are detected,
reset the flag to state FRL trained status before restarting FRL
training.
Fixes: 9488a030ac91 ("drm/i915: Add support for enabling link status and recovery")
Cc: Swati Sharma <swati2.sharma@intel.com>
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com> (v2)
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index fdf82373a22d..fc082a933d59 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3957,6 +3957,8 @@ intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
+ intel_dp->frl.is_trained = false;
+
/* Restart FRL training or fall back to TMDS mode */
intel_dp_check_frl_training(intel_dp);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [Intel-gfx] [PATCH 3/5] drm/i915/dp: Fix DFP RGB->YCBCR conversion
2022-08-22 10:54 [Intel-gfx] [PATCH 0/5] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
2022-08-22 10:54 ` [Intel-gfx] [PATCH 1/5] drm/i915/dp: Add helper to check DSC1.2 for HDMI2.1 DFP Ankit Nautiyal
2022-08-22 10:54 ` [Intel-gfx] [PATCH 2/5] drm/i915/dp: Reset frl trained flag before restarting FRL training Ankit Nautiyal
@ 2022-08-22 10:54 ` Ankit Nautiyal
2022-08-23 11:03 ` Jani Nikula
2022-08-22 10:54 ` [Intel-gfx] [PATCH 4/5] drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC Ankit Nautiyal
` (3 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Ankit Nautiyal @ 2022-08-22 10:54 UTC (permalink / raw)
To: intel-gfx
The decision to use DFP output format conversion capabilities should be
during compute_config phase.
This patch:
-uses the members of intel_dp->dfp to only store the
format conversion capabilities of the DP device.
-adds new members to crtc_state to help configure the DFP
output related conversions.
-pulls the decision making to use DFP conversion capabilities
for every mode during compute config.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
.../drm/i915/display/intel_display_types.h | 7 ++
drivers/gpu/drm/i915/display/intel_dp.c | 88 +++++++++++--------
2 files changed, 59 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0da9b208d56e..065ed19a5dd3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1311,6 +1311,12 @@ struct intel_crtc_state {
/* for loading single buffered registers during vblank */
struct drm_vblank_work vblank_work;
+
+ /* DP DFP color configuration */
+ struct {
+ bool rgb_to_ycbcr;
+ bool ycbcr_444_to_420;
+ } dp_dfp_config;
};
enum intel_pipe_crc_source {
@@ -1704,6 +1710,7 @@ struct intel_dp {
int pcon_max_frl_bw;
u8 max_bpc;
bool ycbcr_444_to_420;
+ bool ycbcr420_passthrough;
bool rgb_to_ycbcr;
} dfp;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index fc082a933d59..8ccbe591b9e2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1201,19 +1201,21 @@ static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
}
-static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
- const struct intel_crtc_state *crtc_state)
+static bool intel_dp_is_ycbcr420(const struct intel_crtc_state *crtc_state)
{
return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
(crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
- intel_dp->dfp.ycbcr_444_to_420);
+ crtc_state->dp_dfp_config.ycbcr_444_to_420) ||
+ (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB &&
+ crtc_state->dp_dfp_config.ycbcr_444_to_420 &&
+ crtc_state->dp_dfp_config.rgb_to_ycbcr);
}
static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
int bpc, bool respect_downstream_limits)
{
- bool ycbcr420_output = intel_dp_is_ycbcr420(intel_dp, crtc_state);
+ bool ycbcr420_output = intel_dp_is_ycbcr420(crtc_state);
int clock = crtc_state->hw.adjusted_mode.crtc_clock;
/*
@@ -1966,6 +1968,30 @@ static bool intel_dp_has_audio(struct intel_encoder *encoder,
return intel_conn_state->force_audio == HDMI_AUDIO_ON;
}
+static void
+intel_dp_compute_dfp_ycbcr420(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ if (!drm_dp_is_branch(intel_dp->dpcd))
+ return;
+
+ /* Mode is YCBCR420, output_format is also YCBCR420: Passthrough */
+ if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ return;
+
+ /* Mode is YCBCR420, output_format is YCBCR444: Downsample */
+ if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
+ crtc_state->dp_dfp_config.ycbcr_444_to_420 = true;
+ return;
+ }
+
+ /* Mode is YCBCR420, output_format is RGB: Convert to YCBCR444 and Downsample */
+ crtc_state->dp_dfp_config.rgb_to_ycbcr = true;
+ crtc_state->dp_dfp_config.ycbcr_444_to_420 = true;
+}
+
static int
intel_dp_compute_output_format(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
@@ -1984,7 +2010,10 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only);
- if (ycbcr_420_only && !intel_dp_is_ycbcr420(intel_dp, crtc_state)) {
+ if (ycbcr_420_only)
+ intel_dp_compute_dfp_ycbcr420(encoder, crtc_state);
+
+ if (ycbcr_420_only && !intel_dp_is_ycbcr420(crtc_state)) {
drm_dbg_kms(&i915->drm,
"YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
@@ -1993,12 +2022,13 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
respect_downstream_limits);
if (ret) {
- if (intel_dp_is_ycbcr420(intel_dp, crtc_state) ||
+ if (intel_dp_is_ycbcr420(crtc_state) ||
!connector->base.ycbcr_420_allowed ||
!drm_mode_is_420_also(info, adjusted_mode))
return ret;
crtc_state->output_format = intel_dp_output_format(connector, true);
+ intel_dp_compute_dfp_ycbcr420(encoder, crtc_state);
ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
respect_downstream_limits);
}
@@ -2668,8 +2698,7 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
str_enable_disable(intel_dp->has_hdmi_sink));
- tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
- intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
+ tmp = crtc_state->dp_dfp_config.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
if (drm_dp_dpcd_writeb(&intel_dp->aux,
DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
@@ -2677,7 +2706,7 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
"Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
- tmp = intel_dp->dfp.rgb_to_ycbcr ?
+ tmp = crtc_state->dp_dfp_config.rgb_to_ycbcr ?
DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
@@ -2686,7 +2715,6 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
str_enable_disable(tmp));
}
-
bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
{
u8 dprx = 0;
@@ -4534,7 +4562,6 @@ intel_dp_update_420(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_connector *connector = intel_dp->attached_connector;
- bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
/* No YCbCr output support on gmch platforms */
if (HAS_GMCH(i915))
@@ -4547,39 +4574,28 @@ intel_dp_update_420(struct intel_dp *intel_dp)
if (IS_IRONLAKE(i915))
return;
- is_branch = drm_dp_is_branch(intel_dp->dpcd);
- ycbcr_420_passthrough =
+ if (!drm_dp_is_branch(intel_dp->dpcd)) {
+ connector->base.ycbcr_420_allowed = true;
+ return;
+ }
+
+ intel_dp->dfp.ycbcr420_passthrough =
drm_dp_downstream_420_passthrough(intel_dp->dpcd,
intel_dp->downstream_ports);
+
/* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
- ycbcr_444_to_420 =
+ intel_dp->dfp.ycbcr_444_to_420 =
dp_to_dig_port(intel_dp)->lspcon.active ||
drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
intel_dp->downstream_ports);
- rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
- intel_dp->downstream_ports,
- DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
-
- if (DISPLAY_VER(i915) >= 11) {
- /* Let PCON convert from RGB->YCbCr if possible */
- if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
- intel_dp->dfp.rgb_to_ycbcr = true;
- intel_dp->dfp.ycbcr_444_to_420 = true;
- connector->base.ycbcr_420_allowed = true;
- } else {
- /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
- intel_dp->dfp.ycbcr_444_to_420 =
- ycbcr_444_to_420 && !ycbcr_420_passthrough;
- connector->base.ycbcr_420_allowed =
- !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
- }
- } else {
- /* 4:4:4->4:2:0 conversion is the only way */
- intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
+ intel_dp->dfp.rgb_to_ycbcr =
+ drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
+ intel_dp->downstream_ports,
+ DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
- connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
- }
+ if (intel_dp->dfp.ycbcr420_passthrough || intel_dp->dfp.ycbcr_444_to_420)
+ connector->base.ycbcr_420_allowed = true;
drm_dbg_kms(&i915->drm,
"[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [Intel-gfx] [PATCH 3/5] drm/i915/dp: Fix DFP RGB->YCBCR conversion
2022-08-22 10:54 ` [Intel-gfx] [PATCH 3/5] drm/i915/dp: Fix DFP RGB->YCBCR conversion Ankit Nautiyal
@ 2022-08-23 11:03 ` Jani Nikula
2022-08-24 7:58 ` Nautiyal, Ankit K
0 siblings, 1 reply; 14+ messages in thread
From: Jani Nikula @ 2022-08-23 11:03 UTC (permalink / raw)
To: Ankit Nautiyal, intel-gfx
On Mon, 22 Aug 2022, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> The decision to use DFP output format conversion capabilities should be
> during compute_config phase.
>
> This patch:
> -uses the members of intel_dp->dfp to only store the
> format conversion capabilities of the DP device.
> -adds new members to crtc_state to help configure the DFP
> output related conversions.
> -pulls the decision making to use DFP conversion capabilities
> for every mode during compute config.
The fact that you have a list here probably indicates it's doing too
much at once.
BR,
Jani.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 7 ++
> drivers/gpu/drm/i915/display/intel_dp.c | 88 +++++++++++--------
> 2 files changed, 59 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 0da9b208d56e..065ed19a5dd3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1311,6 +1311,12 @@ struct intel_crtc_state {
>
> /* for loading single buffered registers during vblank */
> struct drm_vblank_work vblank_work;
> +
> + /* DP DFP color configuration */
> + struct {
> + bool rgb_to_ycbcr;
> + bool ycbcr_444_to_420;
> + } dp_dfp_config;
> };
>
> enum intel_pipe_crc_source {
> @@ -1704,6 +1710,7 @@ struct intel_dp {
> int pcon_max_frl_bw;
> u8 max_bpc;
> bool ycbcr_444_to_420;
> + bool ycbcr420_passthrough;
> bool rgb_to_ycbcr;
> } dfp;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index fc082a933d59..8ccbe591b9e2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1201,19 +1201,21 @@ static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
> drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
> }
>
> -static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
> - const struct intel_crtc_state *crtc_state)
> +static bool intel_dp_is_ycbcr420(const struct intel_crtc_state *crtc_state)
> {
> return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
> - intel_dp->dfp.ycbcr_444_to_420);
> + crtc_state->dp_dfp_config.ycbcr_444_to_420) ||
> + (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB &&
> + crtc_state->dp_dfp_config.ycbcr_444_to_420 &&
> + crtc_state->dp_dfp_config.rgb_to_ycbcr);
> }
>
> static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state,
> int bpc, bool respect_downstream_limits)
> {
> - bool ycbcr420_output = intel_dp_is_ycbcr420(intel_dp, crtc_state);
> + bool ycbcr420_output = intel_dp_is_ycbcr420(crtc_state);
> int clock = crtc_state->hw.adjusted_mode.crtc_clock;
>
> /*
> @@ -1966,6 +1968,30 @@ static bool intel_dp_has_audio(struct intel_encoder *encoder,
> return intel_conn_state->force_audio == HDMI_AUDIO_ON;
> }
>
> +static void
> +intel_dp_compute_dfp_ycbcr420(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state)
> +{
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + if (!drm_dp_is_branch(intel_dp->dpcd))
> + return;
> +
> + /* Mode is YCBCR420, output_format is also YCBCR420: Passthrough */
> + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> + return;
> +
> + /* Mode is YCBCR420, output_format is YCBCR444: Downsample */
> + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
> + crtc_state->dp_dfp_config.ycbcr_444_to_420 = true;
> + return;
> + }
> +
> + /* Mode is YCBCR420, output_format is RGB: Convert to YCBCR444 and Downsample */
> + crtc_state->dp_dfp_config.rgb_to_ycbcr = true;
> + crtc_state->dp_dfp_config.ycbcr_444_to_420 = true;
> +}
> +
> static int
> intel_dp_compute_output_format(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state,
> @@ -1984,7 +2010,10 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
>
> crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only);
>
> - if (ycbcr_420_only && !intel_dp_is_ycbcr420(intel_dp, crtc_state)) {
> + if (ycbcr_420_only)
> + intel_dp_compute_dfp_ycbcr420(encoder, crtc_state);
> +
> + if (ycbcr_420_only && !intel_dp_is_ycbcr420(crtc_state)) {
> drm_dbg_kms(&i915->drm,
> "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
> crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
> @@ -1993,12 +2022,13 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
> ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
> respect_downstream_limits);
> if (ret) {
> - if (intel_dp_is_ycbcr420(intel_dp, crtc_state) ||
> + if (intel_dp_is_ycbcr420(crtc_state) ||
> !connector->base.ycbcr_420_allowed ||
> !drm_mode_is_420_also(info, adjusted_mode))
> return ret;
>
> crtc_state->output_format = intel_dp_output_format(connector, true);
> + intel_dp_compute_dfp_ycbcr420(encoder, crtc_state);
> ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
> respect_downstream_limits);
> }
> @@ -2668,8 +2698,7 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
> drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
> str_enable_disable(intel_dp->has_hdmi_sink));
>
> - tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
> - intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
> + tmp = crtc_state->dp_dfp_config.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
>
> if (drm_dp_dpcd_writeb(&intel_dp->aux,
> DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
> @@ -2677,7 +2706,7 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
> "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
> str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
>
> - tmp = intel_dp->dfp.rgb_to_ycbcr ?
> + tmp = crtc_state->dp_dfp_config.rgb_to_ycbcr ?
> DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
>
> if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
> @@ -2686,7 +2715,6 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
> str_enable_disable(tmp));
> }
>
> -
> bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
> {
> u8 dprx = 0;
> @@ -4534,7 +4562,6 @@ intel_dp_update_420(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> struct intel_connector *connector = intel_dp->attached_connector;
> - bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
>
> /* No YCbCr output support on gmch platforms */
> if (HAS_GMCH(i915))
> @@ -4547,39 +4574,28 @@ intel_dp_update_420(struct intel_dp *intel_dp)
> if (IS_IRONLAKE(i915))
> return;
>
> - is_branch = drm_dp_is_branch(intel_dp->dpcd);
> - ycbcr_420_passthrough =
> + if (!drm_dp_is_branch(intel_dp->dpcd)) {
> + connector->base.ycbcr_420_allowed = true;
> + return;
> + }
> +
> + intel_dp->dfp.ycbcr420_passthrough =
> drm_dp_downstream_420_passthrough(intel_dp->dpcd,
> intel_dp->downstream_ports);
> +
> /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
> - ycbcr_444_to_420 =
> + intel_dp->dfp.ycbcr_444_to_420 =
> dp_to_dig_port(intel_dp)->lspcon.active ||
> drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
> intel_dp->downstream_ports);
> - rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
> - intel_dp->downstream_ports,
> - DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
> -
> - if (DISPLAY_VER(i915) >= 11) {
> - /* Let PCON convert from RGB->YCbCr if possible */
> - if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
> - intel_dp->dfp.rgb_to_ycbcr = true;
> - intel_dp->dfp.ycbcr_444_to_420 = true;
> - connector->base.ycbcr_420_allowed = true;
> - } else {
> - /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
> - intel_dp->dfp.ycbcr_444_to_420 =
> - ycbcr_444_to_420 && !ycbcr_420_passthrough;
>
> - connector->base.ycbcr_420_allowed =
> - !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
> - }
> - } else {
> - /* 4:4:4->4:2:0 conversion is the only way */
> - intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
> + intel_dp->dfp.rgb_to_ycbcr =
> + drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
> + intel_dp->downstream_ports,
> + DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
>
> - connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
> - }
> + if (intel_dp->dfp.ycbcr420_passthrough || intel_dp->dfp.ycbcr_444_to_420)
> + connector->base.ycbcr_420_allowed = true;
>
> drm_dbg_kms(&i915->drm,
> "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [Intel-gfx] [PATCH 3/5] drm/i915/dp: Fix DFP RGB->YCBCR conversion
2022-08-23 11:03 ` Jani Nikula
@ 2022-08-24 7:58 ` Nautiyal, Ankit K
2022-08-24 8:37 ` Jani Nikula
0 siblings, 1 reply; 14+ messages in thread
From: Nautiyal, Ankit K @ 2022-08-24 7:58 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 8/23/2022 4:33 PM, Jani Nikula wrote:
> On Mon, 22 Aug 2022, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>> The decision to use DFP output format conversion capabilities should be
>> during compute_config phase.
>>
>> This patch:
>> -uses the members of intel_dp->dfp to only store the
>> format conversion capabilities of the DP device.
>> -adds new members to crtc_state to help configure the DFP
>> output related conversions.
>> -pulls the decision making to use DFP conversion capabilities
>> for every mode during compute config.
> The fact that you have a list here probably indicates it's doing too
> much at once.
>
> BR,
> Jani.
Alright, perhaps adding new members as a separate patch and using them
in another patch will be better.
Will split this into smaller patches.
Thanks & Regards,
Ankit
>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> .../drm/i915/display/intel_display_types.h | 7 ++
>> drivers/gpu/drm/i915/display/intel_dp.c | 88 +++++++++++--------
>> 2 files changed, 59 insertions(+), 36 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 0da9b208d56e..065ed19a5dd3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1311,6 +1311,12 @@ struct intel_crtc_state {
>>
>> /* for loading single buffered registers during vblank */
>> struct drm_vblank_work vblank_work;
>> +
>> + /* DP DFP color configuration */
>> + struct {
>> + bool rgb_to_ycbcr;
>> + bool ycbcr_444_to_420;
>> + } dp_dfp_config;
>> };
>>
>> enum intel_pipe_crc_source {
>> @@ -1704,6 +1710,7 @@ struct intel_dp {
>> int pcon_max_frl_bw;
>> u8 max_bpc;
>> bool ycbcr_444_to_420;
>> + bool ycbcr420_passthrough;
>> bool rgb_to_ycbcr;
>> } dfp;
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index fc082a933d59..8ccbe591b9e2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -1201,19 +1201,21 @@ static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
>> drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
>> }
>>
>> -static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
>> - const struct intel_crtc_state *crtc_state)
>> +static bool intel_dp_is_ycbcr420(const struct intel_crtc_state *crtc_state)
>> {
>> return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
>> (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
>> - intel_dp->dfp.ycbcr_444_to_420);
>> + crtc_state->dp_dfp_config.ycbcr_444_to_420) ||
>> + (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB &&
>> + crtc_state->dp_dfp_config.ycbcr_444_to_420 &&
>> + crtc_state->dp_dfp_config.rgb_to_ycbcr);
>> }
>>
>> static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
>> const struct intel_crtc_state *crtc_state,
>> int bpc, bool respect_downstream_limits)
>> {
>> - bool ycbcr420_output = intel_dp_is_ycbcr420(intel_dp, crtc_state);
>> + bool ycbcr420_output = intel_dp_is_ycbcr420(crtc_state);
>> int clock = crtc_state->hw.adjusted_mode.crtc_clock;
>>
>> /*
>> @@ -1966,6 +1968,30 @@ static bool intel_dp_has_audio(struct intel_encoder *encoder,
>> return intel_conn_state->force_audio == HDMI_AUDIO_ON;
>> }
>>
>> +static void
>> +intel_dp_compute_dfp_ycbcr420(struct intel_encoder *encoder,
>> + struct intel_crtc_state *crtc_state)
>> +{
>> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> +
>> + if (!drm_dp_is_branch(intel_dp->dpcd))
>> + return;
>> +
>> + /* Mode is YCBCR420, output_format is also YCBCR420: Passthrough */
>> + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
>> + return;
>> +
>> + /* Mode is YCBCR420, output_format is YCBCR444: Downsample */
>> + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
>> + crtc_state->dp_dfp_config.ycbcr_444_to_420 = true;
>> + return;
>> + }
>> +
>> + /* Mode is YCBCR420, output_format is RGB: Convert to YCBCR444 and Downsample */
>> + crtc_state->dp_dfp_config.rgb_to_ycbcr = true;
>> + crtc_state->dp_dfp_config.ycbcr_444_to_420 = true;
>> +}
>> +
>> static int
>> intel_dp_compute_output_format(struct intel_encoder *encoder,
>> struct intel_crtc_state *crtc_state,
>> @@ -1984,7 +2010,10 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
>>
>> crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only);
>>
>> - if (ycbcr_420_only && !intel_dp_is_ycbcr420(intel_dp, crtc_state)) {
>> + if (ycbcr_420_only)
>> + intel_dp_compute_dfp_ycbcr420(encoder, crtc_state);
>> +
>> + if (ycbcr_420_only && !intel_dp_is_ycbcr420(crtc_state)) {
>> drm_dbg_kms(&i915->drm,
>> "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
>> crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
>> @@ -1993,12 +2022,13 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
>> ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
>> respect_downstream_limits);
>> if (ret) {
>> - if (intel_dp_is_ycbcr420(intel_dp, crtc_state) ||
>> + if (intel_dp_is_ycbcr420(crtc_state) ||
>> !connector->base.ycbcr_420_allowed ||
>> !drm_mode_is_420_also(info, adjusted_mode))
>> return ret;
>>
>> crtc_state->output_format = intel_dp_output_format(connector, true);
>> + intel_dp_compute_dfp_ycbcr420(encoder, crtc_state);
>> ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
>> respect_downstream_limits);
>> }
>> @@ -2668,8 +2698,7 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
>> drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
>> str_enable_disable(intel_dp->has_hdmi_sink));
>>
>> - tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
>> - intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
>> + tmp = crtc_state->dp_dfp_config.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
>>
>> if (drm_dp_dpcd_writeb(&intel_dp->aux,
>> DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
>> @@ -2677,7 +2706,7 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
>> "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
>> str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
>>
>> - tmp = intel_dp->dfp.rgb_to_ycbcr ?
>> + tmp = crtc_state->dp_dfp_config.rgb_to_ycbcr ?
>> DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
>>
>> if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
>> @@ -2686,7 +2715,6 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
>> str_enable_disable(tmp));
>> }
>>
>> -
>> bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
>> {
>> u8 dprx = 0;
>> @@ -4534,7 +4562,6 @@ intel_dp_update_420(struct intel_dp *intel_dp)
>> {
>> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>> struct intel_connector *connector = intel_dp->attached_connector;
>> - bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
>>
>> /* No YCbCr output support on gmch platforms */
>> if (HAS_GMCH(i915))
>> @@ -4547,39 +4574,28 @@ intel_dp_update_420(struct intel_dp *intel_dp)
>> if (IS_IRONLAKE(i915))
>> return;
>>
>> - is_branch = drm_dp_is_branch(intel_dp->dpcd);
>> - ycbcr_420_passthrough =
>> + if (!drm_dp_is_branch(intel_dp->dpcd)) {
>> + connector->base.ycbcr_420_allowed = true;
>> + return;
>> + }
>> +
>> + intel_dp->dfp.ycbcr420_passthrough =
>> drm_dp_downstream_420_passthrough(intel_dp->dpcd,
>> intel_dp->downstream_ports);
>> +
>> /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
>> - ycbcr_444_to_420 =
>> + intel_dp->dfp.ycbcr_444_to_420 =
>> dp_to_dig_port(intel_dp)->lspcon.active ||
>> drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
>> intel_dp->downstream_ports);
>> - rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
>> - intel_dp->downstream_ports,
>> - DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
>> -
>> - if (DISPLAY_VER(i915) >= 11) {
>> - /* Let PCON convert from RGB->YCbCr if possible */
>> - if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
>> - intel_dp->dfp.rgb_to_ycbcr = true;
>> - intel_dp->dfp.ycbcr_444_to_420 = true;
>> - connector->base.ycbcr_420_allowed = true;
>> - } else {
>> - /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
>> - intel_dp->dfp.ycbcr_444_to_420 =
>> - ycbcr_444_to_420 && !ycbcr_420_passthrough;
>>
>> - connector->base.ycbcr_420_allowed =
>> - !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
>> - }
>> - } else {
>> - /* 4:4:4->4:2:0 conversion is the only way */
>> - intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
>> + intel_dp->dfp.rgb_to_ycbcr =
>> + drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
>> + intel_dp->downstream_ports,
>> + DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
>>
>> - connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
>> - }
>> + if (intel_dp->dfp.ycbcr420_passthrough || intel_dp->dfp.ycbcr_444_to_420)
>> + connector->base.ycbcr_420_allowed = true;
>>
>> drm_dbg_kms(&i915->drm,
>> "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [Intel-gfx] [PATCH 3/5] drm/i915/dp: Fix DFP RGB->YCBCR conversion
2022-08-24 7:58 ` Nautiyal, Ankit K
@ 2022-08-24 8:37 ` Jani Nikula
2022-08-24 10:21 ` Nautiyal, Ankit K
0 siblings, 1 reply; 14+ messages in thread
From: Jani Nikula @ 2022-08-24 8:37 UTC (permalink / raw)
To: Nautiyal, Ankit K, intel-gfx
On Wed, 24 Aug 2022, "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com> wrote:
> On 8/23/2022 4:33 PM, Jani Nikula wrote:
>> On Mon, 22 Aug 2022, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>>> The decision to use DFP output format conversion capabilities should be
>>> during compute_config phase.
>>>
>>> This patch:
>>> -uses the members of intel_dp->dfp to only store the
>>> format conversion capabilities of the DP device.
>>> -adds new members to crtc_state to help configure the DFP
>>> output related conversions.
>>> -pulls the decision making to use DFP conversion capabilities
>>> for every mode during compute config.
>> The fact that you have a list here probably indicates it's doing too
>> much at once.
>>
>> BR,
>> Jani.
>
> Alright, perhaps adding new members as a separate patch and using them
> in another patch will be better.
>
> Will split this into smaller patches.
You are also changing function parameters, rearranging stuff to new
functions, whitespace changes, functional logic changes, all together.
The point is, if an existing use case regressed and a user bisect
pointed at this commit, would you be able to say what went wrong?
BR,
Jani.
>
> Thanks & Regards,
>
> Ankit
>
>>
>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>> ---
>>> .../drm/i915/display/intel_display_types.h | 7 ++
>>> drivers/gpu/drm/i915/display/intel_dp.c | 88 +++++++++++--------
>>> 2 files changed, 59 insertions(+), 36 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> index 0da9b208d56e..065ed19a5dd3 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> @@ -1311,6 +1311,12 @@ struct intel_crtc_state {
>>>
>>> /* for loading single buffered registers during vblank */
>>> struct drm_vblank_work vblank_work;
>>> +
>>> + /* DP DFP color configuration */
>>> + struct {
>>> + bool rgb_to_ycbcr;
>>> + bool ycbcr_444_to_420;
>>> + } dp_dfp_config;
>>> };
>>>
>>> enum intel_pipe_crc_source {
>>> @@ -1704,6 +1710,7 @@ struct intel_dp {
>>> int pcon_max_frl_bw;
>>> u8 max_bpc;
>>> bool ycbcr_444_to_420;
>>> + bool ycbcr420_passthrough;
>>> bool rgb_to_ycbcr;
>>> } dfp;
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>>> index fc082a933d59..8ccbe591b9e2 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>> @@ -1201,19 +1201,21 @@ static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
>>> drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
>>> }
>>>
>>> -static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
>>> - const struct intel_crtc_state *crtc_state)
>>> +static bool intel_dp_is_ycbcr420(const struct intel_crtc_state *crtc_state)
>>> {
>>> return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
>>> (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
>>> - intel_dp->dfp.ycbcr_444_to_420);
>>> + crtc_state->dp_dfp_config.ycbcr_444_to_420) ||
>>> + (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB &&
>>> + crtc_state->dp_dfp_config.ycbcr_444_to_420 &&
>>> + crtc_state->dp_dfp_config.rgb_to_ycbcr);
>>> }
>>>
>>> static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
>>> const struct intel_crtc_state *crtc_state,
>>> int bpc, bool respect_downstream_limits)
>>> {
>>> - bool ycbcr420_output = intel_dp_is_ycbcr420(intel_dp, crtc_state);
>>> + bool ycbcr420_output = intel_dp_is_ycbcr420(crtc_state);
>>> int clock = crtc_state->hw.adjusted_mode.crtc_clock;
>>>
>>> /*
>>> @@ -1966,6 +1968,30 @@ static bool intel_dp_has_audio(struct intel_encoder *encoder,
>>> return intel_conn_state->force_audio == HDMI_AUDIO_ON;
>>> }
>>>
>>> +static void
>>> +intel_dp_compute_dfp_ycbcr420(struct intel_encoder *encoder,
>>> + struct intel_crtc_state *crtc_state)
>>> +{
>>> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>>> +
>>> + if (!drm_dp_is_branch(intel_dp->dpcd))
>>> + return;
>>> +
>>> + /* Mode is YCBCR420, output_format is also YCBCR420: Passthrough */
>>> + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
>>> + return;
>>> +
>>> + /* Mode is YCBCR420, output_format is YCBCR444: Downsample */
>>> + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
>>> + crtc_state->dp_dfp_config.ycbcr_444_to_420 = true;
>>> + return;
>>> + }
>>> +
>>> + /* Mode is YCBCR420, output_format is RGB: Convert to YCBCR444 and Downsample */
>>> + crtc_state->dp_dfp_config.rgb_to_ycbcr = true;
>>> + crtc_state->dp_dfp_config.ycbcr_444_to_420 = true;
>>> +}
>>> +
>>> static int
>>> intel_dp_compute_output_format(struct intel_encoder *encoder,
>>> struct intel_crtc_state *crtc_state,
>>> @@ -1984,7 +2010,10 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
>>>
>>> crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only);
>>>
>>> - if (ycbcr_420_only && !intel_dp_is_ycbcr420(intel_dp, crtc_state)) {
>>> + if (ycbcr_420_only)
>>> + intel_dp_compute_dfp_ycbcr420(encoder, crtc_state);
>>> +
>>> + if (ycbcr_420_only && !intel_dp_is_ycbcr420(crtc_state)) {
>>> drm_dbg_kms(&i915->drm,
>>> "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
>>> crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
>>> @@ -1993,12 +2022,13 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
>>> ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
>>> respect_downstream_limits);
>>> if (ret) {
>>> - if (intel_dp_is_ycbcr420(intel_dp, crtc_state) ||
>>> + if (intel_dp_is_ycbcr420(crtc_state) ||
>>> !connector->base.ycbcr_420_allowed ||
>>> !drm_mode_is_420_also(info, adjusted_mode))
>>> return ret;
>>>
>>> crtc_state->output_format = intel_dp_output_format(connector, true);
>>> + intel_dp_compute_dfp_ycbcr420(encoder, crtc_state);
>>> ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
>>> respect_downstream_limits);
>>> }
>>> @@ -2668,8 +2698,7 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
>>> drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
>>> str_enable_disable(intel_dp->has_hdmi_sink));
>>>
>>> - tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
>>> - intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
>>> + tmp = crtc_state->dp_dfp_config.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
>>>
>>> if (drm_dp_dpcd_writeb(&intel_dp->aux,
>>> DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
>>> @@ -2677,7 +2706,7 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
>>> "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
>>> str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
>>>
>>> - tmp = intel_dp->dfp.rgb_to_ycbcr ?
>>> + tmp = crtc_state->dp_dfp_config.rgb_to_ycbcr ?
>>> DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
>>>
>>> if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
>>> @@ -2686,7 +2715,6 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
>>> str_enable_disable(tmp));
>>> }
>>>
>>> -
>>> bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
>>> {
>>> u8 dprx = 0;
>>> @@ -4534,7 +4562,6 @@ intel_dp_update_420(struct intel_dp *intel_dp)
>>> {
>>> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>>> struct intel_connector *connector = intel_dp->attached_connector;
>>> - bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
>>>
>>> /* No YCbCr output support on gmch platforms */
>>> if (HAS_GMCH(i915))
>>> @@ -4547,39 +4574,28 @@ intel_dp_update_420(struct intel_dp *intel_dp)
>>> if (IS_IRONLAKE(i915))
>>> return;
>>>
>>> - is_branch = drm_dp_is_branch(intel_dp->dpcd);
>>> - ycbcr_420_passthrough =
>>> + if (!drm_dp_is_branch(intel_dp->dpcd)) {
>>> + connector->base.ycbcr_420_allowed = true;
>>> + return;
>>> + }
>>> +
>>> + intel_dp->dfp.ycbcr420_passthrough =
>>> drm_dp_downstream_420_passthrough(intel_dp->dpcd,
>>> intel_dp->downstream_ports);
>>> +
>>> /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
>>> - ycbcr_444_to_420 =
>>> + intel_dp->dfp.ycbcr_444_to_420 =
>>> dp_to_dig_port(intel_dp)->lspcon.active ||
>>> drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
>>> intel_dp->downstream_ports);
>>> - rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
>>> - intel_dp->downstream_ports,
>>> - DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
>>> -
>>> - if (DISPLAY_VER(i915) >= 11) {
>>> - /* Let PCON convert from RGB->YCbCr if possible */
>>> - if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
>>> - intel_dp->dfp.rgb_to_ycbcr = true;
>>> - intel_dp->dfp.ycbcr_444_to_420 = true;
>>> - connector->base.ycbcr_420_allowed = true;
>>> - } else {
>>> - /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
>>> - intel_dp->dfp.ycbcr_444_to_420 =
>>> - ycbcr_444_to_420 && !ycbcr_420_passthrough;
>>>
>>> - connector->base.ycbcr_420_allowed =
>>> - !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
>>> - }
>>> - } else {
>>> - /* 4:4:4->4:2:0 conversion is the only way */
>>> - intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
>>> + intel_dp->dfp.rgb_to_ycbcr =
>>> + drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
>>> + intel_dp->downstream_ports,
>>> + DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
>>>
>>> - connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
>>> - }
>>> + if (intel_dp->dfp.ycbcr420_passthrough || intel_dp->dfp.ycbcr_444_to_420)
>>> + connector->base.ycbcr_420_allowed = true;
>>>
>>> drm_dbg_kms(&i915->drm,
>>> "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [Intel-gfx] [PATCH 3/5] drm/i915/dp: Fix DFP RGB->YCBCR conversion
2022-08-24 8:37 ` Jani Nikula
@ 2022-08-24 10:21 ` Nautiyal, Ankit K
0 siblings, 0 replies; 14+ messages in thread
From: Nautiyal, Ankit K @ 2022-08-24 10:21 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 8/24/2022 2:07 PM, Jani Nikula wrote:
> On Wed, 24 Aug 2022, "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com> wrote:
>> On 8/23/2022 4:33 PM, Jani Nikula wrote:
>>> On Mon, 22 Aug 2022, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>>>> The decision to use DFP output format conversion capabilities should be
>>>> during compute_config phase.
>>>>
>>>> This patch:
>>>> -uses the members of intel_dp->dfp to only store the
>>>> format conversion capabilities of the DP device.
>>>> -adds new members to crtc_state to help configure the DFP
>>>> output related conversions.
>>>> -pulls the decision making to use DFP conversion capabilities
>>>> for every mode during compute config.
>>> The fact that you have a list here probably indicates it's doing too
>>> much at once.
>>>
>>> BR,
>>> Jani.
>> Alright, perhaps adding new members as a separate patch and using them
>> in another patch will be better.
>>
>> Will split this into smaller patches.
> You are also changing function parameters, rearranging stuff to new
> functions, whitespace changes, functional logic changes, all together.
>
> The point is, if an existing use case regressed and a user bisect
> pointed at this commit, would you be able to say what went wrong?
>
> BR,
> Jani.
Got it. Indeed it will be difficult to root cause the issue in a patch
like this.
I will try to get this in smaller incremental changes.
Regards,
Ankit
>
>> Thanks & Regards,
>>
>> Ankit
>>
>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>> ---
>>>> .../drm/i915/display/intel_display_types.h | 7 ++
>>>> drivers/gpu/drm/i915/display/intel_dp.c | 88 +++++++++++--------
>>>> 2 files changed, 59 insertions(+), 36 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>>>> index 0da9b208d56e..065ed19a5dd3 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>>> @@ -1311,6 +1311,12 @@ struct intel_crtc_state {
>>>>
>>>> /* for loading single buffered registers during vblank */
>>>> struct drm_vblank_work vblank_work;
>>>> +
>>>> + /* DP DFP color configuration */
>>>> + struct {
>>>> + bool rgb_to_ycbcr;
>>>> + bool ycbcr_444_to_420;
>>>> + } dp_dfp_config;
>>>> };
>>>>
>>>> enum intel_pipe_crc_source {
>>>> @@ -1704,6 +1710,7 @@ struct intel_dp {
>>>> int pcon_max_frl_bw;
>>>> u8 max_bpc;
>>>> bool ycbcr_444_to_420;
>>>> + bool ycbcr420_passthrough;
>>>> bool rgb_to_ycbcr;
>>>> } dfp;
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>>>> index fc082a933d59..8ccbe591b9e2 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>>> @@ -1201,19 +1201,21 @@ static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
>>>> drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
>>>> }
>>>>
>>>> -static bool intel_dp_is_ycbcr420(struct intel_dp *intel_dp,
>>>> - const struct intel_crtc_state *crtc_state)
>>>> +static bool intel_dp_is_ycbcr420(const struct intel_crtc_state *crtc_state)
>>>> {
>>>> return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
>>>> (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
>>>> - intel_dp->dfp.ycbcr_444_to_420);
>>>> + crtc_state->dp_dfp_config.ycbcr_444_to_420) ||
>>>> + (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB &&
>>>> + crtc_state->dp_dfp_config.ycbcr_444_to_420 &&
>>>> + crtc_state->dp_dfp_config.rgb_to_ycbcr);
>>>> }
>>>>
>>>> static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
>>>> const struct intel_crtc_state *crtc_state,
>>>> int bpc, bool respect_downstream_limits)
>>>> {
>>>> - bool ycbcr420_output = intel_dp_is_ycbcr420(intel_dp, crtc_state);
>>>> + bool ycbcr420_output = intel_dp_is_ycbcr420(crtc_state);
>>>> int clock = crtc_state->hw.adjusted_mode.crtc_clock;
>>>>
>>>> /*
>>>> @@ -1966,6 +1968,30 @@ static bool intel_dp_has_audio(struct intel_encoder *encoder,
>>>> return intel_conn_state->force_audio == HDMI_AUDIO_ON;
>>>> }
>>>>
>>>> +static void
>>>> +intel_dp_compute_dfp_ycbcr420(struct intel_encoder *encoder,
>>>> + struct intel_crtc_state *crtc_state)
>>>> +{
>>>> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>>>> +
>>>> + if (!drm_dp_is_branch(intel_dp->dpcd))
>>>> + return;
>>>> +
>>>> + /* Mode is YCBCR420, output_format is also YCBCR420: Passthrough */
>>>> + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
>>>> + return;
>>>> +
>>>> + /* Mode is YCBCR420, output_format is YCBCR444: Downsample */
>>>> + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
>>>> + crtc_state->dp_dfp_config.ycbcr_444_to_420 = true;
>>>> + return;
>>>> + }
>>>> +
>>>> + /* Mode is YCBCR420, output_format is RGB: Convert to YCBCR444 and Downsample */
>>>> + crtc_state->dp_dfp_config.rgb_to_ycbcr = true;
>>>> + crtc_state->dp_dfp_config.ycbcr_444_to_420 = true;
>>>> +}
>>>> +
>>>> static int
>>>> intel_dp_compute_output_format(struct intel_encoder *encoder,
>>>> struct intel_crtc_state *crtc_state,
>>>> @@ -1984,7 +2010,10 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
>>>>
>>>> crtc_state->output_format = intel_dp_output_format(connector, ycbcr_420_only);
>>>>
>>>> - if (ycbcr_420_only && !intel_dp_is_ycbcr420(intel_dp, crtc_state)) {
>>>> + if (ycbcr_420_only)
>>>> + intel_dp_compute_dfp_ycbcr420(encoder, crtc_state);
>>>> +
>>>> + if (ycbcr_420_only && !intel_dp_is_ycbcr420(crtc_state)) {
>>>> drm_dbg_kms(&i915->drm,
>>>> "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
>>>> crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
>>>> @@ -1993,12 +2022,13 @@ intel_dp_compute_output_format(struct intel_encoder *encoder,
>>>> ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
>>>> respect_downstream_limits);
>>>> if (ret) {
>>>> - if (intel_dp_is_ycbcr420(intel_dp, crtc_state) ||
>>>> + if (intel_dp_is_ycbcr420(crtc_state) ||
>>>> !connector->base.ycbcr_420_allowed ||
>>>> !drm_mode_is_420_also(info, adjusted_mode))
>>>> return ret;
>>>>
>>>> crtc_state->output_format = intel_dp_output_format(connector, true);
>>>> + intel_dp_compute_dfp_ycbcr420(encoder, crtc_state);
>>>> ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
>>>> respect_downstream_limits);
>>>> }
>>>> @@ -2668,8 +2698,7 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
>>>> drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
>>>> str_enable_disable(intel_dp->has_hdmi_sink));
>>>>
>>>> - tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
>>>> - intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
>>>> + tmp = crtc_state->dp_dfp_config.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
>>>>
>>>> if (drm_dp_dpcd_writeb(&intel_dp->aux,
>>>> DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
>>>> @@ -2677,7 +2706,7 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
>>>> "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
>>>> str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
>>>>
>>>> - tmp = intel_dp->dfp.rgb_to_ycbcr ?
>>>> + tmp = crtc_state->dp_dfp_config.rgb_to_ycbcr ?
>>>> DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
>>>>
>>>> if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
>>>> @@ -2686,7 +2715,6 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
>>>> str_enable_disable(tmp));
>>>> }
>>>>
>>>> -
>>>> bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
>>>> {
>>>> u8 dprx = 0;
>>>> @@ -4534,7 +4562,6 @@ intel_dp_update_420(struct intel_dp *intel_dp)
>>>> {
>>>> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>>>> struct intel_connector *connector = intel_dp->attached_connector;
>>>> - bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr;
>>>>
>>>> /* No YCbCr output support on gmch platforms */
>>>> if (HAS_GMCH(i915))
>>>> @@ -4547,39 +4574,28 @@ intel_dp_update_420(struct intel_dp *intel_dp)
>>>> if (IS_IRONLAKE(i915))
>>>> return;
>>>>
>>>> - is_branch = drm_dp_is_branch(intel_dp->dpcd);
>>>> - ycbcr_420_passthrough =
>>>> + if (!drm_dp_is_branch(intel_dp->dpcd)) {
>>>> + connector->base.ycbcr_420_allowed = true;
>>>> + return;
>>>> + }
>>>> +
>>>> + intel_dp->dfp.ycbcr420_passthrough =
>>>> drm_dp_downstream_420_passthrough(intel_dp->dpcd,
>>>> intel_dp->downstream_ports);
>>>> +
>>>> /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
>>>> - ycbcr_444_to_420 =
>>>> + intel_dp->dfp.ycbcr_444_to_420 =
>>>> dp_to_dig_port(intel_dp)->lspcon.active ||
>>>> drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
>>>> intel_dp->downstream_ports);
>>>> - rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
>>>> - intel_dp->downstream_ports,
>>>> - DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
>>>> -
>>>> - if (DISPLAY_VER(i915) >= 11) {
>>>> - /* Let PCON convert from RGB->YCbCr if possible */
>>>> - if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) {
>>>> - intel_dp->dfp.rgb_to_ycbcr = true;
>>>> - intel_dp->dfp.ycbcr_444_to_420 = true;
>>>> - connector->base.ycbcr_420_allowed = true;
>>>> - } else {
>>>> - /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
>>>> - intel_dp->dfp.ycbcr_444_to_420 =
>>>> - ycbcr_444_to_420 && !ycbcr_420_passthrough;
>>>>
>>>> - connector->base.ycbcr_420_allowed =
>>>> - !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
>>>> - }
>>>> - } else {
>>>> - /* 4:4:4->4:2:0 conversion is the only way */
>>>> - intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
>>>> + intel_dp->dfp.rgb_to_ycbcr =
>>>> + drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
>>>> + intel_dp->downstream_ports,
>>>> + DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
>>>>
>>>> - connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
>>>> - }
>>>> + if (intel_dp->dfp.ycbcr420_passthrough || intel_dp->dfp.ycbcr_444_to_420)
>>>> + connector->base.ycbcr_420_allowed = true;
>>>>
>>>> drm_dbg_kms(&i915->drm,
>>>> "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
^ permalink raw reply [flat|nested] 14+ messages in thread
* [Intel-gfx] [PATCH 4/5] drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC
2022-08-22 10:54 [Intel-gfx] [PATCH 0/5] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
` (2 preceding siblings ...)
2022-08-22 10:54 ` [Intel-gfx] [PATCH 3/5] drm/i915/dp: Fix DFP RGB->YCBCR conversion Ankit Nautiyal
@ 2022-08-22 10:54 ` Ankit Nautiyal
2022-08-22 10:54 ` [Intel-gfx] [PATCH 5/5] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP Ankit Nautiyal
` (2 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Ankit Nautiyal @ 2022-08-22 10:54 UTC (permalink / raw)
To: intel-gfx
Currently we use the highest input BPC supported by DP sink while using
DSC.In cases where PCON with HDMI2.1 as branch device, if PCON supports
DSC but HDMI2.1 sink does not supports DSC, The PCON tries to use same
input BPC that is used between Source and the PCON without DSC, which
might not work even with the maximum FRL rate supported by HDMI2.1
sink.
This patch calculates the max BPC that can be sufficient with either
RGB or YCBCR420 format for the maximum FRL rate supported.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 90 ++++++++++++++++++++++++-
1 file changed, 89 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8ccbe591b9e2..f0a62f71904e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -117,6 +117,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
+static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp);
static bool
is_dfp_hdmi_sink_dsc_1_2(struct intel_dp *intel_dp)
@@ -1455,6 +1456,74 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
return drm_dsc_compute_rc_parameters(vdsc_cfg);
}
+static int
+_intel_dp_pcon_hdmi21_get_bpp_nodsc(struct intel_dp *intel_dp,
+ const struct drm_display_mode *adjusted_mode,
+ int max_bpc, bool is_ycbcr420)
+{
+ struct intel_connector *intel_connector = intel_dp->attached_connector;
+ struct drm_connector *connector = &intel_connector->base;
+ int i, num_bpc;
+ u8 dsc_bpc[3] = {0};
+ int req_rate_gbps;
+ int max_frl_rate = connector->display_info.hdmi.max_lanes *
+ connector->display_info.hdmi.max_frl_rate_per_lane;
+
+ /*
+ * Currently DSC with Ycbcr420 is not supported. So for modes with Ycbcr420,
+ * DSC will use RGB and support for RGB->YCBCR444->YCBCR420 conversion is
+ * required from DP HDMI2.1 PCON.
+ */
+ if (is_ycbcr420 && !(intel_dp->dfp.rgb_to_ycbcr || intel_dp->dfp.ycbcr_444_to_420))
+ return 0;
+
+ num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
+ dsc_bpc);
+ for (i = 0; i < num_bpc; i++) {
+ if (dsc_bpc[i] > max_bpc)
+ continue;
+
+ req_rate_gbps = DIV_ROUND_UP(dsc_bpc[i] * 3 * adjusted_mode->clock, 1000000);
+
+ /* YCBCR420 reduces data rate by 2 */
+ if (is_ycbcr420)
+ req_rate_gbps /= 2;
+
+ if (req_rate_gbps < max_frl_rate)
+ return dsc_bpc[i] * 3;
+ }
+
+ return 0;
+}
+
+static int
+intel_dp_pcon_hdmi21_get_bpp_nodsc(struct intel_dp *intel_dp,
+ struct intel_crtc_state *pipe_config,
+ int max_bpc)
+{
+ const struct drm_display_mode *adjusted_mode =
+ &pipe_config->hw.adjusted_mode;
+ struct intel_connector *connector = intel_dp->attached_connector;
+ const struct drm_display_info *info = &connector->base.display_info;
+ bool is_ycbcr420 = drm_mode_is_420_only(info, adjusted_mode);
+ int pipe_bpp;
+
+ pipe_bpp = _intel_dp_pcon_hdmi21_get_bpp_nodsc(intel_dp, adjusted_mode,
+ max_bpc, is_ycbcr420);
+ if (!pipe_bpp && !is_ycbcr420 && drm_mode_is_420_also(info, adjusted_mode)) {
+ is_ycbcr420 = true;
+ pipe_bpp = _intel_dp_pcon_hdmi21_get_bpp_nodsc(intel_dp, adjusted_mode,
+ max_bpc, is_ycbcr420);
+ }
+
+ if (!pipe_bpp && is_ycbcr420) {
+ pipe_config->dp_dfp_config.rgb_to_ycbcr = true;
+ pipe_config->dp_dfp_config.ycbcr_444_to_420 = true;
+ }
+
+ return pipe_bpp;
+}
+
static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state,
@@ -1473,7 +1542,26 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
+ /*
+ * In cases where PCON with HDMI2.1 as branch device, if PCON supports
+ * DSC but HDMI2.1 sink does not supports DSC, The PCON tries to use same
+ * input DSC bpc that is used between Source and PCON with Ycbcr420
+ * format.
+ * So use the max BPC that will be sufficient to show the mode in YCbcr420
+ * without DSC from PCON->HDMI2.1
+ */
+ if (intel_dp_is_hdmi_2_1_sink(intel_dp) &&
+ !is_dfp_hdmi_sink_dsc_1_2(intel_dp)) {
+ pipe_bpp = intel_dp_pcon_hdmi21_get_bpp_nodsc(intel_dp, pipe_config,
+ conn_state->max_requested_bpc);
+ if (!pipe_bpp) {
+ drm_dbg_kms(&dev_priv->drm,
+ "No BPC possible to support the mode without HDMI2.1 DSC\n");
+ return -EINVAL;
+ }
+ } else {
+ pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
+ }
/* Min Input BPC for ICL+ is 8 */
if (pipe_bpp < 8 * 3) {
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [Intel-gfx] [PATCH 5/5] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP
2022-08-22 10:54 [Intel-gfx] [PATCH 0/5] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
` (3 preceding siblings ...)
2022-08-22 10:54 ` [Intel-gfx] [PATCH 4/5] drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC Ankit Nautiyal
@ 2022-08-22 10:54 ` Ankit Nautiyal
2022-08-22 13:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Patchwork
2022-08-23 0:19 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 14+ messages in thread
From: Ankit Nautiyal @ 2022-08-22 10:54 UTC (permalink / raw)
To: intel-gfx
During FRL bandwidth check for downstream HDMI2.1 sink,
the min BPC supported is incorrectly taken for DP, and the check does
not consider ybcr420 only modes.
This patch fixes the bandwidth calculation similar to the TMDS case, by
taking min 8Bpc and considering Ycbcr420 only modes.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 52 ++++++++++++++++++-------
1 file changed, 39 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f0a62f71904e..7f24f7633078 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -118,6 +118,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp);
+static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp);
static bool
is_dfp_hdmi_sink_dsc_1_2(struct intel_dp *intel_dp)
@@ -917,6 +918,32 @@ intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
return MODE_OK;
}
+static int
+intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock,
+ int bpc, bool ycbcr_420_only)
+{
+ int target_bw;
+ int max_frl_bw;
+ int bpp = bpc * 3;
+
+ if (ycbcr_420_only)
+ target_clock /= 2;
+
+ target_bw = bpp * target_clock;
+
+ /* check for MAX FRL BW for both PCON and HDMI2.1 sink */
+ max_frl_bw = min(intel_dp->dfp.pcon_max_frl_bw,
+ intel_dp_hdmi_sink_max_frl(intel_dp));
+
+ /* converting bw from Gbps to Kbps*/
+ max_frl_bw = max_frl_bw * 1000000;
+
+ if (target_bw > max_frl_bw)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
static enum drm_mode_status
intel_dp_mode_valid_downstream(struct intel_connector *connector,
const struct drm_display_mode *mode,
@@ -925,23 +952,24 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
struct intel_dp *intel_dp = intel_attached_dp(connector);
const struct drm_display_info *info = &connector->base.display_info;
enum drm_mode_status status;
- bool ycbcr_420_only;
+ bool ycbcr_420_only = drm_mode_is_420_only(info, mode);
/* If PCON supports FRL MODE, check FRL bandwidth constraints */
if (intel_dp->dfp.pcon_max_frl_bw) {
- int target_bw;
- int max_frl_bw;
- int bpp = intel_dp_mode_min_output_bpp(connector, mode);
-
- target_bw = bpp * target_clock;
- max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
+ /* Assume 8bpc for the HDMI2.1 FRL BW check */
+ status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, ycbcr_420_only);
- /* converting bw from Gbps to Kbps*/
- max_frl_bw = max_frl_bw * 1000000;
+ if (status != MODE_OK) {
+ if (ycbcr_420_only ||
+ !connector->base.ycbcr_420_allowed ||
+ !drm_mode_is_420_also(info, mode))
+ return status;
- if (target_bw > max_frl_bw)
- return MODE_CLOCK_HIGH;
+ status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, true);
+ if (status != MODE_OK)
+ return status;
+ }
return MODE_OK;
}
@@ -950,8 +978,6 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector,
target_clock > intel_dp->dfp.max_dotclock)
return MODE_CLOCK_HIGH;
- ycbcr_420_only = drm_mode_is_420_only(info, mode);
-
/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
8, ycbcr_420_only, true);
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes
2022-08-22 10:54 [Intel-gfx] [PATCH 0/5] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
` (4 preceding siblings ...)
2022-08-22 10:54 ` [Intel-gfx] [PATCH 5/5] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP Ankit Nautiyal
@ 2022-08-22 13:17 ` Patchwork
2022-08-23 0:19 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2022-08-22 13:17 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 10196 bytes --]
== Series Details ==
Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes
URL : https://patchwork.freedesktop.org/series/107550/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12009 -> Patchwork_107550v1
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_107550v1 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_107550v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/index.html
Participating hosts (34 -> 36)
------------------------------
Additional (3): fi-kbl-soraka bat-dg2-8 fi-hsw-4770
Missing (1): bat-dg2-10
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_107550v1:
### IGT changes ###
#### Warnings ####
* igt@i915_suspend@basic-s3-without-i915:
- fi-kbl-7567u: [INCOMPLETE][1] ([i915#6598]) -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/fi-kbl-7567u/igt@i915_suspend@basic-s3-without-i915.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/fi-kbl-7567u/igt@i915_suspend@basic-s3-without-i915.html
- fi-hsw-g3258: [INCOMPLETE][3] ([i915#4817] / [i915#6598]) -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/fi-hsw-g3258/igt@i915_suspend@basic-s3-without-i915.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/fi-hsw-g3258/igt@i915_suspend@basic-s3-without-i915.html
Known issues
------------
Here are the changes found in Patchwork_107550v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_softpin@allocator-basic-reserve:
- fi-hsw-4770: NOTRUN -> [SKIP][5] ([fdo#109271]) +9 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/fi-hsw-4770/igt@gem_softpin@allocator-basic-reserve.html
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#3012])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/fi-hsw-4770/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: NOTRUN -> [INCOMPLETE][7] ([i915#4785])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
- bat-dg1-6: [PASS][8] -> [DMESG-FAIL][9] ([i915#4494] / [i915#4957])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-pnv-d510: NOTRUN -> [INCOMPLETE][10] ([i915#6598] / [i915#6601])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/fi-pnv-d510/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_chamelium@dp-crc-fast:
- fi-hsw-4770: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +7 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/fi-hsw-4770/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_psr@sprite_plane_onoff:
- fi-hsw-4770: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1072]) +3 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html
* igt@runner@aborted:
- fi-kbl-soraka: NOTRUN -> [FAIL][13] ([i915#6219])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/fi-kbl-soraka/igt@runner@aborted.html
#### Possible fixes ####
* igt@fbdev@read:
- {bat-rpls-2}: [SKIP][14] ([i915#2582]) -> [PASS][15] +4 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/bat-rpls-2/igt@fbdev@read.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/bat-rpls-2/igt@fbdev@read.html
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rplp-1}: [DMESG-WARN][16] ([i915#2867]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/bat-rplp-1/igt@gem_exec_suspend@basic-s0@smem.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/bat-rplp-1/igt@gem_exec_suspend@basic-s0@smem.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-cfl-8109u: [DMESG-FAIL][18] ([i915#5334]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/fi-cfl-8109u/igt@i915_selftest@live@gt_heartbeat.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/fi-cfl-8109u/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@requests:
- {bat-rpls-1}: [INCOMPLETE][20] ([i915#6380]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/bat-rpls-1/igt@i915_selftest@live@requests.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/bat-rpls-1/igt@i915_selftest@live@requests.html
- fi-pnv-d510: [DMESG-FAIL][22] ([i915#4528]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/fi-pnv-d510/igt@i915_selftest@live@requests.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/fi-pnv-d510/igt@i915_selftest@live@requests.html
* igt@kms_frontbuffer_tracking@basic:
- {bat-rpls-2}: [SKIP][24] ([i915#1849]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/bat-rpls-2/igt@kms_frontbuffer_tracking@basic.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/bat-rpls-2/igt@kms_frontbuffer_tracking@basic.html
* igt@prime_vgem@basic-fence-flip:
- {bat-rpls-2}: [SKIP][26] ([fdo#109295] / [i915#1845] / [i915#3708]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/bat-rpls-2/igt@prime_vgem@basic-fence-flip.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/bat-rpls-2/igt@prime_vgem@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5950]: https://gitlab.freedesktop.org/drm/intel/issues/5950
[i915#6219]: https://gitlab.freedesktop.org/drm/intel/issues/6219
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6380]: https://gitlab.freedesktop.org/drm/intel/issues/6380
[i915#6598]: https://gitlab.freedesktop.org/drm/intel/issues/6598
[i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
[i915#6601]: https://gitlab.freedesktop.org/drm/intel/issues/6601
[i915#6642]: https://gitlab.freedesktop.org/drm/intel/issues/6642
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
Build changes
-------------
* Linux: CI_DRM_12009 -> Patchwork_107550v1
CI-20190529: 20190529
CI_DRM_12009: bd2720860fed88141880c48f4dccce77cc7f7591 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6633: 40ec79634da4dc7e94309fc9c6043aff3fafc801 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_107550v1: bd2720860fed88141880c48f4dccce77cc7f7591 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
7732ce753cfe drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP
0d6819604d2e drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC
cdfdc886b8fa drm/i915/dp: Fix DFP RGB->YCBCR conversion
770ee03f5d0c drm/i915/dp: Reset frl trained flag before restarting FRL training
43bc53a410d5 drm/i915/dp: Add helper to check DSC1.2 for HDMI2.1 DFP
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/index.html
[-- Attachment #2: Type: text/html, Size: 10016 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes
2022-08-22 10:54 [Intel-gfx] [PATCH 0/5] Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Ankit Nautiyal
` (5 preceding siblings ...)
2022-08-22 13:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes Patchwork
@ 2022-08-23 0:19 ` Patchwork
6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2022-08-23 0:19 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 24526 bytes --]
== Series Details ==
Series: Handle BPC for HDMI2.1 PCON without DSC1.2 sink and other fixes
URL : https://patchwork.freedesktop.org/series/107550/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12009_full -> Patchwork_107550v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_107550v1_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-snb: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [FAIL][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) ([i915#4338])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb6/boot.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb6/boot.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb6/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb6/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb6/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb6/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb5/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb4/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb4/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb4/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb4/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb4/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb4/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb2/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb2/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb2/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb2/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-snb2/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb6/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb6/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb6/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb6/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb6/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb5/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb5/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb5/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb5/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb5/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb5/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb5/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb4/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb4/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb4/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb4/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb4/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb4/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb2/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb2/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb2/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb2/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb2/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb2/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-snb2/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][51] -> [TIMEOUT][52] ([i915#3070])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-iclb3/igt@gem_eio@unwedge-stress.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-iclb6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-contexts:
- shard-iclb: [PASS][53] -> [SKIP][54] ([i915#4525]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-iclb4/igt@gem_exec_balancer@parallel-contexts.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-iclb8/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: [PASS][55] -> [FAIL][56] ([i915#2842]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-glk6/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][57] -> [FAIL][58] ([i915#2842]) +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][59] ([i915#2842])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-iclb1/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][60] -> [SKIP][61] ([i915#2190])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-tglb3/igt@gem_huc_copy@huc-copy.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-tglb7/igt@gem_huc_copy@huc-copy.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [PASS][62] -> [DMESG-WARN][63] ([i915#5566] / [i915#716])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-apl6/igt@gen9_exec_parse@allowed-all.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-apl1/igt@gen9_exec_parse@allowed-all.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-kbl: NOTRUN -> [SKIP][64] ([fdo#109271])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-kbl4/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_cursor_legacy@flip-vs-cursor@varying-size:
- shard-iclb: [PASS][65] -> [FAIL][66] ([i915#2346]) +2 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-iclb8/igt@kms_cursor_legacy@flip-vs-cursor@varying-size.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor@varying-size.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-kbl: [PASS][67] -> [DMESG-WARN][68] ([i915#180]) +3 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][69] ([i915#2672]) +4 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][70] ([i915#2672] / [i915#3555])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-iclb6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1:
- shard-iclb: [PASS][71] -> [SKIP][72] ([i915#5235]) +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-iclb8/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-apl: [PASS][73] -> [DMESG-WARN][74] ([i915#180])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-apl2/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-apl4/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-kbl: [DMESG-WARN][75] ([i915#180]) -> [PASS][76] +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@vecs0.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@vecs0.html
* igt@gem_eio@in-flight-1us:
- shard-tglb: [TIMEOUT][77] ([i915#3063]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-tglb5/igt@gem_eio@in-flight-1us.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-tglb5/igt@gem_eio@in-flight-1us.html
* igt@gem_eio@kms:
- shard-tglb: [FAIL][79] ([i915#5784]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-tglb3/igt@gem_eio@kms.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-tglb7/igt@gem_eio@kms.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-kbl: [FAIL][81] ([i915#2842]) -> [PASS][82] +2 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-kbl4/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-kbl1/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][83] ([i915#454]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-iclb: [FAIL][85] ([i915#1888] / [i915#2546]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch@pipe-a-dp-1:
- shard-kbl: [FAIL][87] ([i915#1188]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-kbl4/igt@kms_hdr@bpc-switch@pipe-a-dp-1.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-kbl1/igt@kms_hdr@bpc-switch@pipe-a-dp-1.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1:
- shard-iclb: [SKIP][89] ([i915#5176]) -> [PASS][90] +2 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-iclb4/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: [SKIP][91] ([fdo#109441]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-iclb1/igt@kms_psr@psr2_sprite_render.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [FAIL][93] ([i915#6117]) -> [SKIP][94] ([i915#4525])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-iclb7/igt@gem_exec_balancer@parallel-ordering.html
* igt@i915_suspend@forcewake:
- shard-apl: [INCOMPLETE][95] ([i915#6598]) -> [INCOMPLETE][96] ([i915#180] / [i915#6598])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-apl4/igt@i915_suspend@forcewake.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-apl4/igt@i915_suspend@forcewake.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-iclb: [SKIP][97] ([i915#658]) -> [SKIP][98] ([i915#2920])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-iclb8/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][99] ([fdo#111068] / [i915#658]) -> [SKIP][100] ([i915#2920])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-iclb8/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-iclb: [FAIL][101] ([i915#5939]) -> [SKIP][102] ([fdo#109642] / [fdo#111068] / [i915#658])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-iclb2/igt@kms_psr2_su@page_flip-nv12.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-iclb4/igt@kms_psr2_su@page_flip-nv12.html
* igt@runner@aborted:
- shard-apl: ([FAIL][103], [FAIL][104]) ([i915#3002] / [i915#4312] / [i915#5257] / [i915#6599]) -> ([FAIL][105], [FAIL][106], [FAIL][107], [FAIL][108]) ([fdo#109271] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#6599])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-apl6/igt@runner@aborted.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12009/shard-apl1/igt@runner@aborted.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-apl1/igt@runner@aborted.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-apl8/igt@runner@aborted.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-apl4/igt@runner@aborted.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/shard-apl1/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3987]: https://gitlab.freedesktop.org/drm/intel/issues/3987
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4338]: https://gitlab.freedesktop.org/drm/intel/issues/4338
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
[i915#6021]: https://gitlab.freedesktop.org/drm/intel/issues/6021
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6598]: https://gitlab.freedesktop.org/drm/intel/issues/6598
[i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
Build changes
-------------
* Linux: CI_DRM_12009 -> Patchwork_107550v1
CI-20190529: 20190529
CI_DRM_12009: bd2720860fed88141880c48f4dccce77cc7f7591 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6633: 40ec79634da4dc7e94309fc9c6043aff3fafc801 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_107550v1: bd2720860fed88141880c48f4dccce77cc7f7591 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107550v1/index.html
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