* [Intel-gfx] [PATCH v2 1/7] drm/i915: Define bitmasks for ilk pfit window pos/size
2023-04-26 13:50 [Intel-gfx] [PATCH v2 0/7] drm/i915: Scaler/pfit stuff Ville Syrjala
@ 2023-04-26 13:50 ` Ville Syrjala
2023-05-03 8:21 ` Jani Nikula
2023-04-26 13:50 ` [Intel-gfx] [PATCH v2 2/7] drm/i915: Remove dead scaler register defines Ville Syrjala
` (8 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Ville Syrjala @ 2023-04-26 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Define and use the bitmasks for the x/y components
of the ilk+ panel filter window pos/size registers.
Note that we stick to the full 16 bit mask even though
the actual hardware limits are lower (and somewhat
platform dependent). BDW is actually limited to
13 bits horizontal and 12 bits vertical, with the high
bits being hardwired to zero. HSW should have the same
limits as BDW. And pre-HSW should be limited to 12bits
in both directions as that's already the limit of the
transcoder timing registers. Curiously on HSW and earlier
platforms all 16 bits can actually be set, but presumably
the hardware ignores the high bits.
v2: Switch back to full 16bit masks since that's what
we use transcoder timign regs and PIPESRC as well
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++++----
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index bf391a6cd8d6..5e40a0ef3457 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -812,8 +812,10 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
else
intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
PF_FILTER_MED_3x3);
- intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
- intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
+ intel_de_write_fw(dev_priv, PF_WIN_POS(pipe),
+ PF_WIN_XPOS(x) | PF_WIN_YPOS(y));
+ intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe),
+ PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height));
}
static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
@@ -3246,8 +3248,10 @@ static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
drm_rect_init(&crtc_state->pch_pfit.dst,
- pos >> 16, pos & 0xffff,
- size >> 16, size & 0xffff);
+ REG_FIELD_GET(PF_WIN_XPOS_MASK, pos),
+ REG_FIELD_GET(PF_WIN_YPOS_MASK, pos),
+ REG_FIELD_GET(PF_WIN_XSIZE_MASK, size),
+ REG_FIELD_GET(PF_WIN_YSIZE_MASK, size));
/*
* We currently do not free assignements of panel fitters on
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dde6e91055bd..f7294a9b5cfa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4025,8 +4025,16 @@
#define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3)
#define _PFA_WIN_SZ 0x68074
#define _PFB_WIN_SZ 0x68874
+#define PF_WIN_XSIZE_MASK REG_GENMASK(31, 16)
+#define PF_WIN_XSIZE(w) REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w))
+#define PF_WIN_YSIZE_MASK REG_GENMASK(15, 0)
+#define PF_WIN_YSIZE(h) REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h))
#define _PFA_WIN_POS 0x68070
#define _PFB_WIN_POS 0x68870
+#define PF_WIN_XPOS_MASK REG_GENMASK(31, 16)
+#define PF_WIN_XPOS(x) REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x))
+#define PF_WIN_YPOS_MASK REG_GENMASK(15, 0)
+#define PF_WIN_YPOS(y) REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y))
#define _PFA_VSCALE 0x68084
#define _PFB_VSCALE 0x68884
#define _PFA_HSCALE 0x68090
--
2.39.2
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [Intel-gfx] [PATCH v2 1/7] drm/i915: Define bitmasks for ilk pfit window pos/size
2023-04-26 13:50 ` [Intel-gfx] [PATCH v2 1/7] drm/i915: Define bitmasks for ilk pfit window pos/size Ville Syrjala
@ 2023-05-03 8:21 ` Jani Nikula
0 siblings, 0 replies; 16+ messages in thread
From: Jani Nikula @ 2023-05-03 8:21 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Wed, 26 Apr 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Define and use the bitmasks for the x/y components
> of the ilk+ panel filter window pos/size registers.
>
> Note that we stick to the full 16 bit mask even though
> the actual hardware limits are lower (and somewhat
> platform dependent). BDW is actually limited to
> 13 bits horizontal and 12 bits vertical, with the high
> bits being hardwired to zero. HSW should have the same
> limits as BDW. And pre-HSW should be limited to 12bits
> in both directions as that's already the limit of the
> transcoder timing registers. Curiously on HSW and earlier
> platforms all 16 bits can actually be set, but presumably
> the hardware ignores the high bits.
>
> v2: Switch back to full 16bit masks since that's what
> we use transcoder timign regs and PIPESRC as well
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++++----
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
> 2 files changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index bf391a6cd8d6..5e40a0ef3457 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -812,8 +812,10 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
> else
> intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
> PF_FILTER_MED_3x3);
> - intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), x << 16 | y);
> - intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), width << 16 | height);
> + intel_de_write_fw(dev_priv, PF_WIN_POS(pipe),
> + PF_WIN_XPOS(x) | PF_WIN_YPOS(y));
> + intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe),
> + PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height));
> }
>
> static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
> @@ -3246,8 +3248,10 @@ static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
> size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
>
> drm_rect_init(&crtc_state->pch_pfit.dst,
> - pos >> 16, pos & 0xffff,
> - size >> 16, size & 0xffff);
> + REG_FIELD_GET(PF_WIN_XPOS_MASK, pos),
> + REG_FIELD_GET(PF_WIN_YPOS_MASK, pos),
> + REG_FIELD_GET(PF_WIN_XSIZE_MASK, size),
> + REG_FIELD_GET(PF_WIN_YSIZE_MASK, size));
>
> /*
> * We currently do not free assignements of panel fitters on
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dde6e91055bd..f7294a9b5cfa 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4025,8 +4025,16 @@
> #define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3)
> #define _PFA_WIN_SZ 0x68074
> #define _PFB_WIN_SZ 0x68874
> +#define PF_WIN_XSIZE_MASK REG_GENMASK(31, 16)
> +#define PF_WIN_XSIZE(w) REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w))
> +#define PF_WIN_YSIZE_MASK REG_GENMASK(15, 0)
> +#define PF_WIN_YSIZE(h) REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h))
> #define _PFA_WIN_POS 0x68070
> #define _PFB_WIN_POS 0x68870
> +#define PF_WIN_XPOS_MASK REG_GENMASK(31, 16)
> +#define PF_WIN_XPOS(x) REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x))
> +#define PF_WIN_YPOS_MASK REG_GENMASK(15, 0)
> +#define PF_WIN_YPOS(y) REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y))
> #define _PFA_VSCALE 0x68084
> #define _PFB_VSCALE 0x68884
> #define _PFA_HSCALE 0x68090
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v2 2/7] drm/i915: Remove dead scaler register defines
2023-04-26 13:50 [Intel-gfx] [PATCH v2 0/7] drm/i915: Scaler/pfit stuff Ville Syrjala
2023-04-26 13:50 ` [Intel-gfx] [PATCH v2 1/7] drm/i915: Define bitmasks for ilk pfit window pos/size Ville Syrjala
@ 2023-04-26 13:50 ` Ville Syrjala
2023-04-26 13:50 ` [Intel-gfx] [PATCH v2 3/7] drm/i915: Rename skl+ scaler binding bits Ville Syrjala
` (7 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjala @ 2023-04-26 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We have some duplicated scaler register defines that are
never used. Remove them.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f7294a9b5cfa..d3f5771bd82b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4046,18 +4046,6 @@
#define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
#define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
-#define _PSA_CTL 0x68180
-#define _PSB_CTL 0x68980
-#define PS_ENABLE (1 << 31)
-#define _PSA_WIN_SZ 0x68174
-#define _PSB_WIN_SZ 0x68974
-#define _PSA_WIN_POS 0x68170
-#define _PSB_WIN_POS 0x68970
-
-#define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
-#define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
-#define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
-
/*
* Skylake scalers
*/
--
2.39.2
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Intel-gfx] [PATCH v2 3/7] drm/i915: Rename skl+ scaler binding bits
2023-04-26 13:50 [Intel-gfx] [PATCH v2 0/7] drm/i915: Scaler/pfit stuff Ville Syrjala
2023-04-26 13:50 ` [Intel-gfx] [PATCH v2 1/7] drm/i915: Define bitmasks for ilk pfit window pos/size Ville Syrjala
2023-04-26 13:50 ` [Intel-gfx] [PATCH v2 2/7] drm/i915: Remove dead scaler register defines Ville Syrjala
@ 2023-04-26 13:50 ` Ville Syrjala
2023-04-26 13:50 ` [Intel-gfx] [PATCH v2 4/7] drm/i915: s/PS_COEE_INDEX_AUTO_INC/PS_COEF_INDEX_AUTO_INC/ Ville Syrjala
` (6 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjala @ 2023-04-26 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rename the scaler binding bits to match the spec more closely.
Also call the parameters 'plane_id' to make it a bit more clear
what to pass in.
v2: Don't break gvt
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/skl_scaler.c | 12 ++++++------
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 9 +++++----
3 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index ec930aec21c4..a96f8ecbeec1 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -396,7 +396,7 @@ static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_stat
mode = PS_SCALER_MODE_PLANAR;
if (linked)
- mode |= PS_PLANE_Y_SEL(linked->id);
+ mode |= PS_BINDING_Y_PLANE(linked->id);
}
} else if (DISPLAY_VER(dev_priv) >= 10) {
mode = PS_SCALER_MODE_NORMAL;
@@ -741,8 +741,8 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
id = scaler_state->scaler_id;
- ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
- ps_ctrl |= PS_SCALER_EN | scaler_state->scalers[id].mode;
+ ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode |
+ skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
skl_scaler_setup_filter(dev_priv, pipe, id, 0,
crtc_state->hw.scaling_filter);
@@ -804,8 +804,8 @@ skl_program_plane_scaler(struct intel_plane *plane,
uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
}
- ps_ctrl = skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);
- ps_ctrl |= PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode;
+ ps_ctrl = PS_SCALER_EN | PS_BINDING_PLANE(plane->id) | scaler->mode |
+ skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);
skl_scaler_setup_filter(dev_priv, pipe, scaler_id, 0,
plane_state->hw.scaling_filter);
@@ -870,7 +870,7 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
u32 ctl, pos, size;
ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i));
- if ((ctl & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
+ if ((ctl & (PS_SCALER_EN | PS_BINDING_MASK)) != (PS_SCALER_EN | PS_BINDING_PIPE))
continue;
id = i;
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 4b45a041ac5c..a9f7fa9b90bd 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1562,7 +1562,7 @@ static int pf_write(struct intel_vgpu *vgpu,
if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
- offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
+ offset == _PS_1C_CTRL) && (val & PS_BINDING_MASK) != PS_BINDING_PIPE) {
drm_WARN_ONCE(&i915->drm, true,
"VM(%d): guest is trying to scaling a plane\n",
vgpu->id);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d3f5771bd82b..2ced1cf35446 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4061,8 +4061,9 @@
#define SKL_PS_SCALER_MODE_NV12 (2 << 28)
#define PS_SCALER_MODE_PLANAR (1 << 29)
#define PS_SCALER_MODE_NORMAL (0 << 29)
-#define PS_PLANE_SEL_MASK (7 << 25)
-#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
+#define PS_BINDING_MASK (7 << 25)
+#define PS_BINDING_PIPE (0 << 25)
+#define PS_BINDING_PLANE(plane_id) (((plane_id) + 1) << 25)
#define PS_FILTER_MASK (3 << 23)
#define PS_FILTER_MEDIUM (0 << 23)
#define PS_FILTER_PROGRAMMED (1 << 23)
@@ -4078,8 +4079,8 @@
#define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
#define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
#define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
-#define PS_PLANE_Y_SEL_MASK (7 << 5)
-#define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5)
+#define PS_BINDING_Y_MASK (7 << 5)
+#define PS_BINDING_Y_PLANE(plane_id) (((plane_id) + 1) << 5)
#define PS_Y_VERT_FILTER_SELECT(set) ((set) << 4)
#define PS_Y_HORZ_FILTER_SELECT(set) ((set) << 3)
#define PS_UV_VERT_FILTER_SELECT(set) ((set) << 2)
--
2.39.2
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Intel-gfx] [PATCH v2 4/7] drm/i915: s/PS_COEE_INDEX_AUTO_INC/PS_COEF_INDEX_AUTO_INC/
2023-04-26 13:50 [Intel-gfx] [PATCH v2 0/7] drm/i915: Scaler/pfit stuff Ville Syrjala
` (2 preceding siblings ...)
2023-04-26 13:50 ` [Intel-gfx] [PATCH v2 3/7] drm/i915: Rename skl+ scaler binding bits Ville Syrjala
@ 2023-04-26 13:50 ` Ville Syrjala
2023-04-26 13:50 ` [Intel-gfx] [PATCH v2 5/7] drm/i915: Define bitmasks for skl+ scaler window pos/size Ville Syrjala
` (5 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjala @ 2023-04-26 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Fix a typo in the PS_COEF_INDEX_AUTO_INC define.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/skl_scaler.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index a96f8ecbeec1..4437d130293a 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -658,7 +658,7 @@ static void glk_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
int i;
intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set),
- PS_COEE_INDEX_AUTO_INC);
+ PS_COEF_INDEX_AUTO_INC);
for (i = 0; i < 17 * 7; i += 2) {
u32 tmp;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2ced1cf35446..530bc961088f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4151,7 +4151,7 @@
#define _PS_COEF_SET0_INDEX_2A 0x68298
#define _PS_COEF_SET0_INDEX_1B 0x68998
#define _PS_COEF_SET0_INDEX_2B 0x68A98
-#define PS_COEE_INDEX_AUTO_INC (1 << 10)
+#define PS_COEF_INDEX_AUTO_INC (1 << 10)
#define _PS_COEF_SET0_DATA_1A 0x6819C
#define _PS_COEF_SET0_DATA_2A 0x6829C
--
2.39.2
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Intel-gfx] [PATCH v2 5/7] drm/i915: Define bitmasks for skl+ scaler window pos/size
2023-04-26 13:50 [Intel-gfx] [PATCH v2 0/7] drm/i915: Scaler/pfit stuff Ville Syrjala
` (3 preceding siblings ...)
2023-04-26 13:50 ` [Intel-gfx] [PATCH v2 4/7] drm/i915: s/PS_COEE_INDEX_AUTO_INC/PS_COEF_INDEX_AUTO_INC/ Ville Syrjala
@ 2023-04-26 13:50 ` Ville Syrjala
2023-05-03 8:22 ` Jani Nikula
2023-04-26 13:50 ` [Intel-gfx] [PATCH v2 6/7] drm/i915: Use REG_BIT() & co. for pipe scaler registers Ville Syrjala
` (4 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Ville Syrjala @ 2023-04-26 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Define and use the bitmasks for the x/y components
of the skl+ scaler window pos/size registers.
We stick to the full 16 bits mask here even though the
hardware limits are actually lower. The current (ADL)
hardware maximums are in fact: 14 bits for X size, 13 bits
for X pos, 13 bits for Y size/pos. Yes, that is correct,
X pos has less bits than the X size for some reason. But
that doesn't actually matter for now as we don't currently
even support such wide displays without the use of bigjoiner
(due to max plane width limit).
v2: Switch back to full 16bit masks since that's what
we use transcoder timign regs and PIPESRC as well
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/skl_scaler.c | 14 ++++++++------
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index 4437d130293a..1e7c97243fcf 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -754,9 +754,9 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
- x << 16 | y);
+ PS_WIN_XPOS(x) | PS_WIN_YPOS(y));
intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
- width << 16 | height);
+ PS_WIN_XSIZE(width) | PS_WIN_YSIZE(height));
}
void
@@ -816,9 +816,9 @@ skl_program_plane_scaler(struct intel_plane *plane,
intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id),
PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id),
- (crtc_x << 16) | crtc_y);
+ PS_WIN_XPOS(crtc_x) | PS_WIN_YPOS(crtc_y));
intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id),
- (crtc_w << 16) | crtc_h);
+ PS_WIN_XSIZE(crtc_w) | PS_WIN_YSIZE(crtc_h));
}
static void skl_detach_scaler(struct intel_crtc *crtc, int id)
@@ -880,8 +880,10 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
drm_rect_init(&crtc_state->pch_pfit.dst,
- pos >> 16, pos & 0xffff,
- size >> 16, size & 0xffff);
+ REG_FIELD_GET(PS_WIN_XPOS_MASK, pos),
+ REG_FIELD_GET(PS_WIN_YPOS_MASK, pos),
+ REG_FIELD_GET(PS_WIN_XSIZE_MASK, size),
+ REG_FIELD_GET(PS_WIN_YSIZE_MASK, size));
scaler_state->scalers[i].in_use = true;
break;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 530bc961088f..b6f691107571 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4106,12 +4106,20 @@
#define _PS_WIN_POS_1B 0x68970
#define _PS_WIN_POS_2B 0x68A70
#define _PS_WIN_POS_1C 0x69170
+#define PS_WIN_XPOS_MASK REG_GENMASK(31, 16)
+#define PS_WIN_XPOS(x) REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x))
+#define PS_WIN_YPOS_MASK REG_GENMASK(15, 0)
+#define PS_WIN_YPOS(y) REG_FIELD_PREP(PS_WIN_YPOS_MASK, (y))
#define _PS_WIN_SZ_1A 0x68174
#define _PS_WIN_SZ_2A 0x68274
#define _PS_WIN_SZ_1B 0x68974
#define _PS_WIN_SZ_2B 0x68A74
#define _PS_WIN_SZ_1C 0x69174
+#define PS_WIN_XSIZE_MASK REG_GENMASK(31, 16)
+#define PS_WIN_XSIZE(w) REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w))
+#define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0)
+#define PS_WIN_YSIZE(h) REG_FIELD_PREP(PS_WIN_YSIZE_MASK, (h))
#define _PS_VSCALE_1A 0x68184
#define _PS_VSCALE_2A 0x68284
--
2.39.2
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [Intel-gfx] [PATCH v2 5/7] drm/i915: Define bitmasks for skl+ scaler window pos/size
2023-04-26 13:50 ` [Intel-gfx] [PATCH v2 5/7] drm/i915: Define bitmasks for skl+ scaler window pos/size Ville Syrjala
@ 2023-05-03 8:22 ` Jani Nikula
0 siblings, 0 replies; 16+ messages in thread
From: Jani Nikula @ 2023-05-03 8:22 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Wed, 26 Apr 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Define and use the bitmasks for the x/y components
> of the skl+ scaler window pos/size registers.
>
> We stick to the full 16 bits mask here even though the
> hardware limits are actually lower. The current (ADL)
> hardware maximums are in fact: 14 bits for X size, 13 bits
> for X pos, 13 bits for Y size/pos. Yes, that is correct,
> X pos has less bits than the X size for some reason. But
> that doesn't actually matter for now as we don't currently
> even support such wide displays without the use of bigjoiner
> (due to max plane width limit).
>
> v2: Switch back to full 16bit masks since that's what
> we use transcoder timign regs and PIPESRC as well
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_scaler.c | 14 ++++++++------
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
> 2 files changed, 16 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
> index 4437d130293a..1e7c97243fcf 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -754,9 +754,9 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
> intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
> PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
> intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
> - x << 16 | y);
> + PS_WIN_XPOS(x) | PS_WIN_YPOS(y));
> intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
> - width << 16 | height);
> + PS_WIN_XSIZE(width) | PS_WIN_YSIZE(height));
> }
>
> void
> @@ -816,9 +816,9 @@ skl_program_plane_scaler(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id),
> PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
> intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id),
> - (crtc_x << 16) | crtc_y);
> + PS_WIN_XPOS(crtc_x) | PS_WIN_YPOS(crtc_y));
> intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id),
> - (crtc_w << 16) | crtc_h);
> + PS_WIN_XSIZE(crtc_w) | PS_WIN_YSIZE(crtc_h));
> }
>
> static void skl_detach_scaler(struct intel_crtc *crtc, int id)
> @@ -880,8 +880,10 @@ void skl_scaler_get_config(struct intel_crtc_state *crtc_state)
> size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i));
>
> drm_rect_init(&crtc_state->pch_pfit.dst,
> - pos >> 16, pos & 0xffff,
> - size >> 16, size & 0xffff);
> + REG_FIELD_GET(PS_WIN_XPOS_MASK, pos),
> + REG_FIELD_GET(PS_WIN_YPOS_MASK, pos),
> + REG_FIELD_GET(PS_WIN_XSIZE_MASK, size),
> + REG_FIELD_GET(PS_WIN_YSIZE_MASK, size));
>
> scaler_state->scalers[i].in_use = true;
> break;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 530bc961088f..b6f691107571 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4106,12 +4106,20 @@
> #define _PS_WIN_POS_1B 0x68970
> #define _PS_WIN_POS_2B 0x68A70
> #define _PS_WIN_POS_1C 0x69170
> +#define PS_WIN_XPOS_MASK REG_GENMASK(31, 16)
> +#define PS_WIN_XPOS(x) REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x))
> +#define PS_WIN_YPOS_MASK REG_GENMASK(15, 0)
> +#define PS_WIN_YPOS(y) REG_FIELD_PREP(PS_WIN_YPOS_MASK, (y))
>
> #define _PS_WIN_SZ_1A 0x68174
> #define _PS_WIN_SZ_2A 0x68274
> #define _PS_WIN_SZ_1B 0x68974
> #define _PS_WIN_SZ_2B 0x68A74
> #define _PS_WIN_SZ_1C 0x69174
> +#define PS_WIN_XSIZE_MASK REG_GENMASK(31, 16)
> +#define PS_WIN_XSIZE(w) REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w))
> +#define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0)
> +#define PS_WIN_YSIZE(h) REG_FIELD_PREP(PS_WIN_YSIZE_MASK, (h))
>
> #define _PS_VSCALE_1A 0x68184
> #define _PS_VSCALE_2A 0x68284
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v2 6/7] drm/i915: Use REG_BIT() & co. for pipe scaler registers
2023-04-26 13:50 [Intel-gfx] [PATCH v2 0/7] drm/i915: Scaler/pfit stuff Ville Syrjala
` (4 preceding siblings ...)
2023-04-26 13:50 ` [Intel-gfx] [PATCH v2 5/7] drm/i915: Define bitmasks for skl+ scaler window pos/size Ville Syrjala
@ 2023-04-26 13:50 ` Ville Syrjala
2023-04-26 13:50 ` [Intel-gfx] [PATCH v2 7/7] drm/i915: Define more PS_CTRL bits Ville Syrjala
` (3 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Ville Syrjala @ 2023-04-26 13:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pimp the skl+ scaler register bits with REG_BIT()/etc.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 98 ++++++++++++++++++---------------
1 file changed, 53 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b6f691107571..f5ae8d1eb6ff 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4054,52 +4054,58 @@
#define _PS_1B_CTRL 0x68980
#define _PS_2B_CTRL 0x68A80
#define _PS_1C_CTRL 0x69180
-#define PS_SCALER_EN (1 << 31)
-#define SKL_PS_SCALER_MODE_MASK (3 << 28)
-#define SKL_PS_SCALER_MODE_DYN (0 << 28)
-#define SKL_PS_SCALER_MODE_HQ (1 << 28)
-#define SKL_PS_SCALER_MODE_NV12 (2 << 28)
-#define PS_SCALER_MODE_PLANAR (1 << 29)
-#define PS_SCALER_MODE_NORMAL (0 << 29)
-#define PS_BINDING_MASK (7 << 25)
-#define PS_BINDING_PIPE (0 << 25)
-#define PS_BINDING_PLANE(plane_id) (((plane_id) + 1) << 25)
-#define PS_FILTER_MASK (3 << 23)
-#define PS_FILTER_MEDIUM (0 << 23)
-#define PS_FILTER_PROGRAMMED (1 << 23)
-#define PS_FILTER_EDGE_ENHANCE (2 << 23)
-#define PS_FILTER_BILINEAR (3 << 23)
-#define PS_VERT3TAP (1 << 21)
-#define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
-#define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
-#define PS_PWRUP_PROGRESS (1 << 17)
-#define PS_V_FILTER_BYPASS (1 << 8)
-#define PS_VADAPT_EN (1 << 7)
-#define PS_VADAPT_MODE_MASK (3 << 5)
-#define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
-#define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
-#define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
-#define PS_BINDING_Y_MASK (7 << 5)
-#define PS_BINDING_Y_PLANE(plane_id) (((plane_id) + 1) << 5)
-#define PS_Y_VERT_FILTER_SELECT(set) ((set) << 4)
-#define PS_Y_HORZ_FILTER_SELECT(set) ((set) << 3)
-#define PS_UV_VERT_FILTER_SELECT(set) ((set) << 2)
-#define PS_UV_HORZ_FILTER_SELECT(set) ((set) << 1)
+#define PS_SCALER_EN REG_BIT(31)
+#define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */
+#define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)
+#define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1)
+#define SKL_PS_SCALER_MODE_NV12 REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 2)
+#define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
+#define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)
+#define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1)
+#define PS_BINDING_MASK REG_GENMASK(27, 25)
+#define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0)
+#define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1)
+#define PS_FILTER_MASK REG_GENMASK(24, 23)
+#define PS_FILTER_MEDIUM REG_FIELD_PREP(PS_FILTER_MASK, 0)
+#define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1)
+#define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2)
+#define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3)
+#define PS_VERT3TAP REG_BIT(21) /* skl/bxt */
+#define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
+#define PS_PWRUP_PROGRESS REG_BIT(17)
+#define PS_V_FILTER_BYPASS REG_BIT(8)
+#define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */
+#define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5) /* skl/bxt */
+#define PS_VADAPT_MODE_LEAST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0)
+#define PS_VADAPT_MODE_MOD_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 1)
+#define PS_VADAPT_MODE_MOST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 3)
+#define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */
+#define PS_BINDING_Y_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1)
+#define PS_Y_VERT_FILTER_SELECT_MASK REG_BIT(4) /* glk+ */
+#define PS_Y_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_VERT_FILTER_SELECT_MASK, (set))
+#define PS_Y_HORZ_FILTER_SELECT_MASK REG_BIT(3) /* glk+ */
+#define PS_Y_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_HORZ_FILTER_SELECT_MASK, (set))
+#define PS_UV_VERT_FILTER_SELECT_MASK REG_BIT(2) /* glk+ */
+#define PS_UV_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_VERT_FILTER_SELECT_MASK, (set))
+#define PS_UV_HORZ_FILTER_SELECT_MASK REG_BIT(1) /* glk+ */
+#define PS_UV_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_HORZ_FILTER_SELECT_MASK, (set))
#define _PS_PWR_GATE_1A 0x68160
#define _PS_PWR_GATE_2A 0x68260
#define _PS_PWR_GATE_1B 0x68960
#define _PS_PWR_GATE_2B 0x68A60
#define _PS_PWR_GATE_1C 0x69160
-#define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
-#define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
-#define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
-#define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
-#define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
-#define PS_PWR_GATE_SLPEN_8 0
-#define PS_PWR_GATE_SLPEN_16 1
-#define PS_PWR_GATE_SLPEN_24 2
-#define PS_PWR_GATE_SLPEN_32 3
+#define PS_PWR_GATE_DIS_OVERRIDE REG_BIT(31)
+#define PS_PWR_GATE_SETTLING_TIME_MASK REG_GENMASK(4, 3)
+#define PS_PWR_GATE_SETTLING_TIME_32 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0)
+#define PS_PWR_GATE_SETTLING_TIME_64 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 1)
+#define PS_PWR_GATE_SETTLING_TIME_96 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 2)
+#define PS_PWR_GATE_SETTLING_TIME_128 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 3)
+#define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0)
+#define PS_PWR_GATE_SLPEN_8 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0)
+#define PS_PWR_GATE_SLPEN_16 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 1)
+#define PS_PWR_GATE_SLPEN_24 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 2)
+#define PS_PWR_GATE_SLPEN_32 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 3)
#define _PS_WIN_POS_1A 0x68170
#define _PS_WIN_POS_2A 0x68270
@@ -4138,10 +4144,12 @@
#define _PS_VPHASE_1B 0x68988
#define _PS_VPHASE_2B 0x68A88
#define _PS_VPHASE_1C 0x69188
-#define PS_Y_PHASE(x) ((x) << 16)
-#define PS_UV_RGB_PHASE(x) ((x) << 0)
-#define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
-#define PS_PHASE_TRIP (1 << 0)
+#define PS_Y_PHASE_MASK REG_GENMASK(31, 16)
+#define PS_Y_PHASE(x) REG_FIELD_PREP(PS_Y_PHASE_MASK, (x))
+#define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0)
+#define PS_UV_RGB_PHASE(x) REG_FIELD_PREP(PS_UV_RGB_PHASE_MASK, (x))
+#define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
+#define PS_PHASE_TRIP (1 << 0)
#define _PS_HPHASE_1A 0x68194
#define _PS_HPHASE_2A 0x68294
@@ -4159,7 +4167,7 @@
#define _PS_COEF_SET0_INDEX_2A 0x68298
#define _PS_COEF_SET0_INDEX_1B 0x68998
#define _PS_COEF_SET0_INDEX_2B 0x68A98
-#define PS_COEF_INDEX_AUTO_INC (1 << 10)
+#define PS_COEF_INDEX_AUTO_INC REG_BIT(10)
#define _PS_COEF_SET0_DATA_1A 0x6819C
#define _PS_COEF_SET0_DATA_2A 0x6829C
--
2.39.2
^ permalink raw reply related [flat|nested] 16+ messages in thread* [Intel-gfx] [PATCH v2 7/7] drm/i915: Define more PS_CTRL bits
2023-04-26 13:50 [Intel-gfx] [PATCH v2 0/7] drm/i915: Scaler/pfit stuff Ville Syrjala
` (5 preceding siblings ...)
2023-04-26 13:50 ` [Intel-gfx] [PATCH v2 6/7] drm/i915: Use REG_BIT() & co. for pipe scaler registers Ville Syrjala
@ 2023-04-26 13:50 ` Ville Syrjala
2023-05-11 7:29 ` Luca Coelho
2023-04-26 14:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Scaler/pfit stuff (rev3) Patchwork
` (2 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Ville Syrjala @ 2023-04-26 13:50 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
To avoid annoying spec lookups let's define more PS_CTRL
bits in the header.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f5ae8d1eb6ff..e08bb15eddcf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4055,6 +4055,9 @@
#define _PS_2B_CTRL 0x68A80
#define _PS_1C_CTRL 0x69180
#define PS_SCALER_EN REG_BIT(31)
+#define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */
+#define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0)
+#define PS_SCALER_TYPE_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1)
#define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */
#define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)
#define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1)
@@ -4062,6 +4065,7 @@
#define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
#define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)
#define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1)
+#define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */
#define PS_BINDING_MASK REG_GENMASK(27, 25)
#define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0)
#define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1)
@@ -4070,8 +4074,15 @@
#define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1)
#define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2)
#define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3)
+#define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */
+#define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0)
+#define PS_ADAPTIVE_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1)
+#define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */
+#define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */
+#define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */
#define PS_VERT3TAP REG_BIT(21) /* skl/bxt */
#define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
+#define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
#define PS_PWRUP_PROGRESS REG_BIT(17)
#define PS_V_FILTER_BYPASS REG_BIT(8)
#define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */
--
2.39.2
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [Intel-gfx] [PATCH v2 7/7] drm/i915: Define more PS_CTRL bits
2023-04-26 13:50 ` [Intel-gfx] [PATCH v2 7/7] drm/i915: Define more PS_CTRL bits Ville Syrjala
@ 2023-05-11 7:29 ` Luca Coelho
2023-05-11 11:54 ` Ville Syrjälä
0 siblings, 1 reply; 16+ messages in thread
From: Luca Coelho @ 2023-05-11 7:29 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Wed, 2023-04-26 at 16:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> To avoid annoying spec lookups let's define more PS_CTRL
> bits in the header.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f5ae8d1eb6ff..e08bb15eddcf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4055,6 +4055,9 @@
> #define _PS_2B_CTRL 0x68A80
> #define _PS_1C_CTRL 0x69180
> #define PS_SCALER_EN REG_BIT(31)
> +#define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */
> +#define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0)
> +#define PS_SCALER_TYPE_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1)
> #define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */
> #define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)
> #define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1)
> @@ -4062,6 +4065,7 @@
> #define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
> #define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)
> #define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1)
> +#define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */
> #define PS_BINDING_MASK REG_GENMASK(27, 25)
> #define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0)
> #define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1)
> @@ -4070,8 +4074,15 @@
> #define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1)
> #define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2)
> #define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3)
> +#define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */
> +#define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0)
> +#define PS_ADAPTIVE_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1)
> +#define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */
> +#define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */
> +#define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */
> #define PS_VERT3TAP REG_BIT(21) /* skl/bxt */
> #define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
> +#define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
This one is actually a two-bit field, isn't it? 19:18. And why not
define the values for it here too, like with the previous ones?
> #define PS_PWRUP_PROGRESS REG_BIT(17)
> #define PS_V_FILTER_BYPASS REG_BIT(8)
> #define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */
--
Cheers,
Luca.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH v2 7/7] drm/i915: Define more PS_CTRL bits
2023-05-11 7:29 ` Luca Coelho
@ 2023-05-11 11:54 ` Ville Syrjälä
2023-05-11 12:54 ` Luca Coelho
0 siblings, 1 reply; 16+ messages in thread
From: Ville Syrjälä @ 2023-05-11 11:54 UTC (permalink / raw)
To: Luca Coelho; +Cc: intel-gfx
On Thu, May 11, 2023 at 10:29:01AM +0300, Luca Coelho wrote:
> On Wed, 2023-04-26 at 16:50 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > To avoid annoying spec lookups let's define more PS_CTRL
> > bits in the header.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++
> > 1 file changed, 11 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index f5ae8d1eb6ff..e08bb15eddcf 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4055,6 +4055,9 @@
> > #define _PS_2B_CTRL 0x68A80
> > #define _PS_1C_CTRL 0x69180
> > #define PS_SCALER_EN REG_BIT(31)
> > +#define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */
> > +#define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0)
> > +#define PS_SCALER_TYPE_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1)
> > #define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */
> > #define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)
> > #define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1)
> > @@ -4062,6 +4065,7 @@
> > #define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
> > #define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)
> > #define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1)
> > +#define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */
> > #define PS_BINDING_MASK REG_GENMASK(27, 25)
> > #define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0)
> > #define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1)
> > @@ -4070,8 +4074,15 @@
> > #define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1)
> > #define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2)
> > #define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3)
> > +#define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */
> > +#define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0)
> > +#define PS_ADAPTIVE_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1)
> > +#define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */
> > +#define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */
> > +#define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */
> > #define PS_VERT3TAP REG_BIT(21) /* skl/bxt */
> > #define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
> > +#define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
>
> This one is actually a two-bit field, isn't it? 19:18. And why not
> define the values for it here too, like with the previous ones?
It's still a single bit in current hardware.
>
> > #define PS_PWRUP_PROGRESS REG_BIT(17)
> > #define PS_V_FILTER_BYPASS REG_BIT(8)
> > #define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */
>
> --
> Cheers,
> Luca.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH v2 7/7] drm/i915: Define more PS_CTRL bits
2023-05-11 11:54 ` Ville Syrjälä
@ 2023-05-11 12:54 ` Luca Coelho
0 siblings, 0 replies; 16+ messages in thread
From: Luca Coelho @ 2023-05-11 12:54 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, 2023-05-11 at 14:54 +0300, Ville Syrjälä wrote:
> On Thu, May 11, 2023 at 10:29:01AM +0300, Luca Coelho wrote:
> > On Wed, 2023-04-26 at 16:50 +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > To avoid annoying spec lookups let's define more PS_CTRL
> > > bits in the header.
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++
> > > 1 file changed, 11 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index f5ae8d1eb6ff..e08bb15eddcf 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -4055,6 +4055,9 @@
> > > #define _PS_2B_CTRL 0x68A80
> > > #define _PS_1C_CTRL 0x69180
> > > #define PS_SCALER_EN REG_BIT(31)
> > > +#define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */
> > > +#define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0)
> > > +#define PS_SCALER_TYPE_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1)
> > > #define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */
> > > #define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)
> > > #define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1)
> > > @@ -4062,6 +4065,7 @@
> > > #define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
> > > #define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)
> > > #define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1)
> > > +#define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */
> > > #define PS_BINDING_MASK REG_GENMASK(27, 25)
> > > #define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0)
> > > #define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1)
> > > @@ -4070,8 +4074,15 @@
> > > #define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1)
> > > #define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2)
> > > #define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3)
> > > +#define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */
> > > +#define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0)
> > > +#define PS_ADAPTIVE_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1)
> > > +#define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */
> > > +#define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */
> > > +#define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */
> > > #define PS_VERT3TAP REG_BIT(21) /* skl/bxt */
> > > #define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
> > > +#define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
> >
> > This one is actually a two-bit field, isn't it? 19:18. And why not
> > define the values for it here too, like with the previous ones?
>
> It's still a single bit in current hardware.
Oh, sorry, I checked the wrong specs. In that case:
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
--
Cheers,
Luca.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Scaler/pfit stuff (rev3)
2023-04-26 13:50 [Intel-gfx] [PATCH v2 0/7] drm/i915: Scaler/pfit stuff Ville Syrjala
` (6 preceding siblings ...)
2023-04-26 13:50 ` [Intel-gfx] [PATCH v2 7/7] drm/i915: Define more PS_CTRL bits Ville Syrjala
@ 2023-04-26 14:38 ` Patchwork
2023-04-26 14:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-04-26 16:36 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
9 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2023-04-26 14:38 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Scaler/pfit stuff (rev3)
URL : https://patchwork.freedesktop.org/series/116661/
State : warning
== Summary ==
Error: dim checkpatch failed
ac4615b94d96 drm/i915: Define bitmasks for ilk pfit window pos/size
ce3cb0bb3928 drm/i915: Remove dead scaler register defines
d9096dc4ccd6 drm/i915: Rename skl+ scaler binding bits
653e6ee566c0 drm/i915: s/PS_COEE_INDEX_AUTO_INC/PS_COEF_INDEX_AUTO_INC/
2c90e29ecfd0 drm/i915: Define bitmasks for skl+ scaler window pos/size
b5e381d59782 drm/i915: Use REG_BIT() & co. for pipe scaler registers
148d79a1d22b drm/i915: Define more PS_CTRL bits
-:44: WARNING:LONG_LINE_COMMENT: line length of 107 exceeds 100 columns
#44: FILE: drivers/gpu/drm/i915/i915_reg.h:4081:
+#define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */
-:45: WARNING:LONG_LINE_COMMENT: line length of 103 exceeds 100 columns
#45: FILE: drivers/gpu/drm/i915/i915_reg.h:4082:
+#define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */
total: 0 errors, 2 warnings, 0 checks, 31 lines checked
^ permalink raw reply [flat|nested] 16+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Scaler/pfit stuff (rev3)
2023-04-26 13:50 [Intel-gfx] [PATCH v2 0/7] drm/i915: Scaler/pfit stuff Ville Syrjala
` (7 preceding siblings ...)
2023-04-26 14:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Scaler/pfit stuff (rev3) Patchwork
@ 2023-04-26 14:45 ` Patchwork
2023-04-26 16:36 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
9 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2023-04-26 14:45 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4559 bytes --]
== Series Details ==
Series: drm/i915: Scaler/pfit stuff (rev3)
URL : https://patchwork.freedesktop.org/series/116661/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13063 -> Patchwork_116661v3
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/index.html
Participating hosts (38 -> 37)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_116661v3 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [FAIL][1] ([i915#6997] / [i915#7913])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/bat-rpls-2/igt@i915_selftest@live@slpc.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-rpls-2: NOTRUN -> [SKIP][2] ([i915#7828])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/bat-rpls-2/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][3] ([i915#1845] / [i915#5354])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc:
- bat-adlp-9: NOTRUN -> [SKIP][4] ([i915#3546]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/bat-adlp-9/igt@kms_pipe_crc_basic@read-crc.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-rpls-2: NOTRUN -> [SKIP][5] ([i915#1845])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/bat-rpls-2/igt@kms_pipe_crc_basic@suspend-read-crc.html
#### Possible fixes ####
* igt@i915_selftest@live@requests:
- bat-rpls-2: [ABORT][6] ([i915#7913]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13063/bat-rpls-2/igt@i915_selftest@live@requests.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/bat-rpls-2/igt@i915_selftest@live@requests.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-3:
- bat-dg2-9: [FAIL][8] ([fdo#103375]) -> [PASS][9] +2 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13063/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-3.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-dp-3.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-3:
- bat-dg2-9: [FAIL][10] ([fdo#103375] / [i915#7932]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13063/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-3.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-3.html
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
Build changes
-------------
* Linux: CI_DRM_13063 -> Patchwork_116661v3
CI-20190529: 20190529
CI_DRM_13063: d56dad364b19dce932190540edc2f30000c92760 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7271: d12d7eb92226e14745a80e6bdd95384913a43548 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116661v3: d56dad364b19dce932190540edc2f30000c92760 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
f2eea8befe00 drm/i915: Define more PS_CTRL bits
fb489374be0a drm/i915: Use REG_BIT() & co. for pipe scaler registers
d107b29a31ac drm/i915: Define bitmasks for skl+ scaler window pos/size
fc7da0aaacd5 drm/i915: s/PS_COEE_INDEX_AUTO_INC/PS_COEF_INDEX_AUTO_INC/
6402d3e43587 drm/i915: Rename skl+ scaler binding bits
fa48e7d0281b drm/i915: Remove dead scaler register defines
7df33a64a958 drm/i915: Define bitmasks for ilk pfit window pos/size
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/index.html
[-- Attachment #2: Type: text/html, Size: 5596 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Scaler/pfit stuff (rev3)
2023-04-26 13:50 [Intel-gfx] [PATCH v2 0/7] drm/i915: Scaler/pfit stuff Ville Syrjala
` (8 preceding siblings ...)
2023-04-26 14:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-04-26 16:36 ` Patchwork
9 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2023-04-26 16:36 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
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== Series Details ==
Series: drm/i915: Scaler/pfit stuff (rev3)
URL : https://patchwork.freedesktop.org/series/116661/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13063_full -> Patchwork_116661v3_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (7 -> 8)
------------------------------
Additional (1): pig-kbl-iris
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_116661v3_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_endless@dispatch@vecs0:
- {shard-tglu}: [PASS][1] -> [TIMEOUT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13063/shard-tglu-3/igt@gem_exec_endless@dispatch@vecs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/shard-tglu-5/igt@gem_exec_endless@dispatch@vecs0.html
* igt@gem_exec_suspend@basic-s4-devices@lmem0:
- {shard-dg1}: [PASS][3] -> [ABORT][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13063/shard-dg1-16/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/shard-dg1-14/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
* igt@gem_exec_suspend@basic-s4-devices@smem:
- {shard-tglu}: [PASS][5] -> [ABORT][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13063/shard-tglu-2/igt@gem_exec_suspend@basic-s4-devices@smem.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/shard-tglu-10/igt@gem_exec_suspend@basic-s4-devices@smem.html
* igt@i915_pm_rps@waitboost:
- {shard-tglu}: [PASS][7] -> [FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13063/shard-tglu-3/igt@i915_pm_rps@waitboost.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/shard-tglu-5/igt@i915_pm_rps@waitboost.html
Known issues
------------
Here are the changes found in Patchwork_116661v3_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-deadline:
- shard-glk: NOTRUN -> [FAIL][9] ([i915#2846])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/shard-glk2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-glk: NOTRUN -> [FAIL][10] ([i915#2842]) +2 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/shard-glk1/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13063/shard-glk8/igt@gem_exec_fair@basic-pace@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/shard-glk6/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-glk: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) +4 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/shard-glk5/igt@gem_lmem_swapping@verify-ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#3886]) +9 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/shard-glk5/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_color@ctm-green-to-red@pipe-a-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][15] ([fdo#109271]) +36 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/shard-snb1/igt@kms_color@ctm-green-to-red@pipe-a-hdmi-a-1.html
* igt@kms_cursor_crc@cursor-random-max-size:
- shard-glk: NOTRUN -> [SKIP][16] ([fdo#109271]) +151 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/shard-glk1/igt@kms_cursor_crc@cursor-random-max-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [PASS][17] -> [FAIL][18] ([i915#2346])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13063/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-glk: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#658]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/shard-glk5/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-glk: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#2437]) +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/shard-glk5/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@stress-open-close@0-rcs0:
- shard-glk: [PASS][21] -> [ABORT][22] ([i915#7941])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13063/shard-glk8/igt@perf@stress-open-close@0-rcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/shard-glk6/igt@perf@stress-open-close@0-rcs0.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][23] ([i915#2842]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13063/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- {shard-rkl}: [FAIL][25] ([i915#2842]) -> [PASS][26] +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13063/shard-rkl-3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/shard-rkl-1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
- shard-apl: [FAIL][27] ([i915#2842]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13063/shard-apl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/shard-apl2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- {shard-rkl}: [SKIP][29] ([i915#1397]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13063/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/shard-rkl-2/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
### Piglit changes ###
#### Issues hit ####
* igt@i915_suspend@basic-s3-without-i915:
- pig-kbl-iris: NOTRUN -> [INCOMPLETE][31] ([i915#5603])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/pig-kbl-iris/igt@i915_suspend@basic-s3-without-i915.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5603]: https://gitlab.freedesktop.org/drm/intel/issues/5603
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#7941]: https://gitlab.freedesktop.org/drm/intel/issues/7941
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
Build changes
-------------
* Linux: CI_DRM_13063 -> Patchwork_116661v3
CI-20190529: 20190529
CI_DRM_13063: d56dad364b19dce932190540edc2f30000c92760 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7271: d12d7eb92226e14745a80e6bdd95384913a43548 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116661v3: d56dad364b19dce932190540edc2f30000c92760 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116661v3/index.html
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