* [Intel-gfx] [PATCH 0/2] i915: Extract, polish, and document multicast handling
@ 2022-06-11 0:57 Matt Roper
2022-06-11 0:57 ` [Intel-gfx] [PATCH 1/2] drm/i915/gt: Move multicast register handling to a dedicated file Matt Roper
` (6 more replies)
0 siblings, 7 replies; 8+ messages in thread
From: Matt Roper @ 2022-06-11 0:57 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Multicast/replicated (MCR) registers on Intel hardware are a purely
GT-specific concept. Rather than leaving MCR register handling spread
across several places throughout the driver (intel_uncore.c, intel_gt.c,
etc.) with confusing combinations of handler functions living in
different namespaces, let's consolidate it all into a single place
(intel_gt_mcr.c) and provide a more consistent and clearly-documented
interface for the rest of the driver to access such registers:
* intel_gt_mcr_read -- unicast read from specific instance
* intel_gt_mcr_read_any[_fw] -- unicast read from any non-terminated
instance
* intel_gt_mcr_unicast_write -- unicast write to specific instance
* intel_gt_mcr_multicast_write[_fw] -- multicast write to all instances
Matt Roper (2):
drm/i915/gt: Move multicast register handling to a dedicated file
drm/i915/gt: Cleanup interface for MCR operations
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 3 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 36 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 297 +-----------
drivers/gpu/drm/i915/gt/intel_gt.h | 15 -
drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 3 +-
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 483 ++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 34 ++
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 5 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 +-
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu/drm/i915/intel_uncore.c | 112 -----
drivers/gpu/drm/i915/intel_uncore.h | 8 -
14 files changed, 551 insertions(+), 460 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_mcr.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_mcr.h
--
2.35.3
^ permalink raw reply [flat|nested] 8+ messages in thread* [Intel-gfx] [PATCH 1/2] drm/i915/gt: Move multicast register handling to a dedicated file 2022-06-11 0:57 [Intel-gfx] [PATCH 0/2] i915: Extract, polish, and document multicast handling Matt Roper @ 2022-06-11 0:57 ` Matt Roper 2022-06-11 0:57 ` [Intel-gfx] [PATCH 2/2] drm/i915/gt: Cleanup interface for MCR operations Matt Roper ` (5 subsequent siblings) 6 siblings, 0 replies; 8+ messages in thread From: Matt Roper @ 2022-06-11 0:57 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel Handling of multicast/replicated registers is spread across intel_gt.c and intel_uncore.c today. As multicast handling and the related steering logic gets more complicated with the addition of new platforms and new rules it makes sense to centralize it all in one place. For now the existing functions have been moved to the new .c/.h as-is. Function renames and updates to operate in a more consistent manner will be done in subsequent patches. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 1 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 +- drivers/gpu/drm/i915/gt/intel_gt.c | 297 +------------ drivers/gpu/drm/i915/gt/intel_gt.h | 15 - drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 1 + drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 448 ++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 37 ++ drivers/gpu/drm/i915/gt/intel_region_lmem.c | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 + drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 1 + drivers/gpu/drm/i915/i915_drv.h | 2 - drivers/gpu/drm/i915/intel_uncore.c | 112 ----- drivers/gpu/drm/i915/intel_uncore.h | 8 - 14 files changed, 495 insertions(+), 433 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_mcr.c create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_mcr.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index d2b18f03a33c..08f5d0d6e83a 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -103,6 +103,7 @@ gt-y += \ gt/intel_gt_debugfs.o \ gt/intel_gt_engines_debugfs.o \ gt/intel_gt_irq.o \ + gt/intel_gt_mcr.o \ gt/intel_gt_pm.o \ gt/intel_gt_pm_debugfs.o \ gt/intel_gt_pm_irq.o \ diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c index 47b5e0e342ab..da30503d3ca2 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c @@ -13,6 +13,7 @@ #include "gem/i915_gem_lmem.h" #include "gem/i915_gem_region.h" #include "gt/intel_gt.h" +#include "gt/intel_gt_mcr.h" #include "gt/intel_region_lmem.h" #include "i915_drv.h" #include "i915_gem_stolen.h" diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index f0acf8518a51..244af1bdb7db 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -21,8 +21,9 @@ #include "intel_engine_user.h" #include "intel_execlists_submission.h" #include "intel_gt.h" -#include "intel_gt_requests.h" +#include "intel_gt_mcr.h" #include "intel_gt_pm.h" +#include "intel_gt_requests.h" #include "intel_lrc.h" #include "intel_lrc_reg.h" #include "intel_reset.h" diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index f33290358c51..be9877c4b496 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -17,6 +17,7 @@ #include "intel_gt_clock_utils.h" #include "intel_gt_debugfs.h" #include "intel_gt_gmch.h" +#include "intel_gt_mcr.h" #include "intel_gt_pm.h" #include "intel_gt_regs.h" #include "intel_gt_requests.h" @@ -102,107 +103,13 @@ int intel_gt_assign_ggtt(struct intel_gt *gt) return gt->ggtt ? 0 : -ENOMEM; } -static const char * const intel_steering_types[] = { - "L3BANK", - "MSLICE", - "LNCF", - "INSTANCE 0", -}; - -static const struct intel_mmio_range icl_l3bank_steering_table[] = { - { 0x00B100, 0x00B3FF }, - {}, -}; - -static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = { - { 0x004000, 0x004AFF }, - { 0x00C800, 0x00CFFF }, - { 0x00DD00, 0x00DDFF }, - { 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */ - {}, -}; - -static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = { - { 0x00B000, 0x00B0FF }, - { 0x00D800, 0x00D8FF }, - {}, -}; - -static const struct intel_mmio_range dg2_lncf_steering_table[] = { - { 0x00B000, 0x00B0FF }, - { 0x00D880, 0x00D8FF }, - {}, -}; - -/* - * We have several types of MCR registers on PVC where steering to (0,0) - * will always provide us with a non-terminated value. We'll stick them - * all in the same table for simplicity. - */ -static const struct intel_mmio_range pvc_instance0_steering_table[] = { - { 0x004000, 0x004AFF }, /* HALF-BSLICE */ - { 0x008800, 0x00887F }, /* CC */ - { 0x008A80, 0x008AFF }, /* TILEPSMI */ - { 0x00B000, 0x00B0FF }, /* HALF-BSLICE */ - { 0x00B100, 0x00B3FF }, /* L3BANK */ - { 0x00C800, 0x00CFFF }, /* HALF-BSLICE */ - { 0x00D800, 0x00D8FF }, /* HALF-BSLICE */ - { 0x00DD00, 0x00DDFF }, /* BSLICE */ - { 0x00E900, 0x00E9FF }, /* HALF-BSLICE */ - { 0x00EC00, 0x00EEFF }, /* HALF-BSLICE */ - { 0x00F000, 0x00FFFF }, /* HALF-BSLICE */ - { 0x024180, 0x0241FF }, /* HALF-BSLICE */ - {}, -}; - int intel_gt_init_mmio(struct intel_gt *gt) { - struct drm_i915_private *i915 = gt->i915; - intel_gt_init_clock_frequency(gt); intel_uc_init_mmio(>->uc); intel_sseu_info_init(gt); - - /* - * An mslice is unavailable only if both the meml3 for the slice is - * disabled *and* all of the DSS in the slice (quadrant) are disabled. - */ - if (HAS_MSLICE_STEERING(i915)) { - gt->info.mslice_mask = - intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask, - GEN_DSS_PER_MSLICE); - gt->info.mslice_mask |= - (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & - GEN12_MEML3_EN_MASK); - - if (!gt->info.mslice_mask) /* should be impossible! */ - drm_warn(&i915->drm, "mslice mask all zero!\n"); - } - - if (IS_PONTEVECCHIO(i915)) { - gt->steering_table[INSTANCE0] = pvc_instance0_steering_table; - } else if (IS_DG2(i915)) { - gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table; - gt->steering_table[LNCF] = dg2_lncf_steering_table; - } else if (IS_XEHPSDV(i915)) { - gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table; - gt->steering_table[LNCF] = xehpsdv_lncf_steering_table; - } else if (GRAPHICS_VER(i915) >= 11 && - GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) { - gt->steering_table[L3BANK] = icl_l3bank_steering_table; - gt->info.l3bank_mask = - ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & - GEN10_L3BANK_MASK; - if (!gt->info.l3bank_mask) /* should be impossible! */ - drm_warn(&i915->drm, "L3 bank mask is all zero!\n"); - } else if (GRAPHICS_VER(i915) >= 11) { - /* - * We expect all modern platforms to have at least some - * type of steering that needs to be initialized. - */ - MISSING_CASE(INTEL_INFO(i915)->platform); - } + intel_gt_mcr_init(gt); return intel_engines_init_mmio(gt); } @@ -864,206 +771,6 @@ void intel_gt_driver_late_release_all(struct drm_i915_private *i915) } } -/** - * intel_gt_reg_needs_read_steering - determine whether a register read - * requires explicit steering - * @gt: GT structure - * @reg: the register to check steering requirements for - * @type: type of multicast steering to check - * - * Determines whether @reg needs explicit steering of a specific type for - * reads. - * - * Returns false if @reg does not belong to a register range of the given - * steering type, or if the default (subslice-based) steering IDs are suitable - * for @type steering too. - */ -static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt, - i915_reg_t reg, - enum intel_steering_type type) -{ - const u32 offset = i915_mmio_reg_offset(reg); - const struct intel_mmio_range *entry; - - if (likely(!intel_gt_needs_read_steering(gt, type))) - return false; - - for (entry = gt->steering_table[type]; entry->end; entry++) { - if (offset >= entry->start && offset <= entry->end) - return true; - } - - return false; -} - -/** - * intel_gt_get_valid_steering - determines valid IDs for a class of MCR steering - * @gt: GT structure - * @type: multicast register type - * @sliceid: Slice ID returned - * @subsliceid: Subslice ID returned - * - * Determines sliceid and subsliceid values that will steer reads - * of a specific multicast register class to a valid value. - */ -static void intel_gt_get_valid_steering(struct intel_gt *gt, - enum intel_steering_type type, - u8 *sliceid, u8 *subsliceid) -{ - switch (type) { - case L3BANK: - *sliceid = 0; /* unused */ - *subsliceid = __ffs(gt->info.l3bank_mask); - break; - case MSLICE: - GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915)); - *sliceid = __ffs(gt->info.mslice_mask); - *subsliceid = 0; /* unused */ - break; - case LNCF: - /* - * An LNCF is always present if its mslice is present, so we - * can safely just steer to LNCF 0 in all cases. - */ - GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915)); - *sliceid = __ffs(gt->info.mslice_mask) << 1; - *subsliceid = 0; /* unused */ - break; - case INSTANCE0: - /* - * There are a lot of MCR types for which instance (0, 0) - * will always provide a non-terminated value. - */ - *sliceid = 0; - *subsliceid = 0; - break; - default: - MISSING_CASE(type); - *sliceid = 0; - *subsliceid = 0; - } -} - -/** - * intel_gt_read_register_fw - reads a GT register with support for multicast - * @gt: GT structure - * @reg: register to read - * - * This function will read a GT register. If the register is a multicast - * register, the read will be steered to a valid instance (i.e., one that - * isn't fused off or powered down by power gating). - * - * Returns the value from a valid instance of @reg. - */ -u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg) -{ - int type; - u8 sliceid, subsliceid; - - for (type = 0; type < NUM_STEERING_TYPES; type++) { - if (intel_gt_reg_needs_read_steering(gt, reg, type)) { - intel_gt_get_valid_steering(gt, type, &sliceid, - &subsliceid); - return intel_uncore_read_with_mcr_steering_fw(gt->uncore, - reg, - sliceid, - subsliceid); - } - } - - return intel_uncore_read_fw(gt->uncore, reg); -} - -/** - * intel_gt_get_valid_steering_for_reg - get a valid steering for a register - * @gt: GT structure - * @reg: register for which the steering is required - * @sliceid: return variable for slice steering - * @subsliceid: return variable for subslice steering - * - * This function returns a slice/subslice pair that is guaranteed to work for - * read steering of the given register. Note that a value will be returned even - * if the register is not replicated and therefore does not actually require - * steering. - */ -void intel_gt_get_valid_steering_for_reg(struct intel_gt *gt, i915_reg_t reg, - u8 *sliceid, u8 *subsliceid) -{ - int type; - - for (type = 0; type < NUM_STEERING_TYPES; type++) { - if (intel_gt_reg_needs_read_steering(gt, reg, type)) { - intel_gt_get_valid_steering(gt, type, sliceid, - subsliceid); - return; - } - } - - *sliceid = gt->default_steering.groupid; - *subsliceid = gt->default_steering.instanceid; -} - -u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg) -{ - int type; - u8 sliceid, subsliceid; - - for (type = 0; type < NUM_STEERING_TYPES; type++) { - if (intel_gt_reg_needs_read_steering(gt, reg, type)) { - intel_gt_get_valid_steering(gt, type, &sliceid, - &subsliceid); - return intel_uncore_read_with_mcr_steering(gt->uncore, - reg, - sliceid, - subsliceid); - } - } - - return intel_uncore_read(gt->uncore, reg); -} - -static void report_steering_type(struct drm_printer *p, - struct intel_gt *gt, - enum intel_steering_type type, - bool dump_table) -{ - const struct intel_mmio_range *entry; - u8 slice, subslice; - - BUILD_BUG_ON(ARRAY_SIZE(intel_steering_types) != NUM_STEERING_TYPES); - - if (!gt->steering_table[type]) { - drm_printf(p, "%s steering: uses default steering\n", - intel_steering_types[type]); - return; - } - - intel_gt_get_valid_steering(gt, type, &slice, &subslice); - drm_printf(p, "%s steering: sliceid=0x%x, subsliceid=0x%x\n", - intel_steering_types[type], slice, subslice); - - if (!dump_table) - return; - - for (entry = gt->steering_table[type]; entry->end; entry++) - drm_printf(p, "\t0x%06x - 0x%06x\n", entry->start, entry->end); -} - -void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt, - bool dump_table) -{ - drm_printf(p, "Default steering: sliceid=0x%x, subsliceid=0x%x\n", - gt->default_steering.groupid, - gt->default_steering.instanceid); - - if (IS_PONTEVECCHIO(gt->i915)) { - report_steering_type(p, gt, INSTANCE0, dump_table); - } else if (HAS_MSLICE_STEERING(gt->i915)) { - report_steering_type(p, gt, MSLICE, dump_table); - report_steering_type(p, gt, LNCF, dump_table); - } -} - static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr) { int ret; diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h index 44c6cb63ccbc..61d30d5c7e90 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.h +++ b/drivers/gpu/drm/i915/gt/intel_gt.h @@ -93,21 +93,6 @@ static inline bool intel_gt_is_wedged(const struct intel_gt *gt) return unlikely(test_bit(I915_WEDGED, >->reset.flags)); } -static inline bool intel_gt_needs_read_steering(struct intel_gt *gt, - enum intel_steering_type type) -{ - return gt->steering_table[type]; -} - -void intel_gt_get_valid_steering_for_reg(struct intel_gt *gt, i915_reg_t reg, - u8 *sliceid, u8 *subsliceid); - -u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg); -u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg); - -void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt, - bool dump_table); - int intel_gt_probe_all(struct drm_i915_private *i915); int intel_gt_tiles_init(struct drm_i915_private *i915); void intel_gt_release_all(struct drm_i915_private *i915); diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c index d886fdc2c694..ea07f2bb846f 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c @@ -9,6 +9,7 @@ #include "intel_gt.h" #include "intel_gt_debugfs.h" #include "intel_gt_engines_debugfs.h" +#include "intel_gt_mcr.h" #include "intel_gt_pm_debugfs.h" #include "intel_sseu_debugfs.h" #include "pxp/intel_pxp_debugfs.h" diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c new file mode 100644 index 000000000000..1279a1fe1001 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c @@ -0,0 +1,448 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2022 Intel Corporation + */ + +#include "i915_drv.h" + +#include "intel_gt_mcr.h" +#include "intel_gt_regs.h" + +/** + * DOC: GT Multicast/Replicated (MCR) Register Support + * + * Some GT registers are designed as "multicast" or "replicated" registers: + * multiple instances of the same register share a single MMIO offset. MCR + * registers are generally used when the hardware needs to potentially track + * independent values of a register per hardware unit (e.g., per-subslice, + * per-L3bank, etc.). The specific types of replication that exist vary + * per-platform. + * + * MMIO accesses to MCR registers are controlled according to the settings + * programmed in the platform's MCR_SELECTOR register(s). MMIO writes to MCR + * registers can be done in either a (i.e., a single write updates all + * instances of the register to the same value) or unicast (a write updates only + * one specific instance). Reads of MCR registers always operate in a unicast + * manner regardless of how the multicast/unicast bit is set in MCR_SELECTOR. + * Selection of a specific MCR instance for unicast operations is referred to + * as "steering." + * + * If MCR register operations are steered toward a hardware unit that is + * fused off or currently powered down due to power gating, the MMIO operation + * is "terminated" by the hardware. Terminated read operations will return a + * value of zero and terminated unicast write operations will be silently + * ignored. + */ + +#define HAS_MSLICE_STEERING(dev_priv) (INTEL_INFO(dev_priv)->has_mslice_steering) + +static const char * const intel_steering_types[] = { + "L3BANK", + "MSLICE", + "LNCF", + "INSTANCE 0", +}; + +static const struct intel_mmio_range icl_l3bank_steering_table[] = { + { 0x00B100, 0x00B3FF }, + {}, +}; + +static const struct intel_mmio_range xehpsdv_mslice_steering_table[] = { + { 0x004000, 0x004AFF }, + { 0x00C800, 0x00CFFF }, + { 0x00DD00, 0x00DDFF }, + { 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */ + {}, +}; + +static const struct intel_mmio_range xehpsdv_lncf_steering_table[] = { + { 0x00B000, 0x00B0FF }, + { 0x00D800, 0x00D8FF }, + {}, +}; + +static const struct intel_mmio_range dg2_lncf_steering_table[] = { + { 0x00B000, 0x00B0FF }, + { 0x00D880, 0x00D8FF }, + {}, +}; + +/* + * We have several types of MCR registers on PVC where steering to (0,0) + * will always provide us with a non-terminated value. We'll stick them + * all in the same table for simplicity. + */ +static const struct intel_mmio_range pvc_instance0_steering_table[] = { + { 0x004000, 0x004AFF }, /* HALF-BSLICE */ + { 0x008800, 0x00887F }, /* CC */ + { 0x008A80, 0x008AFF }, /* TILEPSMI */ + { 0x00B000, 0x00B0FF }, /* HALF-BSLICE */ + { 0x00B100, 0x00B3FF }, /* L3BANK */ + { 0x00C800, 0x00CFFF }, /* HALF-BSLICE */ + { 0x00D800, 0x00D8FF }, /* HALF-BSLICE */ + { 0x00DD00, 0x00DDFF }, /* BSLICE */ + { 0x00E900, 0x00E9FF }, /* HALF-BSLICE */ + { 0x00EC00, 0x00EEFF }, /* HALF-BSLICE */ + { 0x00F000, 0x00FFFF }, /* HALF-BSLICE */ + { 0x024180, 0x0241FF }, /* HALF-BSLICE */ + {}, +}; + +void intel_gt_mcr_init(struct intel_gt *gt) +{ + struct drm_i915_private *i915 = gt->i915; + + /* + * An mslice is unavailable only if both the meml3 for the slice is + * disabled *and* all of the DSS in the slice (quadrant) are disabled. + */ + if (HAS_MSLICE_STEERING(i915)) { + gt->info.mslice_mask = + intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask, + GEN_DSS_PER_MSLICE); + gt->info.mslice_mask |= + (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & + GEN12_MEML3_EN_MASK); + + if (!gt->info.mslice_mask) /* should be impossible! */ + drm_warn(&i915->drm, "mslice mask all zero!\n"); + } + + if (IS_PONTEVECCHIO(i915)) { + gt->steering_table[INSTANCE0] = pvc_instance0_steering_table; + } else if (IS_DG2(i915)) { + gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table; + gt->steering_table[LNCF] = dg2_lncf_steering_table; + } else if (IS_XEHPSDV(i915)) { + gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table; + gt->steering_table[LNCF] = xehpsdv_lncf_steering_table; + } else if (GRAPHICS_VER(i915) >= 11 && + GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) { + gt->steering_table[L3BANK] = icl_l3bank_steering_table; + gt->info.l3bank_mask = + ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & + GEN10_L3BANK_MASK; + if (!gt->info.l3bank_mask) /* should be impossible! */ + drm_warn(&i915->drm, "L3 bank mask is all zero!\n"); + } else if (GRAPHICS_VER(i915) >= 11) { + /* + * We expect all modern platforms to have at least some + * type of steering that needs to be initialized. + */ + MISSING_CASE(INTEL_INFO(i915)->platform); + } +} + +/** + * uncore_rw_with_mcr_steering_fw - Access a register after programming + * the MCR selector register. + * @uncore: pointer to struct intel_uncore + * @reg: register being accessed + * @rw_flag: FW_REG_READ for read access or FW_REG_WRITE for write access + * @slice: slice number (ignored for multi-cast write) + * @subslice: sub-slice number (ignored for multi-cast write) + * @value: register value to be written (ignored for read) + * + * Return: 0 for write access. register value for read access. + * + * Caller needs to make sure the relevant forcewake wells are up. + */ +static u32 uncore_rw_with_mcr_steering_fw(struct intel_uncore *uncore, + i915_reg_t reg, u8 rw_flag, + int slice, int subslice, u32 value) +{ + u32 mcr_mask, mcr_ss, mcr, old_mcr, val = 0; + + lockdep_assert_held(&uncore->lock); + + if (GRAPHICS_VER(uncore->i915) >= 11) { + mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; + mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); + + /* + * Wa_22013088509 + * + * The setting of the multicast/unicast bit usually wouldn't + * matter for read operations (which always return the value + * from a single register instance regardless of how that bit + * is set), but some platforms have a workaround requiring us + * to remain in multicast mode for reads. There's no real + * downside to this, so we'll just go ahead and do so on all + * platforms; we'll only clear the multicast bit from the mask + * when exlicitly doing a write operation. + */ + if (rw_flag == FW_REG_WRITE) + mcr_mask |= GEN11_MCR_MULTICAST; + } else { + mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; + mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); + } + + old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR); + + mcr &= ~mcr_mask; + mcr |= mcr_ss; + intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); + + if (rw_flag == FW_REG_READ) + val = intel_uncore_read_fw(uncore, reg); + else + intel_uncore_write_fw(uncore, reg, value); + + mcr &= ~mcr_mask; + mcr |= old_mcr & mcr_mask; + + intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); + + return val; +} + +static u32 uncore_rw_with_mcr_steering(struct intel_uncore *uncore, + i915_reg_t reg, u8 rw_flag, + int slice, int subslice, + u32 value) +{ + enum forcewake_domains fw_domains; + u32 val; + + fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, + rw_flag); + fw_domains |= intel_uncore_forcewake_for_reg(uncore, + GEN8_MCR_SELECTOR, + FW_REG_READ | FW_REG_WRITE); + + spin_lock_irq(&uncore->lock); + intel_uncore_forcewake_get__locked(uncore, fw_domains); + + val = uncore_rw_with_mcr_steering_fw(uncore, reg, rw_flag, + slice, subslice, value); + + intel_uncore_forcewake_put__locked(uncore, fw_domains); + spin_unlock_irq(&uncore->lock); + + return val; +} + +u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore, + i915_reg_t reg, int slice, int subslice) +{ + return uncore_rw_with_mcr_steering_fw(uncore, reg, FW_REG_READ, + slice, subslice, 0); +} + +u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore, + i915_reg_t reg, int slice, int subslice) +{ + return uncore_rw_with_mcr_steering(uncore, reg, FW_REG_READ, + slice, subslice, 0); +} + +void intel_uncore_write_with_mcr_steering(struct intel_uncore *uncore, + i915_reg_t reg, u32 value, + int slice, int subslice) +{ + uncore_rw_with_mcr_steering(uncore, reg, FW_REG_WRITE, + slice, subslice, value); +} + +/** + * intel_gt_reg_needs_read_steering - determine whether a register read + * requires explicit steering + * @gt: GT structure + * @reg: the register to check steering requirements for + * @type: type of multicast steering to check + * + * Determines whether @reg needs explicit steering of a specific type for + * reads. + * + * Returns false if @reg does not belong to a register range of the given + * steering type, or if the default (subslice-based) steering IDs are suitable + * for @type steering too. + */ +static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt, + i915_reg_t reg, + enum intel_steering_type type) +{ + const u32 offset = i915_mmio_reg_offset(reg); + const struct intel_mmio_range *entry; + + if (likely(!intel_gt_needs_read_steering(gt, type))) + return false; + + for (entry = gt->steering_table[type]; entry->end; entry++) { + if (offset >= entry->start && offset <= entry->end) + return true; + } + + return false; +} + +/** + * intel_gt_get_valid_steering - determines valid IDs for a class of MCR steering + * @gt: GT structure + * @type: multicast register type + * @sliceid: Slice ID returned + * @subsliceid: Subslice ID returned + * + * Determines sliceid and subsliceid values that will steer reads + * of a specific multicast register class to a valid value. + */ +static void intel_gt_get_valid_steering(struct intel_gt *gt, + enum intel_steering_type type, + u8 *sliceid, u8 *subsliceid) +{ + switch (type) { + case L3BANK: + *sliceid = 0; /* unused */ + *subsliceid = __ffs(gt->info.l3bank_mask); + break; + case MSLICE: + GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915)); + *sliceid = __ffs(gt->info.mslice_mask); + *subsliceid = 0; /* unused */ + break; + case LNCF: + /* + * An LNCF is always present if its mslice is present, so we + * can safely just steer to LNCF 0 in all cases. + */ + GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915)); + *sliceid = __ffs(gt->info.mslice_mask) << 1; + *subsliceid = 0; /* unused */ + break; + case INSTANCE0: + /* + * There are a lot of MCR types for which instance (0, 0) + * will always provide a non-terminated value. + */ + *sliceid = 0; + *subsliceid = 0; + break; + default: + MISSING_CASE(type); + *sliceid = 0; + *subsliceid = 0; + } +} + +/** + * intel_gt_get_valid_steering_for_reg - get a valid steering for a register + * @gt: GT structure + * @reg: register for which the steering is required + * @sliceid: return variable for slice steering + * @subsliceid: return variable for subslice steering + * + * This function returns a slice/subslice pair that is guaranteed to work for + * read steering of the given register. Note that a value will be returned even + * if the register is not replicated and therefore does not actually require + * steering. + */ +void intel_gt_get_valid_steering_for_reg(struct intel_gt *gt, i915_reg_t reg, + u8 *sliceid, u8 *subsliceid) +{ + int type; + + for (type = 0; type < NUM_STEERING_TYPES; type++) { + if (intel_gt_reg_needs_read_steering(gt, reg, type)) { + intel_gt_get_valid_steering(gt, type, sliceid, + subsliceid); + return; + } + } + + *sliceid = gt->default_steering.groupid; + *subsliceid = gt->default_steering.instanceid; +} + +/** + * intel_gt_read_register_fw - reads a GT register with support for multicast + * @gt: GT structure + * @reg: register to read + * + * This function will read a GT register. If the register is a multicast + * register, the read will be steered to a valid instance (i.e., one that + * isn't fused off or powered down by power gating). + * + * Returns the value from a valid instance of @reg. + */ +u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg) +{ + int type; + u8 sliceid, subsliceid; + + for (type = 0; type < NUM_STEERING_TYPES; type++) { + if (intel_gt_reg_needs_read_steering(gt, reg, type)) { + intel_gt_get_valid_steering(gt, type, &sliceid, + &subsliceid); + return intel_uncore_read_with_mcr_steering_fw(gt->uncore, + reg, + sliceid, + subsliceid); + } + } + + return intel_uncore_read_fw(gt->uncore, reg); +} + +u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg) +{ + int type; + u8 sliceid, subsliceid; + + for (type = 0; type < NUM_STEERING_TYPES; type++) { + if (intel_gt_reg_needs_read_steering(gt, reg, type)) { + intel_gt_get_valid_steering(gt, type, &sliceid, + &subsliceid); + return intel_uncore_read_with_mcr_steering(gt->uncore, + reg, + sliceid, + subsliceid); + } + } + + return intel_uncore_read(gt->uncore, reg); +} + +static void report_steering_type(struct drm_printer *p, + struct intel_gt *gt, + enum intel_steering_type type, + bool dump_table) +{ + const struct intel_mmio_range *entry; + u8 slice, subslice; + + BUILD_BUG_ON(ARRAY_SIZE(intel_steering_types) != NUM_STEERING_TYPES); + + if (!gt->steering_table[type]) { + drm_printf(p, "%s steering: uses default steering\n", + intel_steering_types[type]); + return; + } + + intel_gt_get_valid_steering(gt, type, &slice, &subslice); + drm_printf(p, "%s steering: sliceid=0x%x, subsliceid=0x%x\n", + intel_steering_types[type], slice, subslice); + + if (!dump_table) + return; + + for (entry = gt->steering_table[type]; entry->end; entry++) + drm_printf(p, "\t0x%06x - 0x%06x\n", entry->start, entry->end); +} + +void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt, + bool dump_table) +{ + drm_printf(p, "Default steering: sliceid=0x%x, subsliceid=0x%x\n", + gt->default_steering.groupid, + gt->default_steering.instanceid); + + if (IS_PONTEVECCHIO(gt->i915)) { + report_steering_type(p, gt, INSTANCE0, dump_table); + } else if (HAS_MSLICE_STEERING(gt->i915)) { + report_steering_type(p, gt, MSLICE, dump_table); + report_steering_type(p, gt, LNCF, dump_table); + } +} + diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h new file mode 100644 index 000000000000..b570c1571243 --- /dev/null +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2022 Intel Corporation + */ + +#ifndef __INTEL_GT_MCR__ +#define __INTEL_GT_MCR__ + +#include "intel_gt_types.h" + +void intel_gt_mcr_init(struct intel_gt *gt); + +u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore, + i915_reg_t reg, + int slice, int subslice); +u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore, + i915_reg_t reg, int slice, int subslice); +void intel_uncore_write_with_mcr_steering(struct intel_uncore *uncore, + i915_reg_t reg, u32 value, + int slice, int subslice); + +u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg); +u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg); + +static inline bool intel_gt_needs_read_steering(struct intel_gt *gt, + enum intel_steering_type type) +{ + return gt->steering_table[type]; +} + +void intel_gt_get_valid_steering_for_reg(struct intel_gt *gt, i915_reg_t reg, + u8 *sliceid, u8 *subsliceid); + +void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt, + bool dump_table); + +#endif /* __INTEL_GT_MCR__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c index e9c12e0d6f59..1f4e7237a924 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -12,6 +12,7 @@ #include "gem/i915_gem_region.h" #include "gem/i915_gem_ttm.h" #include "gt/intel_gt.h" +#include "gt/intel_gt_mcr.h" #include "gt/intel_gt_regs.h" static int diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 1e982ac931dc..97d7f30b1229 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -9,6 +9,7 @@ #include "intel_engine_regs.h" #include "intel_gpu_commands.h" #include "intel_gt.h" +#include "intel_gt_mcr.h" #include "intel_gt_regs.h" #include "intel_ring.h" #include "intel_workarounds.h" diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index bb197610fd5b..dea138d78111 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -7,6 +7,7 @@ #include "gt/intel_engine_regs.h" #include "gt/intel_gt.h" +#include "gt/intel_gt_mcr.h" #include "gt/intel_gt_regs.h" #include "gt/intel_lrc.h" #include "gt/shmem_utils.h" diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9805c6e6d4da..5cf80fae8baa 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1282,8 +1282,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc) -#define HAS_MSLICE_STEERING(dev_priv) (INTEL_INFO(dev_priv)->has_mslice_steering) - /* * Set this flag, when platform requires 64K GTT page sizes or larger for * device local memory access. diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 33304eb987e4..a852c471d1b3 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -2644,118 +2644,6 @@ intel_uncore_forcewake_for_reg(struct intel_uncore *uncore, return fw_domains; } -/** - * uncore_rw_with_mcr_steering_fw - Access a register after programming - * the MCR selector register. - * @uncore: pointer to struct intel_uncore - * @reg: register being accessed - * @rw_flag: FW_REG_READ for read access or FW_REG_WRITE for write access - * @slice: slice number (ignored for multi-cast write) - * @subslice: sub-slice number (ignored for multi-cast write) - * @value: register value to be written (ignored for read) - * - * Return: 0 for write access. register value for read access. - * - * Caller needs to make sure the relevant forcewake wells are up. - */ -static u32 uncore_rw_with_mcr_steering_fw(struct intel_uncore *uncore, - i915_reg_t reg, u8 rw_flag, - int slice, int subslice, u32 value) -{ - u32 mcr_mask, mcr_ss, mcr, old_mcr, val = 0; - - lockdep_assert_held(&uncore->lock); - - if (GRAPHICS_VER(uncore->i915) >= 11) { - mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; - mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); - - /* - * Wa_22013088509 - * - * The setting of the multicast/unicast bit usually wouldn't - * matter for read operations (which always return the value - * from a single register instance regardless of how that bit - * is set), but some platforms have a workaround requiring us - * to remain in multicast mode for reads. There's no real - * downside to this, so we'll just go ahead and do so on all - * platforms; we'll only clear the multicast bit from the mask - * when exlicitly doing a write operation. - */ - if (rw_flag == FW_REG_WRITE) - mcr_mask |= GEN11_MCR_MULTICAST; - } else { - mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; - mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); - } - - old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR); - - mcr &= ~mcr_mask; - mcr |= mcr_ss; - intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); - - if (rw_flag == FW_REG_READ) - val = intel_uncore_read_fw(uncore, reg); - else - intel_uncore_write_fw(uncore, reg, value); - - mcr &= ~mcr_mask; - mcr |= old_mcr & mcr_mask; - - intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); - - return val; -} - -static u32 uncore_rw_with_mcr_steering(struct intel_uncore *uncore, - i915_reg_t reg, u8 rw_flag, - int slice, int subslice, - u32 value) -{ - enum forcewake_domains fw_domains; - u32 val; - - fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, - rw_flag); - fw_domains |= intel_uncore_forcewake_for_reg(uncore, - GEN8_MCR_SELECTOR, - FW_REG_READ | FW_REG_WRITE); - - spin_lock_irq(&uncore->lock); - intel_uncore_forcewake_get__locked(uncore, fw_domains); - - val = uncore_rw_with_mcr_steering_fw(uncore, reg, rw_flag, - slice, subslice, value); - - intel_uncore_forcewake_put__locked(uncore, fw_domains); - spin_unlock_irq(&uncore->lock); - - return val; -} - -u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore, - i915_reg_t reg, int slice, int subslice) -{ - return uncore_rw_with_mcr_steering_fw(uncore, reg, FW_REG_READ, - slice, subslice, 0); -} - -u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore, - i915_reg_t reg, int slice, int subslice) -{ - return uncore_rw_with_mcr_steering(uncore, reg, FW_REG_READ, - slice, subslice, 0); -} - -void intel_uncore_write_with_mcr_steering(struct intel_uncore *uncore, - i915_reg_t reg, u32 value, - int slice, int subslice) -{ - uncore_rw_with_mcr_steering(uncore, reg, FW_REG_WRITE, - slice, subslice, value); -} - #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) #include "selftests/mock_uncore.c" #include "selftests/intel_uncore.c" diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h index 52fe3d89dd2b..b1fa912a65e7 100644 --- a/drivers/gpu/drm/i915/intel_uncore.h +++ b/drivers/gpu/drm/i915/intel_uncore.h @@ -210,14 +210,6 @@ intel_uncore_has_fifo(const struct intel_uncore *uncore) return uncore->flags & UNCORE_HAS_FIFO; } -u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore, - i915_reg_t reg, - int slice, int subslice); -u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore, - i915_reg_t reg, int slice, int subslice); -void intel_uncore_write_with_mcr_steering(struct intel_uncore *uncore, - i915_reg_t reg, u32 value, - int slice, int subslice); void intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug); void intel_uncore_init_early(struct intel_uncore *uncore, -- 2.35.3 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/gt: Cleanup interface for MCR operations 2022-06-11 0:57 [Intel-gfx] [PATCH 0/2] i915: Extract, polish, and document multicast handling Matt Roper 2022-06-11 0:57 ` [Intel-gfx] [PATCH 1/2] drm/i915/gt: Move multicast register handling to a dedicated file Matt Roper @ 2022-06-11 0:57 ` Matt Roper 2022-06-13 8:13 ` [Intel-gfx] [PATCH 0/2] i915: Extract, polish, and document multicast handling Jani Nikula ` (4 subsequent siblings) 6 siblings, 0 replies; 8+ messages in thread From: Matt Roper @ 2022-06-11 0:57 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel Let's replace the assortment of intel_gt_* and intel_uncore_* functions that operate on MCR registers with a cleaner set of interfaces: * intel_gt_mcr_read -- unicast read from specific instance * intel_gt_mcr_read_any[_fw] -- unicast read from any non-terminated instance * intel_gt_mcr_unicast_write -- unicast write to specific instance * intel_gt_mcr_multicast_write[_fw] -- multicast write to all instances We'll also replace the historic "slice" and "subslice" terminology with "group" and "instance" to match the documentation for more recent platforms; these days MCR steering applies to more types of replication than just slice/subslice. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 2 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 33 ++- drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 225 +++++++++++--------- drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 43 ++-- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 4 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +- 8 files changed, 174 insertions(+), 145 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c index da30503d3ca2..fa54823d1219 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c @@ -835,7 +835,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type, } else { resource_size_t lmem_range; - lmem_range = intel_gt_read_register(&i915->gt0, XEHPSDV_TILE0_ADDR_RANGE) & 0xFFFF; + lmem_range = intel_gt_mcr_read_any(&i915->gt0, XEHPSDV_TILE0_ADDR_RANGE) & 0xFFFF; lmem_size = lmem_range >> XEHPSDV_TILE_LMEM_RANGE_SHIFT; lmem_size *= SZ_1G; } diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 244af1bdb7db..136cc44c3deb 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -1428,14 +1428,6 @@ void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine) ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); } -static u32 -read_subslice_reg(const struct intel_engine_cs *engine, - int slice, int subslice, i915_reg_t reg) -{ - return intel_uncore_read_with_mcr_steering(engine->uncore, reg, - slice, subslice); -} - /* NB: please notice the memset */ void intel_engine_get_instdone(const struct intel_engine_cs *engine, struct intel_instdone *instdone) @@ -1469,28 +1461,33 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine, if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { for_each_instdone_gslice_dss_xehp(i915, sseu, iter, slice, subslice) { instdone->sampler[slice][subslice] = - read_subslice_reg(engine, slice, subslice, - GEN7_SAMPLER_INSTDONE); + intel_gt_mcr_read(engine->gt, + GEN7_SAMPLER_INSTDONE, + slice, subslice); instdone->row[slice][subslice] = - read_subslice_reg(engine, slice, subslice, - GEN7_ROW_INSTDONE); + intel_gt_mcr_read(engine->gt, + GEN7_ROW_INSTDONE, + slice, subslice); } } else { for_each_instdone_slice_subslice(i915, sseu, slice, subslice) { instdone->sampler[slice][subslice] = - read_subslice_reg(engine, slice, subslice, - GEN7_SAMPLER_INSTDONE); + intel_gt_mcr_read(engine->gt, + GEN7_SAMPLER_INSTDONE, + slice, subslice); instdone->row[slice][subslice] = - read_subslice_reg(engine, slice, subslice, - GEN7_ROW_INSTDONE); + intel_gt_mcr_read(engine->gt, + GEN7_ROW_INSTDONE, + slice, subslice); } } if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) { for_each_instdone_gslice_dss_xehp(i915, sseu, iter, slice, subslice) instdone->geom_svg[slice][subslice] = - read_subslice_reg(engine, slice, subslice, - XEHPG_INSTDONE_GEOM_SVG); + intel_gt_mcr_read(engine->gt, + XEHPG_INSTDONE_GEOM_SVG, + slice, subslice); } } else if (GRAPHICS_VER(i915) >= 7) { instdone->instdone = diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c index ea07f2bb846f..dd53641f3637 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c @@ -65,7 +65,7 @@ static int steering_show(struct seq_file *m, void *data) struct drm_printer p = drm_seq_file_printer(m); struct intel_gt *gt = m->private; - intel_gt_report_steering(&p, gt, true); + intel_gt_mcr_report_steering(&p, gt, true); return 0; } diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c index 1279a1fe1001..b6ef51e6cc0b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c @@ -134,23 +134,22 @@ void intel_gt_mcr_init(struct intel_gt *gt) } } -/** - * uncore_rw_with_mcr_steering_fw - Access a register after programming - * the MCR selector register. +/* + * rw_with_mcr_steering_fw - Access a register with specific MCR steering * @uncore: pointer to struct intel_uncore * @reg: register being accessed * @rw_flag: FW_REG_READ for read access or FW_REG_WRITE for write access - * @slice: slice number (ignored for multi-cast write) - * @subslice: sub-slice number (ignored for multi-cast write) + * @group: group number (documented as "sliceid" on older platforms) + * @instance: instance number (documented as "subsliceid" on older platforms) * @value: register value to be written (ignored for read) * * Return: 0 for write access. register value for read access. * * Caller needs to make sure the relevant forcewake wells are up. */ -static u32 uncore_rw_with_mcr_steering_fw(struct intel_uncore *uncore, - i915_reg_t reg, u8 rw_flag, - int slice, int subslice, u32 value) +static u32 rw_with_mcr_steering_fw(struct intel_uncore *uncore, + i915_reg_t reg, u8 rw_flag, + int group, int instance, u32 value) { u32 mcr_mask, mcr_ss, mcr, old_mcr, val = 0; @@ -158,7 +157,7 @@ static u32 uncore_rw_with_mcr_steering_fw(struct intel_uncore *uncore, if (GRAPHICS_VER(uncore->i915) >= 11) { mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; - mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); + mcr_ss = GEN11_MCR_SLICE(group) | GEN11_MCR_SUBSLICE(instance); /* * Wa_22013088509 @@ -176,7 +175,7 @@ static u32 uncore_rw_with_mcr_steering_fw(struct intel_uncore *uncore, mcr_mask |= GEN11_MCR_MULTICAST; } else { mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; - mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); + mcr_ss = GEN8_MCR_SLICE(group) | GEN8_MCR_SUBSLICE(instance); } old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR); @@ -198,10 +197,10 @@ static u32 uncore_rw_with_mcr_steering_fw(struct intel_uncore *uncore, return val; } -static u32 uncore_rw_with_mcr_steering(struct intel_uncore *uncore, - i915_reg_t reg, u8 rw_flag, - int slice, int subslice, - u32 value) +static u32 rw_with_mcr_steering(struct intel_uncore *uncore, + i915_reg_t reg, u8 rw_flag, + int group, int instance, + u32 value) { enum forcewake_domains fw_domains; u32 val; @@ -215,8 +214,7 @@ static u32 uncore_rw_with_mcr_steering(struct intel_uncore *uncore, spin_lock_irq(&uncore->lock); intel_uncore_forcewake_get__locked(uncore, fw_domains); - val = uncore_rw_with_mcr_steering_fw(uncore, reg, rw_flag, - slice, subslice, value); + val = rw_with_mcr_steering_fw(uncore, reg, rw_flag, group, instance, value); intel_uncore_forcewake_put__locked(uncore, fw_domains); spin_unlock_irq(&uncore->lock); @@ -224,31 +222,71 @@ static u32 uncore_rw_with_mcr_steering(struct intel_uncore *uncore, return val; } -u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore, - i915_reg_t reg, int slice, int subslice) +/** + * intel_gt_mcr_read - read a specific instance of an MCR register + * @gt: GT structure + * @reg: the MCR register to read + * @group: the MCR group + * @instance: the MCR instance + * + * Returns the value read from an MCR register after steering toward a specific + * group/instance. + */ +u32 intel_gt_mcr_read(struct intel_gt *gt, + i915_reg_t reg, + int group, int instance) { - return uncore_rw_with_mcr_steering_fw(uncore, reg, FW_REG_READ, - slice, subslice, 0); + return rw_with_mcr_steering(gt->uncore, reg, FW_REG_READ, group, instance, 0); } -u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore, - i915_reg_t reg, int slice, int subslice) +/** + * intel_gt_mcr_unicast_write - write a specific instance of an MCR register + * @gt: GT structure + * @reg: the MCR register to read + * @value: value to write + * @group: the MCR group + * @instance: the MCR instance + * + * Write an MCR register in unicast mode after steering toward a specific + * group/instance. + */ +void intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_reg_t reg, u32 value, + int group, int instance) { - return uncore_rw_with_mcr_steering(uncore, reg, FW_REG_READ, - slice, subslice, 0); + rw_with_mcr_steering(gt->uncore, reg, FW_REG_WRITE, group, instance, value); } -void intel_uncore_write_with_mcr_steering(struct intel_uncore *uncore, - i915_reg_t reg, u32 value, - int slice, int subslice) +/** + * intel_gt_mcr_multicast_write - write a value to all instances of an MCR register + * @gt: GT structure + * @reg: the MCR register to read + * @value: value to write + * + * Write an MCR register in multicast mode to update all instances. + */ +void intel_gt_mcr_multicast_write(struct intel_gt *gt, + i915_reg_t reg, u32 value) { - uncore_rw_with_mcr_steering(uncore, reg, FW_REG_WRITE, - slice, subslice, value); + intel_uncore_write(gt->uncore, reg, value); } /** - * intel_gt_reg_needs_read_steering - determine whether a register read - * requires explicit steering + * intel_gt_mcr_multicast_write_fw - write a value to all instances of an MCR register + * @gt: GT structure + * @reg: the MCR register to read + * @value: value to write + * + * Write an MCR register in multicast mode to update all instances. The caller + * must already be holding any required forcewake. + */ +void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_reg_t reg, u32 value) +{ + intel_uncore_write_fw(gt->uncore, reg, value); +} + +/* + * reg_needs_read_steering - determine whether a register read requires + * explicit steering * @gt: GT structure * @reg: the register to check steering requirements for * @type: type of multicast steering to check @@ -260,14 +298,14 @@ void intel_uncore_write_with_mcr_steering(struct intel_uncore *uncore, * steering type, or if the default (subslice-based) steering IDs are suitable * for @type steering too. */ -static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt, - i915_reg_t reg, - enum intel_steering_type type) +static bool reg_needs_read_steering(struct intel_gt *gt, + i915_reg_t reg, + enum intel_steering_type type) { const u32 offset = i915_mmio_reg_offset(reg); const struct intel_mmio_range *entry; - if (likely(!intel_gt_needs_read_steering(gt, type))) + if (likely(!gt->steering_table[type])) return false; for (entry = gt->steering_table[type]; entry->end; entry++) { @@ -278,29 +316,29 @@ static bool intel_gt_reg_needs_read_steering(struct intel_gt *gt, return false; } -/** - * intel_gt_get_valid_steering - determines valid IDs for a class of MCR steering +/* + * get_nonterminated_steering - determines valid IDs for a class of MCR steering * @gt: GT structure * @type: multicast register type - * @sliceid: Slice ID returned - * @subsliceid: Subslice ID returned + * @group: Group ID returned + * @instance: Instance ID returned * - * Determines sliceid and subsliceid values that will steer reads - * of a specific multicast register class to a valid value. + * Determines group and instance values that will steer reads of the specified + * MCR class to a non-terminated instance. */ -static void intel_gt_get_valid_steering(struct intel_gt *gt, - enum intel_steering_type type, - u8 *sliceid, u8 *subsliceid) +static void get_nonterminated_steering(struct intel_gt *gt, + enum intel_steering_type type, + u8 *group, u8 *instance) { switch (type) { case L3BANK: - *sliceid = 0; /* unused */ - *subsliceid = __ffs(gt->info.l3bank_mask); + *group = 0; /* unused */ + *instance = __ffs(gt->info.l3bank_mask); break; case MSLICE: GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915)); - *sliceid = __ffs(gt->info.mslice_mask); - *subsliceid = 0; /* unused */ + *group = __ffs(gt->info.mslice_mask); + *instance = 0; /* unused */ break; case LNCF: /* @@ -308,96 +346,93 @@ static void intel_gt_get_valid_steering(struct intel_gt *gt, * can safely just steer to LNCF 0 in all cases. */ GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915)); - *sliceid = __ffs(gt->info.mslice_mask) << 1; - *subsliceid = 0; /* unused */ + *group = __ffs(gt->info.mslice_mask) << 1; + *instance = 0; /* unused */ break; case INSTANCE0: /* * There are a lot of MCR types for which instance (0, 0) * will always provide a non-terminated value. */ - *sliceid = 0; - *subsliceid = 0; + *group = 0; + *instance = 0; break; default: MISSING_CASE(type); - *sliceid = 0; - *subsliceid = 0; + *group = 0; + *instance = 0; } } /** - * intel_gt_get_valid_steering_for_reg - get a valid steering for a register + * intel_gt_mcr_get_nonterminated_steering - find group/instance values that + * will steer a register to a non-terminated instance * @gt: GT structure * @reg: register for which the steering is required - * @sliceid: return variable for slice steering - * @subsliceid: return variable for subslice steering + * @group: return variable for group steering + * @instance: return variable for instance steering * - * This function returns a slice/subslice pair that is guaranteed to work for + * This function returns a group/instance pair that is guaranteed to work for * read steering of the given register. Note that a value will be returned even * if the register is not replicated and therefore does not actually require * steering. */ -void intel_gt_get_valid_steering_for_reg(struct intel_gt *gt, i915_reg_t reg, - u8 *sliceid, u8 *subsliceid) +void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt, + i915_reg_t reg, + u8 *group, u8 *instance) { int type; for (type = 0; type < NUM_STEERING_TYPES; type++) { - if (intel_gt_reg_needs_read_steering(gt, reg, type)) { - intel_gt_get_valid_steering(gt, type, sliceid, - subsliceid); + if (reg_needs_read_steering(gt, reg, type)) { + get_nonterminated_steering(gt, type, group, instance); return; } } - *sliceid = gt->default_steering.groupid; - *subsliceid = gt->default_steering.instanceid; + *group = gt->default_steering.groupid; + *instance = gt->default_steering.instanceid; } /** - * intel_gt_read_register_fw - reads a GT register with support for multicast + * intel_gt_mcr_read_any_fw - reads one instance of an MCR register * @gt: GT structure * @reg: register to read * - * This function will read a GT register. If the register is a multicast - * register, the read will be steered to a valid instance (i.e., one that - * isn't fused off or powered down by power gating). + * Reads a GT MCR register. The read will be steered to a non-terminated + * instance (i.e., one that isn't fused off or powered down by power gating). + * The caller should ensure any necessary forcewake is held. * - * Returns the value from a valid instance of @reg. + * Returns the value from a non-terminated instance of @reg. */ -u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg) +u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_reg_t reg) { int type; - u8 sliceid, subsliceid; + u8 group, instance; for (type = 0; type < NUM_STEERING_TYPES; type++) { - if (intel_gt_reg_needs_read_steering(gt, reg, type)) { - intel_gt_get_valid_steering(gt, type, &sliceid, - &subsliceid); - return intel_uncore_read_with_mcr_steering_fw(gt->uncore, - reg, - sliceid, - subsliceid); + if (reg_needs_read_steering(gt, reg, type)) { + get_nonterminated_steering(gt, type, &group, &instance); + return rw_with_mcr_steering_fw(gt->uncore, reg, + FW_REG_READ, + group, instance, 0); } } return intel_uncore_read_fw(gt->uncore, reg); } -u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg) +u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_reg_t reg) { int type; - u8 sliceid, subsliceid; + u8 group, instance; for (type = 0; type < NUM_STEERING_TYPES; type++) { - if (intel_gt_reg_needs_read_steering(gt, reg, type)) { - intel_gt_get_valid_steering(gt, type, &sliceid, - &subsliceid); - return intel_uncore_read_with_mcr_steering(gt->uncore, - reg, - sliceid, - subsliceid); + if (reg_needs_read_steering(gt, reg, type)) { + get_nonterminated_steering(gt, type, &group, &instance); + return rw_with_mcr_steering(gt->uncore, reg, + FW_REG_READ, + group, instance, 0); } } @@ -410,7 +445,7 @@ static void report_steering_type(struct drm_printer *p, bool dump_table) { const struct intel_mmio_range *entry; - u8 slice, subslice; + u8 group, instance; BUILD_BUG_ON(ARRAY_SIZE(intel_steering_types) != NUM_STEERING_TYPES); @@ -420,9 +455,9 @@ static void report_steering_type(struct drm_printer *p, return; } - intel_gt_get_valid_steering(gt, type, &slice, &subslice); - drm_printf(p, "%s steering: sliceid=0x%x, subsliceid=0x%x\n", - intel_steering_types[type], slice, subslice); + get_nonterminated_steering(gt, type, &group, &instance); + drm_printf(p, "%s steering: group=0x%x, instance=0x%x\n", + intel_steering_types[type], group, instance); if (!dump_table) return; @@ -431,10 +466,10 @@ static void report_steering_type(struct drm_printer *p, drm_printf(p, "\t0x%06x - 0x%06x\n", entry->start, entry->end); } -void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt, - bool dump_table) +void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt, + bool dump_table) { - drm_printf(p, "Default steering: sliceid=0x%x, subsliceid=0x%x\n", + drm_printf(p, "Default steering: group=0x%x, instance=0x%x\n", gt->default_steering.groupid, gt->default_steering.instanceid); diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h index b570c1571243..506b0cbc8db3 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h @@ -10,28 +10,25 @@ void intel_gt_mcr_init(struct intel_gt *gt); -u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore, - i915_reg_t reg, - int slice, int subslice); -u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore, - i915_reg_t reg, int slice, int subslice); -void intel_uncore_write_with_mcr_steering(struct intel_uncore *uncore, - i915_reg_t reg, u32 value, - int slice, int subslice); - -u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg); -u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg); - -static inline bool intel_gt_needs_read_steering(struct intel_gt *gt, - enum intel_steering_type type) -{ - return gt->steering_table[type]; -} - -void intel_gt_get_valid_steering_for_reg(struct intel_gt *gt, i915_reg_t reg, - u8 *sliceid, u8 *subsliceid); - -void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt, - bool dump_table); +u32 intel_gt_mcr_read(struct intel_gt *gt, + i915_reg_t reg, + int group, int instance); +u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_reg_t reg); +u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_reg_t reg); + +void intel_gt_mcr_unicast_write(struct intel_gt *gt, + i915_reg_t reg, u32 value, + int group, int instance); +void intel_gt_mcr_multicast_write(struct intel_gt *gt, + i915_reg_t reg, u32 value); +void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, + i915_reg_t reg, u32 value); + +void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt, + i915_reg_t reg, + u8 *group, u8 *instance); + +void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt, + bool dump_table); #endif /* __INTEL_GT_MCR__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c index 1f4e7237a924..2ff448047020 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -105,11 +105,11 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) resource_size_t lmem_range; u64 tile_stolen, flat_ccs_base; - lmem_range = intel_gt_read_register(&i915->gt0, XEHPSDV_TILE0_ADDR_RANGE) & 0xFFFF; + lmem_range = intel_gt_mcr_read_any(&i915->gt0, XEHPSDV_TILE0_ADDR_RANGE) & 0xFFFF; lmem_size = lmem_range >> XEHPSDV_TILE_LMEM_RANGE_SHIFT; lmem_size *= SZ_1G; - flat_ccs_base = intel_gt_read_register(gt, XEHPSDV_FLAT_CCS_BASE_ADDR); + flat_ccs_base = intel_gt_mcr_read_any(gt, XEHPSDV_FLAT_CCS_BASE_ADDR); flat_ccs_base = (flat_ccs_base >> XEHPSDV_CCS_BASE_SHIFT) * SZ_64K; /* FIXME: Remove this when we have small-bar enabled */ diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 97d7f30b1229..e42fbb982bb3 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1083,7 +1083,7 @@ static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal, gt->default_steering.instanceid = subslice; if (drm_debug_enabled(DRM_UT_DRIVER)) - intel_gt_report_steering(&p, gt, false); + intel_gt_mcr_report_steering(&p, gt, false); } static void @@ -1624,13 +1624,13 @@ wa_list_apply(struct intel_gt *gt, const struct i915_wa_list *wal) u32 val, old = 0; /* open-coded rmw due to steering */ - old = wa->clr ? intel_gt_read_register_fw(gt, wa->reg) : 0; + old = wa->clr ? intel_gt_mcr_read_any_fw(gt, wa->reg) : 0; val = (old & ~wa->clr) | wa->set; if (val != old || !wa->clr) intel_uncore_write_fw(uncore, wa->reg, val); if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) - wa_verify(wa, intel_gt_read_register_fw(gt, wa->reg), + wa_verify(wa, intel_gt_mcr_read_any_fw(gt, wa->reg), wal->name, "application"); } @@ -1661,7 +1661,7 @@ static bool wa_list_verify(struct intel_gt *gt, for (i = 0, wa = wal->list; i < wal->count; i++, wa++) ok &= wa_verify(wa, - intel_gt_read_register_fw(gt, wa->reg), + intel_gt_mcr_read_any_fw(gt, wa->reg), wal->name, from); intel_uncore_forcewake_put__locked(uncore, fw); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index dea138d78111..ba7541f3ca61 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -314,7 +314,7 @@ static long __must_check guc_mmio_reg_add(struct intel_gt *gt, * tracking, it is easier to just program the default steering for all * regs that don't need a non-default one. */ - intel_gt_get_valid_steering_for_reg(gt, reg, &group, &inst); + intel_gt_mcr_get_nonterminated_steering(gt, reg, &group, &inst); entry.flags |= GUC_REGSET_STEERING(group, inst); slot = __mmio_reg_add(regset, &entry); -- 2.35.3 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [Intel-gfx] [PATCH 0/2] i915: Extract, polish, and document multicast handling 2022-06-11 0:57 [Intel-gfx] [PATCH 0/2] i915: Extract, polish, and document multicast handling Matt Roper 2022-06-11 0:57 ` [Intel-gfx] [PATCH 1/2] drm/i915/gt: Move multicast register handling to a dedicated file Matt Roper 2022-06-11 0:57 ` [Intel-gfx] [PATCH 2/2] drm/i915/gt: Cleanup interface for MCR operations Matt Roper @ 2022-06-13 8:13 ` Jani Nikula 2022-06-13 22:11 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork ` (3 subsequent siblings) 6 siblings, 0 replies; 8+ messages in thread From: Jani Nikula @ 2022-06-13 8:13 UTC (permalink / raw) To: Matt Roper, intel-gfx; +Cc: dri-devel On Fri, 10 Jun 2022, Matt Roper <matthew.d.roper@intel.com> wrote: > Multicast/replicated (MCR) registers on Intel hardware are a purely > GT-specific concept. Rather than leaving MCR register handling spread > across several places throughout the driver (intel_uncore.c, intel_gt.c, > etc.) with confusing combinations of handler functions living in > different namespaces, let's consolidate it all into a single place > (intel_gt_mcr.c) and provide a more consistent and clearly-documented > interface for the rest of the driver to access such registers: I don't have the time for review, but overall this seems like a nice cleanup. Ack. As to documentation, I think usually documenting static functions using kernel-doc is excessive, and a short regular comment might suffice. On the other hand, the nice documentation doesn't show up anywhere, because you also need to bolt it to some .rst! BR, Jani. > > * intel_gt_mcr_read -- unicast read from specific instance > * intel_gt_mcr_read_any[_fw] -- unicast read from any non-terminated > instance > * intel_gt_mcr_unicast_write -- unicast write to specific instance > * intel_gt_mcr_multicast_write[_fw] -- multicast write to all instances > > Matt Roper (2): > drm/i915/gt: Move multicast register handling to a dedicated file > drm/i915/gt: Cleanup interface for MCR operations > > drivers/gpu/drm/i915/Makefile | 1 + > drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 3 +- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 36 +- > drivers/gpu/drm/i915/gt/intel_gt.c | 297 +----------- > drivers/gpu/drm/i915/gt/intel_gt.h | 15 - > drivers/gpu/drm/i915/gt/intel_gt_debugfs.c | 3 +- > drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 483 ++++++++++++++++++++ > drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 34 ++ > drivers/gpu/drm/i915/gt/intel_region_lmem.c | 5 +- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +- > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 +- > drivers/gpu/drm/i915/i915_drv.h | 2 - > drivers/gpu/drm/i915/intel_uncore.c | 112 ----- > drivers/gpu/drm/i915/intel_uncore.h | 8 - > 14 files changed, 551 insertions(+), 460 deletions(-) > create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_mcr.c > create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_mcr.h -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Extract, polish, and document multicast handling 2022-06-11 0:57 [Intel-gfx] [PATCH 0/2] i915: Extract, polish, and document multicast handling Matt Roper ` (2 preceding siblings ...) 2022-06-13 8:13 ` [Intel-gfx] [PATCH 0/2] i915: Extract, polish, and document multicast handling Jani Nikula @ 2022-06-13 22:11 ` Patchwork 2022-06-13 22:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork ` (2 subsequent siblings) 6 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2022-06-13 22:11 UTC (permalink / raw) To: Matt Roper; +Cc: intel-gfx == Series Details == Series: i915: Extract, polish, and document multicast handling URL : https://patchwork.freedesktop.org/series/105015/ State : warning == Summary == Error: dim checkpatch failed 765b6cf9cb6f drm/i915/gt: Move multicast register handling to a dedicated file Traceback (most recent call last): File "scripts/spdxcheck.py", line 11, in <module> import git ModuleNotFoundError: No module named 'git' Traceback (most recent call last): File "scripts/spdxcheck.py", line 11, in <module> import git ModuleNotFoundError: No module named 'git' -:424: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #424: new file mode 100644 -:610: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #610: FILE: drivers/gpu/drm/i915/gt/intel_gt_mcr.c:182: + old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR); total: 0 errors, 1 warnings, 1 checks, 1019 lines checked 023c00125617 drm/i915/gt: Cleanup interface for MCR operations -:247: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #247: FILE: drivers/gpu/drm/i915/gt/intel_gt_mcr.c:268: +void intel_gt_mcr_multicast_write(struct intel_gt *gt, + i915_reg_t reg, u32 value) total: 0 errors, 0 warnings, 1 checks, 554 lines checked ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: Extract, polish, and document multicast handling 2022-06-11 0:57 [Intel-gfx] [PATCH 0/2] i915: Extract, polish, and document multicast handling Matt Roper ` (3 preceding siblings ...) 2022-06-13 22:11 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork @ 2022-06-13 22:11 ` Patchwork 2022-06-13 22:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-06-14 23:17 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 6 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2022-06-13 22:11 UTC (permalink / raw) To: Matt Roper; +Cc: intel-gfx == Series Details == Series: i915: Extract, polish, and document multicast handling URL : https://patchwork.freedesktop.org/series/105015/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for i915: Extract, polish, and document multicast handling 2022-06-11 0:57 [Intel-gfx] [PATCH 0/2] i915: Extract, polish, and document multicast handling Matt Roper ` (4 preceding siblings ...) 2022-06-13 22:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork @ 2022-06-13 22:35 ` Patchwork 2022-06-14 23:17 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 6 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2022-06-13 22:35 UTC (permalink / raw) To: Matt Roper; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 10861 bytes --] == Series Details == Series: i915: Extract, polish, and document multicast handling URL : https://patchwork.freedesktop.org/series/105015/ State : success == Summary == CI Bug Log - changes from CI_DRM_11755 -> Patchwork_105015v1 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/index.html Participating hosts (44 -> 43) ------------------------------ Additional (1): fi-icl-u2 Missing (2): fi-cml-u2 bat-adlm-1 Known issues ------------ Here are the changes found in Patchwork_105015v1 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_huc_copy@huc-copy: - fi-icl-u2: NOTRUN -> [SKIP][1] ([i915#2190]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-icl-u2/igt@gem_huc_copy@huc-copy.html * igt@gem_lmem_swapping@random-engines: - fi-icl-u2: NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-icl-u2/igt@gem_lmem_swapping@random-engines.html * igt@i915_selftest@live@gt_mocs: - fi-rkl-guc: [PASS][3] -> [DMESG-WARN][4] ([i915#5790]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/fi-rkl-guc/igt@i915_selftest@live@gt_mocs.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-rkl-guc/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770: [PASS][5] -> [INCOMPLETE][6] ([i915#3303] / [i915#4785]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html - fi-bdw-5557u: NOTRUN -> [INCOMPLETE][7] ([i915#3921]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-bdw-5557u/igt@i915_selftest@live@hangcheck.html * igt@i915_selftest@live@requests: - fi-blb-e6850: [PASS][8] -> [DMESG-FAIL][9] ([i915#4528]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/fi-blb-e6850/igt@i915_selftest@live@requests.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-blb-e6850/igt@i915_selftest@live@requests.html * igt@i915_suspend@basic-s3-without-i915: - fi-icl-u2: NOTRUN -> [SKIP][10] ([i915#5903]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-icl-u2/igt@i915_suspend@basic-s3-without-i915.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-pnv-d510: NOTRUN -> [SKIP][11] ([fdo#109271]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-pnv-d510/igt@kms_chamelium@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: NOTRUN -> [SKIP][12] ([fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html * igt@kms_flip@basic-flip-vs-dpms@a-edp1: - fi-tgl-u2: [PASS][13] -> [DMESG-WARN][14] ([i915#402]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/fi-tgl-u2/igt@kms_flip@basic-flip-vs-dpms@a-edp1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-tgl-u2/igt@kms_flip@basic-flip-vs-dpms@a-edp1.html * igt@kms_force_connector_basic@force-connector-state: - fi-icl-u2: NOTRUN -> [WARN][15] ([i915#6008]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-icl-u2/igt@kms_force_connector_basic@force-connector-state.html * igt@kms_force_connector_basic@force-load-detect: - fi-kbl-guc: NOTRUN -> [SKIP][16] ([fdo#109271]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-kbl-guc/igt@kms_force_connector_basic@force-load-detect.html - fi-icl-u2: NOTRUN -> [SKIP][17] ([fdo#109285]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-icl-u2: NOTRUN -> [SKIP][18] ([fdo#109278]) +2 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-icl-u2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html * igt@kms_setmode@basic-clone-single-crtc: - fi-icl-u2: NOTRUN -> [SKIP][19] ([i915#3555]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-icl-u2/igt@kms_setmode@basic-clone-single-crtc.html * igt@prime_vgem@basic-userptr: - fi-icl-u2: NOTRUN -> [SKIP][20] ([fdo#109295] / [i915#3301]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-icl-u2/igt@prime_vgem@basic-userptr.html * igt@runner@aborted: - fi-hsw-4770: NOTRUN -> [FAIL][21] ([fdo#109271] / [i915#4312] / [i915#5594]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-hsw-4770/igt@runner@aborted.html #### Possible fixes #### * igt@i915_pm_rpm@module-reload: - fi-cfl-8109u: [DMESG-FAIL][22] ([i915#62]) -> [PASS][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html * igt@i915_selftest@live@gem_contexts: - fi-bdw-5557u: [INCOMPLETE][24] ([i915#5502]) -> [PASS][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html * igt@i915_selftest@live@gt_heartbeat: - {fi-jsl-1}: [DMESG-FAIL][26] ([i915#5334]) -> [PASS][27] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/fi-jsl-1/igt@i915_selftest@live@gt_heartbeat.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-jsl-1/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_timelines: - {bat-dg2-9}: [DMESG-WARN][28] ([i915#5763]) -> [PASS][29] +3 similar issues [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/bat-dg2-9/igt@i915_selftest@live@gt_timelines.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/bat-dg2-9/igt@i915_selftest@live@gt_timelines.html * igt@i915_selftest@live@late_gt_pm: - fi-cfl-8109u: [DMESG-WARN][30] ([i915#5904]) -> [PASS][31] +29 similar issues [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html * igt@i915_selftest@live@requests: - fi-pnv-d510: [DMESG-FAIL][32] ([i915#4528]) -> [PASS][33] [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/fi-pnv-d510/igt@i915_selftest@live@requests.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-pnv-d510/igt@i915_selftest@live@requests.html * igt@i915_suspend@basic-s2idle-without-i915: - fi-cfl-8109u: [DMESG-WARN][34] ([i915#5904] / [i915#62]) -> [PASS][35] [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/fi-cfl-8109u/igt@i915_suspend@basic-s2idle-without-i915.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-cfl-8109u/igt@i915_suspend@basic-s2idle-without-i915.html * igt@kms_flip@basic-plain-flip@a-edp1: - {bat-adlp-6}: [DMESG-WARN][36] ([i915#3576]) -> [PASS][37] +1 similar issue [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/bat-adlp-6/igt@kms_flip@basic-plain-flip@a-edp1.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/bat-adlp-6/igt@kms_flip@basic-plain-flip@a-edp1.html * igt@kms_frontbuffer_tracking@basic: - fi-cfl-8109u: [DMESG-WARN][38] ([i915#62]) -> [PASS][39] +15 similar issues [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576 [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#5502]: https://gitlab.freedesktop.org/drm/intel/issues/5502 [i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594 [i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763 [i915#5790]: https://gitlab.freedesktop.org/drm/intel/issues/5790 [i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903 [i915#5904]: https://gitlab.freedesktop.org/drm/intel/issues/5904 [i915#6008]: https://gitlab.freedesktop.org/drm/intel/issues/6008 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 Build changes ------------- * Linux: CI_DRM_11755 -> Patchwork_105015v1 CI-20190529: 20190529 CI_DRM_11755: 65b93b94d6bc932ed60bb3fd9d68242db25b1f3b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6522: 5be5a1a1f168a59614101b77385f05f12ec7d30a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_105015v1: 65b93b94d6bc932ed60bb3fd9d68242db25b1f3b @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits d9a93972e971 drm/i915/gt: Cleanup interface for MCR operations 133e78d2d096 drm/i915/gt: Move multicast register handling to a dedicated file == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/index.html [-- Attachment #2: Type: text/html, Size: 12518 bytes --] ^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for i915: Extract, polish, and document multicast handling 2022-06-11 0:57 [Intel-gfx] [PATCH 0/2] i915: Extract, polish, and document multicast handling Matt Roper ` (5 preceding siblings ...) 2022-06-13 22:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2022-06-14 23:17 ` Patchwork 6 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2022-06-14 23:17 UTC (permalink / raw) To: Matt Roper; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 41631 bytes --] == Series Details == Series: i915: Extract, polish, and document multicast handling URL : https://patchwork.freedesktop.org/series/105015/ State : success == Summary == CI Bug Log - changes from CI_DRM_11755_full -> Patchwork_105015v1_full ==================================================== Summary ------- **SUCCESS** No regressions found. Participating hosts (12 -> 11) ------------------------------ Missing (1): shard-dg1 Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_105015v1_full: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * {igt@kms_cdclk@mode-transition-all-outputs}: - shard-iclb: NOTRUN -> [SKIP][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb2/igt@kms_cdclk@mode-transition-all-outputs.html Known issues ------------ Here are the changes found in Patchwork_105015v1_full that come from known issues: ### CI changes ### #### Possible fixes #### * boot: - shard-skl: ([PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [FAIL][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20]) ([i915#5032]) -> ([PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl10/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl9/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl9/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl9/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl7/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl7/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl6/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl6/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl5/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl4/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl4/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl4/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl3/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl3/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl2/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl1/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl1/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl1/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl10/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl9/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl9/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl9/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl7/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl7/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl7/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl7/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl6/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl6/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl5/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl5/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl4/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl4/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl4/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl3/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl2/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl2/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl1/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl1/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl1/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl10/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl10/boot.html ### IGT changes ### #### Issues hit #### * igt@drm_buddy@all@buddy_alloc_smoke: - shard-skl: [PASS][43] -> [INCOMPLETE][44] ([i915#5800]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl9/igt@drm_buddy@all@buddy_alloc_smoke.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl7/igt@drm_buddy@all@buddy_alloc_smoke.html * igt@gem_ccs@block-copy-compressed: - shard-iclb: NOTRUN -> [SKIP][45] ([i915#5327]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb5/igt@gem_ccs@block-copy-compressed.html * igt@gem_ctx_persistence@smoketest: - shard-snb: NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#1099]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-snb6/igt@gem_ctx_persistence@smoketest.html * igt@gem_exec_balancer@parallel-out-fence: - shard-iclb: [PASS][47] -> [SKIP][48] ([i915#4525]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb2/igt@gem_exec_balancer@parallel-out-fence.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb3/igt@gem_exec_balancer@parallel-out-fence.html * igt@gem_exec_endless@dispatch@vecs0: - shard-tglb: [PASS][49] -> [INCOMPLETE][50] ([i915#3778]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-tglb8/igt@gem_exec_endless@dispatch@vecs0.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-tglb8/igt@gem_exec_endless@dispatch@vecs0.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][51] -> [FAIL][52] ([i915#2842]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][53] ([i915#2842]) +1 similar issue [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb1/igt@gem_exec_fair@basic-none@vcs1.html - shard-kbl: [PASS][54] -> [FAIL][55] ([i915#2842]) +3 similar issues [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-kbl7/igt@gem_exec_fair@basic-none@vcs1.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-kbl4/igt@gem_exec_fair@basic-none@vcs1.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-iclb: [PASS][56] -> [FAIL][57] ([i915#2842]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb7/igt@gem_exec_fair@basic-pace@rcs0.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb2/igt@gem_exec_fair@basic-pace@rcs0.html * igt@gem_exec_params@no-vebox: - shard-iclb: NOTRUN -> [SKIP][58] ([fdo#109283]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb2/igt@gem_exec_params@no-vebox.html * igt@gem_lmem_swapping@basic: - shard-skl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#4613]) +5 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl10/igt@gem_lmem_swapping@basic.html * igt@gem_lmem_swapping@heavy-verify-random-ccs: - shard-apl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#4613]) [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-apl1/igt@gem_lmem_swapping@heavy-verify-random-ccs.html * igt@gem_lmem_swapping@verify-random: - shard-iclb: NOTRUN -> [SKIP][61] ([i915#4613]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb5/igt@gem_lmem_swapping@verify-random.html * igt@gem_userptr_blits@invalid-mmap-offset-unsync: - shard-iclb: NOTRUN -> [SKIP][62] ([i915#3297]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb5/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html * igt@gen9_exec_parse@allowed-all: - shard-skl: [PASS][63] -> [DMESG-WARN][64] ([i915#5566] / [i915#716]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl5/igt@gen9_exec_parse@allowed-all.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl7/igt@gen9_exec_parse@allowed-all.html * igt@i915_module_load@load: - shard-skl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#6227]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl9/igt@i915_module_load@load.html * igt@i915_pm_dc@dc6-psr: - shard-skl: NOTRUN -> [FAIL][66] ([i915#454]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl9/igt@i915_pm_dc@dc6-psr.html * igt@i915_pm_rc6_residency@rc6-idle: - shard-iclb: NOTRUN -> [WARN][67] ([i915#2684]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html * igt@i915_selftest@live@hangcheck: - shard-tglb: [PASS][68] -> [DMESG-WARN][69] ([i915#5591]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-tglb6/igt@i915_selftest@live@hangcheck.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-tglb5/igt@i915_selftest@live@hangcheck.html * igt@kms_big_fb@4-tiled-32bpp-rotate-90: - shard-iclb: NOTRUN -> [SKIP][70] ([i915#5286]) +2 similar issues [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb5/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html * igt@kms_big_fb@x-tiled-64bpp-rotate-270: - shard-iclb: NOTRUN -> [SKIP][71] ([fdo#110725] / [fdo#111614]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb2/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip: - shard-tglb: [PASS][72] -> [FAIL][73] ([i915#3743]) +1 similar issue [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-tglb1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-tglb2/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip: - shard-apl: NOTRUN -> [SKIP][74] ([fdo#109271]) +72 similar issues [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-apl6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip: - shard-skl: NOTRUN -> [FAIL][75] ([i915#3763]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip: - shard-skl: NOTRUN -> [FAIL][76] ([i915#3743]) +1 similar issue [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl9/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html * igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs_cc: - shard-iclb: NOTRUN -> [SKIP][77] ([fdo#109278] / [i915#3886]) +2 similar issues [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb5/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs: - shard-glk: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#3886]) +1 similar issue [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-glk3/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs: - shard-skl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#3886]) +12 similar issues [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl2/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc: - shard-apl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#3886]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-apl6/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_dg2_rc_ccs: - shard-iclb: NOTRUN -> [SKIP][81] ([fdo#109278]) +13 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb2/igt@kms_ccs@pipe-d-crc-primary-rotation-180-4_tiled_dg2_rc_ccs.html * igt@kms_chamelium@dp-edid-change-during-suspend: - shard-glk: NOTRUN -> [SKIP][82] ([fdo#109271] / [fdo#111827]) +2 similar issues [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-glk3/igt@kms_chamelium@dp-edid-change-during-suspend.html * igt@kms_chamelium@hdmi-edid-read: - shard-snb: NOTRUN -> [SKIP][83] ([fdo#109271] / [fdo#111827]) +4 similar issues [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-snb6/igt@kms_chamelium@hdmi-edid-read.html * igt@kms_chamelium@hdmi-hpd: - shard-iclb: NOTRUN -> [SKIP][84] ([fdo#109284] / [fdo#111827]) +5 similar issues [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb2/igt@kms_chamelium@hdmi-hpd.html * igt@kms_chamelium@hdmi-hpd-storm-disable: - shard-apl: NOTRUN -> [SKIP][85] ([fdo#109271] / [fdo#111827]) +2 similar issues [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-apl6/igt@kms_chamelium@hdmi-hpd-storm-disable.html * igt@kms_color_chamelium@pipe-a-ctm-0-5: - shard-skl: NOTRUN -> [SKIP][86] ([fdo#109271] / [fdo#111827]) +22 similar issues [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl9/igt@kms_color_chamelium@pipe-a-ctm-0-5.html * igt@kms_color_chamelium@pipe-d-ctm-negative: - shard-iclb: NOTRUN -> [SKIP][87] ([fdo#109278] / [fdo#109284] / [fdo#111827]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb2/igt@kms_color_chamelium@pipe-d-ctm-negative.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-apl: NOTRUN -> [DMESG-WARN][88] ([i915#180]) [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-apl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html * igt@kms_cursor_crc@pipe-c-cursor-512x170-random: - shard-iclb: NOTRUN -> [SKIP][89] ([fdo#109278] / [fdo#109279]) +1 similar issue [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb2/igt@kms_cursor_crc@pipe-c-cursor-512x170-random.html * igt@kms_cursor_crc@pipe-d-cursor-128x128-onscreen: - shard-skl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#1888]) [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl10/igt@kms_cursor_crc@pipe-d-cursor-128x128-onscreen.html * igt@kms_cursor_crc@pipe-d-cursor-64x21-rapid-movement: - shard-glk: NOTRUN -> [SKIP][91] ([fdo#109271]) +28 similar issues [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-glk3/igt@kms_cursor_crc@pipe-d-cursor-64x21-rapid-movement.html * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions: - shard-skl: NOTRUN -> [SKIP][92] ([fdo#109271]) +372 similar issues [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl10/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-skl: NOTRUN -> [FAIL][93] ([i915#2346] / [i915#533]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_draw_crc@draw-method-rgb565-render-4tiled: - shard-iclb: NOTRUN -> [SKIP][94] ([i915#5287]) [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb5/igt@kms_draw_crc@draw-method-rgb565-render-4tiled.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-apl: [PASS][95] -> [FAIL][96] ([i915#4767]) [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: - shard-iclb: NOTRUN -> [SKIP][97] ([fdo#109274]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb2/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1: - shard-skl: [PASS][98] -> [FAIL][99] ([i915#79]) +2 similar issues [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html * igt@kms_flip@flip-vs-suspend@c-dp1: - shard-apl: [PASS][100] -> [DMESG-WARN][101] ([i915#180]) +3 similar issues [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-apl1/igt@kms_flip@flip-vs-suspend@c-dp1.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-apl1/igt@kms_flip@flip-vs-suspend@c-dp1.html * igt@kms_flip@wf_vblank-ts-check@a-edp1: - shard-skl: [PASS][102] -> [FAIL][103] ([i915#2122]) [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl6/igt@kms_flip@wf_vblank-ts-check@a-edp1.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl2/igt@kms_flip@wf_vblank-ts-check@a-edp1.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling: - shard-skl: NOTRUN -> [SKIP][104] ([fdo#109271] / [i915#3701]) +2 similar issues [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling: - shard-iclb: [PASS][105] -> [SKIP][106] ([i915#3701]) [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-onoff: - shard-iclb: NOTRUN -> [SKIP][107] ([fdo#109280]) +12 similar issues [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-onoff.html * igt@kms_hdr@bpc-switch-dpms: - shard-iclb: NOTRUN -> [SKIP][108] ([i915#3555]) [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb2/igt@kms_hdr@bpc-switch-dpms.html * igt@kms_pipe_crc_basic@hang-read-crc-pipe-d: - shard-skl: NOTRUN -> [SKIP][109] ([fdo#109271] / [i915#533]) +3 similar issues [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl10/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: - shard-apl: NOTRUN -> [FAIL][110] ([fdo#108145] / [i915#265]) [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-apl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html * igt@kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-skl: NOTRUN -> [FAIL][111] ([fdo#108145] / [i915#265]) [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html * igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-b-edp-1: - shard-iclb: NOTRUN -> [SKIP][112] ([i915#5176]) +2 similar issues [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb5/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-b-edp-1.html * igt@kms_prime@basic-crc@first-to-second: - shard-iclb: NOTRUN -> [SKIP][113] ([i915#1836]) [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb5/igt@kms_prime@basic-crc@first-to-second.html * igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf: - shard-tglb: NOTRUN -> [SKIP][114] ([i915#2920]) [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-tglb3/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html * igt@kms_psr2_su@page_flip-nv12: - shard-apl: NOTRUN -> [SKIP][115] ([fdo#109271] / [i915#658]) [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-apl1/igt@kms_psr2_su@page_flip-nv12.html * igt@kms_psr2_su@page_flip-xrgb8888: - shard-skl: NOTRUN -> [SKIP][116] ([fdo#109271] / [i915#658]) +1 similar issue [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl4/igt@kms_psr2_su@page_flip-xrgb8888.html * igt@kms_psr@psr2_dpms: - shard-iclb: [PASS][117] -> [SKIP][118] ([fdo#109441]) [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb2/igt@kms_psr@psr2_dpms.html [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb3/igt@kms_psr@psr2_dpms.html * igt@kms_psr@psr2_sprite_plane_onoff: - shard-snb: NOTRUN -> [SKIP][119] ([fdo#109271]) +78 similar issues [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-snb6/igt@kms_psr@psr2_sprite_plane_onoff.html * igt@kms_psr_stress_test@flip-primary-invalidate-overlay: - shard-iclb: [PASS][120] -> [SKIP][121] ([i915#5519]) [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb4/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html * igt@kms_writeback@writeback-invalid-parameters: - shard-iclb: NOTRUN -> [SKIP][122] ([i915#2437]) [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb5/igt@kms_writeback@writeback-invalid-parameters.html * igt@kms_writeback@writeback-pixel-formats: - shard-skl: NOTRUN -> [SKIP][123] ([fdo#109271] / [i915#2437]) +1 similar issue [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl4/igt@kms_writeback@writeback-pixel-formats.html * igt@nouveau_crc@pipe-c-source-outp-complete: - shard-iclb: NOTRUN -> [SKIP][124] ([i915#2530]) [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb2/igt@nouveau_crc@pipe-c-source-outp-complete.html * igt@nouveau_crc@pipe-d-source-outp-inactive: - shard-iclb: NOTRUN -> [SKIP][125] ([fdo#109278] / [i915#2530]) [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb2/igt@nouveau_crc@pipe-d-source-outp-inactive.html * igt@prime_nv_test@nv_write_i915_gtt_mmap_read: - shard-iclb: NOTRUN -> [SKIP][126] ([fdo#109291]) +1 similar issue [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb5/igt@prime_nv_test@nv_write_i915_gtt_mmap_read.html * igt@sw_sync@sync_merge: - shard-skl: NOTRUN -> [FAIL][127] ([i915#6140]) [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl10/igt@sw_sync@sync_merge.html * igt@sysfs_clients@create: - shard-iclb: NOTRUN -> [SKIP][128] ([i915#2994]) [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb5/igt@sysfs_clients@create.html * igt@sysfs_clients@split-25: - shard-skl: NOTRUN -> [SKIP][129] ([fdo#109271] / [i915#2994]) +1 similar issue [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl2/igt@sysfs_clients@split-25.html * igt@sysfs_clients@split-50: - shard-glk: NOTRUN -> [SKIP][130] ([fdo#109271] / [i915#2994]) [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-glk3/igt@sysfs_clients@split-50.html #### Possible fixes #### * igt@core_setmaster@master-drop-set-user: - shard-iclb: [INCOMPLETE][131] -> [PASS][132] +1 similar issue [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb4/igt@core_setmaster@master-drop-set-user.html [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb5/igt@core_setmaster@master-drop-set-user.html * igt@feature_discovery@psr2: - shard-iclb: [SKIP][133] ([i915#658]) -> [PASS][134] [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb7/igt@feature_discovery@psr2.html [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb2/igt@feature_discovery@psr2.html * igt@gem_exec_balancer@parallel-keep-in-fence: - shard-iclb: [SKIP][135] ([i915#4525]) -> [PASS][136] +1 similar issue [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb8/igt@gem_exec_balancer@parallel-keep-in-fence.html [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb1/igt@gem_exec_balancer@parallel-keep-in-fence.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-tglb: [FAIL][137] ([i915#2842]) -> [PASS][138] +1 similar issue [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-tglb7/igt@gem_exec_fair@basic-none-share@rcs0.html [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-tglb8/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-apl: [FAIL][139] ([i915#2842]) -> [PASS][140] [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-apl1/igt@gem_exec_fair@basic-none@vecs0.html [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-apl2/igt@gem_exec_fair@basic-none@vecs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-kbl: [FAIL][141] ([i915#2842]) -> [PASS][142] [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs0.html [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-iclb: [FAIL][143] ([i915#2842]) -> [PASS][144] [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb7/igt@gem_exec_fair@basic-pace@vecs0.html [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb2/igt@gem_exec_fair@basic-pace@vecs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [FAIL][145] ([i915#2849]) -> [PASS][146] [145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb4/igt@gem_exec_fair@basic-throttle@rcs0.html [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_workarounds@suspend-resume: - shard-apl: [DMESG-WARN][147] ([i915#180]) -> [PASS][148] +3 similar issues [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-apl6/igt@gem_workarounds@suspend-resume.html [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-apl1/igt@gem_workarounds@suspend-resume.html * igt@gen9_exec_parse@allowed-all: - shard-glk: [DMESG-WARN][149] ([i915#5566] / [i915#716]) -> [PASS][150] [149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-glk7/igt@gen9_exec_parse@allowed-all.html [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-glk3/igt@gen9_exec_parse@allowed-all.html * igt@i915_module_load@reload-with-fault-injection: - shard-snb: [DMESG-WARN][151] ([i915#6201]) -> [PASS][152] [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-snb7/igt@i915_module_load@reload-with-fault-injection.html [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-snb6/igt@i915_module_load@reload-with-fault-injection.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [FAIL][153] ([i915#454]) -> [PASS][154] [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb7/igt@i915_pm_dc@dc6-psr.html [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb2/igt@i915_pm_dc@dc6-psr.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip: - shard-tglb: [FAIL][155] ([i915#3743]) -> [PASS][156] [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-tglb2/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-tglb8/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-glk: [FAIL][157] ([i915#2346] / [i915#533]) -> [PASS][158] [157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_flip@flip-vs-expired-vblank@a-dp1: - shard-kbl: [FAIL][159] ([i915#79]) -> [PASS][160] [159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-kbl7/igt@kms_flip@flip-vs-expired-vblank@a-dp1.html [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-kbl1/igt@kms_flip@flip-vs-expired-vblank@a-dp1.html * igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2: - shard-glk: [FAIL][161] ([i915#79]) -> [PASS][162] [161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-glk4/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-glk1/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html * igt@kms_psr@psr2_cursor_plane_move: - shard-iclb: [SKIP][163] ([fdo#109441]) -> [PASS][164] [163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb7/igt@kms_psr@psr2_cursor_plane_move.html [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html #### Warnings #### * igt@gem_eio@unwedge-stress: - shard-tglb: [FAIL][165] ([i915#5784]) -> [TIMEOUT][166] ([i915#3063]) [165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-tglb5/igt@gem_eio@unwedge-stress.html [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-tglb6/igt@gem_eio@unwedge-stress.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-iclb: [FAIL][167] ([i915#2852]) -> [FAIL][168] ([i915#2842]) [167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb5/igt@gem_exec_fair@basic-none-rrul@rcs0.html [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb7/igt@gem_exec_fair@basic-none-rrul@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-tglb: [FAIL][169] ([i915#2842]) -> [SKIP][170] ([i915#2848]) +1 similar issue [169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-tglb1/igt@gem_exec_fair@basic-none-solo@rcs0.html [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-tglb2/igt@gem_exec_fair@basic-none-solo@rcs0.html * igt@kms_big_fb@x-tiled-8bpp-rotate-270: - shard-skl: [SKIP][171] ([fdo#109271] / [i915#1888]) -> [SKIP][172] ([fdo#109271]) [171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl2/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl1/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html * igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_mc_ccs: - shard-skl: [SKIP][173] ([fdo#109271]) -> [SKIP][174] ([fdo#109271] / [i915#1888]) +1 similar issue [173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-skl4/igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_mc_ccs.html [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-skl7/igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_mc_ccs.html * igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf: - shard-iclb: [SKIP][175] ([i915#658]) -> [SKIP][176] ([i915#2920]) [175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-iclb4/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html * igt@runner@aborted: - shard-apl: ([FAIL][177], [FAIL][178], [FAIL][179], [FAIL][180], [FAIL][181]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][182], [FAIL][183], [FAIL][184], [FAIL][185], [FAIL][186], [FAIL][187]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) [177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-apl6/igt@runner@aborted.html [178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-apl2/igt@runner@aborted.html [179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-apl6/igt@runner@aborted.html [180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-apl4/igt@runner@aborted.html [181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11755/shard-apl2/igt@runner@aborted.html [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-apl1/igt@runner@aborted.html [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-apl1/igt@runner@aborted.html [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-apl4/igt@runner@aborted.html [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-apl3/igt@runner@aborted.html [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-apl7/igt@runner@aborted.html [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/shard-apl2/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279 [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283 [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283 [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684 [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2848]: https://gitlab.freedesktop.org/drm/intel/issues/2848 [i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849 [i915#2852]: https://gitlab.freedesktop.org/drm/intel/issues/2852 [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856 [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701 [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743 [i915#3763]: https://gitlab.freedesktop.org/drm/intel/issues/3763 [i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778 [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767 [i915#5032]: https://gitlab.freedesktop.org/drm/intel/issues/5032 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287 [i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519 [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566 [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591 [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784 [i915#5800]: https://gitlab.freedesktop.org/drm/intel/issues/5800 [i915#6140]: https://gitlab.freedesktop.org/drm/intel/issues/6140 [i915#6201]: https://gitlab.freedesktop.org/drm/intel/issues/6201 [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 Build changes ------------- * Linux: CI_DRM_11755 -> Patchwork_105015v1 CI-20190529: 20190529 CI_DRM_11755: 65b93b94d6bc932ed60bb3fd9d68242db25b1f3b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6522: 5be5a1a1f168a59614101b77385f05f12ec7d30a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_105015v1: 65b93b94d6bc932ed60bb3fd9d68242db25b1f3b @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105015v1/index.html [-- Attachment #2: Type: text/html, Size: 49654 bytes --] ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-06-14 23:17 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-06-11 0:57 [Intel-gfx] [PATCH 0/2] i915: Extract, polish, and document multicast handling Matt Roper 2022-06-11 0:57 ` [Intel-gfx] [PATCH 1/2] drm/i915/gt: Move multicast register handling to a dedicated file Matt Roper 2022-06-11 0:57 ` [Intel-gfx] [PATCH 2/2] drm/i915/gt: Cleanup interface for MCR operations Matt Roper 2022-06-13 8:13 ` [Intel-gfx] [PATCH 0/2] i915: Extract, polish, and document multicast handling Jani Nikula 2022-06-13 22:11 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork 2022-06-13 22:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-06-13 22:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-06-14 23:17 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox