* [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U
@ 2023-01-07 5:36 Chaitanya Kumar Borah
2023-01-07 5:36 ` [Intel-gfx] [RFC 1/2] drm/i915: Add rplu sub platform Chaitanya Kumar Borah
` (4 more replies)
0 siblings, 5 replies; 16+ messages in thread
From: Chaitanya Kumar Borah @ 2023-01-07 5:36 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala
A new step of 480MHz has been added on SKUs that have an RPL-U
device id. This particular step is to support 120Hz panels
more efficiently.
This patchset adds a new table to include this new CDCLK
step. Details can be found in BSpec entry 55409.
Create a new sub-platform to identify RPL-U which will enable
us to make the differentiation during CDCLK initialization.
Furthermore, we need to make a distinction between ES (Engineering
Sample) and QS (Quality Sample) parts as this change comes only
to QS parts. This version of the patch does not include this change
as we are yet to make a decision if this particular part needs
to be upstreamed.(see comments on previous versions)
Chaitanya Kumar Borah (2):
drm/i915: Add rplu sub platform
drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
arch/x86/kernel/early-quirks.c | 1 +
drivers/gpu/drm/i915/display/intel_cdclk.c | 23 ++++++++++++++++++++++
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 7 +++++++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_step.c | 3 +++
include/drm/i915_pciids.h | 7 +++++--
8 files changed, 43 insertions(+), 2 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [RFC 1/2] drm/i915: Add rplu sub platform
2023-01-07 5:36 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
@ 2023-01-07 5:36 ` Chaitanya Kumar Borah
2023-01-10 1:02 ` Matt Roper
2023-01-07 5:36 ` [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U Chaitanya Kumar Borah
` (3 subsequent siblings)
4 siblings, 1 reply; 16+ messages in thread
From: Chaitanya Kumar Borah @ 2023-01-07 5:36 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala
Adding RPL-U as a sub platform. In RPL-U a new CDCLK step has
been added so we need to make a distinction between RPL-P
and RPL-U while CDCLK initialization.
Adding a sub-platform, enables us to make this differentiation
in the code.
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
arch/x86/kernel/early-quirks.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 7 +++++++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_step.c | 3 +++
include/drm/i915_pciids.h | 7 +++++--
7 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index a6c1867fc7aa..1ba9926c8974 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -559,6 +559,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
INTEL_ADLN_IDS(&gen11_early_ops),
INTEL_RPLS_IDS(&gen11_early_ops),
INTEL_RPLP_IDS(&gen11_early_ops),
+ INTEL_RPLU_IDS(&gen11_early_ops),
};
struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 48fd82722f12..c88e514728a0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -619,6 +619,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
#define IS_ADLP_RPLP(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
+#define IS_ADLP_RPLU(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 6cc65079b18d..e9f3b99b3e00 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1234,6 +1234,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_DG1_IDS(&dg1_info),
INTEL_RPLS_IDS(&adl_s_info),
INTEL_RPLP_IDS(&adl_p_info),
+ INTEL_RPLU_IDS(&adl_p_info),
INTEL_DG2_IDS(&dg2_info),
INTEL_ATS_M_IDS(&ats_m_info),
INTEL_MTL_IDS(&mtl_info),
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 849baf6c3b3c..88f3da63948b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -201,6 +201,10 @@ static const u16 subplatform_rpl_ids[] = {
INTEL_RPLP_IDS(0),
};
+static const u16 subplatform_rplu_ids[] = {
+ INTEL_RPLU_IDS(0),
+};
+
static const u16 subplatform_g10_ids[] = {
INTEL_DG2_G10_IDS(0),
INTEL_ATS_M150_IDS(0),
@@ -268,6 +272,9 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
} else if (find_devid(devid, subplatform_rpl_ids,
ARRAY_SIZE(subplatform_rpl_ids))) {
mask = BIT(INTEL_SUBPLATFORM_RPL);
+ } else if (find_devid(devid, subplatform_rplu_ids,
+ ARRAY_SIZE(subplatform_rplu_ids))) {
+ mask = BIT(INTEL_SUBPLATFORM_RPLU);
} else if (find_devid(devid, subplatform_g10_ids,
ARRAY_SIZE(subplatform_g10_ids))) {
mask = BIT(INTEL_SUBPLATFORM_G10);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index d588e5fd2eea..3e3ca5eb073f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -127,6 +127,7 @@ enum intel_platform {
* bit set
*/
#define INTEL_SUBPLATFORM_N 1
+#define INTEL_SUBPLATFORM_RPLU 2
/* MTL */
#define INTEL_SUBPLATFORM_M 0
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 84a6fe736a3b..df75057eaa65 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -194,6 +194,9 @@ void intel_step_init(struct drm_i915_private *i915)
} else if (IS_ADLP_RPLP(i915)) {
revids = adlp_rplp_revids;
size = ARRAY_SIZE(adlp_rplp_revids);
+ } else if (IS_ADLP_RPLU(i915)) {
+ revids = adlp_rplp_revids;
+ size = ARRAY_SIZE(adlp_rplp_revids);
} else if (IS_ALDERLAKE_P(i915)) {
revids = adlp_revids;
size = ARRAY_SIZE(adlp_revids);
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 4a4c190f7698..87bb7e26dfb6 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -687,10 +687,13 @@
/* RPL-P */
#define INTEL_RPLP_IDS(info) \
INTEL_VGA_DEVICE(0xA720, info), \
- INTEL_VGA_DEVICE(0xA721, info), \
INTEL_VGA_DEVICE(0xA7A0, info), \
+ INTEL_VGA_DEVICE(0xA7A8, info)
+
+/* RPL-U */
+#define INTEL_RPLU_IDS(info) \
INTEL_VGA_DEVICE(0xA7A1, info), \
- INTEL_VGA_DEVICE(0xA7A8, info), \
+ INTEL_VGA_DEVICE(0xA721, info), \
INTEL_VGA_DEVICE(0xA7A9, info)
/* DG2 */
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
2023-01-07 5:36 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
2023-01-07 5:36 ` [Intel-gfx] [RFC 1/2] drm/i915: Add rplu sub platform Chaitanya Kumar Borah
@ 2023-01-07 5:36 ` Chaitanya Kumar Borah
2023-01-10 1:08 ` Matt Roper
2023-01-10 9:06 ` Jani Nikula
2023-01-07 5:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add new CDCLK step for RPL-U (rev3) Patchwork
` (2 subsequent siblings)
4 siblings, 2 replies; 16+ messages in thread
From: Chaitanya Kumar Borah @ 2023-01-07 5:36 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala
A new step of 480MHz has been added on SKUs that have a RPL-U
device id to support 120Hz displays more efficiently. Use a
new quirk to identify the machine for which this change needs
to be applied.
BSpec: 55409
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0c107a38f9d0..a437ac446871 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1329,6 +1329,27 @@ static const struct intel_cdclk_vals adlp_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals rplu_cdclk_table[] = {
+ { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
+ { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
+ { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
+ { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
+ { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
+
+ { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
+ { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
+ { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
+ { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
+ { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
+
+ { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
+ {}
+};
+
static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{ .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
{ .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
@@ -3353,6 +3374,8 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
+ else if (IS_ADLP_RPLU(dev_priv))
+ dev_priv->display.cdclk.table = rplu_cdclk_table;
else
dev_priv->display.cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add new CDCLK step for RPL-U (rev3)
2023-01-07 5:36 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
2023-01-07 5:36 ` [Intel-gfx] [RFC 1/2] drm/i915: Add rplu sub platform Chaitanya Kumar Borah
2023-01-07 5:36 ` [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U Chaitanya Kumar Borah
@ 2023-01-07 5:54 ` Patchwork
2023-01-07 8:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-01-07 9:41 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2023-01-07 5:54 UTC (permalink / raw)
To: Borah, Chaitanya Kumar; +Cc: intel-gfx
== Series Details ==
Series: Add new CDCLK step for RPL-U (rev3)
URL : https://patchwork.freedesktop.org/series/111472/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Add new CDCLK step for RPL-U (rev3)
2023-01-07 5:36 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
` (2 preceding siblings ...)
2023-01-07 5:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add new CDCLK step for RPL-U (rev3) Patchwork
@ 2023-01-07 8:27 ` Patchwork
2023-01-07 9:41 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2023-01-07 8:27 UTC (permalink / raw)
To: Borah, Chaitanya Kumar; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4144 bytes --]
== Series Details ==
Series: Add new CDCLK step for RPL-U (rev3)
URL : https://patchwork.freedesktop.org/series/111472/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12554 -> Patchwork_111472v3
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/index.html
Participating hosts (42 -> 39)
------------------------------
Missing (3): fi-kbl-soraka fi-rkl-11600 fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_111472v3 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [PASS][1] -> [INCOMPLETE][2] ([i915#6972])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
* igt@runner@aborted:
- fi-bsw-kefka: NOTRUN -> [FAIL][3] ([fdo#109271] / [i915#4312])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/fi-bsw-kefka/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_gttfill@basic:
- fi-pnv-d510: [FAIL][4] ([i915#7229]) -> [PASS][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
* igt@i915_selftest@live@migrate:
- bat-adlp-4: [DMESG-FAIL][6] ([i915#7699]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/bat-adlp-4/igt@i915_selftest@live@migrate.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/bat-adlp-4/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@requests:
- {bat-rpls-1}: [INCOMPLETE][8] ([i915#6257]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/bat-rpls-1/igt@i915_selftest@live@requests.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/bat-rpls-1/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@workarounds:
- {bat-adln-1}: [INCOMPLETE][10] ([i915#7467]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/bat-adln-1/igt@i915_selftest@live@workarounds.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/bat-adln-1/igt@i915_selftest@live@workarounds.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
[i915#6972]: https://gitlab.freedesktop.org/drm/intel/issues/6972
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
[i915#7467]: https://gitlab.freedesktop.org/drm/intel/issues/7467
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
Build changes
-------------
* Linux: CI_DRM_12554 -> Patchwork_111472v3
CI-20190529: 20190529
CI_DRM_12554: 77b21315725079a0f62117b62ab9e6fc3c5b325d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7110: db10a19b94d1d7ae5ba62eb48d52c47ccb27766f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111472v3: 77b21315725079a0f62117b62ab9e6fc3c5b325d @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
95d682e137fe drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
dfcc494709f6 drm/i915: Add rplu sub platform
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/index.html
[-- Attachment #2: Type: text/html, Size: 4634 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Add new CDCLK step for RPL-U (rev3)
2023-01-07 5:36 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
` (3 preceding siblings ...)
2023-01-07 8:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-01-07 9:41 ` Patchwork
4 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2023-01-07 9:41 UTC (permalink / raw)
To: Borah, Chaitanya Kumar; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 19012 bytes --]
== Series Details ==
Series: Add new CDCLK step for RPL-U (rev3)
URL : https://patchwork.freedesktop.org/series/111472/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12554_full -> Patchwork_111472v3_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/index.html
Participating hosts (13 -> 11)
------------------------------
Additional (1): shard-rkl0
Missing (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005
Known issues
------------
Here are the changes found in Patchwork_111472v3_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#2842])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2346]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
* igt@perf@stress-open-close:
- shard-glk: [PASS][5] -> [INCOMPLETE][6] ([i915#5213])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-glk5/igt@perf@stress-open-close.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-glk5/igt@perf@stress-open-close.html
* igt@runner@aborted:
- shard-glk: NOTRUN -> [FAIL][7] ([i915#4312])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-glk5/igt@runner@aborted.html
#### Possible fixes ####
* igt@drm_fdinfo@idle@rcs0:
- {shard-rkl}: [FAIL][8] ([i915#7742]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-rkl-4/igt@drm_fdinfo@idle@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-rkl-1/igt@drm_fdinfo@idle@rcs0.html
* igt@fbdev@nullptr:
- {shard-rkl}: [SKIP][10] ([i915#2582]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-rkl-5/igt@fbdev@nullptr.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-rkl-6/igt@fbdev@nullptr.html
* igt@gem_exec_endless@dispatch@bcs0:
- {shard-rkl}: [SKIP][12] ([i915#6247]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-rkl-5/igt@gem_exec_endless@dispatch@bcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-rkl-6/igt@gem_exec_endless@dispatch@bcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- {shard-rkl}: [FAIL][14] ([i915#2842]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-rkl-2/igt@gem_exec_fair@basic-none-vip@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-rkl-5/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- {shard-tglu}: [FAIL][16] ([i915#2842]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-tglu-7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-tglu-2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_reloc@basic-gtt-read:
- {shard-rkl}: [SKIP][18] ([i915#3281]) -> [PASS][19] +6 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-rkl-2/igt@gem_exec_reloc@basic-gtt-read.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-rkl-5/igt@gem_exec_reloc@basic-gtt-read.html
* igt@gem_partial_pwrite_pread@reads:
- {shard-rkl}: [SKIP][20] ([i915#3282]) -> [PASS][21] +3 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-rkl-2/igt@gem_partial_pwrite_pread@reads.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-rkl-5/igt@gem_partial_pwrite_pread@reads.html
* igt@gen9_exec_parse@allowed-single:
- {shard-rkl}: [SKIP][22] ([i915#2527]) -> [PASS][23] +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-rkl-1/igt@gen9_exec_parse@allowed-single.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-rkl-5/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pipe_stress@stress-xrgb8888-ytiled:
- {shard-rkl}: [SKIP][24] ([i915#4098]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-rkl-1/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-rkl-6/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html
* igt@i915_pm_dc@dc6-dpms:
- {shard-rkl}: [SKIP][26] ([i915#3361]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-rkl-5/igt@i915_pm_dc@dc6-dpms.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-rkl-6/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- {shard-dg1}: [FAIL][28] ([i915#3591]) -> [PASS][29] +2 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- {shard-dg1}: [SKIP][30] ([i915#1397]) -> [PASS][31] +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-dg1-14/igt@i915_pm_rpm@dpms-non-lpsp.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-dg1-19/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@i915_pm_rpm@fences-dpms:
- {shard-rkl}: [SKIP][32] ([i915#1849]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-rkl-1/igt@i915_pm_rpm@fences-dpms.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-rkl-6/igt@i915_pm_rpm@fences-dpms.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- {shard-rkl}: [SKIP][34] ([i915#1845] / [i915#4098]) -> [PASS][35] +16 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-rkl-2/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-rkl-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- {shard-tglu}: [SKIP][36] ([i915#1845] / [i915#7651]) -> [PASS][37] +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-tglu-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-tglu-2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
- {shard-tglu}: [SKIP][38] ([i915#7651]) -> [PASS][39] +7 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-tglu-6/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-tglu-2/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- {shard-rkl}: [SKIP][40] ([i915#1849] / [i915#4098]) -> [PASS][41] +10 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_properties@crtc-properties-atomic:
- {shard-tglu}: [SKIP][42] ([i915#1849]) -> [PASS][43] +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-tglu-6/igt@kms_properties@crtc-properties-atomic.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-tglu-2/igt@kms_properties@crtc-properties-atomic.html
* igt@kms_universal_plane@cursor-fb-leak-pipe-b:
- {shard-rkl}: [SKIP][44] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][45] +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-rkl-1/igt@kms_universal_plane@cursor-fb-leak-pipe-b.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-rkl-6/igt@kms_universal_plane@cursor-fb-leak-pipe-b.html
* igt@perf@polling-small-buf:
- {shard-rkl}: [FAIL][46] ([i915#1722]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-rkl-4/igt@perf@polling-small-buf.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-rkl-1/igt@perf@polling-small-buf.html
* igt@prime_vgem@basic-fence-read:
- {shard-rkl}: [SKIP][48] ([fdo#109295] / [i915#3291] / [i915#3708]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12554/shard-rkl-2/igt@prime_vgem@basic-fence-read.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/shard-rkl-5/igt@prime_vgem@basic-fence-read.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2232]: https://gitlab.freedesktop.org/drm/intel/issues/2232
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2532]: https://gitlab.freedesktop.org/drm/intel/issues/2532
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4275]: https://gitlab.freedesktop.org/drm/intel/issues/4275
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6355]: https://gitlab.freedesktop.org/drm/intel/issues/6355
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
[i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7679]: https://gitlab.freedesktop.org/drm/intel/issues/7679
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
Build changes
-------------
* Linux: CI_DRM_12554 -> Patchwork_111472v3
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_12554: 77b21315725079a0f62117b62ab9e6fc3c5b325d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7110: db10a19b94d1d7ae5ba62eb48d52c47ccb27766f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111472v3: 77b21315725079a0f62117b62ab9e6fc3c5b325d @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v3/index.html
[-- Attachment #2: Type: text/html, Size: 13994 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [RFC 1/2] drm/i915: Add rplu sub platform
2023-01-07 5:36 ` [Intel-gfx] [RFC 1/2] drm/i915: Add rplu sub platform Chaitanya Kumar Borah
@ 2023-01-10 1:02 ` Matt Roper
2023-01-12 9:45 ` Borah, Chaitanya Kumar
0 siblings, 1 reply; 16+ messages in thread
From: Matt Roper @ 2023-01-10 1:02 UTC (permalink / raw)
To: Chaitanya Kumar Borah; +Cc: ville.syrjala, intel-gfx
On Sat, Jan 07, 2023 at 11:06:42AM +0530, Chaitanya Kumar Borah wrote:
> Adding RPL-U as a sub platform. In RPL-U a new CDCLK step has
> been added so we need to make a distinction between RPL-P
> and RPL-U while CDCLK initialization.
>
> Adding a sub-platform, enables us to make this differentiation
> in the code.
>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> ---
> arch/x86/kernel/early-quirks.c | 1 +
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.c | 7 +++++++
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> drivers/gpu/drm/i915/intel_step.c | 3 +++
> include/drm/i915_pciids.h | 7 +++++--
> 7 files changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index a6c1867fc7aa..1ba9926c8974 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -559,6 +559,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
> INTEL_ADLN_IDS(&gen11_early_ops),
> INTEL_RPLS_IDS(&gen11_early_ops),
> INTEL_RPLP_IDS(&gen11_early_ops),
> + INTEL_RPLU_IDS(&gen11_early_ops),
> };
>
> struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 48fd82722f12..c88e514728a0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -619,6 +619,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
> #define IS_ADLP_RPLP(dev_priv) \
> IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
> +#define IS_ADLP_RPLU(dev_priv) \
> + IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> #define IS_BDW_ULT(dev_priv) \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 6cc65079b18d..e9f3b99b3e00 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1234,6 +1234,7 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_DG1_IDS(&dg1_info),
> INTEL_RPLS_IDS(&adl_s_info),
> INTEL_RPLP_IDS(&adl_p_info),
> + INTEL_RPLU_IDS(&adl_p_info),
> INTEL_DG2_IDS(&dg2_info),
> INTEL_ATS_M_IDS(&ats_m_info),
> INTEL_MTL_IDS(&mtl_info),
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 849baf6c3b3c..88f3da63948b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -201,6 +201,10 @@ static const u16 subplatform_rpl_ids[] = {
> INTEL_RPLP_IDS(0),
> };
>
> +static const u16 subplatform_rplu_ids[] = {
> + INTEL_RPLU_IDS(0),
> +};
> +
> static const u16 subplatform_g10_ids[] = {
> INTEL_DG2_G10_IDS(0),
> INTEL_ATS_M150_IDS(0),
> @@ -268,6 +272,9 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
> } else if (find_devid(devid, subplatform_rpl_ids,
> ARRAY_SIZE(subplatform_rpl_ids))) {
> mask = BIT(INTEL_SUBPLATFORM_RPL);
> + } else if (find_devid(devid, subplatform_rplu_ids,
> + ARRAY_SIZE(subplatform_rplu_ids))) {
> + mask = BIT(INTEL_SUBPLATFORM_RPLU);
> } else if (find_devid(devid, subplatform_g10_ids,
> ARRAY_SIZE(subplatform_g10_ids))) {
> mask = BIT(INTEL_SUBPLATFORM_G10);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index d588e5fd2eea..3e3ca5eb073f 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -127,6 +127,7 @@ enum intel_platform {
> * bit set
> */
> #define INTEL_SUBPLATFORM_N 1
> +#define INTEL_SUBPLATFORM_RPLU 2
>
> /* MTL */
> #define INTEL_SUBPLATFORM_M 0
> diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
> index 84a6fe736a3b..df75057eaa65 100644
> --- a/drivers/gpu/drm/i915/intel_step.c
> +++ b/drivers/gpu/drm/i915/intel_step.c
> @@ -194,6 +194,9 @@ void intel_step_init(struct drm_i915_private *i915)
> } else if (IS_ADLP_RPLP(i915)) {
> revids = adlp_rplp_revids;
> size = ARRAY_SIZE(adlp_rplp_revids);
> + } else if (IS_ADLP_RPLU(i915)) {
Since the two blocks are identical, it might be slightly preferable to
just combine the conditions; that will also help make it clear that this
is intentional and not a copy/paste mistake.
} else if (IS_ADLP_RPLU(i915) || IS_ADLP_RPLP(i915)) {
...
> + revids = adlp_rplp_revids;
> + size = ARRAY_SIZE(adlp_rplp_revids);
> } else if (IS_ALDERLAKE_P(i915)) {
> revids = adlp_revids;
> size = ARRAY_SIZE(adlp_revids);
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 4a4c190f7698..87bb7e26dfb6 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -687,10 +687,13 @@
> /* RPL-P */
> #define INTEL_RPLP_IDS(info) \
> INTEL_VGA_DEVICE(0xA720, info), \
> - INTEL_VGA_DEVICE(0xA721, info), \
> INTEL_VGA_DEVICE(0xA7A0, info), \
> + INTEL_VGA_DEVICE(0xA7A8, info)
> +
> +/* RPL-U */
> +#define INTEL_RPLU_IDS(info) \
> INTEL_VGA_DEVICE(0xA7A1, info), \
> - INTEL_VGA_DEVICE(0xA7A8, info), \
> + INTEL_VGA_DEVICE(0xA721, info), \
> INTEL_VGA_DEVICE(0xA7A9, info)
I know the bspec orders them like this, but it's probably better to just
sort these two lists numerically. These bspec pages get reshuffled so
often these days that trying to match the bspec's strange ordering isn't
really worth it.
Matt
>
> /* DG2 */
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
2023-01-07 5:36 ` [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U Chaitanya Kumar Borah
@ 2023-01-10 1:08 ` Matt Roper
2023-01-12 9:48 ` Borah, Chaitanya Kumar
2023-01-10 9:06 ` Jani Nikula
1 sibling, 1 reply; 16+ messages in thread
From: Matt Roper @ 2023-01-10 1:08 UTC (permalink / raw)
To: Chaitanya Kumar Borah; +Cc: ville.syrjala, intel-gfx
On Sat, Jan 07, 2023 at 11:06:43AM +0530, Chaitanya Kumar Borah wrote:
> A new step of 480MHz has been added on SKUs that have a RPL-U
> device id to support 120Hz displays more efficiently. Use a
> new quirk to identify the machine for which this change needs
> to be applied.
>
> BSpec: 55409
>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 23 ++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 0c107a38f9d0..a437ac446871 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1329,6 +1329,27 @@ static const struct intel_cdclk_vals adlp_cdclk_table[] = {
> {}
> };
>
> +static const struct intel_cdclk_vals rplu_cdclk_table[] = {
> + { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> + { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
Are we missing an entry for 307.2 MHz here?
> + { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
> + { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> + { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> +
> + { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> + { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
And 312 MHz here?
> + { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
> + { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> + { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
Typo in refclk here? Actually, it looks like we may have the same typo
in the ADL-P table as well.
> +
> + { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> + { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
And missing 307.2 MHz again?
Matt
> + { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
> + { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> + { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> + {}
> +};
> +
> static const struct intel_cdclk_vals dg2_cdclk_table[] = {
> { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
> { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
> @@ -3353,6 +3374,8 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> /* Wa_22011320316:adl-p[a0] */
> if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
> + else if (IS_ADLP_RPLU(dev_priv))
> + dev_priv->display.cdclk.table = rplu_cdclk_table;
> else
> dev_priv->display.cdclk.table = adlp_cdclk_table;
> } else if (IS_ROCKETLAKE(dev_priv)) {
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
2023-01-07 5:36 ` [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U Chaitanya Kumar Borah
2023-01-10 1:08 ` Matt Roper
@ 2023-01-10 9:06 ` Jani Nikula
2023-01-10 15:36 ` Matt Roper
1 sibling, 1 reply; 16+ messages in thread
From: Jani Nikula @ 2023-01-10 9:06 UTC (permalink / raw)
To: Chaitanya Kumar Borah, intel-gfx; +Cc: ville.syrjala
On Sat, 07 Jan 2023, Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> wrote:
> A new step of 480MHz has been added on SKUs that have a RPL-U
> device id to support 120Hz displays more efficiently. Use a
> new quirk to identify the machine for which this change needs
> to be applied.
>
> BSpec: 55409
>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 23 ++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 0c107a38f9d0..a437ac446871 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1329,6 +1329,27 @@ static const struct intel_cdclk_vals adlp_cdclk_table[] = {
> {}
> };
>
> +static const struct intel_cdclk_vals rplu_cdclk_table[] = {
> + { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> + { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> + { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
> + { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> + { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> +
> + { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> + { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> + { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
> + { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> + { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
> +
> + { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> + { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> + { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
> + { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> + { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> + {}
> +};
> +
> static const struct intel_cdclk_vals dg2_cdclk_table[] = {
> { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
> { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
> @@ -3353,6 +3374,8 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> /* Wa_22011320316:adl-p[a0] */
> if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
Are RPL-U A0-B0 going to enter this branch? Is this the right thing to
do?
BR,
Jani.
> + else if (IS_ADLP_RPLU(dev_priv))
> + dev_priv->display.cdclk.table = rplu_cdclk_table;
> else
> dev_priv->display.cdclk.table = adlp_cdclk_table;
> } else if (IS_ROCKETLAKE(dev_priv)) {
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
2023-01-10 9:06 ` Jani Nikula
@ 2023-01-10 15:36 ` Matt Roper
2023-01-10 16:10 ` Jani Nikula
0 siblings, 1 reply; 16+ messages in thread
From: Matt Roper @ 2023-01-10 15:36 UTC (permalink / raw)
To: Jani Nikula; +Cc: ville.syrjala, intel-gfx
On Tue, Jan 10, 2023 at 11:06:14AM +0200, Jani Nikula wrote:
> On Sat, 07 Jan 2023, Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> wrote:
> > A new step of 480MHz has been added on SKUs that have a RPL-U
> > device id to support 120Hz displays more efficiently. Use a
> > new quirk to identify the machine for which this change needs
> > to be applied.
> >
> > BSpec: 55409
> >
> > Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 23 ++++++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 0c107a38f9d0..a437ac446871 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1329,6 +1329,27 @@ static const struct intel_cdclk_vals adlp_cdclk_table[] = {
> > {}
> > };
> >
> > +static const struct intel_cdclk_vals rplu_cdclk_table[] = {
> > + { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> > + { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> > + { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
> > + { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > + { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > +
> > + { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> > + { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> > + { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
> > + { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > + { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
> > +
> > + { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> > + { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> > + { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
> > + { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > + { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > + {}
> > +};
> > +
> > static const struct intel_cdclk_vals dg2_cdclk_table[] = {
> > { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
> > { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
> > @@ -3353,6 +3374,8 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> > /* Wa_22011320316:adl-p[a0] */
> > if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
>
> Are RPL-U A0-B0 going to enter this branch? Is this the right thing to
> do?
There's no such thing as a RPL A0/B0. RPL continues the stepping
progression from ADL, and all RPL parts have E0 or newer display
steppings (bspec 55376).
Matt
>
> BR,
> Jani.
>
>
> > + else if (IS_ADLP_RPLU(dev_priv))
> > + dev_priv->display.cdclk.table = rplu_cdclk_table;
> > else
> > dev_priv->display.cdclk.table = adlp_cdclk_table;
> > } else if (IS_ROCKETLAKE(dev_priv)) {
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
2023-01-10 15:36 ` Matt Roper
@ 2023-01-10 16:10 ` Jani Nikula
0 siblings, 0 replies; 16+ messages in thread
From: Jani Nikula @ 2023-01-10 16:10 UTC (permalink / raw)
To: Matt Roper; +Cc: ville.syrjala, intel-gfx
On Tue, 10 Jan 2023, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Tue, Jan 10, 2023 at 11:06:14AM +0200, Jani Nikula wrote:
>> On Sat, 07 Jan 2023, Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> wrote:
>> > @@ -3353,6 +3374,8 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>> > /* Wa_22011320316:adl-p[a0] */
>> > if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>> > dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
>>
>> Are RPL-U A0-B0 going to enter this branch? Is this the right thing to
>> do?
>
> There's no such thing as a RPL A0/B0. RPL continues the stepping
> progression from ADL, and all RPL parts have E0 or newer display
> steppings (bspec 55376).
Ok, thanks.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
2023-01-12 9:27 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
@ 2023-01-12 9:27 ` Chaitanya Kumar Borah
0 siblings, 0 replies; 16+ messages in thread
From: Chaitanya Kumar Borah @ 2023-01-12 9:27 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala
A new step of 480MHz has been added on SKUs that have a RPL-U
device id to support 120Hz displays more efficiently. Use a
new quirk to identify the machine for which this change needs
to be applied.
BSpec: 55409
v2: (Matt)
- Add missing clock steps
- Correct reference clock typo
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 26 ++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0c107a38f9d0..ba365ef17abc 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1329,6 +1329,30 @@ static const struct intel_cdclk_vals adlp_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals rplu_cdclk_table[] = {
+ { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
+ { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
+ { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
+ { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
+ { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
+ { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
+
+ { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
+ { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
+ { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
+ { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
+ { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
+ { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
+
+ { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
+ {}
+};
+
static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{ .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
{ .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
@@ -3353,6 +3377,8 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
+ else if (IS_ADLP_WITH_480CDCLK(dev_priv))
+ dev_priv->display.cdclk.table = rplu_cdclk_table;
else
dev_priv->display.cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [RFC 1/2] drm/i915: Add rplu sub platform
2023-01-10 1:02 ` Matt Roper
@ 2023-01-12 9:45 ` Borah, Chaitanya Kumar
0 siblings, 0 replies; 16+ messages in thread
From: Borah, Chaitanya Kumar @ 2023-01-12 9:45 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: Syrjala, Ville, intel-gfx@lists.freedesktop.org
Hello Matt,
> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Tuesday, January 10, 2023 6:32 AM
> To: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; jani.nikula@linux.intel.com; Shankar,
> Uma <uma.shankar@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
> Srivatsa, Anusha <anusha.srivatsa@intel.com>; Atwood, Matthew S
> <matthew.s.atwood@intel.com>
> Subject: Re: [RFC 1/2] drm/i915: Add rplu sub platform
>
> On Sat, Jan 07, 2023 at 11:06:42AM +0530, Chaitanya Kumar Borah wrote:
> > Adding RPL-U as a sub platform. In RPL-U a new CDCLK step has been
> > added so we need to make a distinction between RPL-P and RPL-U while
> > CDCLK initialization.
> >
> > Adding a sub-platform, enables us to make this differentiation in the
> > code.
> >
> > Signed-off-by: Chaitanya Kumar Borah
> <chaitanya.kumar.borah@intel.com>
> > ---
> > arch/x86/kernel/early-quirks.c | 1 +
> > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > drivers/gpu/drm/i915/intel_device_info.c | 7 +++++++
> > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > drivers/gpu/drm/i915/intel_step.c | 3 +++
> > include/drm/i915_pciids.h | 7 +++++--
> > 7 files changed, 20 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/x86/kernel/early-quirks.c
> > b/arch/x86/kernel/early-quirks.c index a6c1867fc7aa..1ba9926c8974
> > 100644
> > --- a/arch/x86/kernel/early-quirks.c
> > +++ b/arch/x86/kernel/early-quirks.c
> > @@ -559,6 +559,7 @@ static const struct pci_device_id intel_early_ids[]
> __initconst = {
> > INTEL_ADLN_IDS(&gen11_early_ops),
> > INTEL_RPLS_IDS(&gen11_early_ops),
> > INTEL_RPLP_IDS(&gen11_early_ops),
> > + INTEL_RPLU_IDS(&gen11_early_ops),
> > };
> >
> > struct resource intel_graphics_stolen_res __ro_after_init =
> > DEFINE_RES_MEM(0, 0); diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index 48fd82722f12..c88e514728a0
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -619,6 +619,8 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
> > IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P,
> INTEL_SUBPLATFORM_N)
> > #define IS_ADLP_RPLP(dev_priv) \
> > IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P,
> INTEL_SUBPLATFORM_RPL)
> > +#define IS_ADLP_RPLU(dev_priv) \
> > + IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P,
> INTEL_SUBPLATFORM_RPLU)
> > #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> > (INTEL_DEVID(dev_priv) & 0xFF00) ==
> 0x0C00) #define
> > IS_BDW_ULT(dev_priv) \ diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > b/drivers/gpu/drm/i915/i915_pci.c index 6cc65079b18d..e9f3b99b3e00
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -1234,6 +1234,7 @@ static const struct pci_device_id pciidlist[] = {
> > INTEL_DG1_IDS(&dg1_info),
> > INTEL_RPLS_IDS(&adl_s_info),
> > INTEL_RPLP_IDS(&adl_p_info),
> > + INTEL_RPLU_IDS(&adl_p_info),
> > INTEL_DG2_IDS(&dg2_info),
> > INTEL_ATS_M_IDS(&ats_m_info),
> > INTEL_MTL_IDS(&mtl_info),
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > b/drivers/gpu/drm/i915/intel_device_info.c
> > index 849baf6c3b3c..88f3da63948b 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -201,6 +201,10 @@ static const u16 subplatform_rpl_ids[] = {
> > INTEL_RPLP_IDS(0),
> > };
> >
> > +static const u16 subplatform_rplu_ids[] = {
> > + INTEL_RPLU_IDS(0),
> > +};
> > +
> > static const u16 subplatform_g10_ids[] = {
> > INTEL_DG2_G10_IDS(0),
> > INTEL_ATS_M150_IDS(0),
> > @@ -268,6 +272,9 @@ static void
> intel_device_info_subplatform_init(struct drm_i915_private *i915)
> > } else if (find_devid(devid, subplatform_rpl_ids,
> > ARRAY_SIZE(subplatform_rpl_ids))) {
> > mask = BIT(INTEL_SUBPLATFORM_RPL);
> > + } else if (find_devid(devid, subplatform_rplu_ids,
> > + ARRAY_SIZE(subplatform_rplu_ids))) {
> > + mask = BIT(INTEL_SUBPLATFORM_RPLU);
> > } else if (find_devid(devid, subplatform_g10_ids,
> > ARRAY_SIZE(subplatform_g10_ids))) {
> > mask = BIT(INTEL_SUBPLATFORM_G10);
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > b/drivers/gpu/drm/i915/intel_device_info.h
> > index d588e5fd2eea..3e3ca5eb073f 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -127,6 +127,7 @@ enum intel_platform {
> > * bit set
> > */
> > #define INTEL_SUBPLATFORM_N 1
> > +#define INTEL_SUBPLATFORM_RPLU 2
> >
> > /* MTL */
> > #define INTEL_SUBPLATFORM_M 0
> > diff --git a/drivers/gpu/drm/i915/intel_step.c
> > b/drivers/gpu/drm/i915/intel_step.c
> > index 84a6fe736a3b..df75057eaa65 100644
> > --- a/drivers/gpu/drm/i915/intel_step.c
> > +++ b/drivers/gpu/drm/i915/intel_step.c
> > @@ -194,6 +194,9 @@ void intel_step_init(struct drm_i915_private *i915)
> > } else if (IS_ADLP_RPLP(i915)) {
> > revids = adlp_rplp_revids;
> > size = ARRAY_SIZE(adlp_rplp_revids);
> > + } else if (IS_ADLP_RPLU(i915)) {
>
> Since the two blocks are identical, it might be slightly preferable to just
> combine the conditions; that will also help make it clear that this is
> intentional and not a copy/paste mistake.
>
> } else if (IS_ADLP_RPLU(i915) || IS_ADLP_RPLP(i915)) {
> ...
>
Since in the new implementation RPLU also belongs to RPL sub platform. This change is dropped in the latest version.
> > + revids = adlp_rplp_revids;
> > + size = ARRAY_SIZE(adlp_rplp_revids);
> > } else if (IS_ALDERLAKE_P(i915)) {
> > revids = adlp_revids;
> > size = ARRAY_SIZE(adlp_revids);
> > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> > index 4a4c190f7698..87bb7e26dfb6 100644
> > --- a/include/drm/i915_pciids.h
> > +++ b/include/drm/i915_pciids.h
> > @@ -687,10 +687,13 @@
> > /* RPL-P */
> > #define INTEL_RPLP_IDS(info) \
> > INTEL_VGA_DEVICE(0xA720, info), \
> > - INTEL_VGA_DEVICE(0xA721, info), \
> > INTEL_VGA_DEVICE(0xA7A0, info), \
> > + INTEL_VGA_DEVICE(0xA7A8, info)
> > +
> > +/* RPL-U */
> > +#define INTEL_RPLU_IDS(info) \
> > INTEL_VGA_DEVICE(0xA7A1, info), \
> > - INTEL_VGA_DEVICE(0xA7A8, info), \
> > + INTEL_VGA_DEVICE(0xA721, info), \
> > INTEL_VGA_DEVICE(0xA7A9, info)
>
> I know the bspec orders them like this, but it's probably better to just sort
> these two lists numerically. These bspec pages get reshuffled so often these
> days that trying to match the bspec's strange ordering isn't really worth it.
>
Ack. The new revision has the sequence corrected.
Regards
Chaitanya
>
> Matt
>
> >
> > /* DG2 */
> > --
> > 2.25.1
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
2023-01-10 1:08 ` Matt Roper
@ 2023-01-12 9:48 ` Borah, Chaitanya Kumar
0 siblings, 0 replies; 16+ messages in thread
From: Borah, Chaitanya Kumar @ 2023-01-12 9:48 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: Syrjala, Ville, intel-gfx@lists.freedesktop.org
Hello Matt,
> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Tuesday, January 10, 2023 6:38 AM
> To: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; jani.nikula@linux.intel.com; Shankar,
> Uma <uma.shankar@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
> Srivatsa, Anusha <anusha.srivatsa@intel.com>; Atwood, Matthew S
> <matthew.s.atwood@intel.com>
> Subject: Re: [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
>
> On Sat, Jan 07, 2023 at 11:06:43AM +0530, Chaitanya Kumar Borah wrote:
> > A new step of 480MHz has been added on SKUs that have a RPL-U device
> > id to support 120Hz displays more efficiently. Use a new quirk to
> > identify the machine for which this change needs to be applied.
> >
> > BSpec: 55409
> >
> > Signed-off-by: Chaitanya Kumar Borah
> <chaitanya.kumar.borah@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 23
> > ++++++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index 0c107a38f9d0..a437ac446871 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1329,6 +1329,27 @@ static const struct intel_cdclk_vals
> adlp_cdclk_table[] = {
> > {}
> > };
> >
> > +static const struct intel_cdclk_vals rplu_cdclk_table[] = {
> > + { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> > + { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
>
> Are we missing an entry for 307.2 MHz here?
>
Ack. Added in new version.
> > + { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
> > + { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> > + { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> > +
> > + { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> > + { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
>
> And 312 MHz here?
>
Ack. Added in new version.
> > + { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
> > + { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> > + { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
>
> Typo in refclk here? Actually, it looks like we may have the same typo in the
> ADL-P table as well.
>
Ack. Added in new version. For ADL-P I have created another patch. [1]
>
> > +
> > + { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> > + { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
>
> And missing 307.2 MHz again?
>
Ack. Added in new version.
Regards
Chaitanya
[1] https://patchwork.freedesktop.org/patch/518086/
>
> Matt
>
> > + { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
> > + { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> > + { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> > + {}
> > +};
> > +
> > static const struct intel_cdclk_vals dg2_cdclk_table[] = {
> > { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform =
> 0x8888 },
> > { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34,
> > .waveform = 0x9248 }, @@ -3353,6 +3374,8 @@ void
> intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> > /* Wa_22011320316:adl-p[a0] */
> > if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > dev_priv->display.cdclk.table =
> adlp_a_step_cdclk_table;
> > + else if (IS_ADLP_RPLU(dev_priv))
> > + dev_priv->display.cdclk.table = rplu_cdclk_table;
> > else
> > dev_priv->display.cdclk.table = adlp_cdclk_table;
> > } else if (IS_ROCKETLAKE(dev_priv)) {
> > --
> > 2.25.1
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
2023-01-17 7:42 [Intel-gfx] [RFC 0/2] Add new CDCLK step " Chaitanya Kumar Borah
@ 2023-01-17 7:42 ` Chaitanya Kumar Borah
2023-01-24 14:33 ` Jani Nikula
0 siblings, 1 reply; 16+ messages in thread
From: Chaitanya Kumar Borah @ 2023-01-17 7:42 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala
A new step of 480MHz has been added on SKUs that have a RPL-U
device id to support 120Hz displays more efficiently. Use a
new quirk to identify the machine for which this change needs
to be applied.
BSpec: 55409
v2: (Matt)
- Add missing clock steps
- Correct reference clock typo
v3: - Revert to RPL-U subplatform
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 27 ++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0c107a38f9d0..a5e3497534f3 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1329,6 +1329,30 @@ static const struct intel_cdclk_vals adlp_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals rplu_cdclk_table[] = {
+ { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
+ { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
+ { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
+ { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
+ { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
+ { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
+
+ { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
+ { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
+ { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
+ { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
+ { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
+ { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
+
+ { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
+ {}
+};
+
static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{ .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
{ .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
@@ -3353,6 +3377,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
+ /* Bspec: 55409 */
+ else if (IS_ADLP_RPLU(dev_priv))
+ dev_priv->display.cdclk.table = rplu_cdclk_table;
else
dev_priv->display.cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
2023-01-17 7:42 ` [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps " Chaitanya Kumar Borah
@ 2023-01-24 14:33 ` Jani Nikula
0 siblings, 0 replies; 16+ messages in thread
From: Jani Nikula @ 2023-01-24 14:33 UTC (permalink / raw)
To: Chaitanya Kumar Borah, intel-gfx; +Cc: ville.syrjala
On Tue, 17 Jan 2023, Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> wrote:
> A new step of 480MHz has been added on SKUs that have a RPL-U
> device id to support 120Hz displays more efficiently. Use a
> new quirk to identify the machine for which this change needs
> to be applied.
>
> BSpec: 55409
>
> v2: (Matt)
> - Add missing clock steps
> - Correct reference clock typo
>
> v3: - Revert to RPL-U subplatform
>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 27 ++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 0c107a38f9d0..a5e3497534f3 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1329,6 +1329,30 @@ static const struct intel_cdclk_vals adlp_cdclk_table[] = {
> {}
> };
>
> +static const struct intel_cdclk_vals rplu_cdclk_table[] = {
> + { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> + { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> + { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
> + { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
> + { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> + { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> +
> + { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> + { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> + { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
> + { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
> + { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> + { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
> +
> + { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> + { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> + { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> + { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
> + { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> + { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> + {}
> +};
> +
> static const struct intel_cdclk_vals dg2_cdclk_table[] = {
> { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
> { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
> @@ -3353,6 +3377,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> /* Wa_22011320316:adl-p[a0] */
> if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
> + /* Bspec: 55409 */
Please let's not add bspec references in comments.
BR,
Jani.
> + else if (IS_ADLP_RPLU(dev_priv))
> + dev_priv->display.cdclk.table = rplu_cdclk_table;
> else
> dev_priv->display.cdclk.table = adlp_cdclk_table;
> } else if (IS_ROCKETLAKE(dev_priv)) {
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2023-01-24 14:34 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-01-07 5:36 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
2023-01-07 5:36 ` [Intel-gfx] [RFC 1/2] drm/i915: Add rplu sub platform Chaitanya Kumar Borah
2023-01-10 1:02 ` Matt Roper
2023-01-12 9:45 ` Borah, Chaitanya Kumar
2023-01-07 5:36 ` [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U Chaitanya Kumar Borah
2023-01-10 1:08 ` Matt Roper
2023-01-12 9:48 ` Borah, Chaitanya Kumar
2023-01-10 9:06 ` Jani Nikula
2023-01-10 15:36 ` Matt Roper
2023-01-10 16:10 ` Jani Nikula
2023-01-07 5:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add new CDCLK step for RPL-U (rev3) Patchwork
2023-01-07 8:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-01-07 9:41 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2023-01-12 9:27 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
2023-01-12 9:27 ` [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps " Chaitanya Kumar Borah
2023-01-17 7:42 [Intel-gfx] [RFC 0/2] Add new CDCLK step " Chaitanya Kumar Borah
2023-01-17 7:42 ` [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps " Chaitanya Kumar Borah
2023-01-24 14:33 ` Jani Nikula
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox