From: Jani Nikula <jani.nikula@intel.com>
To: Madhav Chauhan <madhav.chauhan@intel.com>,
intel-gfx@lists.freedesktop.org
Cc: paulo.r.zanoni@intel.com, rodrigo.vivi@intel.com
Subject: Re: [PATCH 04/20] drm/i915/icl: Enable DSI IO power
Date: Mon, 02 Jul 2018 12:56:45 +0300 [thread overview]
Message-ID: <87r2kmq7tu.fsf@intel.com> (raw)
In-Reply-To: <1529058084-31777-5-git-send-email-madhav.chauhan@intel.com>
On Fri, 15 Jun 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> This patch configures mode of operation for DSI
> and enable DDI IO power by configuring power well.
>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi_new.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c b/drivers/gpu/drm/i915/intel_dsi_new.c
> index 0d325ca..5ec4016 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_new.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_new.c
> @@ -55,11 +55,33 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
> }
> }
>
> +static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + enum port port;
> + u32 tmp;
> +
> + for_each_dsi_port(port, intel_dsi->ports) {
> + tmp = I915_READ(ICL_DSI_IO_MODECTL(port));
> + tmp |= COMBO_PHY_MODE_DSI;
> + I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp);
> + }
> +
> + intel_display_power_get(dev_priv, POWER_DOMAIN_PORT_DDI_A_IO);
> +
> + if (intel_dsi->dual_link)
> + intel_display_power_get(dev_priv, POWER_DOMAIN_PORT_DDI_B_IO);
Per bspec, "DSI0 uses DDI A; DSI1 uses DDI B" so shouldn't this be a
for_each_dsi_port() too, with the appropriate mapping to power domain?
> +}
> +
> static void __attribute__((unused)) gen11_dsi_pre_enable(
> struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config,
> const struct drm_connector_state *conn_state)
Please don't end lines in (. You can add a newline before the function
name:
static void __attribute__((unused))
gen11_dsi_pre_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config,
const struct drm_connector_state *conn_state)
> {
> + /* step2: enable IO power */
> + gen11_dsi_enable_io_power(encoder);
> +
> /* step3: enable DSI PLL */
> gen11_dsi_program_esc_clk_div(encoder);
> }
--
Jani Nikula, Intel Open Source Graphics Center
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next prev parent reply other threads:[~2018-07-02 9:57 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-15 10:21 [PATCH 00/20] ICELAKE DSI DRIVER Madhav Chauhan
2018-06-15 10:21 ` [PATCH 01/20] drm/i915/icl: Define register for DSI PLL Madhav Chauhan
2018-06-29 11:43 ` Jani Nikula
2018-06-29 13:31 ` Chauhan, Madhav
2018-06-29 14:18 ` Jani Nikula
2018-06-15 10:21 ` [PATCH 02/20] drm/i915/icl: Program DSI Escape clock Divider Madhav Chauhan
2018-06-15 17:30 ` Paulo Zanoni
2018-06-15 18:00 ` Chauhan, Madhav
2018-06-15 18:11 ` Paulo Zanoni
2018-06-20 8:14 ` Chauhan, Madhav
2018-06-15 10:21 ` [PATCH 03/20] drm/i915/icl: Define DSI mode ctl register Madhav Chauhan
2018-06-29 11:51 ` Jani Nikula
2018-06-29 13:59 ` Chauhan, Madhav
2018-06-29 14:18 ` Jani Nikula
2018-06-15 10:21 ` [PATCH 04/20] drm/i915/icl: Enable DSI IO power Madhav Chauhan
2018-07-02 9:56 ` Jani Nikula [this message]
2018-07-02 10:03 ` Chauhan, Madhav
2018-07-02 10:22 ` Jani Nikula
2018-07-02 10:26 ` Chauhan, Madhav
2018-06-15 10:21 ` [PATCH 05/20] drm/i915/icl: Define PORT_CL_DW_10 register Madhav Chauhan
2018-06-29 13:53 ` Jani Nikula
2018-07-02 8:22 ` Chauhan, Madhav
2018-07-02 10:12 ` Jani Nikula
2018-07-02 10:17 ` Chauhan, Madhav
2018-06-15 10:21 ` [PATCH 06/20] drm/i915/icl: Power down unused DSI lanes Madhav Chauhan
2018-06-29 13:57 ` Jani Nikula
2018-07-02 12:42 ` Jani Nikula
2018-07-02 12:43 ` Chauhan, Madhav
2018-06-15 10:21 ` [PATCH 07/20] drm/i915/icl: Define AUX lane registers for Port A/B Madhav Chauhan
2018-06-15 10:21 ` [PATCH 08/20] drm/i915/icl: Configure lane sequencing of combo phy transmitter Madhav Chauhan
2018-06-15 10:21 ` [PATCH 09/20] drm/i915/icl: DSI vswing programming sequence Madhav Chauhan
2018-06-15 10:21 ` [PATCH 10/20] drm/i915/icl: Enable DDI Buffer Madhav Chauhan
2018-06-15 10:21 ` [PATCH 11/20] drm/i915/icl: Define T_INIT_MASTER registers Madhav Chauhan
2018-06-15 10:21 ` [PATCH 12/20] drm/i915/icl: Program " Madhav Chauhan
2018-06-15 10:21 ` [PATCH 13/20] drm/i915/icl: Define data/clock lanes dphy timing registers Madhav Chauhan
2018-06-15 10:21 ` [PATCH 14/20] drm/i915/icl: Program DSI clock and data lane timing params Madhav Chauhan
2018-06-15 10:21 ` [PATCH 15/20] drm/i915/icl: Define TA_TIMING_PARAM registers Madhav Chauhan
2018-06-15 10:21 ` [PATCH 16/20] drm/i915/icl: Program " Madhav Chauhan
2018-06-15 10:21 ` [PATCH 17/20] drm/i915/icl: Get DSI transcoder for a given port Madhav Chauhan
2018-06-15 10:21 ` [PATCH 18/20] drm/i915/icl: Add macros for MMIO of DSI transcoder registers Madhav Chauhan
2018-06-15 10:21 ` [PATCH 19/20] drm/i915/icl: Define TRANS_DSI_FUNC_CONF register Madhav Chauhan
2018-06-15 10:21 ` [PATCH 20/20] drm/i915/icl: Configure DSI transcoders Madhav Chauhan
2018-06-15 11:06 ` ✗ Fi.CI.CHECKPATCH: warning for ICELAKE DSI DRIVER Patchwork
2018-06-15 11:12 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-06-15 11:21 ` ✓ Fi.CI.BAT: success " Patchwork
2018-06-15 18:14 ` ✓ Fi.CI.IGT: " Patchwork
2018-06-27 6:32 ` [PATCH 00/20] " Chauhan, Madhav
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